E2G0112-18-42 MSM5117800C SOJ28-P-400-1 TSOPII28-P-400-1 MSM5117800C-50 - Datasheet Archive

 

About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI

 

Dear customers, About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd. The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI Semiconductor Co., Ltd. on October 1, 2008. Therefore, please accept that although the terms and marks of "Oki Electric Industry Co., Ltd.", "Oki Electric", and "OKI" remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.". It is a change of the company name, the company trademark, and the logo, etc. , and NOT a content change in documents. October 1, 2008 OKI Semiconductor Co., Ltd. 550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan http://www.okisemi.com/en/ Pr E2G0112-18-42 E2G0112-18-42 el im y 2,097,152-Word ¥ 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE DESCRIPTION The MSM5117800C MSM5117800C is a 2,097,152-word ¥ 8-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM5117800C MSM5117800C achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The MSM5117800C MSM5117800C is available in a 28-pin plastic SOJ or 28-pin plastic TSOP. FEATURES · 2,097,152-word ¥ 8-bit configuration · Single 5 V power supply, ±10% tolerance · Input : TTL compatible, low input capacitance · Output : TTL compatible, 3-state · Refresh : 2048 cycles/32 ms · Fast page mode, read modify write capability · CAS before RAS refresh, hidden refresh, RAS-only refresh capability · Multi-bit test mode capability · Package options: 28-pin 400 mil plastic SOJ (SOJ28-P-400-1 SOJ28-P-400-1.27) (Product : MSM5117800C-xxJS) 28-pin 400 mil plastic TSOP (TSOPII28-P-400-1 TSOPII28-P-400-1.27-K) (Product : MSM5117800C-xxTS-K) (TSOPII28-P-400-1 TSOPII28-P-400-1.27-L) (Product : MSM5117800C-xxTS-L) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA ar This version: Apr. 1998 MSM5117800C MSM5117800C in ¡ Semiconductor MSM5117800C MSM5117800C ¡ Semiconductor Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM5117800C-50 MSM5117800C-50 50 ns 25 ns 13 ns 13 ns 90 ns MSM5117800C-60 MSM5117800C-60 60 ns 30 ns 15 ns 15 ns 110 ns 605 mW MSM5117800C-70 MSM5117800C-70 70 ns 35 ns 20 ns 20 ns 130 ns 550 mW 660 mW 5.5 mW 1/16 ¡ Semiconductor MSM5117800C MSM5117800C PIN CONFIGURATION (TOP VIEW) VCC 1 28 VSS VCC 1 28 VSS VSS 28 1 VCC DQ1 2 27 DQ8 DQ1 2 27 DQ8 DQ8 27 2 DQ1 DQ2 3 26 DQ7 DQ2 3 26 DQ7 DQ7 26 3 DQ2 DQ3 4 25 DQ6 DQ3 4 25 DQ6 DQ6 25 4 DQ3 DQ4 5 24 DQ5 DQ4 5 24 DQ5 DQ5 24 5 DQ4 WE 6 23 CAS WE 6 23 CAS CAS 23 6 WE RAS 7 22 OE RAS 7 22 OE OE 22 7 RAS NC 8 21 A9 NC 8 21 A9 A9 21 8 NC A10R 9 20 A8 A10R 9 20 A8 A8 20 9 A10R A0 10 19 A7 A0 10 19 A7 A7 19 10 A0 A1 11 18 A6 A1 11 18 A6 A6 18 11 A1 A2 12 17 A5 A2 12 17 A5 A5 17 12 A2 A3 13 16 A4 A3 13 16 A4 A4 16 13 A3 VCC 14 15 VSS VCC 14 15 VSS VSS 15 14 VCC 28-Pin Plastic TSOP (K Type) 28-Pin Plastic SOJ Pin Name A0 - A9, A10R Function Address Input RAS Row Address Strobe CAS Column Address Strobe DQ1 - DQ8 Data Input/Data Output OE Output Enable WE Write Enable VCC Power Supply (5 V) VSS Ground (0 V) NC Note : 28-Pin Plastic TSOP (L Type) No Connection The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/16 ¡ Semiconductor MSM5117800C MSM5117800C BLOCK DIAGRAM WE RAS OE Timing Generator I/O Controller CAS 8 Output Buffers 8 DQ1 - DQ8 10 Internal Address Counter A0 - A9 10 A10R Column Address Buffers 1 10 Refresh Control Clock Row Row Address 11 DecoBuffers ders Word Drivers Column Decoders Sense Amplifiers 8 8 I/O Selector Input Buffers 8 8 Memory Cells VCC On Chip VBB Generator On Chip IVCC Generator VSS 3/16 ¡ Semiconductor MSM5117800C MSM5117800C ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on Any Pin Relative to VSS VIN,VOUT ­0.5 to VCC + 0.5 V Voltage on VCC Supply Relative to VSS VCC ­0.5 to 7 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg ­55 to 150 °C *: Ta = 25°C Recommended Operating Conditions (Ta = 0°C to 70°C) Parameter Power Supply Voltage Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 - Input Low Voltage VIL ­0.5*2 - VCC + 0.5*1 0.8 V V Notes : *1. The input voltage is VCC + 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VCC is applied). *2. The input voltage is VSS ­ 2.0 V when the pulse width is less than 20 ns (the pulse width is with respect to the point at which VSS is applied). Capacitance (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Parameter Symbol Typ. Max. Unit Input Capacitance (A0 - A9, A10R) CIN1 - 5 pF Input Capacitance (RAS, CAS, WE, OE) CIN2 - 7 pF Output Capacitance (DQ1 - DQ8) CI/O - 7 pF 4/16 ¡ Semiconductor MSM5117800C MSM5117800C DC Characteristics Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol Condition MSM5117800 MSM5117800 MSM5117800 MSM5117800 MSM5117800 MSM5117800 C-50 C-60 C-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = ­5.0 mA 2.4 VCC 0 0.4 0.4 2.4 0 VCC VOL IOL = 4.2 mA 2.4 0 VCC Output Low Voltage 0.4 V V Input Leakage Current ILI ­10 10 ­10 10 ­10 10 mA ­10 10 ­10 10 ­10 10 mA - 120 - 110 - 100 mA 1, 2 - 2 - 2 - 2 mA 1 - 1 - 1 - 1 - 120 - 110 - 100 mA 1, 2 - 5 - 5 - 5 mA 1 - 120 - 110 - 100 mA 1, 2 - 110 - 100 - 90 mA 1, 3 0 V £ VI £ 6.5 V; All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) Power Supply Current (Standby) ICC2 Current (Standby) (CAS before RAS Refresh) Average Power Supply Current (Fast Page Mode) tRC = Min. RAS, CAS = VIH RAS, CAS RAS cycling, tRC = Min. RAS = VIH, ICC5 CAS = VIL, DQ = enable Average Power Supply Current RAS, CAS cycling, ICC3 CAS = VIH, (RAS-only Refresh) Power Supply 0 V £ VO £ VCC VCC ­0.2 V Average Power Supply Current DQ disable ICC6 RAS cycling, CAS before RAS RAS = VIL, ICC7 CAS cycling, tPC = Min. Notes : 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while RAS = VIL. 3. The address can be changed once or less while CAS = VIH. 5/16 ¡ Semiconductor MSM5117800C MSM5117800C AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter Symbol MSM5117800 MSM5117800 MSM5117800 MSM5117800 MSM5117800 MSM5117800 C-50 C-70 C-60 Unit Note Min. Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time Access Time from RAS Max. Min. Max. Min. Max. tRC tRWC tPC 90 131 35 - - - 110 155 40 - - - 130 185 45 - - - ns ns ns tPRWC 76 - 85 - 100 - ns tRAC - 50 - 60 - 70 ns 4, 5, 6 Access Time from CAS tCAC Access Time from Column Address Access Time from CAS Precharge tAA tCPA - - 13 25 - - 15 30 - - 20 35 ns ns 4, 5 4, 6 - 30 - 35 - 40 ns 4 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ - 0 13 - - 0 15 - - 0 20 - ns ns 4 4 CAS to Data Output Buffer Turn-off Delay Time OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period tOFF tOEZ tT tREF 0 0 3 - 13 0 0 3 - 15 15 50 32 0 0 3 - 20 13 50 32 20 50 32 ns ns ns ms 7 7 3 RAS Precharge Time tRP 30 - 40 - 50 - ns RAS Pulse Width tRAS 50 10,000 60 10,000 70 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 50 100,000 60 100,000 70 100,000 ns RAS Hold Time tRSH tROH 13 13 - - 15 15 - - 20 20 - - ns ns RAS Hold Time referenced to OE CAS Precharge Time (Fast Page Mode) tCP 7 - 10 - 10 - ns CAS Pulse Width tCAS 13 10,000 15 10,000 20 10,000 ns CAS Hold Time CAS to RAS Precharge Time tCSH tCRP 50 5 - - 60 5 - - 70 5 - - ns ns RAS Hold Time from CAS Precharge RAS to CAS Delay Time RAS to Column Address Delay Time tRHCP tRCD tRAD 30 17 12 - 37 25 35 20 15 - 45 30 40 20 15 - 50 35 ns ns ns Row Address Set-up Time tASR 0 - 0 - 0 - ns Row Address Hold Time tRAH 7 - 10 - 10 - ns Column Address Set-up Time tASC 0 - 0 - 0 - ns Column Address Hold Time Column Address to RAS Lead Time tCAH tRAL 7 25 - - 15 30 - - 15 35 - - ns ns Read Command Set-up Time tRCS 0 - 0 - 0 - ns Read Command Hold Time tRCH 0 - 0 - 0 - ns 8 Read Command Hold Time referenced to RAS tRRH 0 - 0 - 0 - ns 8 5 6 6/16 ¡ Semiconductor MSM5117800C MSM5117800C AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12 Parameter Symbol MSM5117800 MSM5117800 MSM5117800 MSM5117800 MSM5117800 MSM5117800 C-50 C-60 C-70 Unit Note Min. Max. Min. Max. Min. Max. tWCS 0 - 0 - 0 - ns Write Command Hold Time tWCH 7 - 10 - 15 - ns Write Command Pulse Width OE Command Hold Time Write Command to RAS Lead Time Write Command to CAS Lead Time tWP tOEH tRWL tCWL 7 13 - - 10 15 - - 10 20 - - ns ns 13 13 - - 15 15 - - 20 20 - - ns Data-in Set-up Time Data-in Hold Time OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time RAS to WE Delay Time tDS tDH tOED tCWD tAWD tRWD 0 7 13 36 48 73 - - - - - - 0 15 15 40 55 85 - - - - - - 0 15 20 50 65 100 - - - - - - ns ns ns ns ns ns 10 10 CAS Precharge WE Delay Time 9 Write Command Set-up Time 9 ns tCPWD 53 - 60 - 70 - ns CAS Active Delay Time from RAS Precharge tRPC 10 - 10 - 10 - ns RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) WE to RAS Precharge Time (CAS before RAS) WE Hold Time from RAS (CAS before RAS) RAS to WE Set-up Time (Test Mode) RAS to WE Hold Time (Test Mode) tCSR tCHR tWRP tWRH tWTS tWTH 10 10 10 10 10 10 - - - - - - 10 10 10 10 10 10 - - - - - - 10 10 10 10 10 10 - - - - - - 9 9 9 ns ns ns ns ns ns 7/16 ¡ Semiconductor Notes: MSM5117800C MSM5117800C 1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD tCWD (Min.) , tRWD tRWD (Min.), tAWD tAWD (Min.) and tCPWD tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/16 E2G0093-17-41F E2G0093-17-41F , , , ¡ Semiconductor MSM5117800C MSM5117800C TIMING WAVEFORM Read Cycle tRC tRP tRAS RAS VIH ­ VIL ­ tCRP tCSH tCRP tRCD VIH ­ CAS VIL ­ tRAD tASR Address VIH ­ VIL ­ tRSH tCAS tRAH tASC tRAL tCAH Column Row tRCS WE VIH ­ VIL ­ tAA tROH tOEA VIH ­ OE VIL ­ tCAC tRAC DQ tRCH tRRH VOH ­ tOEZ Open VOL ­ tOFF Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH ­ VIL ­ tCRP tCRP VIH ­ CAS VIL ­ WE OE VIH ­ VIL ­ tASC Row tCAS tCAH tRAL Column tWCS VIH ­ tWCH tCWL tWP VIL ­ tRWL VIH ­ VIL ­ tDS DQ tRSH tRAD tRAH tASR Address tCSH tRCD VIH ­ VIL ­ tDH Valid Data-in Open "H" or "L" 9/16 , ¡ Semiconductor MSM5117800C MSM5117800C Read Modify Write Cycle tRWC tRAS RAS VIH ­ VIL ­ tRP tCRP tCSH tCRP tRCD tRSH tCAS VIH ­ CAS VIL ­ tASR VIH ­ Address VIL ­ WE VIH ­ VIL ­ OE tRAH tASC tCAH Column Row tRAD tRWD VIH ­ VIL ­ tAA tAWD tRCS tOEA tOED tCAC tRAC DQ VI/OH­ VI/OL­ tCWL tRWL tWP tCWD tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/16 , , , , , ¡ Semiconductor MSM5117800C MSM5117800C Fast Page Mode Read Cycle tRASP VIH ­ RAS V ­ IL VIH ­ CAS VIL ­ Address WE VIH ­ VIL ­ tRP tRHCP tCRP tPC tRCD tCP tASR tCP tCAS tCAS tRAD tRAH tASC tCSH tCAH tASC Column Row VIH ­ VIL ­ Column tRCS tRCH tOFF tOEZ tRRH tCPA tOEA tCAC tRCH tAA tAA tRAC tOEA tOFF tCAC tCAC tOEZ tCLZ Valid Data-out tCLZ tRCS tCPA tOEA VOH ­ DQ VOL ­ tRAL tCAH tASC Column tAA VIH ­ OE VIL ­ tCAS tCAH tRCH tRCS tCRP tRSH tOFF tCLZ tOEZ Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP VIH ­ RAS V ­ IL tCRP VIH ­ CAS VIL ­ Address VIH ­ VIL ­ tCAS tASR tRAH tASC Row tRAD VIH ­ VIL ­ tDS VIH ­ DQ VIL ­ tRHCP tRSH tRCD tWCS WE tRP tPC tCSH tCAH Column tCWL tWCH tWP tDH Valid Data-in tCP tCRP tCP tCAS tASC tCAH tASC Column tCWL tWCS tWCH tWP tDS tDH Valid Data-in tCAS tCAH tRAL Column tRWL tCWL tWCS tWCH tWP tDS tDH Valid Data-in Note: OE = "H" or "L" "H" or "L" 11/16 ¡ Semiconductor MSM5117800C MSM5117800C , , , , Fast Page Mode Read Modify Write Cycle tRASP VIH ­ RAS VIL ­ tRP tCSH tPRWC tRCD VIH ­ CAS VIL ­ tASC tCAH tRAH VIH ­ VIL ­ tCRP tCAS tASC tCAH tCAH Column Column Row tCWD tRCS V WE IH ­ VIL ­ tRCS tCPWD tCWD tCWL tAWD tRAC tCWL tWP tDH VI/OH­ VI/OL ­ Out tCLZ tOEA tOED tOEZ tCAC In tDH tDS tOEA tOEZ tWP tCPA tAA tOED tCAC tCWL tROH tWP tDH tDS tOEA tRWL tAWD tCPA tAA tAA VIH ­ OE V ­ IL tRCS tCPWD tCWD tAWD tDS tRAL Column tASC tRWD DQ tCP tCAS tRAD tASR Address tCP tCAS tRSH Out tOED In tCLZ tOEZ tCAC Out In tCLZ "H" or "L" RAS-Only Refresh Cycle tRC RAS CAS Address VIL ­ VIH ­ VIL ­ VIH ­ VIL ­ tRP tRAS VIH ­ tCRP tASR tRPC tRAH Row tOFF DQ VOH ­ VOL ­ Open Note: WE, OE = "H" or "L" "H" or "L" 12/16 M L K ^ S R Q P ¡ Semiconductor MSM5117800C MSM5117800C CAS before RAS Refresh Cycle tRC tRP RAS tRP tRAS VIH ­ VIL ­ tRPC tRPC CAS tCSR tCHR tWRP tCP tWRH VIH ­ VIL ­ tWRP , , WE VIH ­ VIL ­ DQ VOH ­ VOL ­ tOFF Open Note: OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC tRAS RAS tRP VIL ­ VIH ­ VIL ­ VIH ­ VIL ­ tRSH tRCD tRAD tASC tRAH tASR Address tRAS tRP VIH ­ tCRP CAS tRC Row tCHR tCAH Column tRCS tRAL VIH ­ WE V IL ­ tRRH tAA tROH tOEA VIH ­ OE V IL ­ tRAC DQ VOH ­ VOL ­ tCAC tCLZ tOFF tOEZ Valid Data-out "H" or "L" 13/16 ¡ Semiconductor MSM5117800C MSM5117800C Hidden Refresh Write Cycle tRC tRAS RAS CAS Address VIH ­ VIL ­ OE VIH ­ VIL ­ tASR tRCD tRSH tRAD tASC tCAH tRAH Row tCHR tRAL Column tWCH tWP VIH ­ VIL ­ tWRP tWRH VIH ­ VIL ­ tDS DQ tRP , , , VIH ­ VIL ­ tCRP tWCS WE tRC tRAS tRP VIH ­ VIL ­ tDH Valid Data-in "H" or "L" Test Mode Initiate Cycle tRC tRP RAS VIH ­ VIL ­ tRPC tCP CAS tRAS tCSR VIH ­ VIL ­ tWTS WE tCHR tWTH VIH ­ VIL ­ tOFF DQ VOH ­ VOL ­ Open Note: OE, Address = "H" or "L" "H" or "L" 14/16 ¡ Semiconductor MSM5117800C MSM5117800C PACKAGE DIMENSIONS (Unit : mm) SOJ28-P-400-1 SOJ28-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.30 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/16 ¡ Semiconductor MSM5117800C MSM5117800C (Unit : mm) TSOPII28-P-400-1 TSOPII28-P-400-1.27-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.51 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/16