AN2256/D MSC8101 MSC8101ADS SC140 HDI16 IRQ18 RS232 - Datasheet Archive

 

AN2256/D Rev 1, 2/2002 Performing MSC8101 DMA Data Transfers Between Internal and External Memory by Scott Smith CONTENTS 1

 

Application Note AN2256/D AN2256/D Rev 1, 2/2002 Performing MSC8101 MSC8101 DMA Data Transfers Between Internal and External Memory by Scott Smith CONTENTS 1 MSC8101 MSC8101 Device Technical Overview . 1 2 MSC8101ADS MSC8101ADS Implementation . 4 2.1 Data Flow . 5 2.2 Programming Sequence. 5 3 Development Environment . 7 4 Software Flow, Register Settings, and Configuration Code . 8 Many of today's complex systems require the movement of large amounts of data between memories and peripherals. One efficient way to achieve such data movement on the Motorola MSC8101 MSC8101 digital signal processor (DSP) is to use the direct memory access (DMA) controller. The DMA controller increases data throughput while minimizing the need for intervention by the SC140 SC140 core. This application note describes the functionality of the MSC8101 MSC8101 DMA controller and explains how to configure its channels to perform data transfers between external and internal memory. The discussion includes a software programming example and a recommended programming sequence for configuring and using different modules within the MSC8101 MSC8101. In addition to the DMA controller, this example includes interrupt processing configurations.1 1 MSC8101 MSC8101 Device Technical Overview The Motorola MSC8101 MSC8101 is a versatile and highly integrated single-chip device offering a unique combination of: · RISC Communications Processor Module (CPM) · High-performance SC140 SC140 core that performs at 1200 DSP MIPS using an internal 300 MHz clock at 1.6 V core voltage · 512 KB of internal SRAM · 60x-compatible system bus interface · 16-channel DMA controller · Programmable interrupt controller (PIC) · General-purpose 16-bit host port (HDI16 HDI16) The MSC8101 MSC8101 is the first member of the family of programmable DSPs based on the SC140 SC140 core, which itself is the first implementation of an innovative architecture that addresses the key market needs of next-generation DSP applications. The SC140 SC140 core supports computational-intensive communications applications by providing exceptional performance, low power consumption, efficiently compilable code, and compact code density. The four-ALU SC140 SC140 core uses a variable-length execution set (VLES) execution model, which attains maximum parallelism by allowing multiple address generation and data arithmetic logic units to execute multiple instructions in a single clock cycle. The SC140 SC140 core features high performance, low cost, low power, and superscalar architecture. Figure 1 depicts the MSC8101 MSC8101 system architecture. 1 For details on the structure and function of the MSC8101 MSC8101 DMA and interrupt controllers, refer to their respective chapters in the MSC8101 MSC8101 Reference Manual. For programming information, consult the MSC8101 MSC8101 User's Guide. MSC8101 MSC8101 Device Technical Overview MII TDMs { · · · SIU `MCC' / UART / HDLC / Transparent / Enet / FastEnet / ATM / SCCs UTOPIA 8 Interface Serial Interface and TSA CPM 3 x FCC 2 x MCC Interrupt Controller 64-bit 60x-Compatible System Bus MEMC Timers PIT System Protection Reset Control Clock Control Parallel I/O 4 x SCC 2 x SMC DMA Engine Baud-Rate Generators Dual Ported RAM SIC_EXT Bridge SPI RISC Interrupts SIC 2 x SDMA I2C 64/32-bit System Bus MEMC 64-bit Local Bus Other Peripherals Extended Core Program Sequencer Address Register File Data ALU Register File Q2PPC Bridge 128-bit QBus PIC Interrupts EFCOP Boot ROM HDI16 HDI16 SC140 SC140 Core Address ALU JTAG 8/16-bit Host Interface EOnCETM Power Management Data ALU SRAM 512 KB Clock/PLL L1 Interface 128-bit P-Bus 64-bit XA Data Bus 64-bit XB Data Bus Figure 1. MSC8101 MSC8101 System Architecture Notice that MSC8101 MSC8101 interrupt processing uses these different interrupt controllers: · Programmable interrupt controller (PIC), which operates in the SC140 SC140 core and is accessed via the SC140 SC140 core QBus. The QBus is a high-speed pipelined bus with separate address and data phases. This single-master bus operates at the same frequency as the SC140 SC140 core. · SIU-CPM interrupt controller (SIC), which generates interrupt requests to the PIC. · External SIU-CPM interrupt controller (SIC_EXT), which generates interrupt requests to an external host CPU. This architecture yields maximum flexibility in the interrupt handling, enabling the SC140 SC140 core or an external host, or a combination of the two, to handle interrupts. As Figure 1 shows, the DMA connects to both the 60x-compatible system bus and the local bus and can function as a bridge between them. The MSC8101 MSC8101 multi-channel DMA supports up to 16 time-multiplexed channels with hardware buffer alignment. Moreover, it supports flyby transactions (also known as "single access transactions") to either bus. The DMA enables hot swap between channels, by time-division multiplexing channels, with no cost in clock cycles. Sixteen priority levels are available for synchronous and asynchronous transfers on the bus, providing a varying bus bandwidth per DMA channel. The different requestors serviced by the DMA controller can be any one of four external peripherals, four internal peripherals, or sixteen internal requests generated by the DMA FIFO itself. 2 MSC8101 MSC8101 Device Technical Overview The DMA controller can accommodate a total of six different issued transactions on both the system bus and the local bus. For example, on each bus there can be one transaction in the data phase, one transaction in the address phase, and one pending transaction. Each DMA channel handles a single unidirectional transaction at one time. The transaction can be any one of the following: · Memory to DMA FIFO · DMA FIFO to memory · Peripheral to DMA FIFO · DMA FIFO to peripheral · Memory to peripheral, in Flyby mode · Peripheral to memory, in Flyby mode It is possible to modify each channel attribution because each request activates a buffer according to its type as programmed in the DCPRAM[BD_ATTR] field. Figure 2 shows a diagram of the DMA system. DREQ[1­4] External Peripherals DACK[1­4] DONE[1­2]/DRACK[1­2] 60x-Compatible System Bus DMA System I/F Channel Parameter RAM DMA FIFO External Memory Request Arbiter DMA Local I/F FIFO_WMARK[0­7] FIFO_HUNGRY[0­7] INT_DACK[0­3] Local Bus INT SRAM MSC8101 MSC8101 HDI16 HDI16 EFCOP INT_DREQ[0­3] Figure 2. DMA System Eight internal DMA FIFOs generate service for 16 internal requests. Each FIFO generates a watermark request to indicate that the FIFO contains data for the DMA controller to empty and write to the destination, and a hungry request to indicate that the FIFO can accept more data. Each FIFO is three 3 MSC8101ADS MSC8101ADS Implementation bursts (96 bytes) deep and links two consecutive channels for dual-address transfers. For example, channel 0 and channel 1 use the same FIFO for read and write transfers. Instead of using DMA FIFOs, "flyby" transfers can be performed, but only to transfer data between memory and the internal peripherals, that is, the HDI16 HDI16 or EFCOP. For MSC8101 MSC8101 DMA transfers, buffer descriptors (BDs) contain source or destination addresses, the number of bytes to be transferred, and the specific attributes of the buffer. A maximum of 64 such BDs are available within the DMA controller, and each has flexible configurations to enable the following types of buffers: · Simple buffers · Cyclic buffers · Single address buffers (I/O device) · Incremental address buffers · Chained buffers · Complex buffers, consisting of a combination of the preceding buffer types 2 MSC8101ADS MSC8101ADS Implementation The transactions that occur within the application discussed in this document are memory-to-DMA FIFO and vice versa. Figure 3 shows a transfer between external memory (SDRAM) and internal memory (SRAM). The accesses required to perform these transfers are executed in the following order: internal memory to DMA FIFO and then DMA FIFO to external memory. In the opposite direction-that is, external to internal memory-the following accesses are executed: external memory to DMA FIFO and DMA FIFO to internal memory. System Bus (32-Bit Address/64-Bit Data) DMA Controller Memory Controller System Bus Control Memory Peripheral Bridge Memory Controller Local Bus Control Local Bus (32-Bit Address/64-Bit Data) SRAM EFCOP/ HDI16 HDI16 MSC8101 MSC8101 Read Channel Write Channel Figure 3. Transfer from External Memory to Internal Memory 4 MSC8101ADS MSC8101ADS Implementation 2.1 Data Flow Figure 4 represents the flow of data and the DMA channels associated with each flow. DMA Channel 0 FIFO for DMA Channels 0 and 1 DMA Channel 1 Internal Memory (SRAM) External Memory (SDRAM) DMA Channel 3 FIFO for DMA Channels 2 and 3 DMA Channel 2 Figure 4. DMA Transfer Data Flow 2.2 Programming Sequence The following programming flow for enabling MSC8101 MSC8101 DMA transfers is recommended: 1. Establish a pointer to MSC8101 MSC8101 dual-port RAM (DPRAM) memory map where the DMA BDs and registers reside. 2. Clear the destination locations. 3. Initialize the buffer descriptors. 4. Initialize common DMA parameters. 5. Enable and configure any DMA interrupt vectors and required interrupt service routines. 6. Initialize the DMA Channel Configuration Register (which includes activating the channel). These steps map directly to the source code presented in Section 4 and describe the various configurations required to perform the memory-to-memory transfers. Section 4 also lists the relevant registers and describes the applicable bit fields. The remainder of this section discusses each of these steps in detail. 2.2.1 Create the DPRAM Memory Mapping The msc8101.h header file contains a memory map of all of the MSC8101 MSC8101 registers located in DPRAM in the form of a structure. A pointer to this structure is configured and assigned the value 0x14700000, which is the base address of DPRAM on the MSC8101ADS MSC8101ADS. 2.2.2 Configure Buffer Descriptors Our application demonstrates the cyclic buffer configuration with incremental addressing. This configuration enables DMA transfers to be continuously triggered with the same source and destination addresses without the need to repeatedly update the BDs. Four BDs are used in this application and are paired around two DMA FIFOs to perform "dual" transfers. One pair handles the SRAM-to-SDRAM 5 MSC8101ADS MSC8101ADS Implementation transfer and the other handles the SDRAM-to-SRAM transfer. The following list details how each of the individual BDs is configured. The size of each buffer is determined by a "compile-time" user definition, which is 128 bytes by default: · BD0. Handles the transfer of data from internal memory to the DMA FIFO, so the address given is that of the data buffer in SRAM. The attributes of this BD are configured as follows: - No interrupt upon completion. - Cyclic address (original address is re-instated once buffer is completed). - Read channel, as it is reading from SRAM. - Transfer size of one burst or 64 bits depending upon compile-time user definition. Bursts occur only when the address is 32-byte aligned. · BD1. Handles the transfer of data from the DMA FIFO to external memory, so the address given is that of the data buffer in SDRAM. The attributes of this BD are configured as follows: - Generate interrupt upon completion to notify the SC140 SC140 core when the transfer completes. - Cyclic address (original address is reinstated once buffer is completed). - Write Channel, as it is writing to SDRAM. - Transfer Size of one burst or 64 bits dependent upon compile-time user definition. · BD2. Handles the transfer of data from external memory to the DMA FIFO, so the address given is that of the data buffer in SDRAM. The attributes of this BD are configured as follows: - No interrupt upon completion. - Cyclic address (original address is reinstated once the buffer is completed). - Read channel, as it is reading from SDRAM. - Transfer size of one burst or 64 bits depending upon the compile-time user definition. · BD3. Handles the transfer of data from the DMA FIFO to internal memory, so the address given is that of the data buffer in SRAM. The attributes of this BD are configured as follows: - Generate interrupt upon completion to notify the SC140 SC140 core when the complete transfer completes. - Cyclic address (original address is reinstated once the buffer is completed). - Write channel, as it is writing to SRAM. - Transfer size of one burst or 64 bits depending upon the compile-time user definition. 2.2.3 Initialize Common DMA Parameters Using the DMA Internal Mask Register, interrupts on DMA Channels 1 and 3 are enabled according to the previously-defined BD attributes. Upon initialization, the DMA Status and Transfer Error Address Status registers are cleared for completeness by writing a value of one to them. When a DMA channel interrupt is detected, the interrupt should be acknowledged by writing a value of one to the corresponding field in the DMA Status Register. 2.2.4 Configure DMA Interrupts The DMA Channel interrupt (IRQ18 IRQ18) is configured using the Edge/Level-Triggered Interrupt Priority E Register. We have selected level-triggered with an interrupt priority level of 3. Also, a routine is loaded into the PIC interrupt vector table entry associated with IRQ18 IRQ18 (VBA address + 0xc80). Because only 0x40 bytes are available within the vector table entry, this should be a small routine that calls a larger ISR, if required. Finally, the DMA Status Register should be configured to enable interrupts and the Vector Base Address register initialized. 6 Development Environment 2.2.5 Configure and Activate DMA Channels Our application uses four DMA Channels, so four DMA Channel Configuration Registers must be maintained. The following list details how each register is configured. · DCHCR0. DMA Channel 0 is configured as follows: - Data buffer is on the local bus (SRAM). - Use BD0. - Requestor is internal, so the FIFO status is used to trigger DMA transfers. It is a hungry request. - Priority level is 5 (where 0 is the highest priority). · DCHCR1. DMA Channel 1 is configured as follows: - Data buffer is on the 60x-compatible system bus (SDRAM). - Use BD1. - Requestor is internal, so the FIFO status is used to trigger DMA transfers. It is a watermark request. - Priority level is 6. · DCHCR2. DMA Channel 2 is configured as follows: - Data buffer is on the 60x-compatible system bus (SDRAM). - Use BD2. - Requestor is internal, so the FIFO status is used to trigger DMA transfers. It is a hungry request. - Priority level is 4. · DCHCR3. DMA Channel 0 is configured as follows: - Data buffer is on the local bus (SRAM). - Use BD3. - Requestor is internal, so the FIFO status is used to trigger DMA transfers. It is a watermark request. - Priority level is 3. 3 Development Environment Our application development environment is Metrowerks® CodeWarrior® for StarCore, production release 1.0. The CodeWarrior IDE is an integrated toolset for developing and debugging code that features an intuitive graphical user interface (GUI). The Metrowerks project file requires an 8101_Initialization.cfg file that it uses to configure SDRAM and so on via the debugger. The location of this file can be modified to suit your own implementation of Metrowerks, and the contents of this file are defined in Section 4. Table 1 defines the source code project files. Table 1. Source Code Project Files Module MSC8101 MSC8101 internal to external memory transfer Filename Description dmaRAMtest.mcp Metrowerks project file. dma.c Exercises the DMA controller functionality by performing memory-to-memory transfers in Dual-Address mode. dmatest.h Defines DMA buffer size, Burst or Single-Beat transfer switch, and Internal Memory-Map Register (IMMR) address. msc8101.h MSC8101 MSC8101 register memory mapping (requires MW -nostructpad Passthrough option). types.h Specific variable types used in this application 7 Software Flow, Register Settings, and Configuration Code The MSC8101 MSC8101 Application Development System (MSC8101ADS MSC8101ADS) board is a general development platform with a socketed MSC8101 MSC8101, an on-board Flash and SDRAM memory, plus communication transceivers for Fast Ethernet, ATM 155-Uni, E1/T1, RS232 RS232, and a Crystal stereo audio codec. With this system, developers can start developing software or use the schematics as a reference for their own system development.2 Table 2 defines the default switch configurations for the MSC8101ADS MSC8101ADS platform, with the on/off switch notation referring to the on and off as physically displayed on the DIL switches upon the MSC8101ADS MSC8101ADS board. Table 2. HDI16 HDI16 MSC8101ADS MSC8101ADS Switch Settings Switch Settings Comments SW1 - HOST On-on-on-on SW2 - PPC_CTRL On-on-on-on-on-on-on-on SW5 64 bit 64-bit 60x Bus SW6 64 bit 64-bit 60x Bus SW9 On-on-on-off-on-off-on-off MODCLK #40, HDI16 HDI16 disabled by SW9/8 being on. SW10 On-on-on-on SW11 - S/W_OPT On-on-on-on Our application uses a 16.384 MHz CLKIN crystal on the ADS platform. With the SW9 settings defined previously, MODCLK #40 is selected, yielding a host 60x bus clock speed of ~40 MHz on the host device, a DSP SC140 SC140 core speed of ~200 MHz, and a CPM speed of ~100 MHz. 4 Software Flow, Register Settings, and Configuration Code The SC140 SC140 core need only configure a few control registers to set up and initiate a DMA data transfer, and it is then free to perform any other required tasks in the pipeline while the DMA controller handles the data transfer in the background. Figure 5 details the software flow of the DMA memory-to-memory transfer example in this application note. The source code shown here serves as a functional reference only and has not been optimized, nor does it provide any memory management or application-level data stream I/O functions. This code can, of course, be used as a functional reference, optimized, and reused as production-worthy drivers. 2 8 For details on powering on and setting up the ADS board, consult the MSC8101ADS MSC8101ADS User's Manual. One chapter of this manual presents installation instructions for the MSC8101ADS MSC8101ADS board. Software Flow, Register Settings, and Configuration Code DMA Complete Interrupt DMA Complete ISR Start Initialize Source Buffer Data Pattern in internal memory (SRAM). 1 3 Channel 1 or 3? Clear Destination Buffer in SRAM. Clear the Interrupt. Clear the Interrupt. Initialize DMA Channel Buffer Descriptors Enable External to Internal Memory Transfer DMA Channels (2 and 3). Compare Source and Destination Buffers, Recording Any Errors. Initialize Common DMA Parameters. Increment the Contents of the First Location Within the Source Buffer. Configure and Enable DMA Channel Interrupts and Load Vector Table With ISR Routine Address. Clear the Destination Buffer in SRAM. Enable Internal to External Memory Transfer DMA Channels (0 and 1). Enable Internal to External Memory Transfer DMA Channels (0 and 1). Loop Continuously. Return Figure 5. MSC8101 MSC8101 Software Flow 9 Software Flow, Register Settings, and Configuration Code Table 3 lists all the register settings for the application discussed in this application note. For details on the DMA and interrupt registers, consult the "Programming Model" section of the DMA chapter or the interrupt scheme chapter in the MSC8101 MSC8101 Reference Manual. . Table 3. MSC8101 MSC8101 Register Settings Register Bits Setting Meaning DMA Channel 0 - BD_ADDR (Dynamically Allocated Internal Memory Address) Address of Tx Buffer DMA Channel 0 - BD_SIZE (0x80) Size of the Tx Buffer DMA Channel 0 - BD_ATTR (0x40000230 | 0x40000030) 0 1 2 4 22­24 26 27 0|1 0 0 100 | 000 1 1 DMA Channel 0 - BD_BSIZE (0x80) DMA Channel 0 - DCHCR (0x00000045 | 0x80000045) No interrupt Cyclic Address No continuous buffer Increment address 32 or 8 byte max transfer size Flush FIFO Read Transaction Re-instated Buffer Size once current buffer completes. 0 1 10-15 17 2 5 28­31 0|1 0 000000 0 1 0101 Channel enabled or disabled Local Bus Buffer Descriptor 0 Dual access transaction Internal Requestor Priority 5 DMA Channel 1 - BD_ADDR (0x20000000) SDRAM address DMA Channel 1 - BD_SIZE (0x80) Size of the Tx Buffer DMA Channel 1 - BD_ATTR (0xc00002200xc0000020) 0 1 2 4 22­24 26 27 1 1 0 0 100 000 1 0 DMA Channel 1 - BD_BSIZE (0x80) DMA Channel 1 - DCHCR (0x40010046 | 0x 0xc0010046) Generate interrupt Cyclic Address No continuous buffer Increment Address 32 or 8 byte max transfer size Flush FIFO Write Transaction Re-instated Buffer Size once current buffer completes 0 1 10-15 17 25 28­31 0|1 1 000001 0 1 0110 Channel enabled or disabled 60x Bus Buffer Descriptor 1 Dual access transaction Internal Requestor Priority 6 DMA Channel 2 - BD_ADDR (0x20000000) SDRAM address DMA Channel 2 - BD_SIZE (0x80) Size of the Rx Buffer DMA Channel 2 - BD_ATTR (0x40000230 | 0x40000030) 10 0 1 2 4 22­24 26 27 0|1 0 0 100 000 1 1 No interrupt Cyclic Address No continuous buffer Increment Address 32 or 8 byte max transfer size Flush FIFO Read Transaction Software Flow, Register Settings, and Configuration Code Table 3. MSC8101 MSC8101 Register Settings (Continued) Register Bits Setting DMA Channel 2 - BD_BSIZE (0x80) Meaning Re-instated Buffer Size once current buffer completes. DMA Channel 2 - DCHCR (0x40020044 | 0xc0020044) 0 1 10­15 17 25 28­31 0|1 1 000010 0 1 0100 Channel enabled or disabled 60x Bus Buffer Descriptor 2 Dual access transaction Internal Requestor Priority 4 DMA Channel 3 - BD_ADDR (Dynamically Allocated Internal Memory Address) Address of Rx Buffer DMA Channel 3 - BD_SIZE (0x80) Section 15.6.1 of [1] Size of the Rx Buffer DMA Channel 3 - BD_ATTR (0xc0000220| 0xc0000020) 0 1 2 4 22­24 26 27 1 1 0 0 100 | 000 1 0 DMA Channel 3 - BD_BSIZE (0x80) Generate interrupt Cyclic Address No continuous buffer Increment address 32 or 8 byte max transfer size Flush FIFO Write Transaction Re-instated Buffer Size once current buffer completes. DMA Channel 3 - DCHCR (0x00030043 | 0x80030043) 0 1 10­15 17 25 28­31 0|1 0 000011 0 1 0011 Channel enabled or disabled Local Bus Buffer Descriptor 3 Dual access transaction Internal Requestor Priority 3 DMA Internal Mask Register (DIMR) (0x50000000) 1 3 1 1 Enable Channel 1 Interrupt Enable Channel 3 Interrupt Interrupt Pending Register B (IPRB) (0x 0x0004) 13 1 Clears any pending IRQ18 IRQ18 (DMA) interrupts Edge/Level-Triggered Int Priority Reg E (ELIRE) (0x0300) 4 5­7 0 011 IRQ18 IRQ18 Level Triggered Interrupt Priority Level 3 Following is a listing of the Metrowerks IDE 8101_Initialization.cfg script file for configuring the various MSC8101ADS MSC8101ADS memory banks. Example 1. Configuration File Listing #-# MSC8101 MSC8101 Initialization File #-writeAllmem16 0xf0010006 0xfbc3 writemmr16 IMMR 0x1470 writemmr32 BCR 0x00900000 #SYPCR ############################################### ######### bank0_init ########################## ############################################### #q001->mem_regs[0].memc_or = 0xff800866 writemmr32 OR0 0xff800866 ; 11 Software Flow, Register Settings, and Configuration Code #q001-> mem_regs[0].memc_br writemmr32 BR0 0xff801801 = 0xfc001801; ############################################### ######### bank1_init ########################## ############################################### #q001->mem_regs[1].memc_or = 0xffff8010 writemmr32 OR1 0xffff8010 #q001-> mem_regs[1].memc_br writemmr32 BR1 0x14501801 ; = 0x14501801; ############################################### ######### bank2_init ########################## ############################################### # precharge =(int *) 0x20000020; #q001->memc_psrt = 0xe; writemmr8 PSRT 0xe #q001->mem_regs[2].memc_or = 0xff003080 writemmr32 OR2 0xff003080 #q001-> mem_regs[2].memc_br writemmr32 BR2 0x20000041 = 0x20000041; #SDRAM1 #q001->memc_psdmr = 0xc2689212; writemmr32 PSDMR 0xc2689212 #q001->memc_psdmr = 0xaa689212 writemmr32 PSDMR 0xaa689212 # *precharge = 0 writemem32 0x20000020 0x0 #q001->memc_psdmr = 0x8a689212 writemmr32 PSDMR 0x8a689212 #precharge =(int *) 0x20000000; #*precharge = 0x0 writemem32 0x20000000 0x0 #*precharge = 0x0 writemem32 0x20000000 0x0 #*precharge = 0x0 writemem32 0x20000000 0x0 #*precharge = 0x0 writemem32 0x20000000 0x0 #*precharge = 0x0 writemem32 0x20000000 0x0 12 ; Software Flow, Register Settings, and Configuration Code #*precharge = 0x0 writemem32 0x20000000 0x0 #*precharge = 0x0 writemem32 0x20000000 0x0 #*precharge = 0x0 writemem32 0x20000000 0x0 #q001->memc_psdmr = 0x9a689212 writemmr32 PSDMR 0x9a689212 #precharge = (int *)0x20000032; #*precharge = 0x0 writemem32 0x20000032 0x0 #q001->memc_psdmr = 0xc2689212 writemmr32 PSDMR 0xc2689212 #q001->mem_regs[2].memc_or = 0xff0030a0; writemmr32 OR2 0xff0030a0 #q001-> mem_regs[2].memc_br writemmr32 BR2 0x20000041 = 0x20000041; #q001->memc_psdmr = 0xc2689212 writemmr32 PSDMR 0xc2689212 #q001->memc_psrt = 0x13; writemmr8 PSRT 0x13 #q001->memc_mptpr = 0x2800 writemmr16 MPTPR 0x2800 ############################################### ######### bank11_init ######################### ############################################### # addr = 0x01f00000 #q001->mem_regs[11].memc_br = writemmr32 BR11 0x01f00021 addr+0x21; #q001-> mem_regs[11].memc_or writemmr32 OR11 0xffff0000 = 0xffff0000; ############################################### ######### upmb_init ######################### ############################################### # config_adr = (volatile char *)0x14608000; # q001->mem_regs[4].memc_or = writemmr32 OR4 0xffff8106 # q001->mem_regs[4].memc_br writemmr32 BR4 0x146088a1 0xffff8106; = 0x146088a1; 13 Software Flow, Register Settings, and Configuration Code ###### Program the READ SINGLE routine ######## # q001->memc_mbmr = 0x10010000; writemmr32 MBMR 0x10010000 # q001->memc_mdr = 0xffffff00; writemmr32 MDR 0xffffff00 # *config_adr = 0x0 writemem32 0x14608000 0x0 #q001->memc_mdr = 0x0ffcff00; writemmr32 MDR 0x0ffcff00 #*config_adr = 0x0ffcff00; writemem32 0x14608000 0x0 #q001->memc_mdr = 0x0ffc3f00; writemmr32 MDR 0x0ffc3f00 #*config_adr = 0x0ffc3f00; writemem32 0x14608000 0x0ffc3f00 #q001->memc_mdr = 0x0ffcff04; writemmr32 MDR 0x0ffcff04 #*config_adr = 0x0ffcff04; writemem32 0x14608000 0x0ffcff04 #q001->memc_mdr = 0x0fffff00; writemmr32 MDR 0x0fffff00 #*config_adr = 0x0fffff00; writemem32 0x14608000 0x0fffff00 #q001->memc_mdr = 0x0fffff01; writemmr32 MDR 0x0fffff01 #*config_adr = 0x0fffff01; writemem32 0x14608000 0x0fffff01 #temp_data #temp_adr= #*temp_adr writemem32 = 0x10005418; (int *)0x14710174; = temp_data; 0x14710174 0x10005418 ###### Program the WRITE SINGLE routine ######## #q001->memc_mdr = 0x0fffff00; writemmr32 MDR 0x0fffff00 #*config_adr = 0x0fffff00; writemem32 0x14608000 0x0fffff00 #q001->memc_mdr = 0x0ff3ff00; writemmr32 MDR 0x0ff3ff00 #choke 14 Software Flow, Register Settings, and Configuration Code #*config_adr = 0x0ff3ff00; writemem32 0x14608000 0x0ff3ff00 #q001->memc_mdr = 0x0ff3ff80; writemmr32 MDR 0x0ff3ff80 #*config_adr = 0x0ff3ff80; writemem32 0x14608000 0x0ff3ff80 #q001->memc_mdr = 0x0ff3ff00; writemmr32 MDR 0x0ff3ff00 #*config_adr = 0x0ff3ff00; writemem32 0x14608000 0x0ff3ff00 #q001->memc_mdr = 0x0fffff00; writemmr32 MDR 0x0fffff00 #*config_adr = 0x0fffff00; writemem32 0x14608000 0x0fffff00 #q001->memc_mdr = 0xffffff05; writemmr32 MDR 0xffffff05 #*config_adr = 0xffffff05; writemem32 0x14608000 0xffffff05 ### MBMR #q001->memc_mbmr = 0x0000003c; writemmr32 MBMR 0x0000003c #*config_adr = 0x0000003c; writemem32 0x14608000 0x0000003c ############################################### ############### UPMC Init ##################### ############################################### #config_adr = 0x02000000 #q001->mem_regs[10].memc_br = writemmr32 BR10 0x020000c1 addr+0xc1; #q001-> mem_regs[10].memc_or writemmr32 OR10 0xfff80000 = 0xfff80000 ###### Program the READ SINGLE routine ######## #q001->memc_mcmr = 0x90051240; writemmr32 MCMR 0x90051240 #q001->memc_mdr = 0x00030040; writemmr32 MDR 0x00030040 #*config_adr = 0x0; writemem32 0x02000000 0x0 15 Software Flow, Register Settings, and Configuration Code #q001->memc_mdr = 0x00030040; writemmr32 MDR 0x00030040 #*config_adr = 0x0; writemem32 0x02000000 0x0 #q001->memc_mdr = 0x00030045; writemmr32 MDR 0x00030045 #*config_adr = 0x0; writemem32 0x02000000 0x0 ###### Program the READ Burst routine ######## #q001->memc_mcmr = 0x90051248; writemmr32 MCMR 0x90051248 #q001->memc_mdr = 0x00030c48; writemmr32 MDR 0x00030c48 #*config_adr = 0x0; writemem32 0x02000000 0x0 #q001->memc_mdr = 0x00030c4c; writemmr32 MDR 0x00030c4c #*config_adr = 0x0; writemem32 0x02000000 0x0 #q001->memc_mdr = 0x00030c4c; writemmr32 MDR 0x00030c4c #*config_adr = 0x0; writemem32 0x02000000 0x0 #q001->memc_mdr = 0x00030044; writemmr32 MDR 0x00030044 #*config_adr = 0x0; writemem32 0x02000000 0x0 #q001->memc_mdr = 0x00030045; writemmr32 MDR 0x00030045 #*config_adr = 0x0; writemem32 0x02000000 0x0 ##### Program the WRITE SINGLE routine ######## #q001->memc_mcmr = 0x90051258; writemmr32 MCMR 0x90051258 #q001->memc_mdr = 0x00000040; writemmr32 MDR 0x00000040 #*config_adr = 0x0; writemem32 0x02000000 0x0 16 Software Flow, Register Settings, and Configuration Code #q001->memc_mdr = 0x00000040; writemmr32 MDR 0x00000040 #*config_adr = 0x0; writemem32 0x02000000 0x0 #q001->memc_mdr = 0x00000045; writemmr32 MDR 0x00000045 #*config_adr = 0x0; writemem32 0x02000000 0x0 ###### Program the WRITE a Burst routine ###### #q001->memc_mcmr = 0x90051260; writemmr32 MCMR 0x90051260 #q001->memc_mdr = 0x00000c48; writemmr32 MDR 0x00000c48 #*config_adr = 0x0; writemem32 0x02000000 0x0 #q001->memc_mdr = 0x00000c4c; writemmr32 MDR 0x00000c4c #*config_adr = 0x0; writemem32 0x02000000 0x0 #q001->memc_mdr = 0x00000c4c; writemmr32 MDR 0x00000c4c #*config_adr = 0x0; writemem32 0x02000000 0x0 #q001->memc_mdr = 0x00000044; writemmr32 MDR 0x00000044 #*config_adr = 0x0; writemem32 0x02000000 0x0 #q001->memc_mdr = 0x00000045; writemmr32 MDR 0x00000045 #*config_adr = 0x0; writemem32 0x02000000 0x0 ###### Exception ###### #q001->memc_mcmr = 0x9005127c; writemmr32 MCMR 0x9005127c #q001->memc_mdr = 0xff000001; writemmr32 MDR 0xff000001 #*config_adr = 0x0; writemem32 0x02000000 0x0 17 Software Flow, Register Settings, and Configuration Code ###### Normal operation ###### #q001->memc_mcmr = 0x80011240; writemmr32 MCMR 0x80011240 18 Software Flow, Register Settings, and Configuration Code NOTES: 19 HOW TO REACH US: Information in this document is provided solely to enable system and software implementers to use USA/EUROPE/LOCATIONS NOT LISTED: Motorola products. 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