MSC8101 SC140 HDI16 MSC8101/D MSC8101UG/D MSC8101PG/D MSC8101RM/D MNSC140CORE/D - Datasheet Archive

 

Technical Data MSC8101 Rev. 18, 8/2005 MSC8101 Network Digital Signal Processor SIU MII · TDMs { ·· Serial

 

Freescale Semiconductor Technical Data MSC8101 MSC8101 Rev. 18, 8/2005 MSC8101 MSC8101 Network Digital Signal Processor SIU MII · TDMs { ·· Serial Interface and TSA UTOPIA Interface MCC / UART / HDLC / Transparent / Ethernet / Fast Ethernet / ATM / SCC CPM 3 × FCC 2 × MCC 64-bit System Bus Interrupt Controller MEMC Timers PIT System Protection Reset Control Clock Control Parallel I/O 4 × SCC 2 × SMC DMA Engine Baud Rate Generators Dual Ported RAM SIC_EXT Interrupts Bridge SPI RISC SIC 2 × SDMA I2C 64/32-bit System Bus The Freescale MSC8101 MSC8101 16-bit DSP is the first member of the family of DSPs based on the StarCore SC140 SC140 DSP core. The MSC8101 MSC8101 is available in three core speed levels: 250, 275, and 300 MHz. 64-bit Local Bus Other Peripherals Extended Core Address Register File Program Sequencer Data ALU Register File Q2PPC Bridge 128-bit QBus PIC Interrupts EFCOP Boot ROM HDI16 HDI16 SC140 SC140 Core Address ALU JTAG EOnCETM Power Management Data ALU What's New? MEMC SRAM 512 KB Clock/PLL L1 Interface 128-bit P-Bus 64-bit XA Data Bus 64-bit XB Data Bus 8/16-bit Host Interface Rev. 18 includes the following changes: · The features list on page iii updates the package description. · Table 2-3 updates junctionto-case value. · Section 3.1 adds a note to include the lead-free packaging. · Ordering Information on the back cover adds the leadfree part numbers. Figure 1. MSC8101 MSC8101 Block Diagram The Freescale MSC8101 MSC8101 DSP is a very versatile device that integrates the high-performance SC140 SC140 four-ALU (arithmetic logic unit) DSP core along with 512 KB of internal memory, a communications processor module (CPM), a 64-bit bus, a very flexible System Integration Unit (SIU), and a 16-channel DMA engine on a single device. With its four-ALU core, the MSC8101 MSC8101 can execute up to four multiply-accumulate (MAC) operations in a single clock cycle. The MSC8101 MSC8101 CPM is a 32bit RISC-based communications protocol engine that can network to time-division multiplexed (TDM) highways, Ethernet, and asynchronous transfer mode (ATM) backbones. The MSC8101 MSC8101 60x-compatible bus interface facilitates its connection to multi-master system architectures. The very large internal memory, 512 KB, reduces the need for external program and data memories. The MSC8101 MSC8101 offers 1500 DSP MMACS (1200 core and 300 EFCOP) performance using an internal 300 MHz clock with a 1.6 V core and independent 3.3 V input/output (I/O). © Freescale Semiconductor, Inc., 2001, 2005. All rights reserved. Table of Contents MSC8101 MSC8101 Features . iii Target Applications .iv Product Documentation .iv Chapter 1 Signals/Connections 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Chapter 2 Physical and Electrical Specifications 2.1 2.2 2.3 2.4 2.5 2.6 Chapter 3 Absolute Maximum Ratings . 2-1 Recommended Operating Conditions . 2-2 Thermal Characteristics . 2-2 DC Electrical Characteristics. 2-3 Clock Configuration. 2-4 AC Timings. 2-7 Packaging 3.1 3.2 Chapter 4 Power Signals. 1-4 Clock Signals . 1-4 Reset, Configuration, and EOnCE Event Signals . 1-5 System Bus, HDI16 HDI16, and Interrupt Signals. 1-6 Memory Controller Signals . 1-13 CPM Ports. 1-15 JTAG Test Access Port Signals. 1-36 Reserved Signals. 1-36 FC-PBGA Package Description. 3-1 Lidded FC-PBGA Package Mechanical Drawing . 3-31 Design Considerations 4.1 4.2 4.3 4.4 Thermal Design Considerations. 4-1 Electrical Design Considerations. 4-1 Power Considerations . 4-2 Layout Practices. 4-3 Ordering and Contact Information . Back Cover Data Sheet Conventions pin and pinout Although the device package does not have pins, the term pins and pin-out are used for convenience and indicate specific signal locations within the ball-grid array. OVERBAR Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) "asserted" Means that a high true (active high) signal is high or that a low true (active low) signal is low "deasserted" Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. MSC8101 MSC8101 Technical Data, Rev. 18 ii Freescale Semiconductor MSC8101 MSC8101 Features · · · · · · · · · · · · SC140 SC140 core - Architecture optimized for efficient C/C+ code compilation - Four 16-bit ALUs and two 32-bit AGUs - 1200 DSP MMACS running at 300 MHz - Very low power dissipation - Variable-length execution set (VLES) execution model - JTAG/Enhanced OnCE debug port Communications processor module (CPM) - Programmable protocol machine using a 32-bit RISC engine - 155 Mbps ATM interface (including AAL 0/1/2/5) - 10/100 Mbit Ethernet interface - Up to four E1/T1 interfaces or one E3/T3 interface and one E1/T1 interface - HDLC support up to T3 rates, or 256 channels 64- or 32-bit wide bus interface - Support for bursts for high efficiency - Glueless interface to 60x-compatible bus systems - Multi-master support Enhanced filter coprocessor (EFCOP) - Independently and concurrently executes long filters (such as echo cancellation) - Runs at 250/275/300 MHz and provides 250/275/300 MMACS performance Programmable memory controller - Control for up to eight banks of external memory - User-programmable machines (UPM) allowing glueless interface to various memory types (SRAM, DRAM, EPROM, and Flash memory) and other user-definable peripherals - Dedicated pipelined SDRAM memory interface Large internal SRAM - 256K 16-bit words (512 KB) - Unified program and data space configurable by the application - Word and byte addressable DMA controller - 16 DMA channels, FIFO based, with burst capabilities - Sophisticated addressing capabilities Small foot print package - 17 mm × 17 mm lidded FC-PBGA lead-bearing or lead-free package Very low power consumption - Separate power supply for internal logic (1.6 V) and for I/O (3.3 V) Enhanced 16-bit parallel host interface (HDI16 HDI16) - Supports a variety of microcontroller, microprocessor, and DSP bus interfaces Phase-lock loops (PLLs) - System PLL - CPM DPLLs (SCC and SCM) Process technology - 0.13 micron copper interconnect process technology MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor iii Target Applications The MSC8101 MSC8101 targets applications requiring very high performance, very large amounts of internal memory, and such networking capabilities as: · · · · Third-generation wideband wireless infrastructure systems Packet Telephony systems Multi-channel modem banks Multi-channel xDSL Product Documentation The documents listed in Table 1 are required for a complete description of the MSC8101 MSC8101 and are necessary to design properly with the part. Documentation is available from the following sources (see back cover for details): · · · · A local Freescale distributor A Freescale Semiconductor sales office A Freescale Semiconductor Literature Distribution Center The world wide web (WWW) Table 1. MSC8101 MSC8101 Documentation Name Description Order Number MSC8101 MSC8101 Technical Data MSC8101 MSC8101 features list and physical, electrical, timing, and package specifications MSC8101/D MSC8101/D MSC8101 MSC8101 User's Guide Detailed functional description of the MSC8101 MSC8101 memory configuration, operation, and register programming MSC8101UG/D MSC8101UG/D MSC8101 MSC8101 Pocket Guide Quick reference information for application development. MSC8101PG/D MSC8101PG/D MSC8101 MSC8101 Reference Manual Detailed description of the MSC8101 MSC8101 processor core and instruction set MSC8101RM/D MSC8101RM/D SC140 SC140 DSP Core Reference Manual Detailed description of the SC140 SC140 family processor core and instruction set MNSC140CORE/D MNSC140CORE/D Application Notes Documents describing specific applications or optimized device operation including code examples See the MSC8101 MSC8101 product website MSC8101 MSC8101 Technical Data, Rev. 18 iv Freescale Semiconductor 1 Signals/Connections The MSC8101 MSC8101 external signals are organized into functional groups, as shown in Table 1-1, Figure 1-1, and Figure 1-2. Table 1-1 lists the functional groups, states the number of signal connections in each group, and references the table that gives details on multiplexed signals within each group. Figure 1-1 shows MSC8101 MSC8101 external signals organized by function. Figure 1-2 indicates how the parallel input/output (I/O) ports signals are multiplexed. Because the parallel I/O design supported by the MSC8101 MSC8101 communications processor module (CPM) is a subset of the parallel I/O signals supported by the MPC8260 MPC8260 device, port pins are not numbered sequentially. Table 1-1. MSC8101 MSC8101 Functional Signal Groupings Number of Signal Connections Detailed Description Power (VCC, VDD, and GND) 80 Table 1-2 on page 1-4 Clock 6 Table 1-3 on page 1-4 Reset, configuration, and EOnCE 11 Table 1-4 on page 1-5 System bus, HDI16 HDI16, and interrupts 133 Table 1-5 on page 1-7 Memory Controller 27 Table 1-6 on page 1-13 Port A 26 Table 1-7 on page 1-16 Port B 14 Table 1-8 on page 1-21 Port C 18 Table 1-9 on page 1-24 Port D 8 Table 1-10 on page 1-33 JTAG Test Access Port 5 Table 1-11 on page 1-36 Reserved (denotes connections that are always reserved) 5 Table 1-12 on page 1-36 Functional Group CPM Input/Output Parallel Ports MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-1 Signals/Connections GND GNDSYN GNDSYN1 37 1 1 14 25 1 1 Port A PA[31­6] For the signals multiplexed on Ports A­D, see Figure 1-2 26 Port B PB[31­18] 14 Port C PC[31­22, 15­12, 7­4] 18 Port D PD[31­29, 19­16, 7] TMS TDI TCK TRST TDO EOnCE Event EED EE0 EE1 EE[2­3] EE[4­5] 8 1 1 1 1 1 16 4 1 C P M I / O P O R T S 6 0 x B U S J T A G RESET Configuration DBREQ HPE BTM[0­1] PORESET RSTCONF HRESET SRESET 1 1 1 2 2 1 1 1 1 D[32­47] D[48­51] D52 1 1 D53 D54 1 1 1 1 1 1 4 Reserved DP0 Reserved IRQ1 DP1 IRQ1 EXT_BG2 1 1 1 1 1 1 1 1 1 1 1 1 P O W E R 1 32 5 4 1 1 3 1 1 1 1 1 1 1 1 32 1 VDD VDDH VCCSYN VCCSYN1 DP2 DP3 DP4 DP5 DP6 DP7 Reserved Reserved DREQ3 DREQ4 DACK3 DACK4 EXT_DBG2 EXT_BR3 EXT_BG3 EXT_DBG3 IRQ6 IRQ7 PSDRAS PBS[0­7] PGPL0 PGPL1 PGPL2 PGPL3 PGPL4 PGPL5 A[0­31] TT[0­4] TSIZ[0­3] TBST IRQ1 Reserved BR BG ABB TS AACK ARTRY DBG DBB D[0­31] D55 D56 D57 D58 D59 D60 D[61­63] IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 TA TEA NMI NMI_OUT PSDVAL IRQ7 CLKIN TC[0­2] 8 1 MODCK[1­3] 3 2 1 1 8 1 1 1 1 1 1 TEST THERM[1­2] SPARE1, SPARE5 Note: IRQ2 IRQ3 HDI16 HDI16 Signals HD[0­15] HA[0­3] HCS1 Single DS Double DS HRW HRD/HRD HDS/HDS HWR/HWR Single HR Double HR HREQ/HREQ HTRQ/HTRQ HACK/HACK HRRQ/HRRQ HDSP HDDS H8BIT HCS2 Reserved EXT_Br2 INT_OUT BADDR[27­28] 1 1 IRQ[2­3, 5] CS[0­7] BCTL1 CLKOUT DLLIN BNKSEL[0­2] 1 GBL BADDR[29­31] 1 2 2 M E M C ALE BCTL0 PWE[0­7] PSDA10 PSDA10 PSDWE POE PSDCAS PGTA PSDAMUX PSDDQM[0­7] PUPMWAIT PPBS Refer to the System Interface Unit (SIU) chapter in the MSC8101 MSC8101 Reference Manual for details on how to configure these pins. Figure 1-1. MSC8101 MSC8101 External Signals MSC8101 MSC8101 Technical Data, Rev. 18 1-2 Freescale Semiconductor FCC1 ATM/UTOPIA MPHY MPHY Master Master mux poll dir. poll or Slave FCC1 HDLC/ Ethernet transp. HDLC MII Serial Nibble COL TXENB TXCLAV TXCLAV0 CRS RTS TXSOC (master) TX_ER RXENB TX_EN RXSOC RX_DV (slave) RXCLAV RXCLAV0 TXD0 TXD1 TXD2 TXD3 TXD4 TXD5 TXD6 TXD7 RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 GPIO PA31 PA30 PA29 PA28 PA27 RX_ER TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 SDMA MSNUM0 MSNUM1 TXD3 TXD2 TXD1 TXD0 RXD0 RXD1 RXD2 RXD3 TXD RXD SMC2 SMTXD SMRXD FCC2 HDLC/ Ethernet transp. HDLC MII Serial Nibble TX_ER RX_DV TX_EN RX_ER RTS SMSYN CRS TXD3 TXD2 L1TSYNC SI2 PA7 L1RSYNC SCC2 RXD TXD TDMB2 L1TXD L1RXD L1RSYNC L1TSYNC TDMC2 L1TXD L1RXD L1TSYNC L1RSYNC TDMD2 L1TXD L1RXD L1TSYNC L1RSYNC PA6 PB31 PB30 PB29 PB28 RTS/TENA TXD3 TXD2 L1RXD2 TXD0 RXD0 RXD1 RXD2 RXD3 TXD RXD L1TXD3 L1RXD3 TXD1 TXD1 MSNUM2 MSNUM3 MSNUM4 MSNUM5 SI1 TDMA1 Serial Nibble L1TXD L1TXD0 L1RXD L1RXD0 COL TXD0 RXD0 RXD1 RXD2 RXD3 L1RXD1 L1TXD2 L1TXD1 PB27 PB26 PB25 PB24 PB23 I2C SDA SCL Ext. Req. EXT1 SCC1 CTS/CLSN Ext. Req. DREQ2 EXT2 SCC1 CTS/CLSN CD/RENA FCC1 CLK7 TIN4 PC25 CLK8 TIN3/ TOUT4 PC24 BRG8O LIST2 LIST4 LIST3 CTS PC29 BRG7O SMTXD CTS/CLSN CD/RENA TIN2 BRG5O BRG6O DACK1 DREQ1 LIST1 CLK3 TIN1/ CLK4 PC28 TOUT2 CLK5 TGATE2 PC27 CLK6 TOUT3 PC26 SIU Timer Input BRG4O CLK5 TMCLK DMA DACK2 CLK9 CLK10 CLK10 PC23 PC22 PC15 PC14 PC13 PC12 LIST1 SMC1 SMTXD SMRXD RXD TXD RTS/TENA PC7 LIST2 CD FCC2 CTS CD RXADDR3 RXCLAV2 TXADDR4 TXCLAV3 RXADDR4 RXCLAV3 RXPRTY TXPRTY TXADDR3 TXCLAV2 PB22 PB21 PB20 PB19 BRGs Clocks Timers PB18 BRG1O CLK1 TGATE1 PC31 BRG2O CLK2 TOUT1 PC30 BRG3O CTS/CLSN TXADDR0 RXADDR0 TXADDR1 RXADDR1 TXADDR2/ TXADDR2 TXCLAV1 RXADDR2/ RXADDR2 RXCLAV1 PA26 PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PC6 LIST3 LIST4 PC5 PC4 PD31 PD30 PD29 PD19 PD18 PD17 PD16 PD7 DRACK1/DONE1 DRACK2/DONE2 SPI BRG1O SPISEL SPICLK SPIMOSI BRG2O SPIMISO SMSYN Figure 1-2. CPM Port A­D Pin Multiplexed Functionality MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-3 Signals/Connections 1.1 Power Signals Table 1-2. Power and Ground Signal Inputs Power Name Description VDD Internal Logic Power VDD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VDD power rail. VDDH Input/Output Power This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors. VCCSYN System PLL Power VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. VCCSYN1 SC140 SC140 PLL Power VCC dedicated for use with the SC140 SC140 core PLL. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. GND System Ground An isolated ground for the internal processing logic. This connection must be tied externally to all chip ground connections, except GNDSYN and GNDSYN1. The user must provide adequate external decoupling capacitors. GNDSYN System PLL Ground Ground dedicated for system PLL use. The connection should be provided with an extremely low-impedance path to ground. GNDSYN1 SC140 SC140 PLL Ground 1 Ground dedicated for SC140 SC140 core PLL use. The connection should be provided with an extremely low-impedance path to ground. 1.2 Clock Signals Table 1-3. Signal Name Type Clock Signals Signal Description CLKIN Input Clock In Primary clock input to the MSC8101 MSC8101 PLL. MODCK1 Input Clock Mode Input 1 Defines the operating mode of internal clock circuits. TC0 Output Transfer Code 0 Supplies information that can be useful for debugging bus transactions initiated by the MSC8101 MSC8101. BNKSEL0 Output MODCK2 Input Clock Mode Input 2 Defines the operating mode of internal clock circuits. TC1 Output Transfer Code 1 Supplies information that can be useful for debugging bus transactions initiated by the MSC8101 MSC8101. BNKSEL1 Output MODCK3 Input Clock Mode Input 3 Defines the operating mode of internal clock circuits. TC2 Output Transfer Code 2 Supplies information that can be useful for debugging bus transactions initiated by the MSC8101 MSC8101. BNKSEL2 Output Bank Select 0 Selects the SDRAM bank when the MSC8101 MSC8101 is in 60x-compatible bus mode. Bank Select 1 Selects the SDRAM bank when the MSC8101 MSC8101 is in 60x-compatible bus mode. Bank Select 2 Selects the SDRAM bank when the MSC8101 MSC8101 is in 60x-compatible bus mode. MSC8101 MSC8101 Technical Data, Rev. 18 1-4 Freescale Semiconductor Reset, Configuration, and EOnCE Event Signals Table 1-3. Signal Name Clock Signals (Continued) Type Signal Description CLKOUT Output Clock Out The system bus clock. DLLIN Input DLLIN Synchronizes with an external device. Note: When the DLL is disabled, connect this signal to GND. 1.3 Reset, Configuration, and EOnCE Event Signals Table 1-4. Signal Name DBREQ Type Input EE01 Signal Description Debug Request Determines whether to go into SC140 SC140 Debug mode when PORESET is deasserted. Enhanced OnCE (EOnCE) Event 0 After PORESET is deasserted, you can configure EE0 as an input (default) or an output. Input Output HPE Reset, Configuration, and EOnCE Event Signals Input EE11 Debug request, enable Address Event Detection Channel 0, or generate an EOnCE event. Detection by Address Event Detection Channel 0. Used to trigger external debugging equipment. Host Port Enable When this pin is asserted during PORESET, the Host port is enabled, the system data bus is 32 bits wide, and the Host must program the reset configuration word. EOnCE Event 1 After PORESET is deasserted, you can configure EE1 as an input (default) or an output. Input Output EE21 Enable Address Event Detection Channel 1 or generate an EOnCE event. Debug Acknowledge or detection by Address Event Detection Channel 1. Used to trigger external debugging equipment. EOnCE Event 2 After PORESET is deasserted, you can configure EE2 as an input (default) or an output. Input Output EE31 Enable Address Event Detection Channel 2 or generate an EOnCE event or enable the Event Counter. Detection by Address Event Detection Channel 2. Used to trigger external debugging equipment. EOnCE Event 3 After PORESET is deasserted, you can configure EE3 as an input (default) or an output. See the emulation and debug chapter in the SC140 SC140 DSP Core Reference Manual for details on the ERCV Register. Input Output Enable Address Event Detection Channel 3 or generate one of the EOnCE events. The DSP has read the EOnCE Receive Register (ERCV). Triggers external debugging equipment. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-5 Signals/Connections Table 1-4. Signal Name Reset, Configuration, and EOnCE Event Signals (Continued) Signal Description Input BTM[0­1] Type Boot Mode 0­1 Determines the MSC8101 MSC8101 boot mode when PORESET is deasserted. See the emulation and debug chapter in the SC140 SC140 DSP Core Reference Manual for details on how to set these pins. EE41 EOnCE Event 4 After PORESET is deasserted, you can configure EE4 as an input (default) or an output. See the emulation and debug chapter in the SC140 SC140 DSP Core Reference Manual for details on the ETRSMT Register. Input Output EE51 Enable Address Event Detection Channel 4 or generate an EOnCE event. The DSP wrote the EOnCE Transmit Register (ETRSMT). Triggers external debugging equipment. EOnCE Event 5 After PORESET is deasserted, you can configure EE5 as an input (default) or an output. Input Output EED1 Enable Address Event Detection Channel 5. Detection by Address Event Detection Channel 5. Triggers external debugging equipment. Enhanced OnCE (EOnCE) Event Detection After PORESET is deasserted, you can configure EED as an input (default) or output: Input Output Enable the Data Event Detection Channel. Detection by the Data Event Detection Channel. Triggers external debugging equipment. PORESET Input Power-On Reset When asserted, this line causes the MSC8101 MSC8101 to enter power-on reset state. RSTCONF Input Reset Configuration Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in the "Power-On Reset Flow" and "Hardware Reset Configuration" sections of the MSC8101 MSC8101 Reference Manual. HRESET Input Hard Reset When asserted, this open-drain line causes the MSC8101 MSC8101 to enter the hard reset state. SRESET Input Soft Reset When asserted, this open-drain line causes the MSC8101 MSC8101 to enter the soft reset state. Note: See the emulation and debug chapter in the SC140 SC140 DSP Core Reference Manual for details on how to configure these pins. 1.4 System Bus, HDI16 HDI16, and Interrupt Signals The system bus, HDI16 HDI16, and interrupt signals are grouped together because they use a common set of signal lines. Individual assignment of a signal to a specific signal line is configured through registers in the System Interface Unit (SIU) and the Host Interface (HDI16 HDI16). 1-5 describes the signals in this group. Note: To boot from the host interface, the HDI16 HDI16 must be enabled by pulling up the HPE signal line during PORESET. The configuration word must then be loaded from the host. The configuration word must set the Internal Space Port Size bit in the Bus Control Register (BCR[ISPS]) to change the system data bus width from 64 bits to 32 bits and reassign the upper 32 bits to their HDI16 HDI16 functions. Never set the Host Port Enable (HEN) bit in the Host Port Control Register (HPCR) to enable the HDI16 HDI16, unless the bus size is first changed from 64 bits to 32 bits. Otherwise, unpredictable operation may occur. MSC8101 MSC8101 Technical Data, Rev. 18 1-6 Freescale Semiconductor System Bus, HDI16 HDI16, and Interrupt Signals Although there are eight interrupt request (IRQ) connections to the core processor, there are multiple external lines that can connect to these internal signal lines. After reset, the default configuration includes two IRQ1 and two IRQ7 input lines. The designer must select one line for each required interrupt and reconfigure the other external signal line or lines for alternate functions. Table 1-5. Signal System Bus, HDI16 HDI16, and Interrupt Signals Data Flow Description A[0­31] Input/Output Address Bus When the MSC8101 MSC8101 is in external master bus mode, these pins function as the address bus. The MSC8101 MSC8101 drives the address of its internal bus masters and responds to addresses generated by external bus masters. When the MSC8101 MSC8101 is in Internal Master Bus mode, these pins are used as address lines connected to memory devices and are controlled by the MSC8101 MSC8101 memory controller. TT[0­4] Input/Output Bus Transfer Type The bus master drives these pins during the address tenure to specify the type of transaction. TSIZ[0­3] Input/Output Transfer Size The bus master drives these pins with a value indicating the number of bytes transferred in the current transaction. TBST Input/Output Bus Transfer Burst The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers four quad words). IRQ1 Input Interrupt Request 11 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. GBL Input/Output Global1 When a master within the chip initiates a bus transaction, it drives this pin. When an external master initiates a bus transaction, it should drive this pin. Assertion of this pin indicates that the transfer is global and it should be snooped by caches in the system. Reserved Output The primary configuration is reserved. BADDR29 BADDR29 Output Burst Address 291 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8101 MSC8101 memory controller. IRQ2 Input Interrupt Request 21 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. Reserved Output The primary configuration is reserved. BADDR30 BADDR30 Output Burst Address 301 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8101 MSC8101 memory controller. IRQ3 Input Interrupt Request 31 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. Reserved Output The primary configuration is reserved. BADDR31 BADDR31 Output Burst Address 311 One of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8101 MSC8101 memory controller. IRQ5 Input Interrupt Request 51 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-7 Signals/Connections Table 1-5. Signal Data Flow System Bus, HDI16 HDI16, and Interrupt Signals (Continued) Description Input/Output Output Bus Request2 An output when an external arbiter is used. The MSC8101 MSC8101 asserts this pin to request ownership of the bus. Input An input when an internal arbiter is used. An external master should assert this pin to request bus ownership from the internal arbiter. Input/Output Output Bus Grant2 An output when an internal arbiter is used. The MSC8101 MSC8101 asserts this pin to grant bus ownership to an external bus master. Input An input when an external arbiter is used. The external arbiter should assert this pin to grant bus ownership to the MSC8101 MSC8101. Input/Output Output Address Bus Busy1 The MSC8101 MSC8101 asserts this pin for the duration of the address bus tenure. Following an address acknowledge (AACK) signal, which terminates the address bus tenure, the MSC8101 MSC8101 deasserts ABB for a fraction of a bus cycle and then stops driving this pin. Input The MSC8101 MSC8101 does not assume bus ownership while it this pin is asserted by an external bus master. IRQ2 Input Interrupt Request 21 One of the eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. TS Input/Output Bus Transfer Start Signals the beginning of a new address bus tenure. The MSC8101 MSC8101 asserts this signal when one of its internal bus masters (SC140 SC140 core or DMA controller) begins an address tenure. When the MSC8101 MSC8101 senses this pin being asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled, access internal MSC8101 MSC8101 resources, memory controller support). AACK Input/Output Address Acknowledge A bus slave asserts this signal to indicate that it identified the address tenure. Assertion of this signal terminates the address tenure. ARTRY Input Address Retry Assertion of this signal indicates that the bus transaction should be retried by the bus master. The MSC8101 MSC8101 asserts this signal to enforce data coherency with its internal cache and to prevent deadlock situations. DBG Input/Output Output Data Bus Grant2 An output when an internal arbiter is used. The MSC8101 MSC8101 asserts this pin as an output to grant data bus ownership to an external bus master. Input An input when an external arbiter is used. The external arbiter should assert this pin as an input to grant data bus ownership to the MSC8101 MSC8101. Input/Output Output Data Bus Busy1 The MSC8101 MSC8101 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the MSC8101 MSC8101 deasserts DBB for a fraction of a bus cycle and then stops driving this pin. Input The MSC8101 MSC8101 does not assume data bus ownership while DBB is asserted by an external bus master. IRQ3 Input Interrupt Request 31 One of the eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. D[0­31] Input/Output Data Bus Most Significant Word In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. In Host Port Disabled mode, these 32 bits are part of the 64-bit data bus. In Host Port Enabled mode, these bits are used as the bus in 32-bit mode. BR BG ABB DBB MSC8101 MSC8101 Technical Data, Rev. 18 1-8 Freescale Semiconductor System Bus, HDI16 HDI16, and Interrupt Signals Table 1-5. Signal Data Flow System Bus, HDI16 HDI16, and Interrupt Signals (Continued) Description D[32­47] Input/Output Data Bus Bits 32­47 In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. HD[0­15] Input/Output Host Data2 When the HDI16 HDI16 interface is enabled, these signals are lines 0-15 of the bidirectional tri-state data bus. D[48­51] Input/Output Data Bus Bits 48­51 In write transactions the bus master drives the valid data on these pins. In read transactions the slave drives the valid data on these pins. HA[0­3] Input Host Address Line 0­33 When the HDI16 HDI16 interface bus is enabled, these lines address internal host registers. D52 Input/Output Data Bus Bit 52 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HCS1 Input Host Chip Select3 When the HDI16 HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 HDI16 chip select is a logical OR of HCS1 and HCS2. D53 Input/Output Data Bus Bit 53 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HRW Input Host Read Write Select3 When the HDI16 HDI16 interface is enabled in Single Strobe mode, this is the read/write input (HRW). HRD/HRD Input Host Read Strobe3 When the HDI16 HDI16 is programmed to interface with a double data strobe host bus, this pin is the read data strobe Schmitt trigger input (HRD/HRD). The polarity of the data strobe is programmable. D54 Input/Output Data Bus Bit 54 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HDS/HDS Input Host Data Strobe3 When the HDI16 HDI16 is programmed to interface with a single data strobe host bus, this pin is the data strobe Schmitt trigger input (HDS/HDS). The polarity of the data strobe is programmable. HWR/HWR Input Host Write Data Strobe3 When the HDI16 HDI16 is programmed to interface with a double data strobe host bus, this pin is the write data strobe Schmitt trigger input (HWR/HWR). The polarity of the data strobe is programmable. D55 Input/Output Data Bus Bit 55 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HREQ/HREQ Output Host Request3 When the HDI16 HDI16 is programmed to interface with a single host request host bus, this pin is the host request output (HREQ/HREQ). The polarity of the host request is programmable. The host request may be programmed as a driven or open-drain output. HTRQ/HTRQ Output Transmit Host Request3 When the HDI16 HDI16 is programmed to interface with a double host request host bus, this pin is the transmit host request output (HTRQ/HTRQ). The signal can be programmed as driven or open drain. The polarity of the host request is programmable. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-9 Signals/Connections Table 1-5. Signal System Bus, HDI16 HDI16, and Interrupt Signals (Continued) Data Flow Description D56 Input/Output Data Bus Bit 56 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HACK/HACK Output Host Acknowledge3 When the HDI16 HDI16 is programmed to interface with a single host request host bus, this pin is the host acknowledge Schmitt trigger input (HACK). The polarity of the host acknowledge is programmable. HRRQ/HRRQ Output Receive Host Request3 When the HDI16 HDI16 is programmed to interface with a double host request host bus, this pin is the receive host request output (HRRQ/HRRQ). The signal can be programmed as driven or open drain. The polarity of the host request is programmable. D57 Input/Output Data Bus Bit 57 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HDSP Input Host Data Strobe Polarity3 When the HDI16 HDI16 interface is enabled, this pin is the host data strobe polarity (HDSP). D58 Input/Output Data Bus Bit 58 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HDDS Input Host Dual Data Strobe3 When the HDI16 HDI16 interface is enabled, this pin is the host dual data strobe (HDDS). D59 Input/Output Data Bus Bit 59 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. H8BIT Input H8BIT3 When the HDI16 HDI16 interface is enabled, this bit determines if the interface is in 8-bit or 16-bit mode. D60 Input/Output Data Bus Bit 60 In write transactions the bus master drives the valid data on this pin. In read transactions the slave drives the valid data on this pin. HCS2 Input Host Chip Select 3 When the HDI16 HDI16 interface is enabled, this is one of the two chip-select pins. The HDI16 HDI16 chip select is a logical OR of HCS1 and HCS2. D[61­63] Input/Output Data Bus Bits 61­63 Used only in 60x-mode-only mode. In write transactions the bus master drives the valid data on this bus. In read transactions the slave drives the valid data on this bus. These dedicated signals are reserved when the HDI16 HDI16 is enabled.3 Reserved Reserved Input The primary configuration is reserved. DP0 Input/Output Data Parity 01 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity zero pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and D[0­7]. EXT_BR2 Input External Bus Request 21,2 An external master asserts this pin to request bus ownership from the internal arbiter. MSC8101 MSC8101 Technical Data, Rev. 18 1-10 Freescale Semiconductor System Bus, HDI16 HDI16, and Interrupt Signals Table 1-5. Signal Data Flow System Bus, HDI16 HDI16, and Interrupt Signals (Continued) Description IRQ1 Input Interrupt Request 11 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. DP1 Input/Output Data Parity 11 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity one pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and D[8­15]. EXT_BG2 Output External Bus Grant 21,2 The MSC8101 MSC8101 asserts this pin to grant bus ownership to an external bus master. IRQ2 Input Interrupt Request 21 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. DP2 Input/Output Data Parity 21 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity two pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and D[16­23]. EXT_DBG2 Output External Data Bus Grant 21,2 The MSC8101 MSC8101 asserts this pin to grant data bus ownership to an external bus master. IRQ3 Input Interrupt Request 31 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. DP3 Input/Output Data Parity 31 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity three pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and D[24­31]. EXT_BR3 Input External Bus Request 31,2 An external master asserts this pin to request bus ownership from the internal arbiter. IRQ4 Input Interrupt Request 41 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. DP4 Input/Output Data Parity 41 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity four pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and D[32­39]. DREQ3 Input DMA Request 31 An external peripheral uses this pin to request DMA service. EXT_BG3 Output External Bus Grant 31,2 The MSC8101 MSC8101 asserts this pin to grant bus ownership to an external bus master. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-11 Signals/Connections Table 1-5. Signal Data Flow System Bus, HDI16 HDI16, and Interrupt Signals (Continued) Description IRQ5 Input Interrupt Request 51 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. DP5 Input/Output Data Parity 51 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity five pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and D[40­47]. DREQ4 Input DMA Request 41 An external peripheral uses this pin to request DMA service. EXT_DBG3 Output External Data Bus Grant 31,2 The MSC8101 MSC8101 asserts this pin to grant data bus ownership to an external bus master. IRQ6 Input Interrupt Request 61 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. DP6 Input/Output Data Parity 61 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity six pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and D[48­55]. DACK3 Output DMA Acknowledge 31 The DMA controller drives this output to acknowledge the DMA transaction on the bus. IRQ7 Input Interrupt Request 71 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. DP7 Input/Output Data Parity 71 The master or slave that drives the data bus also drives the data parity signals. The value driven on the data parity seven pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and D[56­63]. DACK4 Output DMA Acknowledge1 The DMA controller drives this output to acknowledge the DMA transaction on the bus. TA Input/Output Transfer Acknowledge Indicates that a data beat is valid on the data bus. For single beat transfers, assertion of TA indicates the termination of the transfer. For burst transfers, TA is asserted four times to indicate the transfer of four data beats with the last assertion indicating the termination of the burst transfer. TEA Input/Output Transfer Error Acknowledge Indicates a bus error. masters within the MSC8101 MSC8101 monitor the state of this pin. The MSC8101 MSC8101 internal bus monitor can assert this pin if it identifies a bus transfer that is hung. NMI Input Non-Maskable Interrupt When an external device asserts this line, the MSC8101 MSC8101 NMI input is asserted. NMI_OUT Output Non-Maskable Interrupt Driven from the MSC8101 MSC8101 internal interrupt controller. Assertion of this output indicates that a non-maskable interrupt, pending in the MSC8101 MSC8101 internal interrupt controller, is waiting to be handled by an external host. PSDVAL Input/Output Data Valid Indicates that a data beat is valid on the data bus. The difference between the TA pin and PSDVAL is that the TA pin is asserted to indicate data transfer terminations while the PSDVAL signal is asserted with each data beat movement. Thus, when TA is asserted, PSDVAL is asserted, but when PSDVAL is asserted, TA is not necessarily asserted. For example when the SDMA initiates a double word (2x64 bits) transfer to a memory device that has a 32-bit port size, PSDVAL is asserted three times without TA, and finally both pins are asserted to terminate the transfer. MSC8101 MSC8101 Technical Data, Rev. 18 1-12 Freescale Semiconductor Memory Controller Signals Table 1-5. Signal System Bus, HDI16 HDI16, and Interrupt Signals (Continued) Data Flow Description IRQ7 Input Interrupt Request 71 One of eight external lines that can request a service routine, via the internal interrupt controller, from the SC140 SC140 core. INT_OUT Output Interrupt Output1 Driven from the MSC8101 MSC8101 internal interrupt controller. Assertion of this output indicates that an unmasked interrupt is pending in the MSC8101 MSC8101 internal interrupt controller. Notes: 1. 2. 3. See the SIU chapter in the MSC8101 MSC8101 Reference Manual for details on how to configure these pins. When used as the bus control arbiter for the system bus, the MSC8101 MSC8101 can support up to three external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or is not a MSC8101 MSC8101 master device. See the Bus Configuration Register (BCR) description in the SIU chapter in the MSC8101 MSC8101 Reference Manual for details on how to configure these pins. The second and third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG) have a dual function. When the MSC8101 MSC8101 is not the bus arbiter, these signals (BR/BG/DBG) are used by the MSC8101 MSC8101 to obtain master control of the bus. See the host interface (HDI16 HDI16) chapter in the MSC8101 MSC8101 Reference Manual for details on how to configure these pins. 1.5 Memory Controller Signals Refer to the memory controller chapter in the MSC8101 MSC8101 Reference Manual (MSC8101RM/D MSC8101RM/D) for detailed information about configuring these signals. Table 1-6. Signal Data Flow Memory Controller Signals Description CS[0­7] Output Chip Select Enable specific memory devices or peripherals connected to MSC8101 MSC8101 buses. BCTL1 Output Buffer Control 1 Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MSC8101 MSC8101 Reference Manual for details. BADDR[27­28] Output Burst Address 27­28 Two of five outputs of the memory controller. These pins connect directly to memory devices controlled by the MSC8101 MSC8101 memory controller. ALE Output Address Latch Enable Controls the external address latch used in external master bus configuration. BCTL0 Output Buffer Control 0 Controls buffers on the data bus. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. See the System Interface Unit (SIU) chapter in the MSC8101 MSC8101 Reference Manual for details. PWE[0­7] Output Bus Write Enable Outputs of the bus General-Purpose Chip-select Machine (GPCM). These pins select byte lanes for write operations. PSDDQM[0­7] Output Bus SDRAM DQM Outputs of the SDRAM control machine. These pins select specific byte lanes of SDRAM devices. PBS[0­7] Output Bus UPM Byte Select Outputs of the User-Programmable Machine (UPM) in the memory controller. These pins select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-13 Signals/Connections Table 1-6. Signal Memory Controller Signals (Continued) Data Flow Description PSDA10 PSDA10 Output Bus SDRAM A10 Output from the bus SDRAM controller. This pin is part of the address when a row address is driven. It is part of the command when a column address is driven. PGPL0 Output Bus UPM General-Purpose Line 0 One of six general-purpose output lines of the UPM. The values and timing of this pin are programmed in the UPM. PSDWE Output Bus SDRAM Write Enable Output from the bus SDRAM controller. This pin should connect to the SDRAM WE input signal. PGPL1 Output Bus UPM General-Purpose Line 1 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. POE Output Bus Output Enable Output of the bus GPCM. Controls the output buffer of memory devices during read operations. PSDRAS Output Bus SDRAM RAS Output from the bus SDRAM controller. This pin should connect to the SDRAM Row Address Strobe (RAS) input signal. PGPL2 Output Bus UPM General-Purpose Line 2 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. PSDCAS Output Bus SDRAM CAS Output from the bus SDRAM controller. This pin should connect to the SDRAM Column Address Strobe (CAS) input signal. PGPL3 Output Bus UPM General-Purpose Line 3 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. PGTA Input GPCM TA Terminates transactions during GPCM operation. Requires an external pull up resistor for proper operation. PUPMWAIT Input Bus UPM Wait Input to the UPM. An external device can hold this pin high to force the UPM to wait until the device is ready for the operation to continue. PPBS Output Bus Parity Byte Select In systems that store data parity in a separate chip, this output is the byte-select for that chip. PGPL4 Output Bus UPM General-Purpose Line 4 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. PSDAMUX Output Bus SDRAM Address Multiplexer Controls the SDRAM address multiplexer when the MSC8101 MSC8101 is in External Master mode. PGPL5 Output Bus UPM General-Purpose Line 5 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. MSC8101 MSC8101 Technical Data, Rev. 18 1-14 Freescale Semiconductor CPM Ports 1.6 CPM Ports The MSC8101 MSC8101 CPM supports the subset of MPC8260 MPC8260 signals as described below. · The MSC8101 MSC8101 CPM includes the following set of communication controllers: · Two full-duplex fast serial communications controllers (FCCs) that support: - Asynchronous transfer mode (ATM) through a UTOPIA 8 interface (FCC1 only)-The MSC8101 MSC8101 can operate as one of the following: ° ° ° UTOPIA slave device UTOPIA multi-PHY master device using direct polling for up to 4 PHY devices UTOPIA multi-PHY master device using multiplex polling that can address up to 31 PHY devices at addresses 0­30 (address 31 is reserved as a null port). - IEEE 802.3/Fast Ethernet through a Media-Independent Interface (MII) - High-level data link control (HDLC) Protocol: ° ° Serial mode-Transfers data one bit at a time Nibble mode-Transfers data four bits at a time - Transparent mode serial operation · One FCC that operates with the TSA only · Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent channels at 64 Kbps each, multiplexed on up to four TDM interfaces · Two full-duplex serial communications controllers (SCCs) that support the following protocols: - IEEE 802.3/fast Ethernet through a media-independent interface (MII) - HDLC Protocol: ° ° - - - - - - Serial mode-Transfers data one bit at a time Nibble mode-Transfers data four bits at a time Synchronous data link control (SDLC) LocalTalk (HDLC-based local area network protocol) Universal asynchronous receiver/transmitter (UART) Synchronous UART (1x clock mode) Binary synchronous (BISYNC) communication Transparent mode serial operation · Two additional SCCs that operate with the TSA only · Two full-duplex serial management controllers (SMCs) that support the following protocols: - General circuit interface (GCI)/integrated services digital network (ISDN) monitor and C/I channels (TSA only) - UART - Transparent mode serial operation · Serial peripheral interface (SPI) support for master or slave operation · Inter-integrated circuit (I2C) bus controller · Time-slot assigner (TSA) that supports multiplexing from any of the SCCs, FCCs, SMCs, and two MCCs onto four time-division multiplexed (TDM) interfaces. The TSA uses two serial interfaces (SI1 and SI2). SI1 uses TDMA1 which supports both serial and nibble mode. SI2 does not support nibble mode and includes TDMB2, TDMC2, and TDMD2, which operate only in serial mode. The individual sets of externals signals associated with a specific protocol and data transfer mode are multiplexed across any or all of the ports, as shown in Figure 1-2. The following sections describe the signals supported by Ports A­D. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-15 Signals/Connections 1.6.1 Port A Signals Table 1-7. Port A Signals Name GeneralPurpose I/O PA31 Peripheral Controller: Dedicated Signal Protocol Dedicated I/O Data Direction Description Output FCC1: TXENB UTOPIA slave Input FCC1: UTOPIA Slave Transmit Enable Asserted by an external UTOPIA master PHY when there is valid transmit cell data (TXD[0­7]). FCC1: COL MII PA30 FCC1: TXENB UTOPIA master Input FCC1: Media Independent Interface Collision Detect Asserted by an external fast Ethernet PHY when collision is detected. Output FCC1: UTOPIA Slave Transmit Cell Available Asserted by the MSC8101 MSC8101 (UTOPIA slave PHY) when the MSC8101 MSC8101 can accept one complete ATM cell. FCC1: TXCLAV UTOPIA slave FCC1: UTOPIA Master Transmit Enable Asserted by the MSC8101 MSC8101 (UTOPIA master PHY) when there is valid transmit cell data (TXD[0­7]). FCC1: TXCLAV UTOPIA master, or Input FCC1: UTOPIA Master Transmit Cell Available Asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. FCC1: TXCLAV0 UTOPIA master, Multi-PHY, direct polling Input FCC1: UTOPIA Master Transmit Cell Available Multi-PHY Direct Polling Asserted by an external UTOPIA slave PHY using direct polling to indicate that it can accept one complete ATM cell. FCC1: RTS HDLC, Serial and Nibble FCC1: CRS MII Output Input FCC1: Request To Send In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). RTS is asynchronous with the data. RTS is typically used in conjunction with CD. The MSC8101 MSC8101 FCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: Media Independent Interface Carrier Sense Asserted by an external fast Ethernet PHY to indicate activity on the cable. Output FCC1: UTOPIA Transmit Start of Cell Asserted by the MSC8101 MSC8101 (UTOPIA master PHY) when TXD[0­7] contains the first valid byte of the cell. Output FCC1: Media Independent Interface Transmit Error Asserted by the MSC8101 MSC8101 to force propagation of transmit errors. FCC1: RXENB UTOPIA master Output FCC1: UTOPIA Master Receive Enable Asserted by the MSC8101 MSC8101 (UTOPIA master PHY) to indicate that RXD[0­7] and RXSOC are to be sampled at the end of the next cycle. RXD[0­7] and RXSOC are enabled only in cycles following those with RXENB asserted. FCC1: RXENB UTOPIA slave Input FCC1: TX_EN MII PA28 FCC1: TXSOC UTOPIA master FCC1: TX_ER MII PA29 Output FCC1: UTOPIA Master Receive Enable Asserted by an external PHY to indicate that RXD[0­7] and RXSOC is to be sampled at the end of the next cycle. RXD[0­7] and RXSOC are enabled only in cycles following those with RXENB asserted. FCC1: Media Independent Interface Transmit Enable Asserted by the MSC8101 MSC8101 when transmitting data. MSC8101 MSC8101 Technical Data, Rev. 18 1-16 Freescale Semiconductor CPM Ports Table 1-7. Port A Signals (Continued) Name GeneralPurpose I/O PA27 Peripheral Controller: Dedicated Signal Protocol Dedicated I/O Data Direction Output FCC1: RX_DV MII PA26 FCC1: RXSOC UTOPIA slave Input FCC1: RXCLAV UTOPIA slave Output Description FCC1: UTOPIA Receive Start of Cell Asserted by the MSC8101 MSC8101 (UTOPIA slave) for an external PHY when RXD[0­7] contains the first valid byte of the cell. FCC1: Media Independent Interface Receive Data Valid Asserted by an external fast Ethernet PHY to indicate that valid data is being sent. The presence of carrier sense but not RX_DV indicates reception of broken packet headers, probably due to bad wiring or a bad circuit. FCC1: UTOPIA Slave Receive Cell Available Asserted by the MSC8101 MSC8101 (UTOPIA slave PHY) when one complete ATM cell is available for transfer. FCC1: RXCLAV UTOPIA master, or Input FCC1: UTOPIA Master Receive Cell Available Asserted by an external PHY when one complete ATM cell is available for transfer. RXCLAV0 UTOPIA master, Multi-PHY, direct polling Input FCC1: UTOPIA Master Receive Cell Available 0 Direct Polling Asserted by an external PHY when one complete ATM cell is available for transfer. FCC1: RX_ER MII Input FCC1: Media Independent Interface Receive Error Asserted by an external fast Ethernet PHY to indicate a receive error, which often indicates bad wiring. PA23 Output FCC1: UTOPIA Transmit Data Bit 0 The MSC8101 MSC8101 outputs ATM cell octets (UTOPIA interface data) on TXD[0­7]. TXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. Output Module Serial Number Bit 0 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0­4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: TXD1 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 1 The MSC8101 MSC8101 outputs ATM cell octets (UTOPIA interface data) on TXD[0­7]. This is bit 1 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. SDMA: MSNUM1 PA24 FCC1: TXD0 UTOPIA SDMA: MSNUM0 PA25 Output Module Serial Number Bit 1 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0­4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: TXD2 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 2 The MSC8101 MSC8101 outputs ATM cell octets (UTOPIA interface data) on TXD[0­7]. This is bit 2 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-17 Signals/Connections Table 1-7. Port A Signals (Continued) Name GeneralPurpose I/O Peripheral Controller: Dedicated Signal Protocol Dedicated I/O Data Direction Description PA22 FCC1: TXD3 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 3 The MSC8101 MSC8101 outputs ATM cell octets (UTOPIA interface data) on TXD[0­7]. This is bit 3 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. PA21 FCC1: TXD4 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 4 The MSC8101 MSC8101 outputs ATM cell octets (UTOPIA interface data) on TXD[0­7]. This is bit 4 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: TXD3 MII and HDLC nibble Output FCC1: MII and HDLC Nibble Transmit Data Bit 3 TXD[3­0] supports MII and HDLC nibble modes in FCC1. TXD3 is the most significant bit. FCC1: TXD5 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 5 The MSC8101 MSC8101 outputs ATM cell octets (UTOPIA interface data) on TXD[0­7]. This is bit 5 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: TXD2 MII and HDLC nibble Output FCC1: MII and HDLC Nibble Transmit Data Bit 2 TXD[3­0] is supported by MII and HDLC nibble modes in FCC1. This is bit 2 of the transmit data. TXD3 is the most significant bit. FCC1: TXD6 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 6 The MSC8101MSC8101 MSC8101MSC8101 outputs ATM cell octets (UTOPIA interface data) on TXD[0­7]. This is bit 6 of the transmit data. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: TXD1 MII and HDLC nibble Output FCC1: MII and HDLC Nibble Transmit Data Bit 1 TXD[3­0] is supported by MII and HDLC transparent nibble modes in FCC1. This is bit 1 of the transmit data. TXD3 is the most significant bit. FCC1: TXD7 UTOPIA Output FCC1: UTOPIA Transmit Data Bit 7. The MSC8101 MSC8101 outputs ATM cell octets (UTOPIA interface data) on TXD[0­7]. TXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. FCC1: TXD0 MII and HDLC nibble Output FCC1: MII and HDLC Nibble Transmit Data Bit 0 TXD[3­0] is supported by MII and HDLC nibble modes in FCC1. TXD0 is the least significant bit. FCC1: TXD HDLC serial and transparent Output FCC1: HDLC Serial and Transparent Transmit Data Bit This is the single transmit data bit in supported by HDLC serial and transparent modes. PA20 PA19 PA18 MSC8101 MSC8101 Technical Data, Rev. 18 1-18 Freescale Semiconductor CPM Ports Table 1-7. Port A Signals (Continued) Name GeneralPurpose I/O PA17 Peripheral Controller: Dedicated Signal Protocol Dedicated I/O Data Direction Description FCC1: MII and HDLC Nibble Receive Data Bit 0 RXD[3­0] is supported by MII and HDLC nibble mode in FCC1. RXD0 is the least significant bit. Input FCC1: HDLC Serial and Transparent Receive Data Bit This is the single receive data bit supported by HDLC and transparent modes. FCC1: RXD6 UTOPIA Input FCC1: UTOPIA Receive Data Bit 6. The MSC8101 MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0­7]. This is bit 6 of the receive data. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0­7] is tri-stated, enabled only when RXENB is asserted. Input FCC1: MII and HDLC Nibble Receive Data Bit 1 This is bit 1 of the receive nibble data. RXD3 is the most significant bit. FCC1: RXD5 UTOPIA Input FCC1: UTOPIA Receive Data Bit 5 The MSC8101 MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0­7]. This is bit 5 of the receive data. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0­7] is tri-stated, enabled only when RXENB is asserted. RXD2 MII and HDLC nibble Input FCC1: MII and HDLC Nibble Receive Data Bit 2 This is bit 2 of the receive nibble data. RXD3 is the most significant bit. FCC1: RXD4 UTOPIA Input FCC1: UTOPIA Receive Data Bit 4. The MSC8101 MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0­7]. RXD7 is the most significant bit. RXD0 is the least significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0­7] is tri-stated, enabled only when RXENB is asserted. FCC1: RXD3 MII and HDLC nibble PA13 Input FCC1: RXD1 MII and HDLC nibble PA14 FCC1: UTOPIA Receive Data Bit 7. The MSC8101 MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0­7]. RXD7 is the most significant bit. When no ATM data is available, idle cells are inserted. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0­7] is tri-stated, enabled only when RXENB is asserted. FCC1: RXD HDLC serial and transparent PA15 Input FCC1: RXD0 MII and HDLC nibble PA16 FCC1: RXD7 UTOPIA Input FCC1: MII and HDLC Nibble Receive Data Bit 3 RXD3 is the most significant bit of the receive nibble bit. FCC1: RXD3 UTOPIA Input FCC1: UTOPIA Receive Data Bit 3 The MSC8101 MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0­7]. RXD7 is the most significant bit. RXD0 is the least significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0­7] is tri-stated, enabled only when RXENB is asserted. SDMA: MSNUM2 Output Module Serial Number Bit 2 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0­4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-19 Signals/Connections Table 1-7. Port A Signals (Continued) Name GeneralPurpose I/O PA12 Peripheral Controller: Dedicated Signal Protocol FCC1: RXD2 UTOPIA SDMA: MSNUM3 PA11 FCC1: RXD1 UTOPIA SDMA: MSNUM4 PA10 FCC1: RXD0 UTOPIA Dedicated I/O Data Direction Input Output Input Output Input Description FCC1: UTOPIA Receive Data Bit 2 The MSC8101 MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0­7]. This is bit 2 of the receive data. RXD7 is the most significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0­7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 3 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0­4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: UTOPIA RX Receive Data Bit 1 The MSC8101 MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0­7]. This is bit 1 of the receive data. RXD7 is the most significant bit. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0­7] is tri-stated, enabled only when RXENB is asserted. Module Serial Number Bit 4 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0­4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. FCC1: UTOPIA RX Receive Data Bit 0 The MSC8101 MSC8101 inputs ATM cell octets (UTOPIA interface data) on RXD[0­7]. RXD0 is the least significant bit of the receive data. A cell is 53 bytes. To support Multi-PHY configurations, RXD[0­7] is tri-stated, enabled only when RXENB is asserted. SDMA: MSNUM5 Module Serial Number Bit 5 The MSNUM has 6 bits that identify devices using the serial DMA (SDMA) modules. MSNUM[0­4] is the sub-block code of the current peripheral controller using SDMA. MSNUM5 indicates the section, transmit (0) or receive (1), that is active during the transfer. The information is recorded in the SDMA transfer error registers. SMC2: SMTXD Output SMC2: Serial Management Transmit Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or generalcircuit interface (GCI). See also PC15. SI1 TDMA1: L1TXD0 TDM nibble PA9 Output Output Time-Division Multiplexing A1: Layer 1 Transmit Data Bit 0 L1TXD0 is the least significant bit of the TDM nibble data. SMC2: SMRXD Input SMC2: Serial Management Receive Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or generalcircuit interface (GCI). SI1 TDMA1: L1RXD0 TDM nibble Input Time-Division Multiplexing A1: Layer 1 Nibble Receive Data Bit 0 L1RXD0 is the least significant bit received in nibble mode. SI1 TDMA1: L1RXD TDM serial PA8 Input Time-Division Multiplexing A1: Layer 1 Serial Receive Data TDMA1 receives serial data from L1RXD. MSC8101 MSC8101 Technical Data, Rev. 18 1-20 Freescale Semiconductor CPM Ports Table 1-7. Port A Signals (Continued) Name GeneralPurpose I/O PA7 Peripheral Controller: Dedicated Signal Protocol Dedicated I/O Data Direction Description SMC2: SMSYN 1.6.2 SMC2: Serial Management Synchronization The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or generalcircuit interface (GCI). SI1 TDMA1: L1TSYNC TDM nibble and TDM serial Input Time-Division Multiplexing A1: Layer 1 Transmit Synchronization The synchronizing signal for the transmit channel. See the Serial Interface with time-slot assigner chapter in the MSC8101 MSC8101 Reference Manual. SI1 TDMA1: L1RSYNC TDM nibble and TDM serial PA6 Input Input Time-Division Multiplexing A1: Layer 1 Receive Synchronization. The synchronizing signal for the receive channel. Port B Signals Table 1-8. Port B Signals Name GeneralPurpose I/O PB31 Peripheral Controller: Dedicated I/O Protocol FCC2: TX_ER MII SCC2: RXD Dedicated I/O Data Direction Output Input Description FCC2: Media Independent Interface Transmit Error Asserted by the MSC8101 MSC8101 to force propagation of transmit errors. SCC2: Receive Data SCC2 receives serial data from RXD. SI2 TDMB2: L1TXD TDM serial PB30 Output Time-Division Multiplexing B2: Layer 1 Transmit Data TDMB2 transmits serial data out of L1TXD. SCC2: TXD Output SCC2: Transmit Data. SCC2 transmits serial data out of TXD. FCC2: RX_DV MII FCC2: Media Independent Interface Receive Data Valid Asserted by an external fast Ethernet PHY to indicate that valid data is being sent. The presence of carrier sense, but not RX_DV, indicates reception of broken packet headers, probably due to bad wiring or a bad circuit. SI2 TDMB2: L1RXD TDM serial PB29 Input Input Time-Division Multiplexing B2: Layer 1 Receive Data TDMB2 receives serial data from L1RXD. Output FCC2: Media Independent Interface Transmit Enable Asserted by the MSC8101 MSC8101 when transmitting data. FCC2: TX_EN MII SI2 TDMB2: L1RSYNC TDM serial Input Time-Division Multiplexing B2: Layer 1 Receive Synchronization The synchronizing signal for the receive channel. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-21 Signals/Connections Table 1-8. Port B Signals (Continued) Name GeneralPurpose I/O PB28 Peripheral Controller: Dedicated I/O Protocol FCC2: RTS HDLC serial, HDLC nibble, and transparent FCC2: RX_ER MII SCC2: RTS, TENA Dedicated I/O Data Direction Output Input Output Description FCC2: Request to Send One of the standard modem interface signals supported by FCC2 (RTS, CTS, and CD). RTS is asynchronous with the data. RTS is typically used in conjunction with CD. The MSC8101 MSC8101 FCC2 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC2: Media Independent Interface Receive Error Asserted by an external fast Ethernet PHY to indicate a receive error, which often indicates bad wiring. SCC2: Request to Send, Transmit Enable Typically used in conjunction with CD supported by SCC2. The MSC8101 MSC8101 SCC2 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. TENA is the signal used in Ethernet mode. SI2 TDMB2: L1TSYNC TDM serial PB27 Input Time-Division Multiplexing B2: Layer 1 Transmit Synchronization The synchronizing signal for the transmit channel. See the serial interface with time-slot assigner chapter in the MSC8101 MSC8101 Reference Manual. FCC2: COL MII Input FCC2: Media Independent Interface Collision Detect Asserted by an external fast Ethernet PHY when a collision is detected. SI2 TDMC2: L1TXD TDM serial Output Time-Division Multiplexing C2: Layer 1 Transmit Data TDMC2 transmits serial data out of L1TXD. Input FCC2: Media Independent Interface Carrier Sense Input Asserted by an external fast Ethernet PHY to indicate activity on the cable. Input Time-Division Multiplexing C2: Layer 1 Receive Data TDMC2 receives serial data from L1RXD. FCC2: TXD3 MII and HDLC nibble Output SI1 TDMA1: L1TXD3 TDM nibble PB25 FCC2: CRS MII SI2 TDMC2: L1RXD TDM serial PB26 Output SI2 TDMC2: L1TSYNC TDM serial Input FCC2: MII and HDLC Nibble Transmit Data Bit 3 TXD3 is bit 3 and the most significant bit of the transmit data nibble. Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 3 L1TXD3 is bit 3 and the most significant bit of the transmit data nibble. Time-Division Multiplexing C2: Layer 1 Transmit Synchronization The synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8101 MSC8101 Reference Manual. FCC2: TXD2 MII and HDLC nibble Output SI1 TDMA1: L1RXD3 nibble Input Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 3 L1RXD3 is bit 3 and the most significant bit of the receive data nibble. SI2 TDMC2: L1RSYNC serial PB24 FCC2: MII and HDLC Nibble: Transmit Data Bit 2 TXD2 is bit 2 of the transmit data nibble. Input Time-Division Multiplexing C2: Layer 1 Receive Synchronization The synchronizing signal for the receive channel. MSC8101 MSC8101 Technical Data, Rev. 18 1-22 Freescale Semiconductor CPM Ports Table 1-8. Port B Signals (Continued) Name GeneralPurpose I/O PB23 Peripheral Controller: Dedicated I/O Protocol Dedicated I/O Data Direction FCC2: TXD1 MII and HDLC nibble Output SI1 TDMA1: L1RXD2 TDM nibble Input Description FCC2: MII and HDLC Nibble: Transmit Data Bit 1 TXD1 is bit 1 of the transmit data nibble. Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 2 L1RXD2 is bit 2 of the receive data nibble. SI2 TDMD2: L1TXD TDM serial Time-Division Multiplexing D2: Layer 1 Transmit Data TDMA1 transmits serial data out of L1TXD. FCC2: TXD0 MII and HDLC nibble Output FCC2: MII and HDLC Nibble Transmit Data Bit 0 TXD0 is bit 0 and the least significant bit of the transmit data nibble. FCC2: TXD HDLC serial and transparent PB22 Output Output FCC2: HDLC Serial and Transparent Transmit Data Serial data is transmitted via TXD. SI1 TDMA1: L1RXD1 TDM nibble Time-Division Multiplexing A1: Nibble Layer 1 Receive Data Bit 1 L1RXD1 is bit 1 of the receive data nibble. SI2 TDMD2: L1RXD TDM serial Input Time-Division Multiplexing D2: Layer 1 Receive Data Serial data is received via L1RXD. FCC2: RXD0 MII and HDLC nibble Input FCC2: MII and HDLC Nibble Receive Data Bit 0 RXD0 is bit 0 and the least significant bit of the receive data nibble. FCC2: RXD HDLC serial and transparent PB21 Input Input FCC2: HDLC Serial and Transparent Receive Data Serial data is received via RXD. SI1 TDMA1: L1TXD2 TDM nibble Input Time-Division Multiplexing D2: Layer 1 Transmit Synchronize Data The synchronizing signal for the transmit channel. See the Serial Interface with Time-Slot Assigner chapter in the MSC8101 MSC8101 Reference Manual. FCC2: RXD1 MII and HDLC nibble Input FCC2: MII and HDLC Nibble: Receive Data Bit 1 RXD1 is bit 1 of the receive data nibble. SI1 TDMA1: L1TXD1 TDM nibble Output Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 1 L1TXD1 is bit 1 of the transmit data nibble. SI2 TDMD2: L1RSYNC TDM serial PB19 Time-Division Multiplexing A1: Nibble Layer 1 Transmit Data Bit 2 L1TXD2 is bit 2 of the transmit data nibble. SI2 TDMD2: L1TSYNC TDM serial PB20 Output Input Time-Division Multiplexing D2: Layer 1 Receive Synchronize Data The synchronizing signal for the receive channel. FCC2: RXD2 MII and HDLC nibble Input FCC2: MII and HDLC Nibble Receive Data Bit 2 RXD2 is bit 2 of the receive data nibble. I2C: SDA Input/ Output I2C: Inter-Integrated Circuit Serial Data The I2C interface comprises two signals: serial data (SDA) and serial clock (SDA). The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. Clock rates run up to 520 kHz@25 MHz system clock. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-23 Signals/Connections Table 1-8. Port B Signals (Continued) Name GeneralPurpose I/O PB18 Peripheral Controller: Dedicated I/O Protocol FCC2: RXD3 MII and HDLC nibble I2C: SCL 1.6.3 Dedicated I/O Data Direction Input Input/Output Description FCC2: MII and HDLC Nibble Receive Data Bit 3 RXD3 is bit 3 and the most significant bit of the receive data nibble. I2C: Inter-Integrated Circuit Serial Clock The I2C interface comprises two signals: serial data (SDA) and serial clock (SDA). The I2C controller uses a synchronous, multimaster bus that can connect several integrated circuits on a board. Clock rates run up to 520 kHz@25 MHz system clock. Port C Signals Table 1-9. Port C Signals Name GeneralPurpose I/O PC31 Peripheral Controller: Dedicated I/O Protocol BRG1O Dedicated I/O Data Direction Output Description Baud-Rate Generator 1 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. BRG1O can be the internal input to the SIU timers. When CLK5 is selected (see PC27 below), it is the source for BRG1O which is the default input for the SIU timers. See the system interface unit (SIU) chapter in the MSC8101 MSC8101 Reference Manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU timers is disabled. CLK1 Input Clock 1 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. TIMER1/2: TGATE1 Input Timer 1/2: Timer Gate 1 The timers can be gated/restarted by an external gate signal. There are two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls timer 3 and/or 4. MSC8101 MSC8101 Technical Data, Rev. 18 1-24 Freescale Semiconductor CPM Ports Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC30 Peripheral Controller: Dedicated I/O Protocol BRG2O CLK2 Timer1: TOUT1 EXT1 Dedicated I/O Data Direction Description Output Baud-Rate Generator 2 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. Input Clock 2 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Output Timer 1: Timer Out 1 The timers (Timer[1­4]) can output a signal on a timer output (TOUT[1­4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also connect internally to the input of another timer, resulting in a 32-bit timer. Input External Request 1 Asserts an internal request to the CPM processor. The signal can be programmed as level- or edge-sensitive, and also has programmable priority. Refer to the RISC Controller Configuration Register (RCCR) description in the Chapter 17 of the MSC8101 MSC8101 Reference Manual for programming information. There are no current microcode applications for this request line. It is reserved for future development. Output Baud-Rate Generator 3 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. CLK3 Input Clock 3 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. TIN2 Input Timer Input 2 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. SCC1: CTS, CLSN PC29 Input SCC1: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8101 MSC8101 SCC1 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC15. BRG3O MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-25 Signals/Connections Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O Peripheral Controller: Dedicated I/O Protocol Dedicated I/O Data Direction Description Output Baud-Rate Generator 4 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. CLK4 Input Clock 4 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. TIN1 PC28 Input Timer Input 1 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. Output Timer 2: Timer Output 2 The timers (Timer[1­4]) can output a signal on a timer output (TOUT[1­4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also be connected internally to the input of another timer, resulting in a 32-bit timer. Input SCC2: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8101 MSC8101 SCC2 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC13. BRG4O Timer2: TOUT2 SCC2: CTS, CLSN PC27 BRG5O Output Baud-Rate Generator 5 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. CLK5 Input Clock 5 When selected, CLK5 is a source for the SIU timers via BRG1O. See the System Interface Unit (SIU) chapter in the MSC8101 MSC8101 Reference Manual for additional information. If CLK5 is not enabled, BRG1O uses an internal input. If TMCLK is enabled (see PC26 below), the BRG1O input to the SIU timers is disabled. TIMER3/4: TGATE2 Input Timer 3/4: Timer Gate 2 The timers can be gated/restarted by an external gate signal. There are two gate signals: TGATE1 controls timer 1 and/or 2 and TGATE2 controls timer 3 and/or 4. MSC8101 MSC8101 Technical Data, Rev. 18 1-26 Freescale Semiconductor CPM Ports Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC26 Peripheral Controller: Dedicated I/O Protocol BRG6O CLK6 Timer3: TOUT3 Dedicated I/O Data Direction Description Output Baud-Rate Generator 6 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. Input Clock 6 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Output Timer 3: Timer Out 3 The timers (Timer[1­4]) can output a signal on a timer output (TOUT[1­4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also connect internally to the input of another timer, resulting in a 32-bit timer. TMCLK BRG7O Output Baud-Rate Generator 7 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or provide an output to one of the 8 BRG pins. CLK7 Input Clock 7 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. TIN4 PC25 Input Input Timer Input 4 A timer can have one of the following sources: another timer, system clock, system clock divided by 16 or a timer input. The CPM supports up to 4 timer inputs. The timer inputs can be captured on the rising, falling or both edges. Output DMA: Data Acknowledge 2 DACK2, DREQ2, DRACK2 and DONE2 belong to the SIU DMA controller. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. DMA: DACK2 Timer Clock When selected, TMCLK is the designated input to the SIU timers. When TMCLK is configured as the input to the SIU timers, the BRG1O input is disabled. See the System Interface Unit (SIU) chapter in the MSC8101 MSC8101 Reference Manual for additional information. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-27 Signals/Connections Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC24 Peripheral Controller: Dedicated I/O Protocol BRG8O Dedicated I/O Data Direction Output Description Baud-Rate Generator 8 Output The CPM supports up to 8 BRGs used internally by the bank-of-clocks selection logic and/or to provide an output to one of the 8 BRG pins. CLK8 Input Clock 8 The CPM supports up to 10 clock input pins. The clocks are sent to the bank-of-clocks selection logic, where they can be routed to the controllers. TIN3 Input Timer Input 3 A timer can have one of the following sources: another timer, system clock, system clock divided by 16, or a timer input. The CPM supports up to four timer inputs. The timer inputs can be captured on the rising, falling, or both edges. Output Timer 4: Timer Out 4 The timers (Timer1­4]) can output a signal on a timer output (TOUT[1­4]) when the reference value is reached. This signal can be an active-low pulse or a toggle of the current output. The output can also be connected internally to the input of another timer, resulting in a 32-bit timer. DMA: DREQ2 Input DMA: Data Request 2 DACK2, DREQ2, DRACK2, and DONE2 belong to the SIU DMA controller. DONE2 and DRACK2 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. CLK9 Input Clock 9 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Timer4: TOUT4 PC23 DMA: DACK1 EXT2 Output DMA: Data Acknowledge 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. Input External Request 2 External request input line 2 asserts an internal request to the CPM processor. The signal can be programmed as level- or edge-sensitive, and also has programmable priority. Refer to the risc controller configuration register (RCCR) description in the Chapter 17 of the MSC8101 MSC8101 Reference Manual for programming information. There are no current microcode applications for this request line. It is reserved for future development. MSC8101 MSC8101 Technical Data, Rev. 18 1-28 Freescale Semiconductor CPM Ports Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC22 Peripheral Controller: Dedicated I/O Protocol SI1: L1ST1 CLK10 CLK10 DMA: DREQ1 Dedicated I/O Data Direction Output Input Description Serial Interface 1: Layer 1 Strobe 1 The MSC8101 MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. Clock 10 The CPM supports up to 10 clock input pins sent to the bank-of-clocks selection logic, where they can be routed to the controllers. Input/ Output DMA: Request 1 DACK1, DREQ1, DRACK1, and DONE1 belong to the SIU DMA controller. DONE1 and DRACK1 are signals on the same pin and therefore cannot be used simultaneously. There are two sets of DMA pins associated with the PIO ports. Output SMC2: Serial Management Transmit Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that support three protocols or modes: UART, transparent, or general-circuit interface (GCI). See also PA9. SCC1: CTS/CLSN Input SCC1: Clear To Send, Collision Typically used in conjunction with RTS. The MSC8101 MSC8101 SCC1 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC29. FCC1: TXADDR0 UTOPIA master Output FCC1: TXADDR0 UTOPIA slave PC15 Input SMC2: SMTXD FCC1: UTOPIA Master Transmit Address Bit 0 This is master transmit address bit 0. FCC1: UTOPIA Slave Transmit Address Bit 0 This is slave transmit address bit 0. Output Serial Interface 1: Layer 1 Strobe 2 The MSC8101 MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also be generate output wave forms for such applications as stepper-motor control. SCC1: CD, RENA Input SCC1: Carrier Detect, Receive Enable Typically used in conjunction with RTS supported by SCC1. The MSC8101MSC8101 MSC8101MSC8101 SCC1 transmitter requests the receiver to send data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: RXADDR0 UTOPIA master Output FCC1: RXADDR0 UTOPIA slave PC14 Input SI1: L1ST2 FCC1: UTOPIA Multi-PHY Master Receive Address Bit 0 This is master receive address bit 0. FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 0 This is slave receive address bit 0. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-29 Signals/Connections Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC13 Peripheral Controller: Dedicated I/O Protocol SI1: L1ST4 SCC2: CTS,CLSN Dedicated I/O Data Direction Description Output Serial Interface 1: Layer 1 Strobe 4 The MSC8101 MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. Input SCC2: Clear to Send, Collision Typically used in conjunction with RTS. The MSC8101 MSC8101 SCC2 transmitter sends out a request to send data signal (RTS). The request is accepted when CTS is returned low. CLSN is the signal used in Ethernet mode. See also PC28. FCC1:TXADDR1 UTOPIA master Output FCC1: TXADDR1 UTOPIA slave Input FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 1 This is master transmit address bit 1. FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 1 This is slave transmit address bit 1. Output Serial Interface 1: Layer 1 Strobe 3 The MSC8101 MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. SCC2: CD, RENA Input SCC2: Carrier Detect, Request Enable Typically used in conjunction with RTS supported by SCC2. The MSC8101 MSC8101 SCC2 transmitter requests to the receiver that it sends data by asserting RTS low. The request is accepted when CTS is returned low. FCC1: RXADDR1 UTOPIA master Output FCC1: RXADDR1 UTOPIA slave PC12 Input SI1: L1ST3 FCC1: UTOPIA Multi-PHY Master Receive Address Bit 1 This is master receive address bit 1. FCC1: UTOPIA Multi-PHY Slave Receive Address Bit 1 This is slave receive address bit 1. MSC8101 MSC8101 Technical Data, Rev. 18 1-30 Freescale Semiconductor CPM Ports Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC7 Peripheral Controller: Dedicated I/O Protocol SI2: L1ST1 FCC1: CTS HDLC serial, HDLC nibble, and transparent Dedicated I/O Data Direction Description Output Serial Interface 2: Strobe 1 The MSC8101 MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. Input FCC1: Clear To Send In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). CTS is asynchronous with the data. FCC1: TXADDR2 UTOPIA master FCC1: TXADDR2 UTOPIA slave Input FCC1: UTOPIA Multi-PHY Slave Transmit Address Bit 2 This is slave transmit address bit 2. FCC1: TXCLAV1 UTOPIA multi-PHY master, direct polling PC6 Output Input FCC1: UTOPIA Multi-PHY Master Transmit Cell Available 1 Direct Polling Asserted by an external UTOPIA slave PHY to indicate that it can accept one complete ATM cell. Output Serial Interface 2: Layer 1 Strobe 2 The MSC8101 MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. Input FCC1: Carrier Detect In the standard modem interface signals supported by FCC1 (RTS, CTS, and CD). CD is an input asynchronous with the data. SI2: L1ST2 FCC1: CD HDLC serial, HDLC nibble, and transparent FCC1: UTOPIA Multi-PHY Master Transmit Address Bit 2 This is master transmit address bit 2. FCC1: RXADDR2 UTOPIA master Output FCC1: RXADDR2 UTOPIA slave Input FCC1: UTOPIA Slave Receive Address Bit 2 This is slave receive address bit 2. FCC1: RXCLAV1 UTOPIA multi-PHY master, direct polling Input FCC1: UTOPIA Multi-PHY Master Receive Cell Available 1 Direct Polling Asserted by an external PHY when one complete ATM cell is available for transfer. FCC1: UTOPIA Multi-PHY Master Receive Address Bit 2 This is master receive address bit 2. MSC8101 MSC8101 Technical Data, Rev. 18 Freescale Semiconductor 1-31 Signals/Connections Table 1-9. Port C Signals (Continued) Name GeneralPurpose I/O PC5 Peripheral Controller: Dedicated I/O Protocol Dedicated I/O Data Direction Description Output SMC1: Transmit Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). SI2: L1ST3 Output Serial Interface 2: Layer 1 Strobe 3 The MSC8101 MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. FCC2: CTS HDLC serial, HDLC nibble, and transparent PC4 SMC1: SMTXD Input FCC2: Clear To Send In the standard modem interface signals supported by FCC2 (RTS, CTS, and CD). CTS is asynchronous with the data. SMC1: SMRXD Input SMC1: Receive Data The SMC interface consists of SMTXD, SMRXD, SMSYN, and a clock. Not all signals are used for all applications. SMCs are full-duplex ports that supports three protocols or modes: UART, transparent, or general-circuit interface (GCI). Output Serial Interface 2: Layer 1 Strobe 4 The MSC8101 MSC8101 time-slot assigner supports up to four strobe outputs that can be asserted on a bit or byte basis. The strobe outputs are useful for interfacing to other devices that do not support the multiplexed interface or for enabling/disabling three-state I/O buffers in a multiple-transmitter architecture. These strobes can also generate output wave forms for such applications as stepper-motor control. SI2: L1ST4 FCC2: CD HDLC serial, HDLC nibble, and transparent Input FCC2: Carrier Detect In the standard modem interface signals supported by FCC2 (RTS, CTS and CD). CD is asynchronous with the data. MSC8101 MSC8101 Technical Data, Rev. 18 1-32 Freescale Semiconductor CPM Ports 1.6.4 Port D Signals Table 1-10. Port D Signals Name GeneralPurpose I/O PD31 Peripheral Controller: Dedicated I/O Protocol SCC1: RXD DMA: