MSC1210 SBAS203E 24-BITS 22-BITS 02PPM/ 32-BIT 16-BIT TQFP-64 MSC1210Y2 - Datasheet Archive

 

SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 Precision Analog-to-Digital Converter (ADC) with 8051 Microcontroller and Flash

 

MSC1210 MSC1210 SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 Precision Analog-to-Digital Converter (ADC) with 8051 Microcontroller and Flash Memory FEATURES ANALOG FEATURES D 24-BITS 24-BITS NO MISSING CODES D 22-BITS 22-BITS EFFECTIVE RESOLUTION AT 10Hz Low Noise: 75nV D PGA FROM 1 TO 128 D PRECISION ON-CHIP VOLTAGE REFERENCE: D D D D D D D D Accuracy: 0.2% Drift: 5ppm/°C 8 DIFFERENTIAL/SINGLE-ENDED CHANNELS ON-CHIP OFFSET/GAIN CALIBRATION OFFSET DRIFT: 0.02PPM/ 02PPM/°C GAIN DRIFT: 0.5PPM/°C ON-CHIP TEMPERATURE SENSOR BURN-OUT SENSOR DETECTION SINGLE-CYCLE CONVERSION SELECTABLE BUFFER INPUT DIGITAL FEATURES Peripheral Features D 34 I/O PINS D ADDITIONAL 32-BIT 32-BIT ACCUMULATOR D THREE 16-BIT 16-BIT TIMER/COUNTERS D SYSTEM TIMERS D PROGRAMMABLE WATCHDOG TIMER D FULL DUPLEX DUAL USART D MASTER/SLAVE SPI D 16-BIT 16-BIT PWM D POWER MANAGEMENT CONTROL D IDLE MODE CURRENT < 1mA D STOP MODE CURRENT < 1mA D PROGRAMMABLE BROWNOUT RESET D PROGRAMMABLE LOW VOLTAGE DETECT D 21 INTERRUPT SOURCES D TWO HARDWARE BREAKPOINTS GENERAL FEATURES D PACKAGE: TQFP-64 TQFP-64 D LOW POWER: 4mW D INDUSTRIAL TEMPERATURE RANGE: Microcontroller Core D 8051 COMPATIBLE D HIGH-SPEED CORE: 4 Clocks per Instruction Cycle D DC TO 33MHz D SINGLE INSTRUCTION 121ns D DUAL DATA POINTER -40°C TO +85°C D POWER SUPPLY: 2.7V to 5.25V APPLICATIONS Memory D UP TO 32kB FLASH MEMORY D FLASH MEMORY PARTITIONING D ENDURANCE 1M ERASE/WRITE CYCLES, 100 YEAR DATA RETENTION D IN-SYSTEM SERIALLY PROGRAMMABLE D EXTERNAL PROGRAM/DATA MEMORY (64kB) D 1,280 BYTES DATA SRAM D FLASH MEMORY SECURITY D 2kB BOOT ROM D PROGRAMMABLE WAIT STATE CONTROL D D D D D D D D D D D INDUSTRIAL PROCESS CONTROL INSTRUMENTATION LIQUID/GAS CHROMATOGRAPHY BLOOD ANALYSIS SMART TRANSMITTERS PORTABLE INSTRUMENTS WEIGH SCALES PRESSURE TRANSDUCERS INTELLIGENT SENSORS PORTABLE APPLICATIONS DAS SYSTEMS Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright 2002-2004, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 PACKAGE/ORDERING INFORMATION(1) PRODUCT FLASH MEMORY MSC1210Y2 MSC1210Y2 PACKAGE-LEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING TQFP-64 TQFP-64 PAG -40°C to +85°C MSC1210Y2 MSC1210Y2 4k ORDERING NUMBER TRANSPORT MEDIA, QUANTITY MSC1210Y2PAGT MSC1210Y2PAGT Tape and Reel, 250 MSC1210Y2PAGR MSC1210Y2PAGR Tape and Reel, 2000 MSC1210Y3PAGT MSC1210Y3PAGT MSC1210Y3 MSC1210Y3 8k TQFP-64 TQFP-64 PAG -40°C to +85°C MSC1210Y3 MSC1210Y3 MSC1210Y4 MSC1210Y4 16k TQFP-64 TQFP-64 PAG -40°C to +85°C MSC1210Y4 MSC1210Y4 MSC1210Y5 MSC1210Y5 32k TQFP-64 TQFP-64 PAG -40°C to +85°C MSC1210Y5 MSC1210Y5 Tape and Reel, 250 MSC1210Y3PAGR MSC1210Y3PAGR Tape and Reel, 2000 MSC1210Y4PAGT MSC1210Y4PAGT Tape and Reel, 250 MSC1210Y4PAGR MSC1210Y4PAGR Tape and Reel, 2000 MSC1210Y5PAGT MSC1210Y5PAGT Tape and Reel, 250 MSC1210Y5PAGR MSC1210Y5PAGR Tape and Reel, 2000 (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this datasheet. ABSOLUTE MAXIMUM RATINGS(1) Analog Inputs Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA, Momentary Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA, Continuous Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . AGND - 0.5V to AVDD + 0.5V Power Supply DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to AVDD +0.3V Digital Input Voltage to DGND . . . . . . . . . . . . . . . . . -0.3V to DVDD +0.3V Digital Output Voltage to DGND . . . . . . . . . . . . . . . . -0.3V to DVDD +0.3V Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C Storage Temperature Range . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Lead Temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C Package Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900mW Output Current All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200mA Output Pin Short Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10s Thermal Resistance, Junction-to-Ambient (qJA) . . . . . . . . . . . . . . 66.6°C/W Thermal Resistance, Junction-to-Case (qJC) . . . . . . . . . . . . . . . . . . 4.3°C/W Digital Outputs Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA, Continuous I/O Source/Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Power Pin Maximum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300mA This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. MSC1210YX MSC1210YX FAMILY FEATURES FEATURES(1) MSC1210Y2 MSC1210Y2(2) MSC1210Y3 MSC1210Y3(2) MSC1210Y4 MSC1210Y4(2) MSC1210Y5 MSC1210Y5(2) Flash Program Memory (Bytes) Up to 4k Up to 8k Up to 16k Up to 32k Flash Data Memory (Bytes) Up to 4k Up to 8k Up to 16k Up to 32k Internal Scratchpad RAM (Bytes) 256 256 256 256 Internal MOVX RAM (Bytes) 1024 1024 1024 1024 64k Program, 64k Data 64k Program, 64k Data 64k Program, 64k Data 64k Program, 64k Data Externally Accessible Memory (Bytes) (1) All peripheral features are the same on all devices; the flash memory size is the only difference. (2) The last digit of the part number (N) represents the onboard flash size = (2N)kBytes. 2 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS: AVDD = 5V All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF = (REF IN+) - (REF IN-) = +2.5V, unless otherwise noted. MSC1210Yx PARAMETER ANALOG INPUT (AIN0-AIN7, AINCOM) Analog Input Range Full-Scale Input Voltage Range Differential Input Impedance Input Current Bandwidth Fast Settling Filter Sinc2 Filter Sinc3 Filter Programmable Gain Amplifier Input Capacitance Input Leakage Current Burnout Current Sources CONDITIONS MIN Buffer OFF Buffer ON (In+) - (In-) Buffer OFF Buffer ON AGND - 0.1 AGND + 50mV -3dB -3dB -3dB User-Selectable Gain Range Buffer On Modulator OFF, T = +25°C Buffer On Normal Mode Rejection Power-Supply Rejection VOLTAGE REFERENCE INPUT Reference Input Range VREF Common-Mode Rejection Common-Mode Rejection Input Current(4) ON-CHIP VOLTAGE REFERENCE Output Voltage Power-Supply Rejection Ratio Short-Circuit Current Source Short-Circuit Current Sink Short-Circuit Duration Drift Output Impedance Startup Time from Power ON Temperature Sensor Voltage Temperature Sensor Coefficient MAX UNITS AVDD + 0.1 AVDD - 1.5 ±VREF/PGA V V V M nA 7/PGA(5) 0.5 0.469 · fDATA 0.318 · fDATA 0.262 · fDATA 1 128 9 0.5 ±2 pF pA µA ±VREF/(2·PGA) OFFSET DAC Offset DAC Range Offset DAC Monotonicity Offset DAC Gain Error Offset DAC Gain Error Drift SYSTEM PERFORMANCE Resolution ENOB Output Noise No Missing Codes Integral Nonlinearity Offset Error Offset Drift(1) Gain Error(2) Gain Error Drift(1) System Gain Calibration Range System Offset Calibration Range Common-Mode Rejection TYP V Bits % of Range ppm/°C 8 ±1.5 1 24 See Typical Characteristics Sinc3 Filter, Decimation > 360 End Point Fit, Differential Input After Calibration Before Calibration After Calibration Before Calibration At DC fCM = 60Hz, fDATA = 10Hz fCM = 50Hz, fDATA = 50Hz fCM = 60Hz, fDATA = 60Hz fSIG = 50Hz, fDATA = 50Hz fSIG = 60Hz, fDATA = 60Hz At DC, dB = -20log(VOUT/VDD)(3) 24 7.5 0.02 0.002 0.5 80 -50 100 80 AGND 0.1 VREFH = 1 at +25°C, ACLK = 1MHz VREFH = 0 2.495 Sourcing 100µA CREF = 0.1µF T = +25°C Bits ±0.0015 REF IN+, REF IN- VREF = (REF IN+) - (REF IN-) At DC fvREFCM = 60Hz, fDATA = 60Hz VREF = 2.5V Sink or Source Bits Bits 22 See Typical Characteristics 120 50 115 130 120 120 100 100 88 2.5 130 120 3 2.5 1.25 65 8 50 Indefinite 5 3 8 115 375 %FSR ppm of FS ppm of FS/°C % ppm/°C % of FS % of FS dB dB dB dB dB dB dB AVDD(2) AVDD V V dB dB µA 2.505 V V dB mA µA ppm/°C ms mV µV/°C (1) Calibration can minimize these errors. The gain calibration cannot have a REF IN+ of more than AVDD -1.5V with Buffer ON. To calibrate gain, turn Buffer OFF. VOUT is change in digital result. (4) 9pF switched capacitor at f SAMP clock frequency (see Figure 13). (5) The input impedance for PGA = 128 is the same as that for PGA = 64 (that is, 7M/64 7M/64). (2) (3) 3 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 ELECTRICAL CHARACTERISTICS: AVDD = 5V (continued) All specifications from TMIN to TMAX, DVDD = +2.7V to 5.25V, fMOD = 15.625kHz, PGA = 1, Buffer ON, fDATA = 10Hz, Bipolar, and VREF = (REF IN+) - (REF IN-) = +2.5V, unless otherwise noted. MSC1210Yx PARAMETER ANALOG POWER-SUPPLY REQUIREMENTS Power-Supply Voltage Analog Current (IADC + IVREF) ADC Current (IADC) VREF Supply Current (IVREF) CONDITIONS MIN TYP MAX UNITS AVDD PDADC = 1, ALVDIS = 1, DAB = 1 PGA = 1, Buffer OFF PGA = 128, Buffer OFF PGA = 1, Buffer ON PGA = 128, Buffer ON ADC ON, VDAC OFF 4.75 5.0 0)(5) ALE LOW to Valid Data In (tMCS = 0)(5) ALE LOW to Valid Data In (tMCS > 0)(5) Address to Valid Data In (tMCS = 0)(5) Address to Valid Data In (tMCS > 0)(5) ALE LOW to RD or WR LOW (tMCS = 0)(5) ALE LOW to RD or WR LOW (tMCS > 0)(5) Address to RD or WR LOW (tMCS = 0)(5) Address to RD or WR LOW (tMCS > 0)(5) Data Valid to WR Transition Data Hold After WR RD LOW to Address Float RD or WR HIGH to ALE HIGH (tMCS = 0)(5) RD or WR HIGH to ALE HIGH (tMCS > 0)(5) 2tCLK - 5 tMCS - 5 2tCLK - 5 tMCS - 5 4 4 4 4 SYMBOL HIGH Time(3) LOW Time(3) Rise Time(3) Fall Time(3) System Clock 1/tCLK(4) Program Memory tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ 1.5tCLK - 5 0.5tCLK - 7 0.5tCLK 2.5tCLK - 35 0.5tCLK 2tCLK - 5 2.5tCLK - 25 0.5tCLK 2tCLK - 5 2tCLK - 40 5 2tCLK - 30 -5 tCLK - 5 3tCLK - 40 0 tCLK 3tCLK - 25 0 ns ns ns ns ns ns ns ns ns ns ns Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH 2tCLK - 5 tMCS - 5 2tCLK - 5 tMCS - 5 2tCLK - 40 tMCS - 40 -5 5 5 ns ns ns ns -5 tCLK 2tCLK 2.5tCLK - 25 tCLK + tMCS - 25 3tCLK - 25 1.5tCLK + tMCS - 40 -5 tCLK - 5 -0.5tCLK - 5 5 tCLK + 5 2tCLK - 30 tMCS - 30 tCLK 2tCLK 2.5tCLK - 40 tCLK + tMCS - 40 3tCLK - 40 0.5tCLK - 5 tCLK - 5 tCLK - 5 2tCLK - 5 -8 tCLK - 8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 0.5tCLK + 5 tCLK + 5 -0.5tCLK - 5 5 tCLK + 5 1.5tCLK + tMCS - 25 0.5tCLK - 5 tCLK - 5 tCLK - 5 2tCLK - 5 -5 tCLK - 5 -5 tCLK - 5 0.5tCLK + 5 tCLK + 5 External Clock tHIGH tLOW tR tF (1) (2) (3) (4) (5) 15 15 10 10 5 5 Parameters are valid over operating temperature range, unless otherwise specified. Load capacitance for Port 0, ALE, and PSEN = 100pF; load capacitance for all other outputs = 80pF. These values are characterized but not 100% production tested. tCLK = 1/fosc = one oscillator clock period. tMCS is a time period related to the Stretch MOVX selection. The following table shows the value of tMCS for each stretch selection. MD2 0 MD1 0 MD0 0 MOVX DURATION 2 Machine Cycles tMCS 0 0 0 1 3 Machine Cycles (default) 0 1 0 4tCLK 8tCLK 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 4 Machine Cycles 5 Machine Cycles 6 Machine Cycles 7 Machine Cycles 8 Machine Cycles 9 Machine Cycles 12tCLK 16tCLK 20tCLK 24tCLK 28tCLK 7 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 EXPLANATION OF THE AC SYMBOLS Each Timing Symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designators are: RRD Signal AAddress CClock tTime DInput Data VValid HLogic Level HIGH WWR Signal IInstruction (program memory contents) XNo Longer a Valid Logic Level LLogic Level LOW, or ALE ZFloat PPSEN Examples: (1) tAVLL = Time for address valid to ALE LOW. QOutput Data (2) tLLPL = Time for ALE LOW to PSEN LOW. tLHLL ALE tAVLL t PLPH tLLPL tLLIV tPLIV PSEN tPXIZ t LLAX tPLAZ A0-A7 PORT 0 tPXIX INSTR IN A0-A7 tAVIV A8-A15 A8-A15 PORT 2 A8-A15 A8-A15 Figure 1. External Program Memory Read Cycle ALE tWHLH PSEN tLLDV tLLWL tRLRH RD tAVLL t LLAX tRLAZ PORT 0 tRHDZ tRLDV A0-A7 from RI or DPL t RHDX DATA IN A0-A7from PCL t AVWL tAVDV PORT 2 P2.0-P2.7 or A8-A15 A8-A15 from DPH Figure 2. External Data Memory Read Cycle 8 A8-A15 A8-A15 from PCH INSTR IN MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 ALE tWHLH PSEN tLLWL tWLWH WR tAVLL tLLAX tQ V W X tWHQX t DW PORT 0 A0-A7 from RI or DPL DATA OUT A0-A7 from PCL INSTR IN tAVWL PORT 2 P2.0-P2.7or A8-A15 A8-A15 from DPH A 8-A15 8-A15 from PCH Figure 3. External Data Memory Write Cycle t HIGH VIH1 0.8V tf tr VIH1 0.8V VIH1 tLOW VIH1 0.8V 0.8V t CLK Figure 4. External Clock Drive CLK 9 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 RESET AND POWER-ON TIMING tRW RST tRRD tRFD tRRD tRFD PSEN ALE t RS tRH EA NOTE: PSEN and ALE are internally pulled up with ~9kduring RST high. Figure 5. Reset Timing tRW RST tRFD tRRD PSEN tRS tRRD tRH ALE NOTE: PSEN and ALE are internally pulled up with ~9kduring RST high. Figure 6. Parallel Flash Programming Power-On Timing (EA is ignored) tRW RST tRRD tRS tRH PSEN t RRD t RFD ALE NOTE: PSEN and ALE are internally pulled up with ~9k during RST high. Figure 7. Serial Flash Programming Power-On Timing (EA is ignored) SYMBOL PARAMETER tRW tRRD tRFD tRS RST falling to PSEN and ALE start tRH 10 RST width RST falling to input signal hold time RST rise to PSEN ALE internal pull HIGH Input signal to RST falling setup time MIN MAX 2tOSC - - UNIT ns 5 µs - (217 + 512)tOSC ns tOSC (217 + 512)tOSC - ns - ns MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 P0.3/AD3 P0.4/AD4 P0.5/AD5 58 P0.2/AD2 59 P0.1/AD1 P1.2/RxD1 60 P0.0/AD0 P1.3/TxD1 61 P1.0/T2 P1.4/INT2/SS 62 P1.1/T2EX P1.5/INT3/MOSI 63 DGND P1.6/INT4/MISO 64 DVD D P1.7/INT5/SCK PIN ASSIGNMENTS 57 56 55 54 53 52 51 50 49 XOUT 1 48 EA XIN 2 47 P0.6/AD6 P3.0/RxD0 3 46 P0.7/AD7 P3.1/TxD0 4 45 ALE P3.2/INT0 5 44 PSEN/OSCCLK/MODCLK P3.3/INT1/TONE/PWM 6 43 P2.7/A15 7/A15 P3.4/T0 7 42 DV DD P3.5/T1 8 P3.6/WR 41 DGND MSC1210 MSC1210 9 40 P2.6/A14 6/A14 P3.7/RD 10 39 P2.5/A13 5/A13 DV DD 11 38 P2.4/A12 4/A12 DGND 12 37 P2.3/A11 3/A11 RST 13 36 P2.2/A10 2/A10 DV DD 14 35 P2.1/A09 1/A09 DV DD 15 34 P2.0/A08 0/A08 27 28 29 30 31 32 REF IN+ NC AIN4 26 REF OUT AIN3 25 AVD D AIN2 24 REF IN AIN1 23 AGND 22 AINCOM 21 AIN7/EXTA 20 AIN5 19 AIN6/EXTD 18 - 17 AIN0 33 NC AGND NC 16 PIN DESCRIPTIONS PIN # NAME DESCRIPTION 1 XOUT The crystal oscillator pin XOUT supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XOUT serves as the output of the crystal amplifier. 2 XIN 3-10 P3.0-P3.7 The crystal oscillator pin XIN supports parallel resonant AT cut fundamental frequency crystals and ceramic resonators. XIN can also be an input if there is an external clock source instead of a crystal. Port 3 is a bidirectional I/O port. The alternate functions for Port 3 are listed below. PORT P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 11, 14, 15, 42, 58 ALTERNATE RxD0 TxD0 INT0 INT1/TONE/PWM T0 T1 WR RD MODE Serial Port 0 Input Serial Port 0 Output External Interrupt 0 External Interrupt 1/TONE/PWM Output Timer 0 External Input Timer 1 External Input External Data Memory Write Strobe External Data Memory Read Strobe 12, 41, 57 DVDD DGND Digital Power Supply 13 RST A HIGH on the reset input for two tOSC periods will reset the device. 16, 32, 33 NC No Connection 17, 27 AGND Analog Ground 18 AIN0 Digital Ground Analog Input Channel 0 11 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 PIN DESCRIPTIONS (Continued) PIN # 19 20 21 22 23 24 25 26 NAME AIN1 AIN2 AIN3 AIN4 AIN5 AIN6, EXTD AIN7, EXTA AINCOM 28 29 30 31 34-40, 43 AVDD REF IN- REF IN+ REFOUT P2.0-P2.7 DESCRIPTION Analog Input Channel 1 Analog Input Channel 2 Analog Input Channel 3 Analog Input Channel 4 Analog Input Channel 5 Analog Input Channel 6, Digital Low Voltage Detect Input, Generates DLVD Interrupt Analog Input Channel 7, Analog Low Voltage Detect Input, Generates ALVD Interrupt Analog Common for Single-Ended Inputs or Analog Input for Differential Inputs Analog Power Supply Voltage Reference Negative Input (must be tied to AGND for internal VREF) Voltage Reference Positive Input Voltage Reference Output (tie to REFIN+ for internal VREF use) Port 2 is a bidirectional I/O port. The alternate functions for Port 2 are listed below. Refer to P2DDR, SFR B1H-B2H. PORT P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 44 PSEN OSCCLK MODCLK ALTERNATE A8 A9 A10 A11 A12 A13 A14 A15 MODE Address Bit 8 Address Bit 9 Address Bit 10 Address Bit 11 Address Bit 12 Address Bit 13 Address Bit 14 Address Bit 15 Power Store Enable: Connected to optional external memory as a chip enable. PSEN will provide an active low pulse. In programming mode, PSEN is used as an input along with ALE to define serial or parallel programming mode. PSEN is held HIGH for parallel programming mode and LOW for serial programming. This pin can also be selected (when not using external memory) to output the Oscillator clock, Modulator clock, HIGH, or LOW. Care should be taken so that loading on this pin should not inadvertently cause the device to enter programming mode. ALE NC 0 NC 0 PSEN NC NC 0 0 PROGRAM MODE SELECTION DURING RESET Normal Operation (user application mode) Parallel Programming Serial Programming Reserved 45 ALE Address Latch Enable: Used for latching the low byte of the address during an access to external memory. ALE is emitted at a constant rate of 1/4 the oscillator frequency, and can be used for external timing or clocking. One ALE pulse is skipped during each access to external data memory. In programming mode, ALE is used as an input along with PSEN to define serial or parallel programming mode. ALE is held HIGH for parallel programming mode and LOW for parallel programming. This pin can also be selected (when not using external memory) to output HIGH or LOW. Care should be taken so that loading on this pin should not inadvertently cause the device to enter programming mode. 48 EA External Access Enable: EA must be externally held LOW at the end of RESET to enable the device to fetch code from external program memory locations starting with 0000H 0000H. No internal pull-up on this pin. 46, 47, 49-54 P0.0-P0.7 Port 0 is a bidirectional I/O port. The alternate functions for Port 0 are listed below. P1.0-P1.7 PORT ALTERNATE MODE P0.0 AD0 Address/Data Bit 0 P0.1 AD1 Address/Data Bit 1 P0.2 AD2 Address/Data Bit 2 P0.3 AD3 Address/Data Bit 3 P0.4 AD4 Address/Data Bit 4 P0.5 AD5 Address/Data Bit 5 P0.6 AD6 Address/Data Bit 6 P0.7 AD7 Address/Data Bit 7 Port 1 is a bidirectional I/O port. The alternate functions for Port 1 are listed below. Refer to P1DDR, SFR AEH-AFH. 55, 56, 59-64 PORT P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 12 ALTERNATE T2 T2EX RxD1 TxD1 INT2/SS INT3/MOSI INT4/MISO INT5/SCK MODE T2 Input T2 External Input Serial Port Input Serial Port Output External Interrupt/Slave Select External Interrupt/Master Out-Slave In External Interrupt/Master In-Slave Out External Interrupt/Serial Clock MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fDATA = 10Hz, Buffer ON, and VREF = (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 PGA2 PGA1 PGA1 PGA8 PGA32 PGA32 PGA64 PGA64 PGA8 20 PGA128 PGA128 PGA4 21 19 ENOB (rms) ENOB (rms) EFFECTIVE NUMBER OF BITS vs DATA RATE 23 22 21 20 19 18 17 16 15 14 13 12 11 10 18 PGA16 PGA16 17 PGA32 PGA32 PGA64 PGA64 16 15 14 Sinc3 Filter, Buffer OFF 1 10 Sinc3 Filter, Buffer OFF 13 100 Data Rate (SPS) 12 1000 0 500 1000 1500 EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 22 PGA2 PGA1 PGA8 PGA4 21 PGA1 20 19 19 ENOB (rms) 20 ENOB (rms) fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO PGA8 PGA4 PGA2 21 2000 fMOD Decimation Ratio = 18 17 PGA128 PGA128 PGA64 PGA64 PGA32 PGA32 16 PGA16 PGA16 18 17 PGA16 PGA16 PGA32 PGA32 PGA128 PGA128 PGA64 PGA64 16 15 15 14 14 Sinc3 Filter, Buffer ON AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer OFF 13 13 12 12 0 500 1000 1500 Decimation Ratio = 2000 0 500 f MOD 1000 1500 Decimation Ratio = fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 2000 f MOD fDATA EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 22 22 PGA2 21 PGA4 PGA2 PGA8 21 PGA1 PGA4 PGA8 PGA1 20 19 19 ENOB (rms) 20 ENOB (rms) PGA128 PGA128 18 17 16 PGA16 PGA16 15 PGA32 PGA32 PGA128 PGA128 PGA64 PGA64 18 17 PGA32 PGA32 PGA16 PGA16 PGA64 PGA64 15 14 14 AVDD = 3V, Sinc3 Filter, VREF = 1.25V, Buffer ON 13 PGA128 PGA128 16 Sinc2 Filter 13 12 12 0 500 1000 Decimation Ratio = 1500 fMOD fDATA 2000 0 500 1000 Decimation Ratio = 1500 2000 fMOD fDATA 13 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fDATA = 10Hz, Buffer ON, and VREF = (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) FAST SETTLING FILTER EFFECTIVE NUMBER OF BITS vs DECIMATION RATIO 25 22 21 fMOD = 203kHz 20 20 ENOB (rms) ENOB (rms) 19 18 17 16 fMOD = 15.6kHz fMOD = 110kHz 15 fMOD = 31.25kHz 10 15 14 5 Fast Settling Filter fMOD = 62.5kHz 13 0 12 0 500 1500 1000 Decimation Ratio = 1 2000 10 100k 1.5 2.5 NOISE vs INPUT SIGNAL 0.8 DEC = 2020 DEC = 500 0.7 DEC = 50 DEC = 255 15 Noise (rms, ppm of FS) 20 ENOB (rms) 10k fDATA EFFECTIVE NUMBER OF BITS vs fMOD (set with ACLK) WITH FIXED DECIMATION 25 100 1k Data Rate (SPS) fMOD DEC = 20 10 5 DEC = 10 100 1k Data Rate (SPS) 10k 0.5 0.4 0.3 0.2 0.1 0 -2.5 0 10 0.6 100k -1.5 -0.5 0.5 VIN (V) GAIN vs TEMPERATURE OFFSET vs TEMPERATURE 1.00010 50 PGA16 PGA16 PGA1 1.00006 Gain (Normalized) Offset (ppm of FS) 0 -50 PGA64 PGA64 -100 0.99994 0.99990 0.99986 -50 -30 -10 10 30 Temperature (°C) 14 0.99998 PGA128 PGA128 -150 -200 1.00002 50 70 90 -50 -30 -10 10 30 Temperature (°C) 50 70 90 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fDATA = 10Hz, Buffer ON, and VREF = (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. INTEGRAL NON-LINEARITY vs INPUT SIGNAL INTEGRAL NON-LINEARITY vs INPUT SIGNAL 10 30 VREF = AVDD, Buffer OFF 8 -40 °C 4 2 INL (ppm of FS) INL (ppm of FS) 6 20 +85 °C 0 -2 +25 °C -4 -6 10 0 -10 -20 -8 -10 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 -30 2.5 VIN = -VREF 0 VIN (V) ADC INTEGRAL NONLINEARITY vs VREF INL ERROR vs PGA 35 100 VIN = VREF Buffer OFF 30 AVDD = 3V 90 80 25 INL (ppm of FS) ADC INL (ppm of FS) VIN = +VREF VIN (V) 20 AVDD = 5V 15 10 70 60 50 40 30 20 5 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 5.0 5.5 1 2 4 8 VREF (V) 2.4 2.3 64 128 64 128 900 +85°C PGA = 128, ADC ON, Brownout Detect ON, All VDACs ON = FFFFH , VDACs REF = AVDD AVDD = 5V, Buffer = ON 800 Buffer = OFF +25°C 700 600 2.2 -40°C 2.1 2.0 1.9 IADC (µ A) Analog Supply Current (mA) 2.5 32 ADC CURRENT vs PGA MAXIMUM ANALOG SUPPLY CURRENT 2.6 16 PGA Setting 500 AVDD = 3V, Buffer = ON 400 Buffer = OFF 300 1.8 200 1.7 100 1.6 0 1.5 2.5 3.0 3.5 4.0 4.5 Analog Supply Voltage (V) 5.0 5.5 0 1 2 4 8 16 32 PGA Setting 15 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fDATA = 10Hz, Buffer ON, and VREF = (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. HISTOGRAM OF OUTPUT DATA VREFOUT vs LOAD CURRENT 2.508 3500 2.506 3000 2.504 VREFOUT (V) 2.510 4000 Number of Occurrences 4500 2500 2000 1500 2.502 2.500 2.498 2.496 1000 2.494 500 2.492 0 -2 -1.5 -1 -0.5 2.490 0 0.5 1 1.5 2 0 0.4 ppm of FS 0.8 1.2 1.6 2.0 2.4 VREFOUT Current Load (mA) OFFSET DAC: GAIN vs TEMPERATURE OFFSET DAC: OFFSET vs TEMPERATURE 1.00006 10 8 1.00004 4 Normalized Gain Offset (ppm of FSR) 6 2 0 -2 -4 -6 -8 1.00002 1 0.99998 0.99996 -10 -12 0.99994 -40 +25 +85 -40 +25 Temperature (°C) Temperature (°C) DIGITAL CURRENT vs FREQUENCY DIGITAL STOP CURRENT vs FREQUENCY with EXT CLOCK 100 RUN Digital Current (µA) Supply Current (mA) 100 10 IDLE 1 0.1 0.1 1 10 Clock Frequency (MHz) 16 +85 100 10 1 0.1 0 10 20 Clock Frequency (MHz) 30 40 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 TYPICAL CHARACTERISTICS (Continued) AVDD = +5V, DVDD = +5V, fOSC = 8MHz, PGA = 1, fDATA = 10Hz, Buffer ON, and VREF = (REF IN+) - (REF IN-) = +2.5V, unless otherwise specified. NORMALIZED GAIN vs PGA DIGITAL SUPPLY CURRENT vs SUPPLY VOLTAGE 101 +85°C 100 Normalized Gain (%) 15 -40°C +25°C 10 5 99 98 97 Buffer = ON 0 96 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1 2 4 8 16 32 64 128 PGA Setting Supply Voltage (V) CMOS DIGITAL OUTPUT 5.0 4.5 5V Low Output 4.0 Output Voltage (V) Digital Supply Current (mA) 20 3.5 3V Low Output 3.0 2.5 2.0 1.5 5V 1.0 0.5 3V 0 0 10 20 30 40 50 60 70 Output Current (mA) 17 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 DESCRIPTION core, given the same clock source. That makes it possible to run the device at a lower external clock frequency and achieve the same performance at lower power than the standard 8051 core. The MSC1210Yx is a completely integrated family of mixed-signal devices incorporating a high-resolution delta-sigma ADC, 8-channel multiplexer, burnout current sources, selectable buffered input, offset DAC (Digital-to-Analog Converter), Programmable Gain Amplifier (PGA), temperature sensor, voltage reference, 8-bit microcontroller, Flash Program Memory, Flash Data Memory, and Data SRAM, as shown in Figure 8. The MSC1210Yx allows the user to uniquely configure the Flash and SRAM memory maps to meet the needs of their application. The Flash is programmable down to 2.7V using both serial and parallel programming methods. The Flash endurance is 1 million Erase/Write cycles. In addition, 1280 bytes of RAM are incorporated on-chip. On-chip peripherals include an additional 32-bit accumulator, an SPI-compatible serial port, dual USARTs, multiple digital input/output ports, watchdog timer, low-voltage detect, on-chip power-on reset, 16-bit PWM, and system timers, brownout reset, and three timer/counters. The part has separate analog and digital supplies, which can be independently powered from 2.7V to +5.5V. At +3V operation, the power dissipation for the part is typically less than 4mW. The MSC1210Yx is packaged in a TQFP-64 TQFP-64 package. The device accepts low-level differential or single-ended signals directly from a transducer. The ADC provides 24 bits of resolution and 24 bits of no-missing-code performance using a Sinc3 filter with a programmable sample rate. The ADC also has a selectable filter that allows for high-resolution single-cycle conversion. The MSC1210Yx is designed for high-resolution measurement applications in smart transmitters, industrial process control, weigh scales, chromatography, and portable instrumentation. The microcontroller core is 8051 instruction set compatible. The microcontroller core is an optimized 8051 core that executes up to three times faster than the standard 8051 AVDD AGND REF OUT REF IN+ (1) REF IN- DVD D DGND +AVDD LVD VR EF Timers/ Counters EA ALE PSEN BOR Temperature Sensor AIN0 8- Bit PGA Offset WDT REF AIN1 Alternate Functions AIN2 PORT0 BUFFER PGA Modulator Up to 32K FLASH AINCOM 8 ADDR 8 UART1 EXT T0 T1 RW ACC 1.2K SRAM AIN7 T2 SPI/EXT UART2 Digital Filter AIN5 AIN6 8 PORT2 MUX ADDR DATA PORT3 AIN4 8 PORT1 AIN3 8051 SFR Clock Generator SPI RST POR AGND XIN XOUT NOTE: (1) REF IN- needs to be tied to AGND when using internal VREF. Figure 8. Block Diagram 18 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 CLK instr_cycle cpu_cycle n+1 C1 C2 n+2 C3 C4 C1 C2 C3 C4 C1 Figure 9. Instruction Timing Cycle Therefore, a device frequency of 33MHz for the MSC1210Yx actually performs at an equivalent execution speed of 82.5MHz compared to the standard 8051 core. This allows the user to run the device at slower external clock speeds which reduces system noise and power consumption, but provides greater throughput. This performance difference can be seen in Figure 10. The timing of software loops will be faster with the MSC1210 MSC1210. However, the timer/counter operation of the MSC1210 MSC1210 may be maintained at 12 clocks per increment or optionally run at 4 clocks per increment. Additionally, it can stretch the number of memory cycles to access external Data Memory from between two and nine instruction cycles in order to accommodate different speeds of memory or devices, as shown in Table 1. The MSC1210 MSC1210 provides an external memory interface with a 16-bit address bus (P0 and P2). The 16-bit address bus makes it necessary to multiplex the low address byte through the P0 port. To enhance P0 and P2 for high-speed memory access, hardware configuration control is provided to configure the ports for external memory/peripheral interface or general-purpose I/O. Furthermore, improvements were made to peripheral features that off-load processing from the core, and the user, to further improve efficiency. For instance, the SPI interface uses double buffering, which allows the SPI interface to transmit and receive data with minimum overhead needed from the core. Also, a 32-bit accumulator was added to significantly reduce the CKCON (8EH) MD2:MD0 INSTRUCTION CYCLES (for MOVX) RD or WR STROBE WIDTH (SYS CLKs) RD or WR STROBE WIDTH (ms) AT 12MHz 000 2 2 0.167 001 3 (default) 4 0.333 010 4 8 0.667 011 5 12 1.000 100 6 16 1.333 101 7 20 1.667 110 8 24 2.000 111 9 28 2.333 Single-Byte, Single-Cycle Instruction ALE PSEN 0 The MSC1210 MSC1210 also provides dual data pointers (DPTRs) to speed block Data Memory moves. Table 1. Memory Cycle Stretching. Stretching of MOVX timing as defined by MD2, MD1, and MD0 bits in CKCON register (address 8EH). MSC121 MSC121 Timing All instructions in the MSC1210 MSC1210 family perform exactly the same functions as they would in a standard 8051. The effect on bits, flags, and registers is the same. However, the timing is different. The MSC1210 MSC1210 family utilizes an efficient 8051 core which results in an improved instruction execution speed of between 1.5 and 3 times faster than the original core for the same external clock speed (4 clock cycles per instruction versus 12 clock cycles per instruction, as shown in Figure 9). The internal system clock is equal to the external oscillator frequency. This translates into an effective throughput improvement of more than 2.5 times, using the same code and same external clock speed. processing overhead for the multiple byte data from the ADC or other sources. This allows for 32-bit addition and shifting to be accomplished in a few instruction cycles, compared to hundreds of instruction cycles through a software implementation. AD0- AD7 PORT 2 4 Cycles CLK 12 Cycles Standard 8051 Timing ENHANCED 8051 CORE ALE PSEN AD0- AD7 PORT 2 Single-Byte, Single-Cycle Instruction Figure 10. Comparison of MSC1210 MSC1210 Timing to Standard 8051 Timing 19 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 Family Device Compatibility OVERVIEW The hardware functionality and pin configuration across the MSC1210 MSC1210 family is fully compatible. To the user the only difference between family members is the memory configuration. This makes migration between family members simple. Code written for the MSC1210Y2 MSC1210Y2 can be executed directly on an MSC1210Y3 MSC1210Y3, MSC1210Y4 MSC1210Y4, or MSC1210Y5 MSC1210Y5. This gives the user the ability to add or subtract software functions and to freely migrate between family members. Thus, the MSC1210 MSC1210 can become a standard device used across several application platforms. The MSC1210 MSC1210 ADC structure is shown in Figure 11. The figure lists the components that make up the ADC, along with the corresponding special function register (SFR) associated with each component. INPUT MULTIPLEXER The input multiplexer provides for any combination of differential inputs to be selected as the input channel, as shown in Figure 12. If AIN0 is selected as the positive differential input channel, any other channel can be selected as the negative differential input channel. With this method, it is possible to have up to eight fully differential input channels. It is also possible to switch the polarity of the differential input pair to negate any offset voltages. Family Development Tools The MSC1210 MSC1210 is fully compatible with the standard 8051 instruction set. This means that the user can develop software for the MSC1210 MSC1210 with their existing 8051 development tools. Additionally, a complete, integrated development environment is provided with each demo board, and third-party developers also provide support. In addition, current sources are supplied that will source or sink current to detect open or short circuits on the pins. TEMPERATURE SENSOR Power Down Modes On-chip diodes provide temperature sensing capability. When the configuration register for the input MUX is set to all 1s, the diodes are connected to the input of the ADC. All other channels are open. The MSC1210 MSC1210 can power several of the on-chip peripherals and put the CPU into IDLE. For more information, see page 24. AV DD AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AINCOM Burnout Detect REFIN+ fSA M P Input Multiplexer In+ Sample and Hold Buffer In- PGA Temperature Sensor Burnout Detect D7 H ADMUX REFIN+ f MO D Offset DAC REFIN- AGND DC H ADC0N0 F6 H ACLK E6H ODAC fDA TA FAST V IN ADC Modulator SINC2 X Offset Calibration Register SINC3 ADC Result Register Gain Calibration Register AUTO REFIN- Summation Block DD H ADCON1 OCR GCR ADRES DEH ADCON2 D3H D2 H D1 H D6H D5H D4 H DBH DA H D9 H DFH ADCON3 SUMR E5 H E4 H E3 H E2H E1H Figure 11. MSC1210 MSC1210 ADC Structure 20 SSCON MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 power-supply current is higher. If the limitation of input voltage range is acceptable, then the buffer is always preferred. AIN 0 AIN 1 The input impedance of the MSC1210 MSC1210 without the buffer is 7M/PGA. The buffer is controlled by the state of the BUF bit in the ADC control register (ADCON0 DCH). AV D D Burnout Detect Current Source ANALOG INPUT AIN 2 When the buffer is not selected, the input impedance of the analog input changes with ACLK clock frequency (ACLK F6H) and gain (PGA). The relationship is: AIN 3 In+ AIN Impedance(W) + AIN 4 1 ACLK Frequency @ 7MW PGA In- where ACLK frequency + AIN 5 Burnout Detect Current Sink AIN 6 and modclk + f MOD + 80 · I f ACLK . 64 NOTE: The input impedance for PGA = 128 is the same as that for 7MW PGA = 64 ( that is, ). 64 Temperature Sensor AGND AIN 7 f OSC (ACLK)1) I Figure 13 shows the basic input structure of the MSC1210 MSC1210. AIN CO M Rswitch (3k typical) High Impedance > 1G AIN CS (9pF typical) Figure 12. Input Multiplexer Configuration BURNOUT DETECT When the Burnout Detect (BOD) bit is set in the ADC control configuration register (ADCON0 DCH), two current sources are enabled. The current source on the positive input channel sources approximately 2µA of current. The current source on the negative input channel sinks approximately 2µA. This allows for the detection of an open circuit (full-scale reading) or short circuit (small differential reading) on the selected input differential pair. Buffer should be on for sensor burnout detection. INPUT BUFFER The analog input impedance is always high, regardless of PGA setting (when the buffer is enabled). With the buffer enabled, the input voltage range is reduced and the analog Sampling Frequency = fSAMP PGA fSAMP 1, 2, 4 modclk 8 2 * modclk 16 4 * modclk 32 8 * modclk 64, 128 16 * modclk PGA 1 2 4 to 128 AGND CS 9pF 18pF 36pF Figure 13. Analog Input Structure MODULATOR The modulator is a single-loop 2nd-order system. The modulator runs at a clock speed (fMOD) that is derived from the CLK using the value in the Analog Clock (ACLK) register (SFR F6H). The data rate is: Data Rate + f MOD Decimation Ratio where f MOD + f OSC (ACLK)1) @ 64 21 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 PGA The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128. Using the PGA can actually improve the effective resolution of the ADC. For instance, with a PGA of 1 on a ±2.5V full-scale range, the ADC can resolve to 1.5µV. With a PGA of 128 on a ±19mV full-scale range, the ADC can resolve to 75nV, as shown in Table 2. Table 2. Sampling Frequency versus PGA Setting RMS PGA FULL-SCALE ENOB MEASUREMENT SETTING RANGE (V) AT 10HZ RESOLUTION (nV) 1 2 4 8 16 32 64 128 ±2.5V ±1.25 ±0.625 ±0.313 ±0.156 ±0.0781 ±0.039 ±0.019 21.7 21.5 21.4 21.2 20.8 20.4 20 19 1468 843 452 259 171 113 74.5 74.5 Calibration should be performed after power on, a change in temperature, decimation ratio, buffer, or a change of the PGA. Calibration will remove the effects of the Offset DAC; therefore, changes to the Offset DAC register must be done after calibration. At the completion of calibration, the ADC Interrupt bit goes HIGH which indicates the calibration is finished and valid data is available. DIGITAL FILTER The Digital Filter can use either the Fast Settling, Sinc2, or Sinc3 filter, as shown in Figure 14. In addition, the Auto mode changes the Sinc filter after the input channel or PGA is changed. When switching to a new channel, it will use the Fast Settling filter for the next two conversions (the first of which should be discarded). It will then use the Sinc2 followed by the Sinc3 filter to improve noise performance. Adjustable Digital Filter Sinc3 OFFSET DAC The analog input to the PGA can be offset by up to half the full-scale input range of the PGA by using the ODAC register (SFR E6H). The ODAC (Offset DAC) register is an 8-bit value; the MSB is the sign and the seven LSBs provide the magnitude of the offset. Since the ODAC introduces an analog (instead of digital) offset to the PGA, using the ODAC does not reduce the range of the ADC. CALIBRATION The offset and gain errors in the MSC1210 MSC1210, or the complete system, can be reduced with calibration. Calibration is controlled through the ADCON1 register (SFR DDH), bits CAL2:CAL0. Each calibration process takes seven tDATA (data conversion time) periods to complete. Therefore, it takes 14 tDATA periods to complete both an offset and gain calibration. For system calibration, the appropriate signal must be applied to the inputs. The system offset command requires a "zero" differential input signal. It then computes an offset value that will nullify offsets in the system. The system gain command requires a positive "full-scale" differential input signal. It then computes a value to nullify gain errors in the system. Each of these calibrations will take seven tDATA periods to complete. 22 Modulator Sinc2 Data Out Fast Settling FILTER SETTLING TIME SETTLING TIME FILTER (Conversion Cycles)(1) Sinc3 3 Sinc2 2 Fast 1 NOTE: (1) MUX change may add one cycle. AUTO MODE FILTER SELECTION CONVERSION CYCLE 1 2 3 Discard Fast Sinc2 4 Sinc3 Figure 14. Filter Step Responses This combines the low-noise advantage of the Sinc3 filter with the quick response of the Fast Settling Time filter. The frequency response of each filter is shown in Figure 15. MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 VOLTAGE REFERENCE The voltage reference used for the MSC1210 MSC1210 can be either internal or external. The power-up configuration for the voltage reference is 2.5V internal. The selection for the voltage reference is made through the ADCON0 register (SFR DCH). The internal voltage reference is selectable as either 1.25V (AVDD = 2.7V to 5.25V) or 2.5V (AVDD = 3.3V to 5.25V). If the internal VREF is not used, it should be turned off. The VREFOUT pin should have a 0.1µF capacitor to AGND. The external voltage reference is differential and is represented by the voltage difference between the pins: REF IN+ and REF IN­. The absolute voltage on either pin (REF IN+ and REF IN­) can range from AGND to AVDD. The differential voltage reference provides easy means of performing ratiometric measurement. POWER-UP-SUPPLY VOLTAGE RAMP RATE The built-in (on-chip) power-on reset circuitry was designed to accommodate analog or digital supply ramp rates as slow as 1V/10ms. To ensure proper operation, the power supply should ramp monotonically at the specified rate. If power-on reset (POR) is enabled, the ramp rate can be slower. SINC3 FILTER RESPONSE (-3dB = 0.262 · f DATA) SINC 2 FILTER RESPONSE (-3dB = 0.318 · fDATA) -20 -40 -40 Gain (dB) 0 -20 -60 -80 -60 -80 -100 -100 -120 -120 0 1 2 3 4 5 0 1 2 fDATA 3 4 5 fDATA FAST SETTLING FILTER RESPONSE (-3dB = 0.469 · f DATA) 0 -20 -40 Gain (dB) Gain (dB) 0 -60 -80 -100 -120 0 1 2 3 4 5 fDATA NOTE: f DATA = Data Output Rate = 1/tDATA Figure 15. Filter Frequency Responses 23 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 POWER-DOWN MODES The MSC1210 MSC1210 can power several of the on-chip peripherals and put the CPU into IDLE. This is accomplished by shutting off the clocks to those sections, as shown in Figure 16. For lowest power, be sure that the FRCM bit in FMCON is set. SYS Clock STOP Oscillator SPICON/ I2CCON 9A tC LK SCK PDCON.0 PWMHI A3 PWM Clock PWMLOW A2 PDCON.4 µs USEC FTCON Flash Write (30µs to 40µs) [3:0] EF Timing FB ms MSECH MSECL FD FC Flash Erase (5ms to 11ms) Timing FTCON [7:4] EF milliseconds interrupt MSINT FA PDCON.1 seconds interrupt SECINT F9 100ms HMSEC WDTCON FF FE watchdog hardware configuration bits, which disables erase and writes to 4kB of Program Flash Memory or the entire Program Flash Memory in user application mode. The MSC1210 MSC1210 includes 1kB of SRAM on-chip. SRAM starts at address 0 and is accessed through the MOVX instruction. This SRAM can also be located to start at 8400H 8400H and can be accessed as both Program and Data Memory. FLASH MEMORY The MSC1210 MSC1210 uses a memory addressing scheme that separates Program Memory (FLASH/ROM) from Data Memory (FLASH/RAM). Each area is 64kB beginning at address 0000H 0000H and ending at FFFFH, as shown in Figure 17. The program and data segments can overlap since they are accessed in different ways. Program Memory is fetched by the microcontroller automatically. There is one instruction (MOVC) that is used to explicitly read the program area. This is commonly used to read lookup tables. PDCON.2 divide by 64 ADC Power Down ADCON3 ADCON2 DF DE Decimation Ratio ADCON0 PDCON.3 DC Program Memory ADC Output Rate fS AM P (see Figure 13) USART0/1 CPU Clock S elect in M CO N Timers 0/1/2 F FF F H F FF F H F 80 0 H External Program Memory fM O D IDLE 2 k In tern al Boo t R O M Data Memory 1 k RA M or Ex te rna l Exte rn al M e mo ry 88 00 H 84 00 H 80 00 H , 3 2k (Y 5) 40 00 H , 1 6k (Y 4) Figure 16. MSC1210 MSC1210 Timing Chain and Clock Control MEMORY MAP The MSC1210 MSC1210 contains on-chip SFR, Flash Memory, Scratchpad SRAM Memory, Boot ROM, and SRAM. THe SFR registers are primarily used for control and status. The standard 8051 features and additional peripheral features of the MSC1210 MSC1210 are controlled through the SFR. Reading from an undefined SFR and writing to undefined SFR registers is not recommended, and will have indeterminate effects. Flash Memory is used for both Program Memory and Data Memory. The user has the ability to select the partition size of Program and Data Memories. The partition size is set through hardware configuration bits, which are programmed through either the parallel or serial programming methods. Both Program and Data Flash Memories are erasable and writable (programmable) in user application mode. However, program execution can only occur from Program Memory. As an added precaution, a lock feature can be activated through the 24 On-Chip Flash External Data Memory M a pp ed to B oth M em ory S p ace s (von Ne um a nn ) 20 00 H , 8 k (Y3 ) 1k R AM o r E xtern al S elect in MC ON F6 S e le ct in HC R 0 ACLK 44 0 0 H , 17 k (Y4 ) On-Chip Flash 24 0 0 H , 9k (Y 3) 14 0 0 H , 5k (Y 2) 10 00 H , 4 k (Y2 ) 00 00 H , 0 k 88 0 0 H 84 0 0 H , 33 k (Y5 ) 1k R AM o r E xtern al 04 0 0 H , 1k Figure 17. Memory Map The Data Memory area is accessed explicitly using the MOVX instruction. This instruction provides multiple ways of specifying the target address. It is used to access the 64kB of Data Memory. The address and data range of devices with on-chip Program and Data Memory overlap the 64kB memory space. When on-chip memory is enabled, accessing memory in the on-chip range will cause the device to access internal memory. Memory accesses beyond the internal range will be addressed externally via Ports 0 and 2. The MSC1210 MSC1210 has two Hardware Configuration registers (HCR0 and HCR1) that are programmable only during Flash Memory Programming mode. MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 The MSC1210 MSC1210 allows the user to partition the Flash Memory between Program Memory and Data Memory. For instance, the MSC1210Y5 MSC1210Y5 contains 32kB of Flash Memory on-chip. Through the HW configuration registers, the user can define the partition between Program Memory (PM) and Data Memory (DM), as shown in Table 3 and Table 4. The MSC1210 MSC1210 family offers four memory configurations, as shown. Table 3. MSC1210 MSC1210 Flash Partitioning HCR0 MSC1210Y2 MSC1210Y2 MSC1210Y3 MSC1210Y3 MSC1210Y4 MSC1210Y4 MSC1210Y5 MSC1210Y5 DFSEL PM DM PM DM PM DM PM DM 000 0kB 4kB 0kB 8kB 0kB 16kB 0kB 32kB 001 0kB 4kB 0kB 8kB 0kB 16kB 0kB 32kB 010 0kB 4kB 0kB 8kB 0kB 16kB 16kB 16kB 011 0kB 4kB 0kB 8kB 8kB 8kB 24kB 8kB 100 0kB 4kB 4kB 4kB 12kB 4kB 28kB 4kB 101 2kB 2kB 6kB 2kB 14kB 2kB 30kB 2kB 110 3kB 1kB 7kB 1kB 15kB 1kB 31kB 1kB 111 (default) 4kB 0kB 8kB 0kB 16kB 0kB 32kB 0kB NOTE: When a 0kB program memory configuration is selected, program execution is external. Table 4. MSC1210 MSC1210 Flash Memory Partitioning HCR0 MSC1210Y3 MSC1210Y3 MSC1210Y4 MSC1210Y4 DFSEL MSC1210Y2 MSC1210Y2 PM DM PM DM PM DM MSC1210Y5 MSC1210Y5 PM DM 000 0000 040013FF 040013FF 0000 040023FF 040023FF 0000 040043FF 040043FF 0000 000083FF 000083FF 001 0000 040013FF 040013FF 0000 040023FF 040023FF 0000 040043FF 040043FF 0000 040083FF 040083FF 010 0000 040013FF 040013FF 0000 040023FF 040023FF 0000 040043FF 040043FF 00003FFF 00003FFF 040043FF 040043FF 011 0000 040013FF 040013FF 0000 040023FF 040023FF 00001FFF 00001FFF 040023FF 040023FF 00005FFF 00005FFF 040023FF 040023FF 100 0000 040013FF 040013FF 00000FFF 00000FFF 040013FF 040013FF 00002FFF 00002FFF 040013FF 040013FF 00006FFF 00006FFF 040013FF 040013FF 101 000007FF 000007FF 04000BFF 04000BFF 000017FF 000017FF 04000BFF 04000BFF 000037FF 000037FF 04000BFF 04000BFF 000077FF 000077FF 04000BFF 04000BFF 110 00000BFF 00000BFF 040007FF 040007FF 00001BFF 00001BFF 040007FF 040007FF 00003BFF 00003BFF 040007FF 040007FF 00007BFF 00007BFF 040007FF 040007FF 111 (default) 00000FFF 00000FFF 0000 00001FFF 00001FFF 0000 00003FFF 00003FFF 0000 00007FFF 00007FFF 0000 NOTE: Program memory accesses above the highest listed address will access external program memory. It is important to note that the Flash Memory is readable and writable by the user through the MOVX instruction when configured as either Program or Data Memory (via the MXWS bit in the MWS, SFR 8FH). This means that the user may partition the device for maximum Flash Program Memory size (no Flash Data Memory) and use Flash Program Memory as Flash Data Memory. This may lead to undesirable behavior if the PC points to an area of Flash Program Memory that is being used for data storage. Therefore, it is recommended to use Flash partitioning when Flash Memory is used for data storage. Flash partitioning prohibits execution of code from Data Flash Memory. Additionally, the Program Memory erase/write can be disabled through hardware configuration bits (HCR0), while still providing access (read/write/erase) to Data Flash Memory. The effect of memory mapping on Program and Data Memory is straightforward. The Program Memory is decreased in size from the top of internal Program Memory. Therefore, if the MSC1210Y5 MSC1210Y5 is partitioned with 31kB of Flash Program Memory and 1kB of Flash Data Memory, external Program Memory execution will begin at 7C00H 7C00H (versus 8000H 8000H for 32kB). The Flash Data Memory is added on top of the SRAM memory. Therefore, access to Data Memory (through MOVX) will access SRAM for addresses 0000H-03FFH 0000H-03FFH and access Flash Memory for addresses 0400H-07FFH 0400H-07FFH. Data Memory The MSC1210 MSC1210 can address 64kB of Data Memory. Scratchpad Memory provides 256 bytes in addition to the 64kB of Data Memory. The MOVX instruction is used to access the Data SRAM Memory. This includes 1,024 bytes of on-chip Data SRAM Memory. The data bus values do not appear on Port 0 (during data bus timing) for internal memory access. The MSC1210 MSC1210 also has on-chip Flash Data Memory which is readable and writable (depending on Memory Write Select register) during normal operation (full VDD range). This memory is mapped into the external Data Memory space directly above the SRAM. The MOVX instruction is used to write the flash memory. Flash memory must be erased before it can be written. Flash memory is erased in 128 byte pages. REGISTER MAP The Register Map is illustrated in Figure 18. It is entirely separate from the Program and Data Memory areas mentioned before. A separate class of instructions is used to access the registers. There are 256 potential register locations. In practice, the MSC1210 MSC1210 has 256 bytes of Scratchpad RAM and up to 128 SFRs. This is possible, since the upper 128 Scratchpad RAM locations can only be accessed indirectly. Thus, a direct reference to one of the upper 128 locations must be an SFR access. Direct RAM is reached at locations 0 to 7FH (0 to 127). 25 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 255 FFH 255 Indirect RAM 128 127 80H 128 7FH Direct RAM 0 FFH Direct Special Function Registers FFH Indirect RAM 7FH 80H Direct RAM SFR Registers 2FH 00H 7F 7E 7D 7C 7B 7A 79 78 77 76 75 74 73 72 71 70 2DH 6F 6E 6D 6C 6B 6A 69 68 2CH 67 66 65 64 63 62 61 60 2BH 5F 5E 5D 5C 5B 5A 59 58 SFRs are accessed directly between 80H and FFH (128 to 255). The RAM locations between 128 and 255 can be reached through an indirect reference to those locations. Scratchpad RAM is available for general-purpose data storage. It is commonly used in place of off-chip RAM when the total data contents are small. When off-chip RAM is needed, the Scratchpad area will still provide the fastest general-purpose access. Within the 256 bytes of RAM, there are several special-purpose areas. 2AH 57 56 55 54 53 52 51 50 29H 4F 4E 4D 4C 4B 4A 49 48 28H 47 46 45 44 43 42 41 40 27H 3F 3E 3D 3C 3B 3A 39 38 26H 37 36 35 34 33 32 31 30 25H 2F 2E 2D 2C 2B 2A 29 28 24H 27 26 25 24 23 22 21 20 Bit Addressable Locations 23H 1F 1E 1D 1C 1B 1A 19 18 In addition to direct register access, some individual bits are also accessible. These are individually addressable bits in both the RAM and SFR area. In the Scratchpad RAM area, registers 20H to 2FH are bit addressable. This provides 128 (16 · 8) individual bits available to software. A bit access is distinguished from a full-register access by the type of instruction. In the SFR area, any register location ending in a 0 or 8 is bit addressable. Figure 19 shows details of the on-chip RAM addressing including the locations of individual RAM bits. 22H 17 16 15 14 13 12 11 10 21H 0F 0E 0D 0C 0B 0A 09 08 20H 07 06 05 04 03 02 01 00 Scratchpad RAM Figure 18. Register Map 1FH Bank 3 18H 17H 26 Bank 2 10H 0FH Bank 1 08H 07H Working Registers As part of the lower 128 bytes of RAM, there are four banks of Working Registers, as shown in Figure 19. The Working Registers are general-purpose RAM locations that can be addressed in a special way. They are designated R0 through R7. Since there are four banks, the currently selected bank will be used by any instruction using R0-R7. This allows software to change context by simply switching banks. This is controlled via the Program Status Word register (PSW; 0D0H) in the SFR area described below. Registers R0 and R1 also allow their contents to be used for indirect addressing of the upper 128 bytes of RAM. Thus, an instruction can designate the value stored in R0 (for example) to address the upper RAM. The 16 bytes immediately above the R0-R7 registers are bit addressable. So any of the 128 bits in this area can be directly accessed using bit addressable instructions. Bit Addressable 2EH Bank 0 0000H 0000H MSB LSB Figure 19. Scratchpad Register Addressing Stack Another use of the Scratchpad area is for the programmer's stack. This area is selected using the Stack Pointer (SP; 81H) SFR. Whenever a call or interrupt is invoked, the return address is placed on the Stack. It also is available to the programmer for variables, etc., since the Stack can be moved and there is no fixed location within the RAM designated as Stack. The Stack Pointer will default to 07H on reset. The user can then move it as MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 needed. A convenient location would be the upper RAM area (> 7FH) since this is only available indirectly. The SP will point to the last used value. Therefore, the next value placed on the Stack is put at SP + 1. Each PUSH or CALL will increment the SP by the appropriate value. Each POP or RET will decrement as well. Program Memory After reset, the CPU begins execution from Program Memory location 0000H 0000H. The selection of where Program Memory execution begins is made by tying the EA pin to DVDD for internal access, or DGND for external access. When EA is tied to DVDD, any PC fetches outside the internal Program Memory address occur from external memory. If EA is tied to DGND, then all PC fetches address external memory. The standard internal Program Memory size for MSC1210 MSC1210 family members is shown in Table 5. If enabled the Boot ROM will appear from address F800H F800H to FFFFH. Table 5. MSC1210 MSC1210 Maximum Internal Program Memory Sizes MODEL NUMBER STANDARD INTERNAL PROGRAM MEMORY SIZE (BYTES) MSC1210Y5 MSC1210Y5 32k MSC1210Y4 MSC1210Y4 16k MSC1210Y3 MSC1210Y3 8k MSC1210Y2 MSC1210Y2 4k ACCESSING EXTERNAL MEMORY If external memory is used, P0 and P2 can be configured as address and data lines. If external memory is not used, P0 and P2 can be configured as general-purpose I/O lines through the Hardware Configuration Register. To enable access to external memory bits 0 and 1 of the HCR1 register must be set to 0. When these bits are enabled all memory addresses for both internal and external memory will appear on ports 0 and 2. During the data portion of the cycle for internal memory, Port 0 will be zero for security purposes. Accesses to external memory are of two types: accesses to external Program Memory and accesses to external Data Memory. Accesses to external Program Memory use signal PSEN (program store enable) as the read strobe. Accesses to external Data Memory use RD or WR (alternate functions of P3.7 and P3.6) to strobe the memory. External Program Memory and external Data Memory may be combined if desired by applying the RD and PSEN signals to the inputs of an AND gate and using the output of the gate as the read strobe to the external Program/Data Memory. Program fetches from external Program Memory always use a 16-bit address. Accesses to external Data Memory can use either a 16-bit address (MOVX @DPTR) or an 8-bit address (MOVX @RI). If Port 2 is selected for external memory use (HCR1, bit 0), it cannot be used as general-purpose I/O. This bit (or Bit 1 of HCR1) also forces bits P3.6 and P3.7 to be used for WR and RD instead of I/O. Port 2, P3.6, and P3.7 should all be written to `1.' If an 8-bit address is being used (MOVX @RI), the contents of the MPAGE (92H) SFR remain at the Port 2 pins throughout the external memory cycle. This will facilitate paging. In any case, the low byte of the address is time-multiplexed with the data byte on Port 0. The ADDR/DATA signals use CMOS drivers in the Port 0, Port 2, WR, and RD output buffers. Thus, in this application the Port 0 pins are not open-drain outputs, and do not require external pull-ups for high-speed access. Signal ALE (Address Latch Enable) should be used to capture the address byte into an external latch. The address byte is valid at the negative transition of ALE. Then, in a write cycle, the data byte to be written 27 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 appears on Port 0 just before WR is activated, and remains there until after WR is deactivated. In a read cycle, the incoming byte is accepted at Port 0 just before the read strobe is deactivated. The functions of Port 0 and Port 2 are selected in Hardware Configuration Register 1. This can only be changed during the Flash Program mode. There is no conflict in the use of these registers; they will either be used as general-purpose I/O or for external memory access. The default state is for Port 0 and Port 2 to be used as general-purpose I/O. If an external memory access is attempted when they are configured as general-purpose I/O, the values of Port 0 and Port 2 will not be affected. External Program Memory is accessed under two conditions: 1) Whenever signal EA is LOW during reset, then all future accesses are external; or 2) Whenever the Program Counter (PC) contains a number that is outside of the internal Program Memory address range, if the ports are enabled. If Port 0 and Port 2 are selected for external memory, all 8 bits of Port 0 and Port 2, as well as P3.6 and P3.7, are dedicated to an output function and may not be used for general-purpose I/O. During external program fetches, Port 2 outputs the high byte of the PC. Programming Flash Memory The MSC1210 MSC1210 is shipped with Flash Memory erased (all 1s). Parallel programming methods typically involve a third-party programmer. Serial programming methods typically involve in-system programming. User Application mode allows Flash Program and Data Memory programming. The actual code for Flash programming cannot execute from Flash. That code must execute from the Boot ROM or internal (von Neumann) RAM. Flash Programming Mode There are two programming modes: parallel and serial. The programming mode is selected by the state of the ALE and PSEN signals during power-on reset. Serial programming mode is selected with PSEN = 0 and ALE = 1. Parallel programming mode is selected with PSEN = 1 and ALE = 0 (see Figure 20). If they are both HIGH, the MSC1210 MSC1210 will operate in normal user mode. Both signals LOW is a reserved mode and is not defined. Programming mode is exited with a reset (BOR, WDT, software, or POR) and the normal mode selected. PSEL P2[7] AddrHi[6:0] NC AddrLo[7:0] P1[7:0] Data[7:0] ALE P0[7:0] Cmd[2:0] P3[7:5] P3[4] 1. P3[3] 2. Reset sector (4kB) (not to be confused with the 2kB Boot ROM). 3. Program Memory. 4 Flash Programmer P2[6:0] PSEN There are four sections of Flash Memory for programming. 128 configuration bytes. HOST MSC1210 MSC1210 P3[2] RST Req ACK Pass RST Data Memory. Boot ROM There is a 2kB Boot ROM that controls operation during serial or parallel programming. Additionally, the Boot ROM routines can be accessed during the user mode if it is enabled. When enabled, the Boot ROM routines will be located at memory addresses F800H-FFFFH F800H-FFFFH during user mode. In program mode the Boot ROM is located in the first 2kB of Program Memory. For additional information, refer to the Application Note SBAA085 SBAA085, available for download from the TI web site (www.ti.com). 28 XIN CLK Figure 20. Parallel Programming Configuration The MSC1210 MSC1210 is shipped with Flash Memory erased (all 1s). Parallel programming methods typically involve a third-party programmer. Serial programming methods typically involve in-system programming. User Application mode allows Flash Program and Data Memory programming. The actual code for Flash programming cannot execute from Flash. That code must execute from the Boot ROM, internal (von Neumann) RAM or external memory. MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 INTERRUPTS HARDWARE CONFIGURATION MEMORY The MSC1210 MSC1210 uses a three-priority interrupt system. As shown in Table 6, each interrupt source has an independent priority bit, flag, interrupt vector, and enable (except that nine interrupts share the Auxiliary Interrupt (AI) at the highest priority). In addition, interrupts can be globally enabled or disabled. The interrupt structure is compatible with the original 8051 family. All of the standard interrupts are available. The 128 configuration bytes can only be written during the program mode. The bytes are accessed through SFR registers CADDR (SFR 93H) and CDATA (SFR 94H). Two of the configuration bytes control Flash partitioning and system control. If the security bit is set, these bits can not be changed except with a Mass Erase command that erases all of the Flash Memory including the 128 configuration bytes. Table 6. Interrupt Summary INTERRUPT ADDR 33H NUM 6 PRIORITY HIGH AVDD Low Voltage SPI Receive SPI Transmit Milliseconds Timer ADC Summation Register Seconds Timer External Interrupt 0 Timer 0 Overflow External Interrupt 1 Timer 1 Overflow Serial Port 0 33H 33H 33H 33H 33H 33H 33H 03H 0BH 13H 0BH 23H 6 6 6 6 6 6 6 0 1 2 3 4 0 0 0 0 0 0 0 1 2 3 4 5 Timer 2 Overflow Serial Port 1 2BH 3BH 5 7 6 7 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 Watchdog 43H 4BH 53H 5BH 63H 8 9 10 11 12 8 9 10 11 12 LOW INTERRUPT/EVENT DVDD Low Voltage/HW Breakpoint (1) (2) (3) (4) FLAG EDLVB (AIE.0)(1) EBP (BPCON.0)(1) EALV (AIE.1)(1) ESPIR (AIE.2)(1) ESPIT (AIE.3)(1) EMSEC (AIE.4)(1) EADC (AIE.5)(1) ESUM (AIE.6)(1) ESEC (AIE.7)(1) IE0 (TCON.1)(2) TF0 (TCON.5)(3) IE1 (TCON.3)(2) TF1 (TCON.7)(3) RI_0 (SCON0.0) TI_0 (SCON0.1) TF2 (T2CON.7) RI_1 (SCON1.0) TI_1 (SCON1.1) IE2 (EXIF.4) IE3 (EXIF.5) IE4 (EXIF.6) IE5 (EXIF.7) WDTI (EICON.3) ENABLE EDLVB (AIE.0)(1) EBP (BPCON.0)(1) EALV (AIE.1)(1) ESPIR (AIE.2)(1) ESPIT (AIE.3)(1) EMSEC (AIE.4)(1) EADC (AIE.5)(1) ESUM (AIE.6)(1) ESEC (AIE.7)(1) EX0 (IE.0)(4) ET1 (IE.1)(4) EX1 (IE.2)(4) ET1 (IE.3)(4) ES0 (IE.4)(4) PRIORITY CONTROL N/A N/A N/A N/A N/A N/A N/A N/A PX0 (IP.0) PT0 (IP.1) PX1 (IP.2) PT1 (IP.3) PS0 (IP.4) ET2 (IE.5)(4) ES1 (IE.6)(4) PT2 (IP.5) PS1 (IP.6) EX2 (EIE.0)(4) EX3 (EIE.1)(4) EX4 (EIE.2)(4) EX5 (EIE.3)(4) EWDI (EIE.4)(4) PX2 (EIP.0) PX3 (EIP.1) PX4 (EIP.2) PX5 (EIP.3) PWDI (EIP.4) These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). If edge-triggered, cleared automatically by hardware when the service routine is vectored to. If level-triggered, the flag follows the state of the pin. Cleared automatically by hardware when interrupt vector occurs. Globally enabled by EA (IE.7). 29 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 Hardware Configuration Register 0 (HCR0)-Accessed Using SFR Registers CADDR and CDATA. bit 7 CADDR 7FH bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 EPMA PML RSL EBR EWDR DFSEL2 DFSEL1 DFSEL0 To read this register during normal operation, refer to the register descriptions for CADDR and CDATA. EPMA Enable Programming Memory Access (Security Bit). bit 7 0: After reset in programming modes, Flash Memory can only be accessed in UAM mode until a mass erase is done. 1: Fully Accessible (default) PML Program Memory Lock (PML has Priority Over RSL). bit 6 0: Enable all Flash Programming Modes in program mode, can be written in UAM. 1: Enable read-only for program mode, can't be written in UAM (default). RSL Reset Sector Lock. bit 5 0: Enable Reset Sector Writing 1: Enable Read Only Mode for Reset Sector (4kB) (default) The reset sector can be used to provide another method of Flash Memory programming. This will allow Program Memory updates without changing the jumpers for in-circuit code updates or program development. The code in this boot sector would then provide the monitor and programming routines with the ability to jump into the main Flash code when programming is finished. EBR Enable Boot ROM. Boot ROM is 2kB of code located in ROM, not to be confused with the 4kB Boot Sector located in Flash Memory. bit 4 0: Disable Internal Boot ROM 1: Enable Internal Boot ROM (default) EWDR Enable Watchdog Reset. bit 3 0: Disable Watchdog Reset 1: Enable Watchdog Reset (default) DFSEL Data Flash Memory Size. (See Table 3.) bits 2-0 000: Reserved 001: 32kB, 16kB, 8kB, or 4kB Data Flash Memory 010: 16kB, 8kB, or 4kB Data Flash Memory 011: 8kB or 4kB Data Flash Memory 100: 4kB Data Flash Memory 101: 2kB Data Flash Memory 110: 1kB Data Flash Memory 111: No Data Flash Memory (default) 30 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 Hardware Configuration Register 1 (HCR1) bit 7 CADDR 7EH bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DBLSEL1 DBLSEL0 ABLSEL1 ABLSEL0 DAB DDB EGP0 EGP23 EGP23 To read this register during normal operation, refer to the register descriptions for CADDR and CDATA. DBLSEL Digital Brownout Level Select bits 7-6 00: 4.5V 01: 4.2V 10: 2.7V 11: 2.5V (default) ABLSEL Analog Brownout Level Select bits 5-4 00: 4.5V 01: 4.2V 10: 2.7V 11: 2.5V (default) DAB Disable Analog Power-Supply Brownout Reset bit 3 0: Enable Analog Brownout Reset 1: Disable Analog Brownout Reset (default) (will not disable unless AVDD > 2.0V) DDB Disable Digital Power-Supply Brownout Reset bit 2 0: Enable Digital Brownout Reset 1: Disable Digital Brownout Reset (default) EGP0 Enable General-Purpose I/O for Port 0 bit 1 0: Port 0 is Used for External Memory, P3.6 and P3.7 Used for WR and RD. 1: Port 0 is Used as General-Purpose I/O (default) EGP23 EGP23 Enable General-Purpose I/O for Ports 2 and 3 bit 0 0: Port 2 is Used for External Memory, P3.6 and P3.7. Used for WR and RD. 1: Port 2 and Port3 are Used as General-Purpose I/O (default) Configuration Memory Programming Certain key functions such as Brownout Reset and Watchdog Timer are controlled by the hardware configuration bits. These bits are nonvolatile and can only be changed through serial and parallel programming. Other peripheral control and status functions, such as ADC configuration timer setup, and Flash control are controlled through the SFRs. 31 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 SFR Definitions (Boldface definitions indicate that the register is unique to the MSC1210YX MSC1210YX) ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUES 80H 81H P0 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 FFH 82H 83H DPL0 84H 85H DPL1 86H 87H DPS 0 0 0 0 0 0 0 SEL PCON SMOD 0 1 1 GF1 GF0 STOP IDLE 88H 89H TCON TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 SP 07H 00H DPH0 00H 00H DPH1 - Timer 1 - TMOD GATE C/T M1 M0 - Timer 0 - GATE C/T M1 00H 00H 30H 00H 00H M0 8AH 8BH TL0 00H 00H 8CH 8DH TH0 8EH 8FH CKCON 0 0 T2M T1M T0M MD2 MD1 MD0 MWS 0 0 0 0 0 0 0 MXWS 90H P1 P1.7 P1.6 P1.5 P1.4 INT4/MISO INT3/MOSI INT2/SS P1.3 TXD1 P1.2 RXD1 P1.1 T2EX P1.0 T2 FFH INT5/SCK IE5 IE4 IE3 IE2 1 0 0 0 08H 00H TL1 00H 00H TH1 91H 92H EXIF 93Hv 94H CADDR 95H 96H MCON BPSEL 0 0 SCON0 SM0_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_0 SCK2 SCK1 SCK0 FIFO ORDER CLK_EN DRV_DLY DRV_EN P2.7 P2.6 P2.5 P2.4 97H 98H MPAGE 01H 00H 00H 00H CDATA RAMMAP 00H 00H TI_0 RI_0 00H 00H MSTR CPHA CPOL 00H 00H P2.3 P2.2 P2.1 P2.0 99H 9AH SBUF0 9BH 9DH SPIDATA A0H A1H P2 PPOL PWMSEL SPDSEL TPCNTL2 TPCNTL1 TPCNTL0 A2H PWMLOW TONELOW PWM7 TDIV7 PWM6 TDIV6 PWM5 TDIV5 PWM4 TDIV4 PWM3 TDIV3 PWM2 TDIV2 PWM1 TDIV1 PWM0 TDIV0 00H A3H PWMHI TONEHI PWM15 PWM15 TDIV15 TDIV15 PWM14 PWM14 TDIV14 TDIV14 PWM13 PWM13 TDIV13 TDIV13 PWM12 PWM12 TDIV12 TDIV12 PWM11 PWM11 TDIV11 TDIV11 PWM10 PWM10 TDIV10 TDIV10 PWM9 TDIV9 PWM8 TDIV8 00H 00H 00H A4H A5H SPICON SPITCON PWMCON 00H FFH 00H PAI 0 0 0 0 PAI3 PAI2 PAI1 PAI0 A6H A7H AIE ESEC ESUM EADC EMSEC ESPIT ESPIR EALV EDLVB AISTAT SEC SUM ADC MSEC SPIT SPIR ALVD DLVD A8H A9H IE EA ES1 ET2 ES0 ET1 EX1 ET0 EX0 BPCON BP 0 0 0 0 0 PMSEL EBP AAH ABH BPL ACH ADH P0DDRL P03H P03L P02H P02L P01H P01L P00H P00L P0DDRH P07H P07L P06H P06L P05H P05L P04H P04L AEH AFH P1DDRL P13H P13L P12H P12L P11H P11L P10H P10L 00H 00H P1DDRH P17H P17L P16H P16L P15H P15L P14H P14L 00H 32 BPH 00H 00H 00H 00H 00H 00H MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 SFR Definitions (Continued) ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET VALUES B0H P3 P3.7 RD P3.6 WR P3.5 T1 P3.4 T0 P3.3 INT1 P3.2 INT0 P3.1 TXD0 P3.0 RXD0 FFH B1H B2H P2DDRL P23H P23L P22H P22L P21H P21L P20H P20L P2DDRH P27H P27L P26H P26L P25H P25L P24H P24L 00H 00H B3H B4H P3DDRL P33H P33L P32H P32L P31H P31L P30H P30L P3DDRH P37H P37L P36H P36L P35H P35L P34H P34L 00H 00H IP 1 PS1 PT2 PS0 PT1 PX1 PT0 PX0 80H SCON1 SM0_1 SM1_1 SM2_1 REN_1 TB8_1 RB8_1 TI_1 RI_1 00H 00H EWUWDT EWUEX1 EWUEX0 00H TR2 C/T2 CP/RL2 00H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH C0H C1H C2H SBUF1 C3H C4H C5H C6H EWU C7H C8H T2CON C9H CAH RCAP2L CBH CCH EXF2 RCLK TCLK EXEN2 00H 00H RCAP2H CDH CEH TF2 TH2 TL2 00H 00H CFH D0H D1H PSW CY AC F0 RS1 RS0 OV F1 P D2H D3H OCM D4H D5H GCL D6H D7H GCH MSB ADMUX INP3 INP2 INP1 INP0 INN3 INN2 D8H D9H EICON SMOD1 1 EAI AI WDTI 0 DAH DBH ADRESM ADRESH MSB DCH DDH ADCON0 - BOD EVREF VREFH EBUF PGA2 PGA1 PGA0 ADCON1 OF_UF POL SM1 SM0 - CAL2 CAL1 CAL0 DEH DFH ADCON2 DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 ADCON3 0 0 0 0 0 DR10 DR9 DR8 E0H E1H ACC 06H 00H SSCON1 SSCON0 SCNT2 SCNT1 SCNT0 SHF2 SHF1 SHF0 E2H E3H SUMR0 00H 00H E4H E5H SUMR2 E6H E7H ODAC LVDCON ALVDIS ALVD2 ALVD1 ALVD0 DLVDIS DLVD2 DLVD1 DLVD0 E8H E9H EIE 1 1 1 EWDI EX5 EX4 EX3 EX2 HWPC0 0 0 0 0 0 0 OCL OCH LSB 00H 00H MSB LSB 5AH ECH 5FH INN1 INN0 0 0 01H 40H GCM ADRESL SSCON 00H 00H LSB SUMR1 00H 00H 00H 30H 0000_0000B 0000B 1BH 00H 00H SUMR3 00H 00H MEMORY SIZE 00H E0H 0000_00xxB 33 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 SFR Definitions (Continued) ADDRESS REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 EAH EBH HWPC1 0 0 0 0 0 0 0 0 ECH EDH Reserved EEH EFH FMCON 0 PGERA 0 FRCM 0 BUSY 1 0 FTCON FER3 FER2 FER1 FER0 FWR3 FWR2 FWR1 FWR0 F0H F1H B B.7 B.6 B.5 B.4 B.3 B.2 B.1 B.0 PDCON 0 0 0 PDPWM PDADC PDWDT PDST PDSPI F2H F3H PASEL 0 0 PSEN2 PSEN1 PSEN0 0 ALE1 ALE0 F6H F7H ACLK 0 FREQ6 FREQ5 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 SRST 0 0 0 0 0 0 0 RSTREQ F8H F9H EIP 1 1 1 PWDI PX5 PX4 PX3 PX2 SECINT WRT SECINT6 SECINT5 SECINT4 SECINT3 SECINT2 SECINT1 SECINT0 FAH FBH MSINT WRT MSINT6 MSINT5 MSINT4 MSINT3 MSINT2 MSINT1 MSINT0 USEC 0 0 0 FREQ4 FREQ3 FREQ2 FREQ1 FREQ0 FCH MSECL FDH MSECH FEH FFH HMSEC HDWVER RESET VALUES 00H xxH 00H 00H Reserved 02H A5H 00H 1FH 00H F4H F5H 34 WDTCON 03H 00H E0H 7FH 7FH 03H 9FH 0FH EWDT DWDT RWDT WDCNT4 WDCNT3 WDCNT2 WDCNT1 WDCNT0 63H 00H MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 Port 0 (P0) bit 7 SFR 80H P0.7-0 bits 7-0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 FFH Port 0. This port functions as a multiplexed address/data bus during external memory access, and as a general-purpose I/O port when external memory access is not needed. During external memory cycles, this port will contain the LSB of the address when ALE is HIGH, and Data when ALE is LOW. When used as a general-purpose I/O, this port drive is selected by P0DDRL and P0DDRH (ACH, ADH). Whether Port 0 is used as general-purpose I/O or for external memory access is determined by the Flash Configuration Register (HCR1.1) Stack Pointer (SP) bit 7 SFR 81H SP.7-0 bits 7-0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value SP.7 SP.6 SP.5 SP.4 SP.3 SP.2 SP.1 SP.0 07H Stack Pointer. The stack pointer identifies the location where the stack will begin. The stack pointer is incremented before every PUSH or CALL operation and decremented after each POP or RET/RETI. This register defaults to 07H after reset. Data Pointer Low 0 (DPL0) bit 7 SFR 82H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value DPL0.7 DPL0.6 DPL0.5 DPL0.4 DPL0.3 DPL0.2 DPL0.1 DPL0.0 00H DPL0.7-0 Data Pointer Low 0. This register is the low byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 bits 7-0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H). Data Pointer High 0 (DPH0) bit 7 SFR 83H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value DPH0.7 DPH0.6 DPH0.5 DPH0.4 DPH0.3 DPH0.2 DPH0.1 DPH0.0 00H DPH0.7-0 Data Pointer High 0. This register is the high byte of the standard 8051 16-bit data pointer. DPL0 and DPH0 bits 7-0 are used to point to non-scratchpad data RAM. The current data pointer is selected by DPS (SFR 86H). Data Pointer Low 1 (DPL1) bit 7 SFR 84H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value DPL1.7 DPL1.6 DPL1.5 DPL1.4 DPL1.3 DPL1.2 DPL1.1 DPL1.0 00H DPL1.7-0 Data Pointer Low 1. This register is the low byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) bits 7-0 (SFR 86H) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer High 1 (DPH1) bit 7 SFR 85H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value DPH1.7 DPH1.6 DPH1.5 DPH1.4 DPH1.3 DPH1.2 DPH1.1 DPH1.0 00H DPH1.7-0 Data Pointer High. This register is the high byte of the auxiliary 16-bit data pointer. When the SEL bit (DPS.0) bits 7-0 (SFR 86H) is set, DPL1 and DPH1 are used in place of DPL0 and DPH0 during DPTR operations. Data Pointer Select (DPS) bit 7 SFR 86H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value 0 0 0 0 0 0 0 SEL 00H SEL Data Pointer Select. This bit selects the active data pointer. bit 0 0: Instructions that use the DPTR will use DPL0 and DPH0. 1: Instructions that use the DPTR will use DPL1 and DPH1. 35 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 Power Control (PCON) bit 7 SFR 87H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value SMOD 0 1 1 GF1 GF0 STOP IDLE 30H SMOD bit 7 Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0. 0: Serial Port 0 baud rate will be a standard baud rate. 1: Serial Port 0 baud rate will be double that defined by baud rate generation equation when using Timer 1. GF1 bit 3 General-Purpose User Flag 1. This is a general-purpose flag for software control. GF0 bit 2 General-Purpose User Flag 0. This is a general-purpose flag for software control. STOP bit 1 Stop Mode Select. Setting this bit will halt the oscillator and block external clocks. This bit will always read as a 0. Exit with RESET. IDLE bit 0 Idle Mode Select. Setting this bit will freeze the CPU, Timer 0, 1, and 2, and the USARTs; other peripherals remain active. This bit will always be read as a 0. Exit with AI (A6H) and EWU (C6H) interrupts. Timer/Counter Control (TCON) bit 7 SFR 88H bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset Value TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H TF1 bit 7 Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine. 0: No Timer 1 overflow has been detected. 1: Timer 1 has overflowed its maximum count. TR1 Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer will preserve the current count in TH1, TL1. 0: Timer is halted. 1: Timer is enabled. TF0 bit 5 Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode. This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine. 0: No Timer 0 overflow has been detected. 1: Timer 0 has overflowed its maximum count. TR0 bit 4 Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer will preserve the current count in TH0, TL0. 0: Timer is halted. 1: Timer is enabled. IE1 bit 3 Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will inversely reflect the state of the INT1 pin. IT1 bit 2 Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge or level triggered interrupts. 0: INT1 is level triggered. 1: INT1 is edge triggered. IE0 bit 3 Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will inversely reflect the state of the INT0 pin. IT0 bit 2 Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge or level triggered interrupts. 0: INT0 is level triggered. 1: INT0 is edge triggered. 36 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 Timer Mode Control (TMOD) 7 6 5 4 3 2 TIMER 1 SFR 89H GATE C/T 1 0 M1 M0 Reset Value 00H TIMER 0 M1 M0 GATE C/T GATE bit 7 Timer 1 Gate Control. This bit enables/disables the ability of Timer 1 to increment. 0: Timer 1 will clock when TR1 = 1, regardless of the state of pin INT1. 1: Timer 1 will clock only when TR1 = 1 and pin INT1 = 1. C/T bit 6 Timer 1 Counter/Timer Select. 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on T1 pin when TR1 (TCON.6, SFR 88H) is 1. M1, M0 bits 5-4 Timer 1 Mode Select. These bits select the operating mode of Timer 1. M1 M0 0 0 MODE Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Two 8-bit counters. GATE bit 3 Timer 0 Gate Control. This bit enables/disables the ability of Timer 0 to increment. 0: Timer 0 will clock when TR0 = 1, regardless of the state of pin INT0 (software control). 1: Timer 0 will clock only when TR0 = 1 and pin INT0 = 1 (hardware control). C/T bit 2 Timer 0 Counter/Timer Select. 0: Timer is incremented by internal clocks. 1: Timer is incremented by pulses on pin T0 when TR0 (TCON.4, SFR 88H) is 1. M1, M0 bits 1-0 Timer 0 Mode Select. These bits select the operating mode of Timer 0. M1 M0 0 0 MODE Mode 0: 8-bit counter with 5-bit prescale. 0 1 Mode 1: 16 bits. 1 0 Mode 2: 8-bit counter with auto reload. 1 1 Mode 3: Two 8-bit counters. Timer 0 LSB (TL0) 7 TL0.7-0 bits 7-0 6 5 4 3 2 1 0 Reset Value TL0.7 SFR 8AH TL0.6 TL0.5 TL0.4 TL0.3 TL0.2 TL0.1 TL0.0 00H Timer 0 LSB. This register contains the least significant byte of Timer 0. Timer 1 LSB (TL1) 7 TL1.7-0 bits 7-0 6 5 4 3 2 1 0 Reset Value TL1.7 SFR 8BH TL1.6 TL1.5 TL1.4 TL1.3 TL1.2 TL1.1 TL1.0 00H Timer 1 LSB. This register contains the least significant byte of Timer 1. Timer 0 MSB (TH0) 7 SFR 8CH TH0.7-0 bits 7-0 6 5 4 3 2 1 0 Reset Value TH0.7 TH0.6 TH0.5 TH0.4 TH0.3 TH0.2 TH0.1 TH0.0 00H Timer 0 MSB. This register contains the most significant byte of Timer 0. 37 MSC1210 MSC1210 www.ti.com SBAS203E SBAS203E - MARCH 2002 - REVISED SEPTEMBER 2004 Timer 1 MSB (TH1) 7 TH1.7-0 bits 7-0 6 5 4 3 2 1 0 Reset Value TH1.7 SFR 8DH TH1.6 TH1.5 TH1.4 TH1.3 TH1.2 TH1.1 TH1.0 00H Timer 1 MSB. This register contains the most significant byte of Timer 1. Clock Control (CKCON) 7 T2M bit 5 6 5 4 3 2 1 0 Reset Value 0 SFR 8EH 0 T2M T1M T0M MD2 MD1 MD0 01H Timer 2 Clock Select. This bit controls the division of the system clock that drives Timer 2. This bit has no effect when the timer is in baud rate generator or clock output modes. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 2 uses a divide by 12 of the crystal frequency. 1: Timer 2 uses a divide by 4 of the crystal frequency. T1M bit 4 Timer 1 Clock Select. This bit controls the division of the system clock that drives Timer 1. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 1 uses a divide by 12 of the crystal frequency. 1: Timer 1 uses a divide by 4 of the crystal frequency. T0M bit 3 Timer 0 Clock Select. This bit controls the division of the system clock that drives Timer 0. Clearing this bit to 0 maintains 8051 compatibility. This bit has no effect on instruction cycle timing. 0: Timer 0 uses a divide by 12 of the crystal frequency. 1: Timer 0 uses a divide by 4 of the crystal frequency. MD2, MD1, MD0 Stretch MOVX Select 2-0. These bits select the time by which external MOVX cycles are to be stretched. This allows bits 2-0 slower memory or peripherals to be accessed without using ports or manual software intervention. The width of the RD or WR strobe will be stretched by the specified interval, which will be transparent to the software except for the increased time to execute the MOVX instruction. All internal MOVX instructions on devices containing MOVX SRAM are performed at the 2 instruction cycle rate. RD or WR STROBE WIDTH (SYS CLKs) RD or WR STROBE WIDTH (ms) at 12MHz 2 Instruction Cycles 2 0.167 3 Instruction Cycles (default) 4 0.333 2 4 Instruction Cycles 8 0.667 1 3 5 Instruction Cycles 12 1.000 0 0 4 6 Instruction Cycles 16 1.333 1 0 1 5 7 Instruction Cycles 20 1.667 1 1 0 6 8 Instruction Cycles 24 2.000 1 1 1 7 9 Instruction Cycles 28 2.333 MD2 MD1 MD0 STRETCH VALUE 0 0 0 0 0 0 1 1 0 1 0 0 1 1 MOVX DURATI