E2C0034-27-Y5 MSC1162A MSC1162 SSOP60-P-700-0 65-BK MSC1162AGS-BK HVO40 PO1-40 - Datasheet Archive

 

About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI

 

Dear customers, About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd. The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI Semiconductor Co., Ltd. on October 1, 2008. Therefore, please accept that although the terms and marks of "Oki Electric Industry Co., Ltd.", "Oki Electric", and "OKI" remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.". It is a change of the company name, the company trademark, and the logo, etc. , and NOT a content change in documents. October 1, 2008 OKI Semiconductor Co., Ltd. 550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan http://www.okisemi.com/en/ E2C0034-27-Y5 E2C0034-27-Y5 ¡ Semiconductor MSC1162A MSC1162A ¡ Semiconductor This version: Nov. 1997 MSC1162A MSC1162A Previous version: Jul. 1996 40-Bit Vacuum Fluorescent Display Tube Grid/Anode Driver GENERAL DESCRIPTION The MSC1162A MSC1162A is a monolithic IC designed for directly driving the grid and anode of the vacuum fluorescent display tube. The device contains a 40-bit bidirectional shift register, a 40-bit latch circuit, and 40-output circuit on a single chip. Display data is serially stored in the shift register at the rising edge of a clock pulse. Setting the CL pin low allows all the driver outputs to be driven low, which makes it possible to set the display blanking. Also, setting both of the CL and CHG pins high allows all the driver outputs to be driven high, which provides the easy testing of all lights after final assembly of a VFD tube panel. The MSC1162A MSC1162A is compatible with the MSC1162 MSC1162. FEATURES · Logic Supply Voltage (VCC) : 5V · Driver Supply Voltage (VHV): 65V · Driver Output Current IOHVH1 (Only one driver output : "H") : ­40mA IOHVH2 (All the driver outputs : "H") : ­2mA IOHVL:1mA · Directly connected to VFD tube without pull-down resistors · Data Transfer Speed: 4MHz · Package : 60-pin plastic SSOP (SSOP60-P-700-0 SSOP60-P-700-0.65-BK 65-BK) (Product name : MSC1162AGS-BK MSC1162AGS-BK) 1/14 ¡ Semiconductor MSC1162A MSC1162A BLOCK DIAGRAM V HV V CC V CC CL CHG LS DIN CLK C SI HVO1 PO1 I-1 O-1 PO2 I-2 O-2 HVO2 40-Bit Bidirectional Shift Register 40-Bit Latch HVO40 HVO40 PO40 GND1 GND2 I-40 O-40 SO DOUT 2/14 ¡ Semiconductor MSC1162A MSC1162A INPUT AND OUTPUT CONFIGURATION Schematic Diagrams of Logic portion Input/Output Circuits and Driver Output Circuits Input Pin VCC VCC INPUT GND1 GND2 Output Pin VCC VCC DOUT GND2 GND1 3/14 ¡ Semiconductor MSC1162A MSC1162A Driver Output Circuit VHV VHV Output GND 1 GND 1 4/14 , ¡ Semiconductor MSC1162A MSC1162A PIN CONFIGURATION (TOP VIEW) HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO HVO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VHV GND 1 GND 2 CL NC LS NC R/L DIN VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 HVO 40 HVO 39 HVO 38 HVO 37 HVO 36 HVO 35 HVO 34 HVO 33 HVO 32 HVO 31 HVO 30 HVO 29 HVO 28 HVO 27 HVO 26 HVO 25 HVO 24 HVO 23 HVO 22 HVO 21 VHV GND 1 GND 2 NC CHG NC CLK NC DOUT VCC NC : No-connection pin 60-Pin Plastic SSOP 5/14 ¡ Semiconductor MSC1162A MSC1162A PIN DESCRIPTION Symbol Type Description CLK I Shift register clock input pin. Shift register reads data through DIN while the CLK pin is low state and the data in the shift register is shifted from one stage to the next stage at the rising edge of the clock. DIN I Serial data input pin of the shift register. Display data (positive logic) is input in through the DIN pin synchronization with clock. DOUT O Serial data output pin of the shift register. Data is output through the DOUT pin in synchronization with the CLK signal. When R/L = High, the data of PO40 in the shift register is output through the DOUT pin. When R/L = Low, the data of PO1 pin in the shift register is output through the DOUT pin. LS I Latch strobe input pin When LS is high, the parallel output data (PO1-40 PO1-40) of the shift register read out. When LS goes from high to low, the parallel output data (PO1-40 PO1-40) of the shift register is held. I Clear input pin with a built-in pull-up resistor The CL pin is normally being set high. If the CL pin is high and the CHG pin is low, the driver outputs (HV01 to HV40) are in phase with the corresponding latch outputs (O1 to O40). If the CL pin is high and the CHG pin is high, the driver outputs (HV01 to HV40) are high irrespective of the states of the latch outputs. If the CL pin is set low, the driver outputs are driven low irrespective of the states of the CHG pin and latch outputs. This allows display blanking to be set. CHG I Input for testing (with a pull-down resistor) The CL pin is normally being set low. If the CHG pin is low and the CL pin is high, the driver outputs (HV01 to HV40) are in phase with the corresponding latch outputs (O1 to O40). If the CHG pin is low and the CL pin is low, the driver outputs (HV01 to HV40) are low irrespective of the states of the latch outputs. If the CHG pin is set high, the driver outputs are driven high irrespective of the states of the latch outputs. This provides the easy testing of all lights after final assembly. VHO1-40 VHO1-40 O High voltage driver outputs for driving VFD tube The driver outputs are in phase with the corresponding latch outputs (O1 to O40). The direct connection to the grid or anode of a VFD tube eliminates pull-down resistors. CL VHV VCC Power supply pin for driver circuits of VFD tube Power supply pin for logic GND1 GND pin for driver circuits of a VFD tube. (D-GND) Since the GND1 is not be connected to L-GND, connect this pin to the external L-GND. GND2 GND pin for the logic circuits. (L-GND) Since the GND2 pin is not be connected to D-GND, connect this pin to the external D-GND. 6/14 ¡ Semiconductor MSC1162A MSC1162A ABSOLUTE MAXIMUM RATINGS Parameter Symbol Condition Rating Unit *1 Logic Supply Voltage Driver Supply Voltage *1, *2 VCC VHV Applicable to logic supply pin Applicable to driver supply pin ­0.3 to +6.5 ­0.3 to +70 V V *1 VIN Applicable to all input pins ­0.3 to VCC +0.3 V *1 Output Voltage Driver Driving Frequency VO fDRV Applicable to data output pin Applicable to driver output pin ­0.3 to VCC +0.3 0 to 15 V kHz VHVO Applicable to driver output pin ­0.3 to VHV +0.3 V PD Ta £ 25°C 860 mW Package Thermal Resistance *3 Rj-a Ta > 25°C 145 °C/W Storage Temperature TSTG - ­55 to +150 °C Input Voltage Withstand Output Voltage *1, *2 Power Dissipation Notes: *1 Maximum Supply Voltage with respect to L-GND and D-GND *2 Permanent damage may be caused if the voltage is supplied over the rating value. *3 Package Thermal Resistance (between junction and ambient) The junction temperature (Tj) expressed by the equation indicated below should not exceed 150°C. Tj=P ¥ Rj­a+Ta (P: Maximum power consumption) 7/14 ¡ Semiconductor MSC1162A MSC1162A RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Max. Unit Logic Supply Voltage VCC Applicable to logic supply voltage pin 4.5 5.5 V Driver Supply Voltage VHV Applicable to driver supply voltage pin 10 65 V High Level Input Voltage VIH Applicable to all input pins 3.6 - V Low Level Input Voltage VIL Applicable to all input pins - 1.1 V High Level Driver Output Current IOHVH1 Only one output is high - ­40 mA All outputs are high - ­2 mA - 1 mA IOHVH2 Applicable to driver output pin Low Level Driver Output Current IOHVL CLK Frequency fCLK - 4 MHz CLK Pulse Width tw(CLK) 75 - ns Data Setup Time tSU(D-CLK) 80 - ns Data Hold Time th(CLK-D) 50 - ns 140 - ns Data Pulse Width Applicable to all driver output pins tw(D) See timing diagram 80 - ns CLK-LS tsu(CLK-LS) 50 - ns LS-CLK tsu(LS-CLK) 0 - ns LS-CHG tsu(LS-CHG) 0 - ms Latch Probe Pulse Width Setup Time 0 - ms CHG tw(CHG) - 2 - ms CL tw(CL) - 2 - ms Top - ­40 85 °C LS-CL Pulse Width tw(LS) Operating Temperature tsu(LS-CL) 8/14 ¡ Semiconductor MSC1162A MSC1162A ELECTRICAL CHARACTERISTICS DC Characteristics (VCC=4.5 to 5.5V, VHV=10 to 65V, Ta=­40 to +85°C) Parameter Symbol ICC1 Logic Supply Current ICC2 IHV1 Driver Supply Current High Level Input Current Low Level Input Current Input Capacitance High Level Data Output Voltage Low Level Data Output Voltage High Level Driver Output Voltage Low Level Driver Output Voltage IHV2 Condition Typ. Max. All input: Low - 4.3 6.65 All input: High, Ta=25°C No load VCC=5.5V Min. - 0.5 1.0 - 1.0 mA 2.45 3.8 mA All input: Low No load VCC=5.5V All input: High Ta=25°C - Unit mA VCC=5.5V, VIN=5.5V Inputs excluding CHG ­1 - 1 mA VCC=5.5V, VIN=5.5V CHG input 5 - 80 mA VCC=5.5V, VIN=0V Inputs excluding CL ­1 - 1 mA VCC=5.5V, VIN=0V CL input ­5 - ­80 mA Ta=25°C - 15 - pF VCC=4.5V 3.5 - - V VCC=5.5V 4.5 - - V VCC=4.5V - - 1.1 V VCC=5.5V - - 1.1 V IIH IIL CI VODH VODL IOH=­0.1mA IOL=0.1mA VOHVH1 IOH=­40mA VHV­4 - - V VOHVH2 IOH=­2mA VHV­4 - - V VOHVL IOL=1mA - - 3.0 V AC Characteristics (VCC=5V, VHV=65V, Ta=25°C) Parameter Symbol Condition Min. Typ. Max. Unit CLK-DOUT Delay Time tPD - - - 300 ns Delay Time Low to High tDLH - - 0.3 1.0 ms Transit Time Low to High tTLH - - 2.0 5.0 ms Delay Time High to Low tDHL - - 0.3 1.0 ms Transit Time High to Low tTHL - - 2.0 5.0 ms 9/14 T1/2 CLK T3/4 T39/40 T39/40 T1/2 tsu(D-CLK) th(CLK-D) T3/4 tw(CLK) DIN tw(D) tPD ¡ Semiconductor TIMING DIAGRAM 1/fCLK tPD DOUT tsu(CLK-LS) tw(LS) tsu(LS-CLK) LS tsu(LS-CHG) tw(CHG) tw(CHG) CHG tw(CL) tsu(LS-CL) CL tDLH tDLH tw(CL) tDHL tDHL HVO (1, 2, 39, 40) HVO (OTHERS) tTLH tTHL tTHL 10/14 MSC1162A MSC1162A tTLH ¡ Semiconductor MSC1162A MSC1162A FUNCTIONAL DESCRIPTION Function Table Shift register Input CLK Shift Register Parallel Out R/L DIN X PO1 PO2 X PO39 Output PO40 Not changed DOUT Not changed H L L PO1n PO38n PO39n PO40 H H H PO1n PO38n PO39n PO40 L L PO2n PO3n PO40n L PO1 L H PO2n PO3n PO40n H PO1 X: Don't Care PO1n to PO40n : PO1 to PO40 data just before CLOCK rises. Latch Input Shift Register Parallel Out Latch Output LS POm Om I X Not changed H L L H H H X: Don't Care, m: 1 to 40 Driver output Input Latch Output Driver Output CL CHG Om HVOm L X X L H H X H H L L L H L H H X: Don't Care, m: 1 to 40 11/14 ¡ Semiconductor MSC1162A MSC1162A NOTES ON USE 1. Connect GND1 to GND2 externally to be an equal potential voltage. 2. The contents of the shift register are undefined when the power is applied. Therefore, unnecessary driver outputs may be driven high just after power-on, and the VFD tube may flicker. To avoid this, follow the procedures: 1) Apply the driver power supply after applying the logic power supply, with the CL pin remained low. 2) Start displaying by setting the CL pin high after in putting display data the shift register through the DIN pin. 12/14 ¡ Semiconductor MSC1162A MSC1162A Test circuit 20pF VHV VCC HVO1 1.5kW HVO2 5.0V GND1, 2 CL CHG R/L DIN LS HVO40 HVO40 CLK 65V DOUT 30pF 13/14 ¡ Semiconductor MSC1162A MSC1162A PACKAGE DIMENSIONS (Unit : mm) SSOP60-P-700-0 SSOP60-P-700-0.65-BK 65-BK Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.21 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 14/14