MSC0408 MSC0408TS/D MSC0408/MCP AN1050/D 12MSZ19139A M68HC05 MSC04 MSC02 - Datasheet Archive

 

MSC0408 8-bit microcontroller with 8K EEPROM and advanced security features MSC0408TS/D Rev. 0 page 1 of 36 Important notice to

 

Technical Summary MSC0408 MSC0408 8-bit microcontroller with 8K EEPROM and advanced security features MSC0408TS/D MSC0408TS/D Rev. 0 page 1 of 36 Important notice to readers. This document is intended to provide a summary of the functionality of the MSC0408 MSC0408 product. This document does not replace or supersede the MSC0408 MSC0408 technical data sheet (MSC0408/MCP MSC0408/MCP). The warranty for the MSC0408 MSC0408 is contained in the applicable Motorola agreed warranty clause with which the MSC0408 MSC0408 product is sold. No security guarantee or warranty is given with the MSC0408 MSC0408 product. The security of any system in which the MSC0408 MSC0408 product is used will depend on the system's security as a whole. Where security features are mentioned in this document this refers to features which are intended to increase the security of the MSC0408 MSC0408 product under normal use and in normal circumstances. Motorola reserves the right to make changes without further notice to any products herein. "Typical" parameters can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Customer purchase or use Motorola products for any such unintended or unauthorized application, Customer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part, to the maximum extent permitted by law. Motorola and !are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. This document contains information on new products. Specifications and information herein are subject to change without notice. All Trade Marks recognized. Motorola, Inc., and its subsidiaries, is licensed by Bull CP8 under French patent 2,461,301 and its counterpart patents in Great Britain, Germany, Hong Kong, Japan, and the USA. Government export restrictions may apply to this product and its derivatives. (See Section 16 of this document). © MOTOROLA LTD., 1997 ekb page 2 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 About this document. This document is copyrighted to Motorola. However it may be freely copied and distributed, provided it is not altered in any way. This document provides a technical summary of the hardware features that are implemented on the MSC0408 MSC0408 device and that are available to the user under normal operating conditions.This document is not a technical data sheet and should not be used for design reference purposes. Anyone intending to design with the MSC0408 MSC0408 must make sure they have a copy of the latest revision of the technical data sheet (MSC0408/MCP MSC0408/MCP), and any associated documents. Further background, programming and applications information may be available in other Motorola publications: please contact your local sales office for further details Please contact your local sales office, quoting reference: MSC0408TS/D MSC0408TS/D Rev. 0, if you require further copies of this document, or if you wish to make any comment on this document. Information on the current availability of specific device options should also be obtained from your local sales office. Note: In this document, specifications in italics are estimated values only, and are provided as an indication of the intended performance of the MSC0408 MSC0408. Guaranteed values will be determined during the MSC0408 MSC0408 qualification programme and will be available when this programme is complete. Related documents. MSC0408 MSC0408 technical data sheet (MSC0408/MCP MSC0408/MCP) This document is issued only to customers who have successfully completed the Motorola Smartcard Customer Approval Procedure. Contact your local Motorola Sales Office for availability. Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers (AN1050/D AN1050/D) ­ This document is freely available from the Motorola Literature Distribution Center. Contact your local Motorola Sales Office. Smartcard Burn-in Software Specification (12MSZ19139A 12MSZ19139A) ­ Contact your local Motorola Sales Office. EKB Reliability Audit Program ­ MSC0408TS/D MSC0408TS/D Rev. 0 Contact your local Motorola Sales Office. page 3 of 36 Conventions and definitions. Unless stated otherwise, this document describes how the MSC0408 MSC0408 functions under normal operating conditions of voltage, current, timing and temperature, as defined by the parameters specified in the Electrical Specifications sections, and under the control of user software residing in the on-board memory. "Unused location". An unused location is an undefined location. The state of the data bus during a read of an unused location is undefined. Pin names. ISO standards, and other documentation, may refer to some of the functions of the MSC0408 MSC0408's connections by alternative names; this has no affect on functionality. In this context, the following statements apply (terms used in this document are given first): ­ VDD is equivalent to VCC, ­ RESET is equivalent to RST, ­ PA0 is equivalent to I/O. . An overbar is used to designate an active-low signal, for example: RESET Other conventions. $ = hexadecimal. % = binary. page 4 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 TABLE OF CONTENTS page 1 1.1 1.2 INTRODUCTION . 7 Features . 7 Mask options . 8 Figure 1-1 MSC0408 MSC0408 block diagram . 8 2 FUNCTIONAL PIN DESCRIPTION . 9 Figure 2-1 Standard I/O port structure . 9 Table 2-1 I/O pin states . 9 3 MEMORY AND REGISTERS. 10 3.1 RAM . 10 3.2 ROM . 10 3.3 EEPROM. 10 3.3.1 EEPROM programming . 10 Figure 3-1 Four-byte programming . 10 3.4 Registers . 11 3.4.1 I/O registers . 11 3.4.2 Other register bits . 11 3.5 CPU registers . 11 Figure 3-2 Programming model . 11 Figure 3-3 Stacking order . 11 4 4.1 INSTRUCTION SET AND ADDRESSING MODES . 13 Addressing modes . 13 Table 4-1 M68HC05 M68HC05 opcode map . 15 5 5.1 5.2 5.3 RESETS. 16 Power-up detection reset. 16 Watchdog reset . 16 Software reset . 16 6 6.1 6.2 INTERRUPTS . 17 Software interrupt . 17 Hardware controlled interrupt sequence . 17 Table 6-1 Interrupt priorities . 17 7 7.1 7.2 LOW POWER MODES . 18 STOP instruction . 18 WAIT instruction . 18 8 8.1 8.2 TIME BASE AND WATCHDOG. 19 Time base operation. 19 Watchdog system. 19 Figure 8-1 STOP execution when watchdog is enabled . 19 MSC0408TS/D MSC0408TS/D Rev. 0 page 5 of 36 TABLE OF CONTENTS page 9 9.1 9.2 9.3 9.4 SECURITY FEATURES . 20 Physical security . 20 `Out of bounds' detectors . 20 Accumulator and index register clearing . 20 Control bytes . 20 10 10.1 10.2 FACTORY TEST . 21 Burn-in of assembled product . 21 Programming the EEPROM with customer specified data. 22 11 DC LATCH-UP PROTECTION. 23 Figure 11-1 DC latch-up test fixture. 23 12 ESD PROTECTION . 24 Figure 12-1 ESD test . 24 13 13.1 ELECTRICAL SPECIFICATIONS . 25 Maximum ratings . 25 Table 13-1 Maximum ratings . 25 EEPROM characteristics. 26 AC electrical characteristics . 27 DC electrical characteristics. 28 13.2 13.3 13.4 14 PACKAGING AND PIN ASSIGNMENTS . 29 Figure 14-1 MSC0408 MSC0408 bond pad layout. 29 Figure 14-2 MSC0408 MSC0408 production packaging . 29 15 BONDING INFORMATION . 30 Figure 15-1 MSC0408 MSC0408 die layout - top view. 30 16 ORDERING INFORMATION. 31 16.1 Export control . 31 16.1.1 When to apply for a licence . 31 16.1.2 What ".the above goods are for our own use." means . 31 Figure 16-1 Sample customer declaration for export licence application for silicon . 32 Figure 16-2 Sample customer declaration for export licence application for emulator systems and technical documentation . 33 16.2 Customer specified data for MSC0408 MSC0408 ROM . 34 16.2.1 Verification media . 34 16.2.2 ROM verification units (RVUs). 34 16.2.3 Security verification units (SVUs) . 34 Figure 16-3 RVU pinout . 35 page 6 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 MSC0408 MSC0408 8-bit microcontroller with 8K EEPROM and advanced security features 1 INTRODUCTION The MSC0408 MSC0408 microcontroller (MCU) is a member of Motorola's family of single chip MCUs designed specifically for incorporation into embedded conditional access systems and other security conscious systems. It is based on the industry-standard M68HC05 M68HC05 low power HCMOS core and gives access to the powerful instruction set of this widely used family of devices. The MSC0408 MSC0408 is currently available in sawn wafer form, and in 52-pin PLCC packages. The new range of MSC04 MSC04 devices provides enhanced security capability over and above their MSC02 MSC02 counterparts; performance and ESD protection have also been improved. All MSC04 MSC04 devices are manufactured using a new process that allows the test circuitry on the silicon to be physically removed after testing. All MSC04 MSC04 devices include EEPROM featuring 2ms programming and, typically, more than 1,200,000 write/erase cycles, and greater than 10 years data retention. This circuit is designed in accordance with the ISO standard for integrated circuit cards (ISO 7816), where appropriate. A full data sheet on this device is available under nondisclosure agreement. 1.1 Features · HCMOS technology - fully static operation · Full use of the industry-standard M68HC05 M68HC05 instruction set, including: 8 x 8 bits unsigned multiply instruction, true bit manipulation, memory-mapped I/O · Advanced physical security, including removal of test mode when testing is complete · "Out of bounds" detectors · Operating voltage: 3.0V ± 10% and 5.0V ± 10% · 5.0 MHz maximum internal bus frequency at 5.0 V. · 2.0 MHz maximum internal bus frequency at 3.0 V. · 8144 bytes of on-chip EEPROM, including control bytes · 12800 bytes of on-chip ROM, including ten bytes reserved for vectors · 240 bytes of on-chip RAM · On-chip charge pump for EEPROM programming, driven by an independent internal oscillator · EEPROM: 2ms programming; 10 years data retention; and typically more than 1,200,000 write/erase cycles MSC0408TS/D MSC0408TS/D Rev. 0 page 7 of 36 · Power saving WAIT and very low power STOP modes · One bidirectional I/O line (1-bit ISO 7816/3 standard I/O port) · External maskable interrupt on ISO standard I/O port (PA0) · Time base circuitry with maskable interrupt capability · Watchdog capability · Power-up detection · Access control logic · Parity bit (allows the parity of the contents of any legal address to be determined) · Accumulator and Index register cleared on reset · ESD protection to ± 4000 V · Bond pad layout conforming to ISO standard ISO 7816/2 ROM ­ 12800 bytes EEPROM ­ 8144 bytes RAM ­ 240 bytes Charge pump EEPROM oscillator CLK ÷ 2 or 1 Control logic Time base and watchdog VDD VSS DDRA RESET Interrupt control PORT A M68HC05 M68HC05 CPU PA0 Security logic Figure 1-1 MSC0408 MSC0408 block diagram 1.2 Mask options There are several mask options available on the MSC0408 MSC0408; these allow the user to select different configurations for certain hardware features, such as clock generation, Watchdog operation and Memory access. page 8 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 2 FUNCTIONAL PIN DESCRIPTION VDD and VSS Power is supplied to the microcontroller via these pins. VDD is the positive supply and VSS is ground. It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care must be taken to provide good power supply bypassing at the MCU. Bypass capacitors should have good high frequency characteristics and be as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded. RESET This active low input pin has an internal pull-up resistor and is used to reset the MCU. Applying a logic zero to this pin forces the device to a known start-up state. CLK The CLK pin provides the chip with an external clock signal which is divided by one or two to generate the internal clocks. This pin has an internal pull-up resistor. PA0 This line comprises the 1-bit port A. The bidirectional port line may be programmed as input or output under software control. The direction is determined by the state of the corresponding bit in the port data direction register (DDR). PA0 is configured as an output if its corresponding DDR bit is set (to a logic one). PA0 is configured as an input if its corresponding DDR bit is cleared (to a logic zero). M68HC05 M68HC05 internal connections At reset, the DDR is cleared, whether the clock is running or not, thus configuring PA0 as input. The data direction register can be written to, or read by, the MCU. During the programmed output state, a read of the data register actually reads the value of the output data buffer and not the I/O pin. The operation of the port hardware is shown schematically in Figure 2-1. Data direction register bit VDD DDRn Pull-up Latched data register bit Data Output buffer I/O pin O/P data buffer DDRn Output Input buffer Input Data I/O pin 1 0 0 1 1 1 0 0 tristate 0 1 tristate Figure 2-1 Standard I/O port structure Table 2-1 I/O pin states R/W(1) DDRn Action of MCU write to/read of data bit 0 0 0 1 The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch, and output to the I/O pin. The state of the I/O pin is read. The I/O pin is in output mode. The output data latch is read. 1 0 1 1 (1) Note that R/W is an internal signal, not available to the user. MSC0408TS/D MSC0408TS/D Rev. 0 page 9 of 36 3 MEMORY AND REGISTERS 3.1 RAM The RAM contains 240 bytes. Of these 240 bytes, 64 are shared with the stack area. The stack is used to store the return address for subroutine calls and the machine state during interrupts. Note: 3.2 Using the stack area for data storage, or temporary work locations, requires care, to prevent data being overwritten due to stacking from an interrupt or a subroutine call. ROM The user ROM contains 12800 bytes, including ten bytes for the reset and interrupt vectors in its highest locations. 3.3 EEPROM The EEPROM array has a total size of 8160 bytes. Erased EEPROM memory locations read as logic zero. A write operation writes only ones (i.e. existing ones will not be overwritten to zero). Note: The first 16 bytes are reserved for Motorola use. Although these reserved bytes are accessible to the user, they may have been exercised extensively during factory testing and are not guaranteed to be erased to zero before delivery to the customer. It is not recommended that these bytes be used in a customer's application. The two modes of operation of the EEPROM are the read mode and the programming mode. The programming mode can be, in turn, a write mode or an erase mode. Selection of the two programming modes is controlled by the W/E bit. 3.3.1 EEPROM programming Special programming circuitry embedded in the EEPROM block allows a group of up to four different bytes to be written or erased simultaneously. These four bytes must be located in the set of addresses which share the same 13 most significant bits out of the 15 used to define a byte address, and are referred to as a 32-bit word (see Figure 3-1). A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 Word location deÞnition A3 A2 A1 A0 Data location Figure 3-1 Four-byte programming page 10 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 3.4 Registers 3.4.1 I/O registers The 1-bit port A has a data register and a 1-bit data direction register. For further information, see also the pin descriptions in Section 2. 3.4.2 Other register bits Register bits are used to control the functions on t he MSC0408 MSC0408. These functions include: checking the parity of any legally addressable byte; selection of the clock source; enabling/disabling timebase interrupts; enabling/disabling the watchdog; selection of the EEPROM programming mode; and enabling/disabling EEPROM programming 3.5 CPU registers The MSC0408 MSC0408 contains five registers, as shown in the programming model of Figure 3-2. The interrupt stacking order is shown in Figure 3-3. 7 0 7 0 7 0 7 0 Accumulator Index register 15 0 Program counter 15 0 0 0 0 0 0 0 0 1 1 7 Stack pointer 0 1 1 1 H I NZC Condition code register Carry / borrow Zero Negative Interrupt mask Half carry Figure 3-2 Programming model Unstack 0 Condition code register Accumulator Index register Program counter high Program counter low Stack Interrupt Increasing memory address Return 7 Decreasing memory address Figure 3-3 Stacking order MSC0408TS/D MSC0408TS/D Rev. 0 page 11 of 36 Accumulator (A) The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. This register is cleared on reset. Index register (X) The index register is an 8-bit register, which can contain the indexed addressing value used to create an effective address. The index register may also be used as a temporary storage area. This register is cleared on reset. Program counter (PC) The program counter is a 16-bit register, which contains the address of the next byte to be fetched. Although the M68HC05 M68HC05 core is capable of addressing up to 64K bytes of memory, the actual address range of the MSC0408 MSC0408 is limited to 32K bytes.The most significant bit of the program counter is therefore not used and is always read as zero. Stack pointer (SP) The stack pointer is a 16-bit register, which contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to the top of the stack.The stack pointer is then decremented as data is pushed onto the stack and incremented as data is pulled from the stack. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and overwrites the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. Condition code register (CCR) The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually tested by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. ­ ­ Interrupt (I) - When this bit is set all maskable interrupts are masked. If an interrupt occurs while this bit is set, the interrupt is latched and remains pending until the interrupt bit is cleared. ­ Negative (N) - When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. ­ Zero (Z) - When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. ­ page 12 of 36 Half carry (H) - This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Carry/borrow (C) - When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit is also affected during `bit test and branch' instructions and during shifts and rotates. MSC0408TS/D MSC0408TS/D Rev. 0 4 INSTRUCTION SET AND ADDRESSING MODES The MSC0408 MSC0408 addressing modes are described in the following paragraphs; the instruction set and opcode map is as shown in Table 4-1. The MCU has a set of 62 basic instructions. They can be grouped into five different types as follows: · Register/memory instructions - Most of these instructions use two operands. The first operand is either the accumulator or the index register. The second operand is obtained from memory using one of the addressing modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. · Branch instructions - These instructions cause the program to branch if a particular condition is met; otherwise, no operation is performed. Branch instructions are two-byte instructions. · Bit manipulation instructions - The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space (Page 0). An additional feature allows the software to test and branch on the state of any bit within these locations. The bit set, bit clear, bit test, and branch functions are all implemented with single instructions. For the test and branch instructions, the value of the bit tested is also placed in the carry bit of the condition code register. · Read/modify/write instructions - These instructions read a memory location or a register, modify or test its contents, and write the modified value back to memory or to the register. The test for negative or zero (TST) instruction is an exception to this sequence of reading, modifying and writing, since it does not modify the value. · Control instructions - These instructions are register reference instructions and are used to control processor operation during program execution. 4.1 Addressing modes Ten different addressing modes provide programmers with the flexibility to optimize their code for all situations. The various indexed addressing modes make it possible to locate data tables, code conversion tables, and scaling tables anywhere in the memory space. Short indexed accesses are single byte instructions; the longest instructions (three bytes) permit accessing tables throughout memory. Short absolute (direct) and long absolute (extended) addressing is also included. One or two byte direct addressing instructions access all data bytes in most applications. Extended addressing permits jump instructions to reach all memory locations. The term `effective address' (EA) is used in describing the various addressing modes. Effective address is defined as the address from which the argument for an instruction is fetched or stored. The ten addressing modes of the processor are described below. Parentheses are used to indicate `contents of' the location or register referred to. For example, (PC) indicates the contents of the location pointed to by the PC (program counter). An arrow indicates `is replaced by' and a colon indicates concatenation of two bytes. · Inherent - In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations specifying only the index register or accumulator as well as the control instruction with no other arguments are included in this mode. These instructions are one byte long. · Immediate - In the immediate addressing mode, the operand is contained in the byte immediately following the opcode. The immediate addressing mode is used to access constants that do not change during program execution (e.g., a constant used to initialize a loop counter). EA = PC+1; PC PC+2 · Direct - In the direct addressing mode, the effective address of the argument is contained in a single byte following the opcode byte. Direct addressing allows the user to directly address the lowest 256 bytes in memory with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) · Extended - In the extended addressing mode, the effective address of the argument is contained in the two bytes following the opcode byte. Instructions with extended addressing mode are capable of referencing arguments anywhere MSC0408TS/D MSC0408TS/D Rev. 0 page 13 of 36 in memory with a single three-byte instruction. When using the Motorola assembler, the user need not specify whether an instruction uses direct or extended addressing. The assembler automatically selects the short form of the instruction. EA = (PC+1):(PC+2); PC PC+3 Address bus high (PC+1); Address bus low (PC+2) · Indexed, no offset - In the indexed, no offset addressing mode, the effective address of the argument is contained in the 8-bit index register. This addressing mode can access the first 256 memory locations. These instructions are only one byte long. This mode is often used to move a pointer through a table or to hold the address of a frequently referenced RAM or I/O location. EA = X; PC PC+1 Address bus high 0; Address bus low X · Indexed, 8-bit offset - In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the operand can be located anywhere within the lowest 511 memory locations. This addressing mode is useful for selecting the mth element in an n element table. EA = X+(PC+1); PC PC+2 Address bus high K; Address bus low X+(PC+1) where K = the carry from the addition of X and (PC+1) · Indexed, 16-bit offset - In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. EA = X+[(PC+1):(PC+2)]; PC PC+3 Address bus high (PC+1)+K; Address bus low X+(PC+2) where K = the carry from the addition of X and (PC+2) · Relative - The relative addressing mode is only used in branch instructions. In relative addressing, the contents of the 8-bit signed byte (the offset) following the opcode is added to the PC if, and only if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of relative addressing is from ­126 to +129 from the opcode address. The programmer need not calculate the offset when using the Motorola assembler, since it calculates the proper offset and checks to see that it is within the span of the branch. EA = PC+2+(PC+1); PC EA if branch taken; otherwise EA = PC PC+2 · Bit set/clear - In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte following the opcode specifies the address of the byte in which the specified bit is to be set or cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively set or cleared with a single two-byte instruction. EA = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) · Bit test and branch - The bit test and branch addressing mode is a combination of direct addressing and relative addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The address of the byte to be tested is in the single byte immediately following the opcode byte (EA1). The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set or cleared in the specified memory location. This single three-byte instruction allows the program to branch based on the condition of any readable bit in the first 256 locations of memory. The span of branch is from ­125 to +130 from the opcode address. The state of the tested bit is also transferred to the carry bit of the condition code register. EA1 = (PC+1); PC PC+2 Address bus high 0; Address bus low (PC+1) EA2 = PC+3+(PC+2); PC EA2 if branch taken; otherwise PC PC+3 page 14 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 MSC0408TS/D MSC0408TS/D Rev. 0 BSC BTB DIR EXT INH IMM Bit set/clear Bit test and branch Direct Extended Inherent Immediate NEGX 2 2 2 IX IX1 IX2 REL A X CLR TST INH 1INH Indexed (no offset) Indexed, 1 byte (8-bit) offset Indexed, 2 byte (16-bit) offset Relative Accumulator Index register DIR 1 CLRX 3 3 CLRA 5 TSTX INH 1INH INH 1INH 3 3 TSTA DIR 1 DIR 1 4 INCX 3 3 INCA 5 INC INH 1INH DECX DIR 1 DECA ROLX INH 1INH 3 3 ROLA LSLX INH 1INH 3 3 LSLA ASRX INH 1INH 3 3 INH 1INH 3 3 ASRA 2 DEC DIR 1 5 DIR 1 5 DIR 1 5 RORX 3 3 RORA 5 LSRX INH 1INH LSRA COMX INH 1INH 3 3 INH 3 3 11 COMA MUL DIR 1 5 ROL LSL 1 3 3 INH 1INH NEGA 2 2 2 2 2 2 2 2 2 2 2 CLR TST INC DEC ROL LSL ASR ROR LSR COM NEG Read/modify/write INH INH IX1 4 5 6 0100 0101 0110 DIR 1 ROR ASR 5 DIR 1 5 COM LSR 5 DIR 1 NEG DIR 3 0011 2 2 2 2 2 2 2 Abbreviations for address modes and registers Bit manipulation Branch BTB BSC REL High 0 1 2 Low 0000 0001 0010 5 5 3 0 0000 3BRSET0 2 BSET0 2 BRAREL BTB BSC 5 5 3 1 0001 3BRCLR0 2 BCLR0 2 BRNREL BTB BSC 5 5 3 2 0010 3BRSET1 2 BSET1 2 BHI REL BTB BSC 5 5 3 3 0011 3BRCLR1 2 BCLR1 2 BLSREL BTB BSC 5 5 3 4 0100 3BRSET2 2 BSET2 2 BCCREL BTB BSC 5 5 3 5 0101 3BRCLR2 2 BCLR2 2 BCSREL BTB BSC 5 5 3 6 0110 3BRSET3 2 BSET3 2 BNEREL BTB BSC 5 5 3 7 0111 3BRCLR3 2 BCLR3 2 BEQREL BTB BSC 5 5 3 8 1000 3BRSET4 2 BSET4 2 BHCC BTB BSC REL 5 5 3 9 1001 3BRCLR4 2 BCLR4 2 BHCS BTB BSC REL 5 5 3 A 1010 3BRSET5 2 BSET5 2 BPLREL BTB BSC 5 5 3 B 1011 3BRCLR5 2 BCLR5 2 BMIREL BTB BSC 5 5 3 C 1100 3BRSET6 2 BSET6 2 BMC BTB BSC REL 5 5 3 D 1101 3BRCLR6 2 BCLR6 2 BMSREL BTB BSC 5 5 3 E 1110 3BRSET7 2 BSET7 2 BIL REL BTB BSC 5 5 3 F 1111 3BRCLR7 2 BCLR7 2 BIH REL BTB BSC 9403 IX1 1 6 IX1 1 IX1 1 5 6 IX1 1 IX1 1 6 IX1 1 6 IX1 1 6 IX1 1 6 6 IX1 1 IX1 1 6 6 IX1 1 6 CLR TST INC DEC ROL LSL ASR ROR LSR COM NEG IX 7 0111 5 1 IX 1 5 IX IX 4 5 IX IX 5 IX 5 IX 5 IX 5 5 IX IX 1 5 1 IX 1 5 INH 6 9 1 1 1 1 1 1 1 TXA 2 2 2 2 2 2 2 2 INH 2 2 INH 2 INH 2 INH 2 2 INH 2 2 INH 2 2 INH 2 2 INH 2 NOP RSP SEI CLI SEC CLC TAX Not implemented INH 1 WAIT INH 2 2 INH 10 INH STOP SWI RTS RTI Control INH INH 8 9 1000 1001 2 STX LDX JSR JMP ADD Bytes Cycles SUB F 1111 IX 3 EXT 3 EXT 3 5 STX LDX EXT 3 6 EXT 3 4 JSR JMP EXT 3 3 EXT 3 4 ADD ORA EXT 3 4 EXT 3 4 ADC EOR EXT 3 5 EXT 3 4 STA LDA EXT 3 4 EXT 3 4 AND EXT 3 4 EXT 3 4 CPX EXT 3 4 SBC BIT 4 EXT 3 4 CMP SUB 5 IX2 2 IX2 2 6 IX2 2 5 IX2 2 7 IX2 2 4 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 6 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX2 2 5 IX1 1 IX1 1 5 IX1 1 4 IX1 1 6 IX1 1 3 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 5 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 IX1 1 4 4 STX LDX JSR JMP ADD ORA ADC EOR STA LDA BIT AND CPX SBC CMP SUB IX F 1111 IX IX 4 IX 3 IX 5 IX 2 IX 3 IX 3 IX 3 IX 3 IX 4 IX 3 IX 3 IX 3 IX 3 IX 3 IX 3 3 M68HC05 M68HC05 Opcode in binary Low 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 A 1010 B 1011 C 1100 D 1101 E 1110 F 1111 High Opcode in hexadecimal STX LDX JSR JMP ADD ORA ADC EOR STA LDA BIT AND CPX SBC CMP SUB IX1 E 1110 Address mode 0 0000 STX LDX JSR JMP ADD ORA ADC EOR STA LDA BIT AND CPX SBC CMP SUB Register/memory EXT IX2 C D 1100 1101 1 DIR 3 DIR 3 4 DIR 3 3 DIR 3 5 DIR 3 2 DIR 3 3 DIR 3 3 DIR 3 3 ORA ADC DIR 3 3 DIR 3 4 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 DIR 3 3 EOR STA LDA BIT AND CPX SBC 3 DIR 3 3 CMP SUB DIR B 1011 Mnemonic Legend 2 IMM 2 LDX 6 REL 2 2 BSR IMM 2 IMM 2 2 ADD ORA IMM 2 2 ADC 2 IMM 2 2 EOR 2 IMM 2 LDA IMM 2 2 IMM 2 2 AND IMM 2 2 IMM 2 2 CPX IMM 2 2 SBC BIT 2 IMM 2 2 CMP SUB IMM A 1010 Table 4-1 M68HC05 M68HC05 opcode map page 15 of 36 5 RESETS The active low RESET pin forces the chip to a known internal state and provides an orderly software start-up procedure. A reset may be initiated also by software. 5.1 Power-up detection reset Even if the RESET pin is not held low during power-up, the power-up detection circuitry will trigger an internal reset of the device when the supply voltage is applied to VDD. 5.2 Watchdog reset The watchdog system is controlled by the WDOG bit; it uses the time base to trigger an internal reset of the device. If the watchdog counter reaches its largest value after a time base timeout, then a watchdog reset will be activated (see Section 8.2). This feature is intended to detect program runaway, and to force resumption of the correct program flow. 5.3 Software reset To initiate a reset, the program can execute a STOP instruction anywhere in memory (except at STOPADD) while the watchdog system is active. page 16 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 6 INTERRUPTS Microprocessor based systems may require that normal processing be interrupted so that external events can be serviced; polling for asynchronous events (i.e. `interrupts') can be done by dedicated hardware. Background tasks, then, do not have to be suspended during polling; they will be interrupted only when necessary. The MSC0408 MSC0408 can be interrupted in three ways: two maskable hardware interrupt (on PA0 or from the time base) and a non-maskable software interrupt (SWI), which is executed regardless of the I-bit value. If both a maskable hardware interrupt and SWI occur at the same time then SWI is executed first. When an interrupt is serviced, normal processing is suspended at the end of the current instruction execution. The processor registers are then saved on the stack and the interrupt mask bit I is set to prevent additional interrupts from being serviced. The appropriate interrupt vector then points to the starting address of the interrupt service routine. Upon completion of that routine, the RTI instruction (which is usually part of the interrupt service routine) causes the processor registers' contents to be recovered from the stack before returning to normal processing; in particular, the I-bit is cleared. Interrupt priorities are summarized in Table 6-1. Table 6-1 Interrupt priorities Source Flags Vector address Priority - - $xxxx highest - - - $xxxx External interrupt (IRQ) I-bit INTFF INTFF $xxxx Time base interrupt (TIRQ) 6.1 Enable - Software interrupt (SWI) Note: Mask Reset I-bit TBEN TBF $xxxx lowest The interrupt test and branch instructions BIH and BIL test the condition of the Port A interrupt. Software interrupt Software interrupt (SWI) is an executable instruction that is executed regardless of the state of the interrupt mask bit I. 6.2 Hardware controlled interrupt sequence The three functions: STOP, WAIT and reset, are not in the strictest sense interrupts; however, they are acted upon in a similar manner. MSC0408TS/D MSC0408TS/D Rev. 0 page 17 of 36 7 LOW POWER MODES There are two power saving modes on the MSC0408 MSC0408, STOP and WAIT. These modes reduce the power consumption of the device significantly. 7.1 STOP instruction The STOP instruction places the MSC0408 MSC0408 in its lowest power consumption mode. In this mode, the internal clocks are turned off, with the exception of that required for the interrupt circuitry. To achieve the lowest possible power consumption in STOP mode, the external clock must be either tristated, or halted in the high state. During STOP mode the I-bit is cleared to enable external interrupts. All other registers and memory and all I/O lines remain unchanged. This state continues until an external interrupt (on PA0) or reset is sensed, at which time the processor clocks are turned on. Normal processing then resumes by loading the program counter with the appropriate vectors. Note: If a STOP instruction is executed (from an address other than `STOPADD') while the watchdog system is enabled, then a watchdog reset will occur. This `software reset' will thus reset the MSC0408 MSC0408. (See Figure 8-1 on how to execute a STOP instruction.) Note: Before an external interrupt can be recognized, the external clock must be active. 7.2 WAIT instruction The WAIT instruction places the MSC0408 MSC0408 in a low power consumption mode. In this mode the internal clock remains active, but the processor clocks are stopped causing all internal processing to be halted. During WAIT mode, the I-bit in the condition code register is cleared to enable external interrupts. All other registers and memory and all input/output lines remain unchanged. This state continues until an interrupt (on PA0, or from the timebase) or reset is sensed, at which time the processor clocks are turned on. Normal processing then resumes by loading the program counter with the appropriate vectors. page 18 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 8 TIME BASE AND WATCHDOG A time base and watchdog system is built into the MSC0408 MSC0408. A time base interrupt request is generated on each time base timeout, which will occur periodically, at a rate fTB. 8.1 Time base operation The time base is a 13-bit up-counter, which can either increment at the processor clock rate, or at a rate determined by an independent internal free-running oscillator, dependent on TBCLK. An overflow signal is generated each time counter roll-over from $1FFF to $0000 occurs. 8.2 Watchdog system The watchdog system uses the time base to trigger an internal reset of the MSC0408 MSC0408. If the watchdog counter reaches its largest value ($F), after a time base timeout, then a watchdog reset will be activated. To prevent any watchdog resets from occurring, the watchdog counter must be periodically cleared by software, at a rate faster than 15 times the time base overflow period. This is called a watchdog refresh, and is accomplished by executing a `JSR' instruction to the watchdog address, `WDOGADD'. This address contains an `RTS' instruction, thus returning control to the user software. During WAIT mode the watchdog system continues to operate, and a watchdog reset will thus occur after a maximum time 15tTB since the last watchdog refresh. In order to reduce the power consumption, the time base interrupt may be used to periodically wake up the processor from the WAIT mode and run some software, before going back into WAIT mode. If a STOP instruction is executed while the watchdog system is enabled, a reset is triggered, hence preventing entry into STOP mode. The only exception to this is the STOP instruction located at STOPADD. This STOP instruction may be executed by using a `JSR' to `STOPADD'. When the MSC0408 MSC0408 is brought out of STOP through an external interrupt, the interrupt routine is executed in the normal way, and the `RTS' instruction returns control to the main program (see Figure 8-1). main program flow `Stop' JSR $xxxx PA0 interrupt routine 1 $xxxx 4 $xxxx STOP 2 RTS 3 `Watchdog refresh' JSR $xxxx 1 Going into STOP mode 2 External interrupt on PA0 3 Return from interrupt 4 Exit STOP mode RTI Figure 8-1 STOP execution when watchdog is enabled MSC0408TS/D MSC0408TS/D Rev. 0 page 19 of 36 9 SECURITY FEATURES When the MSC0408 MSC0408 is in its normal operating mode (user mode), the degree of device testing and verification is limited, by intention. To test the features and performance of each individual device more fully, the MSC0408 MSC0408 design incorporates a test mode, that is used in the factory to verify the product's functionality and conformance to specification. Security features, designed to inhibit unauthorized entry into the test mode, are also implemented on the MSC0408 MSC0408. Motorola will normally activate these features (as described in this section) prior to shipment of product to the customer. The user's system design must take into account the features of the MSC0408 MSC0408, and their limitations, in order to achieve the best possible level of overall system security. 9.1 Physical security The MSC0408 MSC0408 has two modes of operation: user mode and test mode (used to test the device at the factory). Once testing is complete, the silicon containing the test pads and test circuitry is electrically isolated from the rest of the die, and then physically removed. All normal communications with the chip are now limited to the user pads and to the control of the customer's on-chip software. 9.2 `Out of bounds' detectors The MSC0408 MSC0408 incorporates `out of bounds' detectors which monitor the operation of the device and take some action whenever they detect that some abnormal operating condition has occurred. 9.3 Accumulator and index register clearing The accumulator and the index register are cleared on reset. 9.4 Control bytes Control bytes are provided to allow the user to configure on-chip security features. There are several options for the factory programming of these bytes (see Section 10). page 20 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 10 FACTORY TEST This product is tested, both functionally and parametrically, during the wafer probe test. At this point, the EEPROM can be programmed with customer specified data, if required (see Section 10.2 for options). Note: 10.1 For maximum test effectiveness it is essential that customers specify to Motorola the form and content of the `Answer-to-reset' sequence for each of their ROM codes. This may be used during probe testing and is mandatory for packaged product. Contact the sales office for further details. Burn-in of assembled product The burn-in of assembled smartcard product (to detect early lifetime EEPROM failures) is performed by running a section of burn-in code from within the user's ROM area. This implies that the customer controls entry to the burn-in software, as no special self-check or bootloader modes are available after assembly. The customer must supply burn-in code; Motorola can provide demonstration burn-in code if required. The software must comply with Motorola's burn-in specification as defined in the document Smartcard Burn-in Software Specification (12MSZ19139A 12MSZ19139A). Customers buying packaged parts should obtain a copy of this specification from Motorola. This document includes demonstration burn-in software routines. Because of the security features of this product, production testing of devices in packaged form is limited to basic tests to screen out assembly damage; not all failure mechanisms are detectable by this type of test. The test routine includes parametric tests on user pins, plus verification of any customer-specified `Answer-to-reset' sequence. Note: MSC0408TS/D MSC0408TS/D Rev. 0 Customers should be aware that burn-in of unpackaged devices (sawn wafer-on-tape) is not possible. page 21 of 36 10.2 Programming the EEPROM with customer specified data Motorola may, (unless instructed otherwise) write unique `traceability information' into some or all of the control bytes of each die as part of the factory testing. Part of this information may be specified by the customer. In addition, Motorola offers the option of writing further, customer specified, information to other areas of the EEPROM during factory testing. This information may be fixed, or vary according to agreed algorithms. Unless otherwise specified, all user EEPROM locations will be erased ($00). The options for factory programming of EEPROM data are: 1) Motorola standard traceability data is to be written into the control bytes ­ yes/no 2) Customer data (fixed or variable) is to be written into the `Transport key' ­ yes/no 3) Customer data (fixed or variable) to be written into other areas of EEPROM (200 bytes maximum) ­ yes/no In order to make effective use of the unique die identification provided by the traceability data, customers should include features to make use of this data as part of their ROM codes. This can, for example, provide useful access control capabilities or a manufacturing audit trail. If any option requiring customer specific data to be written to the EEPROM is selected, a standard form (Customer specified data for MSC0408 MSC0408 EEPROM) must be submitted to the factory for approval, before the submission of the ROM code. Such data will only be written to the EEPROM after the customer has received an approved and signed copy of the form back from the factory. Depending on the complexity of the customer's requirements, this process may take up to three weeks (when variable data is involved). Contact the local sales office for further details. page 22 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 11 DC LATCH-UP PROTECTION All input pins, output pins and input/output pins must sustain an input/output current of ±200mA without indication of latch-up or damage. Figure 11-1 shows the test circuit used; the maximum allowed voltage on the pin under test is 10 volts. The signal applied to the pin under test is a full wave rectified 50Hz or 60Hz AC signal. (This signal can be produced by a curve tracer.) All I/O pins should be in tristate mode or set up as input. The test is performed at room temperature, with no clock signal applied to the CLK pin. IDD Positive latch-up A VDD 5.0 V Pin under test + IIN Test voltage VSS V IDD Negative latch-up A VDD 5.0 V + Pin under test IIN Test voltage VSS V Figure 11-1 DC latch-up test fixture The test sequence is as follows: Slowly adjust the variable voltage above VDD (positive latch-up) or below VSS (negative latch-up) until the current IDD makes a sudden jump to its current limited value; this is a sign that latch-up has occurred. Record the value of IIN just prior to the sudden increase in IDD. MSC0408TS/D MSC0408TS/D Rev. 0 page 23 of 36 12 ESD PROTECTION The electrostatic discharge (ESD) failure mechanism is simulated with electrostatic pulses generated by the circuit shown in Figure 12-1. The test is performed at room temperature by applying positive pulses, then negative pulses, with a time interval of one second, to each of the pins to be tested, with VSS applied and all other pins floating. A failure occurs when the leakage current measured on a pin exceeds the value given in the electrical specification. It should be noted that pins with internal pull-ups cannot be checked for absolute leakage current, and therefore cannot be easily checked for ESD failure. Note: This test meets ISO 7816 requirements. Motorola devices meet, or exceed, these requirements; contact the sales office for current data. 1500 VP (to pin under test) VESD V 100pF VSS ESD test fixture VP 100% ESD test signal waveform 90% 36.8% 10% 15ns max. 150ns typical t Figure 12-1 ESD test page 24 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 13 Note: 13.1 ELECTRICAL SPECIFICATIONS Specifications in italics are estimated values only, and are provided as an indication of the intended performance of the MSC0408 MSC0408. Guaranteed values will be determined during the MSC0408 MSC0408 qualification programme and will be available when this programme is complete. Maximum ratings This device contains circuitry designed to protect against damage due to high electrostatic voltages or fields. However, it is recommended that normal precautions be taken to avoid the application of any voltages higher than those given in Table 13-1. Table 13-1 Maximum ratings Parameter Supply voltage Input voltage Operating temperature Storage temperature sawn wafer-on-tape packaged product Symbol Min. Max. Unit VDD ­ 0.3 7.0 V VIN VSS ­ 0.3 VDD + 0.3 V TA ­ 25 + 85 °C 3 ­ 55 6 125 TSTG °C Caution: Stresses in excess of those listed in Table 13-1 may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions outwith those indicated in the operational sections of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect reliability, including EEPROM data retention and write/erase endurance. These absolute maximum conditions can be met in the presence of potentially out-of-specification signal excursions by using silicon diode clamps to the supply rails. The current capability of these diodes should be chosen to suit the maximum expected current as determined by the source impedance of the hardware connected to the pin. It may be appropriate to add a series resistor to increase the impedance to a value whereby this current is limited within the maximum rating and can be clamped with a low cost diode. MSC0408TS/D MSC0408TS/D Rev. 0 page 25 of 36 13.2 EEPROM characteristics (VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = ­ 25 to + 85 °C) Characteristic(1) Programming/erase time Write/erase endurance Data retention Symbol Min. Max. tPROG 2 - ms 50,000(2) - cycles 10 - years tDR Unit (1) These parameters are temperature dependent and the values quoted are typical, for the worst case (+ 85°C) conditions. Better performance will usually be obtained for operation at normal temperatures. For example, at 25°C and for VDD = 5.0 V, a typical value of 1,200,000 write-erase cycles could be expected. Refer also to Motorola's current Reliability Report for up-to-date failure rate information. (2) This figure is based on a maximum programming time of 3 ms. (VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = ­ 25 to + 85 °C) Characteristic(1) Programming/erase time Write/erase endurance Data retention Symbol Min. Max. tPROG 7 - ms 50,000(2) - cycles 10 - years tDR Unit (1) These parameters are temperature dependent and the values quoted are typical, for the worst case (+ 85°C) conditions. Better performance will usually be obtained for operation at normal temperatures. For example, at 25°C and for VDD = 5.0 V, a typical value of 1,200,000 write-erase cycles could be expected. Refer also to Motorola's current Reliability Report for up-to-date failure rate information. (2) This figure is based on a maximum programming time of 7 ms. page 26 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 13.3 AC electrical characteristics (VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = ­ 25 to + 85 °C, unless otherwise indicated) Clock option = ÷ 1 Characteristic Clock option = ÷ 2 Symbol Min. Max. Min. Max. Unit External clock frequency fOSC dc 5.0 dc 10.0 MHz External clock rise/fall time tR , tF - 500 - 500 ns External clock duty cycle RCLK 45 55 40 60 % fOP dc 5.0 dc 5.0 MHz MCU bus frequency Processor cycle time tCYC 200 200 ns Input hold time ­ ports tHOLD 2 - 2 - tCYC Power-on reset delay tPORL 32 - 32 - tCYC Recovery from STOP delay tILCH - 11 - 11 tCYC tRL 2 - 2 - tCYC External interrupt pulse width ITLOW 1 - 1 - tCYC ESD protection (see Section 12) VESD ± 4000 - ± 4000 - V RESET pulse width (VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = ­ 25 to + 85 °C, unless otherwise indicated) Clock option = ÷ 1 Characteristic Clock option = ÷ 2 Symbol Min. Max. Min. Max. Unit External clock frequency fOSC dc 2.0 dc 4.0 MHz External clock rise/fall time tR , tF - 500 - 500 ns External clock duty cycle RCLK 45 55 40 60 % fOP dc 2.0 dc 2.0 MHz MCU bus frequency Processor cycle time tCYC 500 500 ns Input hold time ­ ports tHOLD 2 - 2 - tCYC Power-on reset delay tPORL 32 - 32 - tCYC Recovery from STOP delay tILCH - 11 - 11 tCYC tRL 2 - 2 - tCYC External interrupt pulse width ITLOW 1 - 1 - tCYC ESD protection (see Section 12) VESD ± 4000 - ± 4000 - V RESET pulse width MSC0408TS/D MSC0408TS/D Rev. 0 page 27 of 36 13.4 DC electrical characteristics (VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = ­ 25 to + 85 °C) Symbol Min. Max. Unit Output high voltage (ILOAD = ­0.1 mA) Characteristic VOH 0.7 VDD - V Output low voltage (ILOAD = +1.6 mA) VOL - 0.4 V Input high voltage PA0, CLK RESET VIH 0.7 VDD VDD ­ 0.7 VDD + 0.3 VDD + 0.3 Input low voltage PA0 CLK RESET VIL 0 0 0 1.0 0.5 0.6 Input current (VIN = VSS to VDD) PA0 CLK RESET IIN ­ 1000 ­ 100 ­ 200 20 20 20 Supply current(1) RUN WAIT(2) (no programming) STOP(2) (clock running) STOP(2) (no external clock) IDD - - - - 5 1300 600 50 V V µA mA µA µA µA (1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs. External clock frequency 10.0 MHz, internal operating frequency 5.0 MHz, unless otherwise stated. (2) No DC loads, all inputs at VDD, VDD = 5.0V + 10%. (VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = ­ 25 to + 85 °C) Symbol Min. Max. Unit Output high voltage (ILOAD = ­0.1 mA) Characteristic VOH 0.7VDD - V Output low voltage (ILOAD = +1.6 mA) VOL - 0.4 V Input high voltage PA0, CLK RESET VIH 0.7 VDD TBD VDD + 0.3 VDD + 0.3 Input low voltage PA0 CLK RESET VIL 0 0 0 0.6 0.3 0.36 Input current (VIN = VSS to VDD) PA0 CLK RESET IIN ­ 1000 ­ 100 ­ 200 20 20 20 µA Supply current(1) RUN WAIT(2) (no programming) STOP(2) (clock running) STOP(2) (no external clock) IDD - - - - 2.4 350 150 25 mA µA µA µA V V (1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching currents inherent in CMOS designs. External clock frequency 4.0 MHz internal operating frequency 2.0 MHz, unless otherwise stated. (2) No DC loads, all inputs at VDD, VDD = 3.0 V + 10%. page 28 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 14 PACKAGING AND PIN ASSIGNMENTS All pins are ISO standard connections (marked with a dagger, thus: VDD). Note: A VPP connection is also defined in ISO standard ISO7816/2 ISO7816/2, to provide for devices that require an external programming voltage; this connection is not required on the MSC0408 MSC0408. Note: Smartcard applications do not usually require packaged product. However, industry standard packaging options are available. Please contact your local Motorola sales office if you require packaged product. VSS VDD RESET CLK PA0 47 48 49 50 51 52 2 3 4 5 6 7 VSS Figure 14-1 MSC0408 MSC0408 bond pad layout 8 46 9 45 10 44 11 43 12 42 VDD 41 13 52-pin PLCC (Case outline: 778) 14 15 40 39 33 32 31 30 29 28 27 CLK PA0 26 34 25 35 20 24 36 19 23 37 18 22 17 RESET 38 21 16 Note: all unlabelled pins must be left unconnected Figure 14-2 MSC0408 MSC0408 production packaging MSC0408TS/D MSC0408TS/D Rev. 0 page 29 of 36 15 BONDING INFORMATION Figure 15-1 is a top view of the MSC0408 MSC0408 die, showing the location of the user bond pads. Figure 15-1 applies only to the mask set specified; please contact Motorola for the correct bonding information for other mask sets. B VSS F VDD User bond pad sizes: 110 x 110 110 x 220 (VDD) C A RESET D CLK PA0 Dim. A B E µm Notes 4959.0 1.All dimensions in micron (µm). 4486 2.VDD and VSS pads are aligned. C 2278 D 1917 Dim. µm E 432 F 332 3.Do not scale. 4.Nominal die size: 5.04 x 5.61 mm. Figure 15-1 MSC0408 MSC0408 die layout - top view page 30 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 16 ORDERING INFORMATION To order an MSC0408 MSC0408 the customer must provide Motorola with the details of the customer-specific code that is to be programmed into the device (ROM or EEPROM) during manufacture. This may be supplied on EPROM or on a floppy disk. The MSC0408 MSC0408 is available in sawn wafer form and in industry standard packaging; it is NOT available in unsawn wafer form. 16.1 Export control The United Kingdom Government (H.M.G.), in common with many other governments, requires an export control compliance declaration as to whether mask ROM products include any information security (for example, encryption or decryption algorithms) as part of their software or hardware. If the customer requires Motorola to program any information security into the device during manufacture, then the appropriate information must be supplied, in order that Motorola can obtain an export licence for the product. Many conditional access and other security conscious systems include some form of information security as a means of protection against unauthorized access to data. For example, one such method uses a standard encryption algorithm for authentication purposes, such as PIN verification. Typical algorithms include: DES, DSS, GSM proprietary, COMP128 COMP128, etc. This practice is acceptable and will not normally affect the granting of an export licence. It is essential that the purpose of any information security processes be declared, whether it is for authenticative access control, integrity of data, non-repudiation, protection of confidentiality through encryption of data, or key management and associated supplementary services, and that brief details of the application be supplied. It is mandatory that the correct algorithm used be declared and, if it is a proprietary one, that details of the algorithm be supplied. Caution: If information submitted to Motorola is found to be false, then the granting of an export licence may be delayed or refused, resulting in late or non-shipment of the customer's product. In such a case, Motorola cannot be held responsible and the customer will be liable for the full resale value for all product and work-in-progress inventory held by Motorola, whether an export licence is granted or not. 16.1.1 When to apply for a licence If an export licence is required (see above) then H.M.G. requires a further undertaking from the customer of the form shown in Figure 16-1 (for silicon) and in Figure 16-2 (for emulator systems and technical data). This communication must be on the customer's headed notepaper and must be an original (not a photocopy or fax); it must be signed by a partner or principal officer of the company. Motorola will forward this to H.M.G. For most products, it is appropriate to apply for an export licence when placing the initial mask order with Motorola. An export licence declaration, quoting approximate maximum volumes anticipated over the next two years should be submitted to Motorola with the order. It will be necessary to renew the export licence, when the time period and/or the quantity run out. (See Figure 16-1) Because of the powerful encryption capabilities offered by Motorola's Modular Arithmetic Processor unit (MAP), smartcard devices containing this module are subject to tighter governmental controls. Before any product, or development system, or detailed technical information, can be supplied, an initial export licence must be obtained. (see Figure 16-2.) 16.1.2 What ".the above goods are for our own use." means For the purposes of export control, this phrase in the export licence declaration (Figure 16-1 and Figure 16-2) refers only to the integrated circuit die, as shipped by Motorola. These die are considered, by H.M.G., to be a raw material, for use in another product, such as a Smartcard. The export licence needed by Motorola covers only the use of this raw material. Any subsequent processing of the die, such as encapsulation or programming the EEPROM, means that an export licence for the new product may be required. This must be obtained from the country now exporting the product. MSC0408TS/D MSC0408TS/D Rev. 0 page 31 of 36 A COMPANY (Registered address) Department of Trade and Industry, London. Dear Sir, We, (name and address of the company), certify that the goods shown below have been ordered by us from (name and address of Motorola Sales Office) in (country) as sales office for Motorola, Colvilles Road, Kelvin Estate, East Kilbride, Glasgow, G75 0TG, Scotland. The goods to be supplied are (device type and approximate quantity, to cover the next two years) of integrated circuit die and are to be used for the following purposes: .(Insert use, e.g. Smartcards for mobile phones/ Smartcards for banking purposes/Smartcards for access control/etc.) We also certify that the goods above are for our own use and will not be re-exported or sold for export. We also certify that the goods will not be used for military purposes. We confirm that the above goods will not be used for purposes associated with chemical, biological or nuclear weapons, or missiles capable of delivering such weapons, nor will they be resold if we know or suspect that they are intended or likely to be used for such a purpose. Yours faithfully, Name (BLOCK CAPITALS): _ Position/title: _ Date: _ Figure 16-1 Sample customer declaration for export licence application for silicon page 32 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 A COMPANY (Registered address) Department of Trade and Industry, London. Dear Sir, We, (name and address of the company), certify that the goods shown below have been ordered by us from (name and address of Motorola Sales Office) in (country) as sales office for Motorola, Colvilles Road, Kelvin Estate, East Kilbride, Glasgow, G75 0TG, Scotland. The goods to be supplied are (description/part numbers and approximate quantity, to cover the next two years) of development tools or technical data and are to be used for the following purposes: .(Insert use, e.g. product evaluation, or development of software for mobile phones, banking, access control, etc.) We also certify that the goods above are for our own use and will not be re-exported or sold for export. We also certify that we do not intend to sell or otherwise dispose of the goods above. We also certify that the goods will not be used for military purposes. We confirm that the above goods will not be used for purposes associated with chemical, biological or nuclear weapons, or missiles capable of delivering such weapons, nor will they be resold. For and on behalf of (company name), (authorized signature) Name (BLOCK CAPITALS): _ Position/title: _ Date: _ Figure 16-2 Sample customer declaration for export licence application for emulator systems and technical documentation MSC0408TS/D MSC0408TS/D Rev. 0 page 33 of 36 16.2 Customer specified data for MSC0408 MSC0408 ROM To initiate a ROM pattern for the MSC0408 MSC0408, the customer should first contact his local sales office or Motorola representative for further information on how to transfer the data to Motorola. The customer-specified ROM data may be supplied on EPROM or on disk, as detailed below. EPROM A single EPROM programmed with the customer's software (using positive logic representation for address and data) should be submitted to Motorola for pattern generation. The EPROM should be programmed such that the contents of the last byte of the MSC0408 MSC0408 memory map are contained in the last byte of the EPROM. The offset from the bottom of the EPROM to the first byte of customer code should be clearly stated. All unused bytes must be programmed to $00. EPROMs should be clearly labelled, placed in a conductive IC carrier and securely packed. Disk An IBM format floppy disk, containing a file with the customer's software in S-record format, should be submitted to Motorola for pattern generation. The file should specify the contents of every byte of the MSC0408 MSC0408's ROM, with unused bytes containing $00. 16.2.1 Verification media All original pattern media (EPROMs, disks) are filed for contractual purposes and cannot be returned. A computer listing of the ROM code will be generated and returned along with a listing verification form. The listing should be thoroughly checked and the verification form completed, signed and returned to Motorola. The signed verification form constitutes the contractual agreement for creation of the custom mask. If desired, Motorola will program blank EPROMs (supplied by the customer) from the data file used to create the custom mask, to aid in the verification process. 16.2.2 ROM verification units (RVUs) Ten MCUs containing the customer's ROM pattern will be sent for program verification. These units will have been made using the custom mask but are for the purpose of ROM verification only. For expediency, they are usually unmarked and are tested only at room temperature (25°C) and at 5V. These RVUs are included in the mask charge and are not production parts. They are neither backed nor guaranteed by Motorola Quality Assurance. RVUs are supplied in 52-pin CERQUAD packages (see Figure 16-3). At the customer's request, an RVU wafer can be supplied; this will be shipped against the customer's initial production order. 16.2.3 Security verification units (SVUs) Security verification units can be supplied to allow the customer to verify that Motorola has correctly programmed fixed and/or variable data into the private key area of the EPROM. page 34 of 36 MSC0408TS/D MSC0408TS/D Rev. 0 47 48 49 50 51 52 VSS 2 3 4 5 6 7 8 46 9 45 10 44 11 43 12 42 VDD 41 13 52-pin CERQUAD (Case outline: 778) 14 15 40 39 33 32 31 30 29 28 27 CLK PA0 26 34 25 35 20 24 36 19 23 37 18 22 17 RESET 38 21 16 Note: all unlabelled pins must be left unconnected Figure 16-3 RVU pinout MSC0408TS/D MSC0408TS/D Rev. 0 page 35 of 36 page 36 of 36 MSC0408TS/D MSC0408TS/D Rev. 0