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MSC0 Datasheet

Part Manufacturer Description PDF Type
MSC-01-D-00-50 Methode Electronics Connector: SMC: M: 0 to 10G: 50: CRMP: THRU: Gold Original
MSC-01-D-00-75 Methode Electronics Connector: SMC: M: 0 to 10G: 75: CRMP: THRU: Gold Original
MSC-01-D-00-95 Methode Electronics Connector: SMC: M: 0 to 10G: 95: CRMP: THRU: Gold Original
MSC-01-D-01-50 Methode Electronics Connector: SMC: M: 0 to 10G: 50: CRMP: THRU: Gold Original
MSC-01-D-01-75 Methode Electronics Connector: SMC: M: 0 to 10G: 75: CRMP: THRU: Gold Original
MSC-01-D-02-75 Methode Electronics Connector: SMC: M: 0 to 10G: 75: CRMP: THRU: Gold Original
MSC-01-D-02-95 Methode Electronics Connector: SMC: M: 0 to 10G: 95: CRMP: THRU: Gold Original
MSC-01-D-03-50 Methode Electronics Connector: SMC: M: 0 to 10G: 50: CRMP: THRU: Gold Original
MSC0402 Atmel 8-bit microcontroller with 8K EEPROM and advanced security features Original
MSC0406 Atmel 8-bit microcontrollern with 1.3K EEPROM and advanced security features Original
MSC0407 Atmel IC MCU 8-Bit MSC04 CISC 23KB ROM 5MHZ 5V Original
MSC0501 Atmel 8-bit microcontroller with Modular Exponentiation Unit Original
MSC0801 Atmel 8-bit microcontroller for applications in contactless smartcards and smartcards with contacts Original

MSC0

Catalog Datasheet MFG & Type PDF Document Tags

hct595

Abstract: HC595 (counter+ > 10000u) { counter = clear; } /* software update */ if (update = 1) { MSC0_DD.U = data; MSC0_ISC.B.SDP = true; update = clear; } /* turn off repeat mode */ if (update = 2) { MSC0_DSC.B.TM = false; update = clear; } /* turn on repeat mode */ if (update = 3) { MSC0_DSC.B.TM = true; update = clear , and usage with the HCT595 and MSC0. Note: The TC1796 allows for a maximum expansion of 56 outputs. 32 , calculated by 2 data transfers on the MSC0. 1 .9 2 u s e c 1 .1 8 u s e c Figure 7 GPTA PWM Change
Infineon Technologies
Original
HC595 AP3201 Infineon Tricore TC1796 EN01 LTC24 msc diode AP32101

278240

Abstract: PDMA :CDB20 = 1 Flash memory with a Plcyc of 0.16 µs 288 milliseconds 712 milliseconds/ (MSC0:RDF0 = 08 17.8 MBytes/second MSC0:RRR0 = 3) MDCNFG:TDL0 = 10) Application Note 9 , (MSC0:RDF0 = 08 22.1 MBytes/second MDCNFG:DWID0 = 0 MSC0:RRR0 = 3) MDCAS02 = 0101 0101 0101 , 0110 0011 0001 288 milliseconds (MSC0:RDF0 = 08 MDCNFG:TRP0 = 4 MSC0:RDN0 = 9 MDCNFG:CDB20 = 1 712 milliseconds/ 26.5 MBytes/second MSC0:RRR0 = 3) MDCNFG:TDL0 = 00) SDRAM with
Intel
Original
SA-1110 278240 PDMA

28F320J3

Abstract: pxa210 accesses within Static Memory Banks 0 and 1, respectively. MSC0 contains two identical configuration , configures nCS0 for asynchronous page-mode reads as follows: · · · · RBUFF0 (MSC0[15]) = 0b0 (Slower device - Return Data Buffer) RRR0 (MSC0[14:12]) = 0b010 (read recovery: 2 * 2 + 1 = 5 MEMCLKs) RDN0 (MSC0[11:8]) = 0x0010 (ROM delay - next access: 2 + 1 = 3 MEMCLKs) RDF0 (MSC0[7:4]) = 0b1011 (ROM delay - first access: 11+ 2 = 13 MEMCLKs) (nWE assert: 5 + 1 = 6 MEMCLKs) · RBW0 (MSC0[3]) = 0b1
Intel
Original
AP-762 28F320J3 pxa210 INTEL 28F320J3 PXA250 and PXA210 manual Intel AP-762 PXA210

28F640K3C110

Abstract: PXA250 : · RBUFF0 (MSC0[15]) = 0b0 (Slower device - Return Data Buffer) · RRR0 (MSC0[14:12]) = 0b001 (read recovery: 30 ns) · RDN0 (MSC0[11:8]) = 0x0010 (ROM delay - next access: 30 ns) 7 AP-748 · RDF0 (MSC0[7:4]) = 0b1011 (ROM delay - first access: 130 ns) · RBW0 (MSC0[3]) = 0b0 (data bus width: 32 bits) · RT0 (MSC0[2:0]) = 0b011 (memory type: burst-of-eight flash w/ non-burst writes) 5.0 Bus , into MSC0:RDF0+1 determines the number of MEMCLK cycles that nWE (WE#) is asserted for page-mode flash
Intel
Original
PXA250 28F640K3C110 Intel AP-748 28F640K3 R305 290737 AP-738 PXA250/

Infineon Tricore TC1792

Abstract: TC1792 PLL_CLC Register fCPU CPU Clock fSYS SSC1 fCLC0 fMSC0 MSC0 fCLC1 fMSC1 MSC1 CAN_CLC CAN_FDR CPU fCLC1 fSSC1 MSC1_CLC MSC1_FDR TriCore TM SSC0 MSC0_CLC MSC0_FDR , / SCU SSC0 / SSC1 / GPTA Port 3 GPTA Port 4 Port 5 ASC0 / ASC1 / MSC0 / MLI0 Port 6 SSC0 / SSC1 / CAN Port 7 ADC0 / ADC1 Port 8 MLI1 / GPTA Port 9 MSC0 / GPTA Port 10 , Move Engine 0 M/S Slave ASC0 System Peripheral Bus M/S MSC1 Slave MSC0 DMA
Infineon Technologies
Original
TC1792 Infineon Tricore TC1792 TTCAN TR10 TR11 TR12 GT00RUN GT01RUN GT10RUN GT11RUN MCA06001

AP-702

Abstract: ap702 bits. If it is pulled high, the ROM width is 32 bits. 3.3 Control Signal Generation MSC1/MSC0 , ) contains information for two memory regions as selected by CS3:0. MSC0 (Bits 31-16) control the CS1 memory region MSC0 (Bits 15-0) control the CS0 memory region MSC1 (Bits 31-16) control the CS3 memory , configure the 3 Volt Intel StrataFlash memory read region as shown in Figure 1, the MSC0[15:0] register
Intel
Original
AP-702 28F128J3A 28F640J3A ap702 Intel AP-702 28F320J3A SA-1100 38F320J3A AP-677

tc1766

Abstract: tms 3874 MSC0 MLI1 MLI0 Mem Check MCB06056_bd Figure 1 Data Sheet TC1766 Block Diagram , Configuration Alternate Functions PORST HDRST General Control MSC0 Control ADC Analog Inputs Port 0 , -Bit AN[35:0] SSC0/1, MLI0, GPTA, MSC0 Port 3 16-Bit FCLP0A FCLN0 SOP0A SON0 GPTA, SSC1 , Ground 153 FCLN0 O 2886 7852 MSC0 Differential Driver Clock Output Negative 154 FCLP0A O 2766 7852 MSC0 Differential Driver Clock Output Positive A 155 SON0A O
Infineon Technologies
Original
tms 3874 TC1766ED Infineon Tricore TC1766 tricore 1797 ME 4946 SAL-TC1766-192F80U

292235

Abstract: StrongARM SA-1100 relates to flash: 3.2 Static Memory Control Registers (MSC1-0) MSC1/MSC0 are control registers , diagram while Figure 3 shows a write timing diagram. MSC0 (Bits 31­16) control the CS1 memory region MSC0 (Bits 15­0) control the CS0 memory region MSC1 (Bits 31­16) control the CS3 memory region MSC1
Intel
Original
AP-687 28F640J5 292235 StrongARM SA-1100 StrongARM SA1100 AP-647 CORPORATION1997 28F320J5 AP-664 AP-663

CC-1075

Abstract: TC1165 . . . . . . . . . . . . . . Micro Second Bus Interfaces (MSC0) . . . . . . . . . . . . . . . . . . . , SSC1 8 ch. SMIF Ext. Request Unit Multi CAN (2 Nodes, 64 Buffer) 1) FADC 2 ch. MSC0 , Symbol GPTA, SCU GPTA, SSC1, ADC SSC0/1, MLI0, GPTA, MSC0 ASC0/1, SSC0/1, SCU, CAN GPTA, SCU GPTA, OCDS L2, MLI0/1 1) MSC0 Control ADC Analog Inputs OCDS / JTAG Control Oscillator 1 , port which can be alternatively used for GPTA I/O, and interface for MLI0, MSC0 or SSC0/1. TCLK0A IN32
Infineon Technologies
Original
CC-1075 TC1165 TC1165/TC1166 EIA/JESD22A114-B JESD22-C101-C J-STD-020C

3182N

Abstract: Infineon Tricore TC1762 BOOT (SSC0) . . . . . . . . . . . . . . . . . . .35 Micro Second Bus Interface (MSC0) . . . . . . . . . . . . , , 64 Buffer) MSC0 Mem Check MLI0 Figure 2-1 TC1762 Block Diagram Data Sheet 6 Ana , XTAL1 XTAL2 VDDOSC3 VSSOSC3 VDDOSC VSSOSC MCB06066 GPTA, SCU GPTA, ADC SSC0, MLI0, GPTA, MSC0 ASC0/1, SSC0, SCU, CAN GPTA, SCU GPTA, OCDS L2, MLI0 MSC0 Control ADC Analog Inputs TC1762 OCDS , alternatively used for GPTA I/O, and interface for MLI0, MSC0 or SSC0. TCLK0A IN32 / OUT32 TREADY0A IN33 / OUT33
Infineon Technologies
Original
3182N Infineon Tricore TC1762 BOOT SAK-TC1762-128F66HL TC1796 v1.3

Infineon Tricore TC1762 BOOT

Abstract: TC1762 (SSC0) . . . . . . . . . . . . . . . . . . .35 Micro Second Bus Interface (MSC0) . . . . . . . . . . . . , Nodes, 64 Buffer) MSC0 Mem Check MLI0 Figure 2-1 TC1762 Block Diagram Data Sheet 6 , , GPTA, MSC0 ASC0/1, SSC0, SCU, CAN GPTA, SCU GPTA, OCDS L2, MLI0 MSC0 Control ADC Analog Inputs , generalpurpose I/O port which can be alternatively used for GPTA I/O, and interface for MLI0, MSC0 or SSC0 , .12 P2.13 SLSO04 EN00 SLSO05 EN01 FCLP0B SOP0B SDI0 SSC0 Slave Select output 4 MSC0 enable output 0
Infineon Technologies
Original
Infineon Tricore TC1762

Kern

Abstract: D400 amplifier . Micro Second Bus Interfaces (MSC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . , Instruction Cache Scratch-Pad RAM Local Data RAM Overlay RAM Boot ROM Program Flash Data Flash MSC0 , Functions PORST HDRST General Control Port 0 16-bit Port 1 15-bit MSC0 Control ADC Analog , /1, SSC0, SCU, CAN Port 4 4-bit AN[35:0] SSC0, MLI0, GPTA, MSC0 Port 3 16-bit FCLP0A , can be alternatively used for GPTA I/O, and interface for MLI0, MSC0 or SSC0. A2 TCLK0A A2
Infineon Technologies
Original
Kern D400 amplifier microsecond bus TC1161 TC1162 TC1161/TC1162 256-K
Abstract: Figure 1 Data Sheet Multi CAN (3 Nodes, 128 MO) MSC0 SSC2 (LVDS) 3.3V Ext. FADC , (3 Nodes, 128 MO) MSC0 3.3V Ext. FADC Supply SSC2 (LVDS ) BlockDiagram SAK-TC1782N , Multi CAN (3 Nodes, 128 MO) MSC0 3.3V Ext. FADC Supply SSC2 (LVDS) BlockDiagram , TC1782 4 Port 0 Port 1 Port 2 Port 3 1) GPTA, SCU, E-RAY, MSC0 GPTA, SSC1, ADC0, OCDS GPTA, SSC0/1, MLI 0, MSC0 GPTA, ASC0/1, SSC0/1, SCU, CAN, MSC0 Port 4 GPTA, SCU, CAN Port 5 Infineon Technologies
Original
SAK-TC1782N-320N160HR SAK-TC1782F-320F160HR SAK-TC1782N-320N160HL SAK-TC1782F-320F160HL SAK-TC1782F-256F133HR SAK-TC1782F-256F133HL

TC1766ED

Abstract: transistor D400 pin diagram . . . . . . . .37 Micro Second Bus Interfaces (MSC0) . . . . . . . . . . . . . . . . . . . . . . . , SystemPeri p heral Bus (SPB) OCDSDebug Interface/JTAG FPI-Bus Interface 8 KBPRAM MSC0 MLI0 , -bit GPTA, SSC1, ADC Port 2 14-bit SSC0/1, MLI0, GPTA, MSC0 FCLP 0A FCLN0 Port 3 16-bit ASC0 , , MLI0 HDRST General Control MSC0 Control ADC Analog Inputs NMI BYPASS TESTMODE AN[35:0 , alternatively used for GPTA I/O, and interface for MLI0, MSC0 or SSC0/1. A2 TCLK0 A2 IN32 / OUT32
Infineon Technologies
Original
TC1764 transistor D400 pin diagram single phase ac motor control CERBERUS ocds DATA SHEET OF D400 transistor transistor D400 pin diagram application

tc1782

Abstract: TC1782ED . Request Unit Multi CAN (3 Nodes, 128 MO) FADC (3.3V max) 4 3.3V Ext. FADC Supply MSC0 , ) 4 3.3V Ext. FADC Supply MSC0 (LVDS) SSC2 BlockDiagram SAK-TC1782256F133HL Figure 2 , 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 1) GPTA, SCU, E-RAY, MSC0 GPTA, SSC1, ADC0, OCDS GPTA, SSC0/1, MLI 0, MSC0 GPTA, ASC0/1, SSC0/1, SCU, CAN, MSC0 OCDS / JTAG Control TDI / BRKIN TDO , D VD D FL3 9 10 11 GPTA, SCU, CAN GPTA, MLI0, E-RAY, SSC2 GPTA, MSC0 1) Analog Inputs
Infineon Technologies
Original
TC1782ED SAK-TC1782 F180HL TC 1782 SAKTC1782-256F t51 0007 212
Abstract: selected by setting the MSC0# jumper on the ISDN TA daughter module. The demonstration program should be , sets up the code to access the packet SRAM using MSC0#. If the /D SMALLSRAM option is set, the code , to work on the CDP, the CDP must be set up for accessing SRAM with memory chip select 0 (MSC0) by jumpering MSC0 on JP10. The demonstration program should be compiled with the DRAM option defined with the Advanced Micro Devices
Original
186TMCC/CH/CU 186CC/CH/CU 79C961A E86MON

TC1796 multican

Abstract: TC1796ED Bus Interfaces (MSC0, MSC1) . . . . . . . . . . . . . . . . . . . . . . MultiCAN Controller (CAN) . . , ASC0 / ASC1 / MSC0 / MSC1 /MLI0 SSC0 / SSC1 / MSC0 / MSC1 / CAN ADC0 / ADC1 MLI1 / GPTA MSC0 / MSC1 , ASC0/1 or MSC0/1 lines. RXD0A ASC0 receiver input/output A TXD0A ASC0 transmitter output A RXD1A ASC1 , BYPASS = 1 and stored in inverted state as bit OSC_CON.MOSC. EN00 MSC0 device select output 0 RREADY0B MLI0 receive channel ready output B SDI0 MSC0 serial data input EN10 MSC1 device select output 0
Infineon Technologies
Original
TC1796 multican TC1796ED TC1796 Pin Reliability in Overload Infineon Technologies TC1796ED static SRAM dual-port P-BGA-416

tc1766

Abstract: Infineon Tricore TC1766 High-Speed Synchronous Serial Interfaces (SSC0 and SSC1) . . . . . . . . . Micro Second Bus Interfaces (MSC0 , Interface/JTAG FPI-Bus Interface 8 KB PRAM MSC0 MLI1 MLI0 Mem Check MCB06056_mod , /1, MLI0, GPTA, MSC0 FCLP 0A FCLN0 Port 3 16-bit ASC0/1, SSC0/1, SCU, CAN SOP0A SON0 , Control MSC0 Control ADC Analog Inputs NMI BYPASS TESTMODE VDDM TRST VSSM V DDMF ADC , generalpurpose I/O port which can be alternatively used for GPTA I/O, and interface for MLI0, MSC0 or SSC0/1
Infineon Technologies
Original
SAK-TC1766-192F80HL PS3 power supply sak-tc1766-192F80HL BB TC1766 bd sak-tc1766 MCB06195
Abstract: SSC1) . . . . . . . . . .37 Micro Second Bus Interfaces (MSC0) . . . . . . . . . . . . . . . . . . . . , ADC0 32 ch. FADC 2 ch. 8 ch. SMIF Ext. Request Unit Multi CAN (2 Nodes, 64 Buffer) MSC0 , VDDOSC VSSOSC Oscillator GPTA, SCU GPTA, SSC1, ADC SSC0/1, MLI0, GPTA, MSC0 ASC0/1, SSC0/1, SCU, CAN GPTA, SCU GPTA, OCDS L2, MLI0 MSC0 Control ADC Analog Inputs TC1764 OCDS / JTAG Control , -bit bi-directional generalpurpose I/O port which can be alternatively used for GPTA I/O, and interface for MLI0, MSC0 Infineon Technologies
Original
Abstract: Unit Figure 1 Data Sheet Multi CAN (3 Nodes, 128 MO) MSC0 SSC2 (LVDS) 3.3V Ext , Figure 2 Data Sheet Multi CAN (3 Nodes, 128 MO) MSC0 3.3V Ext. FADC Supply SSC2 , (3 Nodes, 128 MO) MSC0 3.3V Ext. FADC Supply SSC2 (LVDS) BlockDiagram SAK-TC1782F , Multi CAN (3 Nodes, 128 MO) MSC0 3.3V Ext. FADC Supply SSC2 (LVDS) BlockDiagram , , E-RAY, MSC0 GPTA, SSC1, ADC0, OCDS GPTA, SSC0/1, MLI 0, MSC0 GPTA, ASC0/1, SSC0/1, SCU, CAN, MSC0 Infineon Technologies
Original
SAK-TC1182N-320F180HR SAK-TC1182N-320F180HL SAKTC1182N-256F133HR SAK-TC1182N-256F133HL SAKTC1782N-320F160HL SAK-TC1782N-320F160HR

TAD32

Abstract: TIC bus MSC0 MLI1 MLI0 Mem Check MCB06056_bd Figure 1 Data Sheet TC1766 Block Diagram , Configuration Alternate Functions PORST HDRST General Control MSC0 Control ADC Analog Inputs Port 0 , -Bit AN[35:0] SSC0/1, MLI0, GPTA, MSC0 Port 3 16-Bit FCLP0A FCLN0 SOP0A SON0 GPTA, SSC1 , Ground 153 FCLN0 O 2886 7852 MSC0 Differential Driver Clock Output Negative 154 FCLP0A O 2766 7852 MSC0 Differential Driver Clock Output Positive A 155 SON0A O
Siemens
Original
TAD32 TIC bus CRC-16 SIEMENS CRC-16 T7110-XV11-L2-7600 D-81541 CD15-0 CD15-8
Abstract: (SSC0) . . . . . . . . . . . . . . . . . . .35 Micro Second Bus Interface (MSC0) . . . . . . . . . . . . , Nodes, 64 Buffer) MSC0 Mem Check MLI0 Figure 2-1 TC1762 Block Diagram Data Sheet 6 , , GPTA, MSC0 ASC0/1, SSC0, SCU, CAN GPTA, SCU GPTA, OCDS L2, MLI0 MSC0 Control ADC Analog Inputs , generalpurpose I/O port which can be alternatively used for GPTA I/O, and interface for MLI0, MSC0 or SSC0 , .12 P2.13 SLSO04 EN00 SLSO05 EN01 FCLP0B SOP0B SDI0 SSC0 Slave Select output 4 MSC0 enable output 0 -
OCR Scan
T7110-XV10-D3-7600 P-TQFP-100

gp914

Abstract: PSB 7200 / SCU SSC0 / SSC1 / GPTA Port 3 GPTA Port 4 Port 5 ASC0 / ASC1 / MSC0 / MLI0 Port 6 SSC0 / SSC1 / CAN Port 7 ADC0 / ADC1 Port 8 MLI1 / GPTA Port 9 MSC0 / GPTA Port 10 , PLL_CLC Register fCPU CPU Clock fSYS SSC1 fCLC0 fMSC0 MSC0 fCLC1 fMSC1 MSC1 , Move Engine 0 M/S Slave ASC0 System Peripheral Bus M/S MSC1 Slave MSC0 DMA , for MSC0/MSC1 or GPTA0/GPTA1 I/O lines. Compared to TC1796, the I/O line connections of Port 2 with
Siemens
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gp914 PSB 7200 CD10 GP10 PCM24 bel 3726 FALCTM54

PSB 7200

Abstract: PSB7110 max) LTCA2 4 SSC1 Ext. Request Unit Figure 1 Multi CAN (3 Nodes, 128 MO) MSC0 , Circuitry Power Supply TC1784 VDDP V SS VSSP 14 Port 3 GPTA, SCU. E-RAY, MSC0 GPTA, SSC1, ADC0, OCDS GPTA, SSC0/1, MLI0, MSC0 GPTA, ASC0/1, SSC 0/1, SCU, CAN, MSC 0 Port 4 GPTA, SCU , MSC0 Serial Data Input 1 HWCFG1 I Hardware Configuration Input 1 OUT1 O1 GPTA0 Output , 14 REQ4 External Request Input 4 O1 GPTA0 Output 14 FCLP0C O2 MSC0 Clock Output
Siemens
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PSB7110 7110F
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