IEEE1149 QL6250-PQ208 QL6250 QL6325-6PT280C - Datasheet Archive

 

Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 Utopia Level 2 Slave to Utopia Level 1 Master

 

MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 Utopia Level 2 Slave to Utopia Level 1 Master Multiplexer Datasheet 1 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 CONTENTS 1 INTRODUCTION . 3 1.1 2 UTOPIA OVERVIEW . 3 UTOPIA L2 SLAVE TO L1 MASTER MULTIPLEXER APPLICATION . 4 UTOPIA LEVEL 2/1 MULTIPLEXER CORE FEATURES . 5 3 APPLICATION. 6 4 CORE PINOUT . 7 4.1 SIGNAL DESCRIPTIONS . 8 5 GLOBAL SIGNAL DISTRIBUTION . 12 6 FUNCTIONAL DESCRIPTION ­ UTOPIA INTERFACE . 13 6.1 UTOPIA INTERFACE SINGLE PHY TRANSMIT INTERFACE (L1) . 13 Cell Level Transfer ­ Single Cell . 13 Cell Level Transfer ­ Back to Back Cells.14 6.2 UTOPIA INTERFACE SINGLE PHY RECEIVE INTERFACE (L1) . 14 Cell Level Transfer ­ Single Cell . 14 Cell Level Transfer ­ Back to Back Cells.15 6.3 UTOPIA INTERFACE MPHY TRANSMIT (L2) . 16 MPHY Operation with Direct Status. 16 6.4 UTOPIA INTERFACE MPHY RECEIVE (L2) . 17 MPHY Operation with Direct Status. 17 7 CORE MANAGEMENT AND ERROR HANDLING . 18 8 COMPLEXITY AND PERFORMANCE SUMMARY. 19 8.1 8.2 9 TIMING PARAMETERS DEFINITION . 19 ECLIPSE IMPLEMENTATION . 20 DEVICE PINOUT . 21 9.1 9.2 9.3 SIGNALS OVERVIEW . 21 280 PIN FPBGA PINOUT TABLE. 23 280 PIN FPBGA DEVICE DIAGRAM . 24 10 REFERENCES . 25 11 CONTACT . 25 2 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 1 Introduction 1.1 Utopia Overview The Utopia (Universal Test & Operations PHY Interface for ATM) interface is defined by the ATM Forum to provide a standard interface between ATM devices and ATM PHY or SAR (segmentation and Re-assembly) devices. Higher Layers Management AAL Master Utopia Slave ATM Master Utopia Slave PHY Figure 1: Utopia Reference Model The Utopia Standard defines a full duplex bus interface with a Master/Slave paradigm. The Slave interface responds to the requests from the Master. The Master performs PHY arbitration and initiates data transfers to and from the Slave device. The ATM forum has standardized the Utopia Levels 1 (L1) to 3 (L3). Each level extends the maximum supported interface speed from OC3, 155Mbps (L1) over OC12, 622Mbps (L2) to 3.2Gbit/s (L3). The following Table 1 gives an overview of the main differences in these three levels. Table 1: Utopia Level Differences Utopia Level Interface Width Max. Interface Speed Theoretic (typical) Throughput 1 8 bit 25 MHz 200Mbps (typ. OC3 155Mbps) 2 8 bit, 16 bit 50 MHz 800Mbps (typ. OC12 622MBps) 3 8 bit, 32 bit 104MHz 3.2Gbps (typ. OC 48 2.5GBps) Utopia Level 1 implements an 8-bit interface running at up to 25MHz. Level 2 adds a 16 Bit interface and increases the speed to 50MHz. Level 3 extends the interface further by a 32 Bit word-size and speeds up to 104MHz providing rates up to 3.2 Gbit/s over the interface. 3 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 In addition to the differences in throughput, Utopia Level 2 uses a shared bus offering to physically share a single interface bus between one master and up to 31 slave devices (Multi-PHY or MPHY operation). This allows the implementation of aggregation units that multiplex several slave devices to a single Master device. The Level 1 and Level 3 are point-to-point only, whereas Level 1 has no notion of multiple slaves. Level 3 still has the notion of multiple slaves, but they must be implemented in a single physical device connected to the Utopia Interface. 2 Utopia L2 Slave to L1 Master Multiplexer Application Utopia Level 2 offers the notion of multiple PHYs (MPHY) and a shared bus topology to connect several PHY devices to a single ATM Layer device, or use PHY devices with multiple ports. The L2 Slave to L1 Master Multiplexer implements the necessary interfaces enabling to connect multiple Level 1 PHY devices to a Level 2 topology. The Multiplexer itself implements two or more Ports and aggregates them on the Level 2 interface. As Utopia Level 2 allows for higher speed, at least two Level 1 devices can be aggregated into a single Level 2 interface without exceeding bandwidth. A bus extension to 16 bit on the L2 side can enable up to four Level 1 devices without exceeding the Level 2 interface bandwidth. rxclav[0] rxclav[1] Utopia Master rxclav[0] rxclav[1] TX and RX data and address busses txclav[0] txclav[1] Utopia 1 Slave Utopia 1 Master Utopia 1 Slave PHY Device 0 Utopia 2 Slave txclav[0] txclav[1] ATM Layer Device: 2 PHY support with direct status indication Utopia 1 Master PHY Device 1 Multiplexer Utopia Level 2 Utopia Level 1 Figure 2: Utopia 2 Port Multiplexer Example 4 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 Utopia Level 2/1 Multiplexer Core Features · Implements an Utopia L2 Slave and two to four Utopia L1 Masters providing a solution to aggregate Utopia Level 1 Slave devices to a Level 2 Master · Compliant with ATM-Forum af-phy-0039.000 (Level 2) and af-phy-0017.000 (Level 1) · Implements 8bit data busses · Level 2 interface implements MPHY mode with direct status indication · Round Robin port arbitration independent for Egress (TX) and Ingress (RX) data pathes · Level 2 interface meets 50MHz performance offering up to 400Mbps cell rate transfers · Level 1 interface meets 25MHz performance offering up to 200Mbps cell rate transfers per Port · Single chip solution with up to 3 east ports for improved system integration · Supports cell level transfer mode · Cell and clock rate decoupling with on chip FIFOs · Up to 1 KByte of on chip FIFO per data direction · Integrated management interface and built-in errored cell discard · ATM Cell size programmable via external pins from 16 to 128 bytes · Level 2 MPHY address programmable via external pins · Optional Utopia parity generation/checking enable/disable via external pin · Built in JTAG port (IEEE1149 IEEE1149 compliant) · Simulation model available for system level verification (Contact Quicklogic or MorethanIP for details) · Solution also available as flexible Soft-IP core, delivered with a full device modelization and verification testbenches. 5 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 3 Application Utopia L1 Master TxClav RxClk RxClav RxEnb* RxAddr[4:0] TxClav TxEnb* TxData[7:0] RxData[7:0] RxSoc TxSoc TxClk TxClk TxClav TxEnb* TxData[7:0] TxSoc TxClk TxClav TxEnb* TxAddr[4:0] TxData[7:0] TxSoc TxSoc TxClk RxData[7:0] RxSoc TxData[7:0] Port N-1 TxEnb* TxAddr[4:0] Utopia L1 Slave RxEnb* RxData[7:0] RxSoc L2 Slave Port 0 RxClk RxClav RxEnb* RxAddr[4:0] RxData[7:0] RxSoc RxClk RxClav RxEnb* L2 Master RxClk RxClav Utopia L1 Master ATM Device Eclipse Utopia L1 Slave ATM PHYs Figure 3: L2 to L1 Multiplexer Data flows from the West side TX Interface to the corresponding TX Port on the east side of the multiplexer and the RX Ports to the RX Interface accordingly. All Ports are served in a round-robin fashion, whereas the TX and RX sides are decoupled, too. 6 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 4 Core Pinout On the Utopia interfaces, the Core implements all the required Utopia signals and provides all the Utopia optional signals (Indicated by an `O' in the following tables). The optional Utopia signals are activated during the Core configuration and inactive Utopia signals should be left unconnected (Outputs) or tied to a zero logic level (inputs) as specified in the following Tables. In addition to the Utopia Interface signals, error indication signals are available for error monitoring or statistics. An error indication always shows that a cell has been discarded by the multiplexer. Possible errors are parity or cell-length errors on the receive interface of the corresponding Utopia Interfaces. All Utopia interfaces work in the same transfer mode (cell level). A mix is not possible. To identify the sides of the core the notion "WEST" and "EAST" for the corresponding interfaces is used. WEST EAST Slave Interface (L2) Master Interface(s) (L1) wtxclav[3:0] Utopia Transmit etxclav() etxenb() wtxenb wtxaddr[4:0] etxdat()[7:0] wtxdat[N:0] wtxsoc wtxprty Egress Egress Utopia Receive wrxclav[3:0] Utopia L2 Slave/ Utopia L1 Master Multiplexer erxclk() erxclav() erxenb() wrxenb erxdat()[7:0] wrxaddr[4:0] wrxdat[N:0] wrxsoc wrxprty Error Indication from Transmit etxsoc() etxprty() etxclk() wtxclk wrxclk Utopia Transmit Ingress Ingress erxsoc() erxprty() erx_err() erx_err_stat()[1:0] wtx_err wtx_err_stat[1:0] waddr[4:0] prty_en reset cellsize[7:0] Figure 4: L2 to L1 Multiplexer Top Entity 7 Utopia Receive Error Indication from Receive Configuration MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 4.1 Signal descriptions Table 2: Global Signal Pin Mode reset In Description Active high chip reset. Table 3: Device Management Interface Pin wtx_err Mode Out Description Transmit error indication on west interface. When driven high, indicates that an errored cell (Wrong parity or wrong length) was received from the device connected to the west interface and is discarded. Transmit error status information for west interface. When wtx_err is driven, indicates the error status of the discarded cell: · wtx_err_stat(1:0) erx_err(n) Out Out wtx_err_stat(0) : When set to `1' indicates that a cell is discarded because of a parity error. · wtx_err_stat(1) : When set to `1' indicates that a cell is discarded because it has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia interface within less than a complete cell time). Receive error indication on east interface port n (n=0.3). When driven high, indicates that an errored cell (Wrong parity or wrong length) was received from the device connected to the corresponding east interface port. Receive error status information for east receive interface port n (n=0.3). When etx_err is driven, indicates the error status of the discarded cell: · etx_err_stat(2n) : When set to `1' indicates that a cell is discarded because of a parity error. · erx_err_stat(2n+1:2n) etx_err_stat(2n+1) : When set to `1' indicates that a cell is discarded because it has a wrong length (Consecutive assertion of ut_tx_soc on the Utopia interface within less than a complete cell time). Out Note: wtx_. signals are sampled with west transmit clock (wtxclk). erx_. signals are sampled with west receive clock (wrxclk). Table 4: West Utopia Level 2 Slave Transmit Interface Pin Mode wtxclk In Description 50MHz transmit byte clock. The Core samples all Utopia Transmit signals on txclk rising edge. 8 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 wtxdata[N:0] In Transmit data bus. The width of the data bus is be 8 Bit. N is the MSB. Transmit data bus parity. Standard odd or non-standard even parity can be optionally checked by the connected Slave. wtxprty(O) In wtxsoc In Transmit start of cell. Asserted by the Master to indicate that the current word is the first word of a cell. wtxenb In Active low transmit data transfer enable. When the parity check is disabled during the Core configuration, or not used in the design, the pin txprty should be tied to '0'. Out Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space to accept one cell. wtxclav[3:1] Out Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status indication is selected during the Core configuration, one txclav signal is implemented per PHY port. The maximum number of clav signals is limited to four. wtxaddr[4:0] In wtxclav[0] Utopia transmit address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. Note: (O) indicates optional signals. Table 5: West Utopia Level 2 Slave Receive Interface Pin Mode wrxclk In 50MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk rising edge. wrxdata[N:0] Out Receive data bus. The width of the data bus is 8 bit. Bit N is the MSB. wrxprty (O) Out wrxsoc Out wrxenb In wrxclav[0] Out Description Receive data bus parity. Standard odd or non standard even parity can be optionally generated by the Utopia Slave Core. When the parity generation is disabled during the Core configuration, the pin rxprty can be let unconnected. Receive start of cell. Asserted to indicate that the current word is the first word of a cell. Active low transmit data transfer enable. Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space one cell available in the FIFO. 9 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 wrxclav[3:1] Out Extra FIFO Full / Cell buffer available. In MPHY mode and when direct status indication is selected, one rxclav signal is implemented per PHY port. The maximum number of clav signals is limited to four. Not used and not available. wrxaddr(4:0) In Utopia receive address. When the Core operates in MPHY mode, address bus used during polling and slave port selection. Bit 4 is the MSB. Table 6: East Utopia Level 1 Master Transmit Interface (per Port, n=0.3) Pin Mode etxclk(n) In etxdata(n)[7:0] Out Description 25MHz transmit byte clock port n. The Core samples all Utopia Transmit signals on txclk rising edge. Transmit data bus. The width of the data bus is 8 bit. Bit N is the MSB. Transmit data bus parity. Standard odd or non-standard even parity can be optionally checked by the connected Slave. etxprty(n) (O) Out etxsoc(n) Out Transmit start of cell. Asserted by the Master to indicate that the current word is the first word of a cell. etxenb(n) Out Active low transmit data transfer enable. etxclav(n) In When the parity check is disabled during the Core configuration, or not used in the design, the pin txprty should be left open. Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost full (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space to accept one cell. Note: (O) indicates optional signals. Table 7: East Utopia Level 1 Master Receive Interface (per Port, n=0.3) Pin Mode erxclk(n) In 25MHz receive byte clock. The Core samples all Utopia Receive signals on rxclk rising edge. erxdata(n)[7:0] In Receive data bus. The width of the data bus can be 8 or 16bit. Bit N is the MSB. erxprty(n) (O) In erxsoc(n) In Description Receive data bus parity. Standard odd or non standard even parity can be optionally generated by the Utopia Slave Core. When the parity generation is disabled during the Core configuration, the pin rxprty can be let unconnected. Receive start of cell. Asserted to indicate that the current word is the first word of a cell. 10 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 erxenb(n) erxclav(n) Out In Active low transmit data transfer enable. Cell buffer available. Asserted in octet level transfers to indicate to the Master that the FIFO is almost empty (Active low) or, in cell level transfers, to indicate to the Master that the PHY port FIFO has space one cell available in the FIFO. Table 8: Device Configuration Pins Pin Mode Description waddr[4:0] In Programs the Utopia L2 Slave address used on the west interfaces (tx and rx). Enable parity checking on the Utopia interface. prty_en In cellsize[7:0] In If disabled (tied to 0), the wrx_err_stat(0) signal can be ignored and left open and the rx parity input should be tied to 0. Also the tx parity pins can be left open. Define cellsize: sets the size in bytes of a cell. Binary value to be set usually by board wiring. The configuration pins are not intended for change during operation. They are usually board wired to configure the device for operation. 11 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 5 Global Signal Distribution The externally provided Utopia Transmit and Receive clocks are connected to global resources to provide low skew and fast chip level distribution. In both data directions, the corresponding Utopia Interfaces are decoupled by asynchronous FIFOs. Therefore each interface runs completely independent, each at its own tx and rx clocks which typically are up to 50 MHz on the WEST and up to 25 MHz on the EAST interfaces. The Error indications of all receive interfaces are always sampled within the west clock domains. The errors of the east rx interfaces are available on the erx_err(n) signal (one per Port), which is handled using the west clock domain (wrxclk). The west tx (receiving) error is directly derived from the west tx block (wtxclk). wrxclk WEST Interface (SLAVE) EAST Interface (MASTER) ~ read erxclk ~ write (Ingress clock) RX RX erx_err wtxclk ~ write etxclk ~ read (Egress clock) TX TX wtx_err Clocks West Clocks East Figure 5: Slave/Master Multiplexer Clock Distribution (one east port shown) 12 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 6 Functional Description ­ Utopia Interface The Utopia Multiplexer implements a single port on the west and separate single-PHY interfaces on the east. The West Interface (Utopia L2) operates in MPHY mode with direct status indication. It implements a single clav signal per direction and port (t/rxclav[X]) and the address bus to select the device within a shared bus topology. The East Interface (L1) has no notion of MPHY. It has a single clav signal and no address bus. 6.1 Utopia Interface Single PHY Transmit Interface (L1) The Transmit interface is controlled by the Master. The transmit interface has data flowing in the same direction as the ATM enable ut_tx_enb. The ATM transmit block generates all output signals on the rising edge of the ut_txclk. Transmit data is transferred from the Master to Slave via the following procedure. The Slave indicates it can accept data using the ut_txclav signal, then the Master drives data onto ut_txdat and asserts ut_txenb. The Slave controls the flow of data via the ut_txclav signal. Cell Level Transfer ­ Single Cell The Slave asserts ut_txclav 1 when it is capable of accepting the transfer of a whole cell. The Master asserts ut_txenb (Low) to indicates that it drives valid data to the Slave 2. Together with the first octet of a cell, the Master device asserts ut_txsoc for one clock cycle 3. To ensure that the Master does not cause transmit overrun, the Slave deasserts ut_txclav at least 4 cycles before the end of a cell if it cannot accept the immediate transfer of the subsequent cell 4. The Master can pause the cell transfer by de-asserting ut_txenb 5. To complete the transfer to the Slave, the Master de-asserts ut_tx_enb 6. 4 1 2 6 5 3 ut_txclk ut_txclav_dir ut_txenb ut_txsoc /ut_txdat 1 1 19 1A 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 ut_txprty Figure 6: Single Cell Transfer ­ Cell Level Transfer 13 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 Cell Level Transfer ­ Back to Back Cells When, during a cell transfer, the Slave is able to receive a subsequent cell, the Master can keep ut_txenb asserted between two cells 1 and asserts ut_txsoc, to start a new cell transfer, immediately after the last octet of the previous cell 2. 1 2 ut_txclk ut_txclav ut_txenb ut_txsoc ut_txdat 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 0001 0002 0003 0004 0005 0006 0007 0008 0009 000A 000B 000C 000D 000E 000F 0010 0011 0012 0013 0014 0015 0016 0017 0018 0019 001A 001B 0000 ut_txprty Cell N Cell N+1 Figure 7: Back to Back Cell Transfer ­ Cell Level Transfer 6.2 Utopia Interface Single PHY Receive Interface (L1) The Receive interface is controlled by the Master. The receive interface has data flowing in the opposite direction to the Master enable ut_rxenb. Receive data is transferred from the Slave to Master via the following procedure. The Slave indicates it has valid data, then the Master asserts ut_rxenb to read this data from the Slave. The Slave indicates valid data (thereby controlling the data flow) via the ut_rxclav signal. Cell Level Transfer ­ Single Cell The Slave asserts ut_rx_clav when it is ready to send a complete cell to the Master device 1. The Master interface asserts ut_rxenb to start the cell transfer. The Slave samples ut_rxenb and starts driving data 2. The Slave asserts ut_rxsoc together with the cell first word to indicate the start of a cell 3. The Master can pause a transfer by de-asserting ut_rxenb 4. The Slave samples high ut_rxenb and stops driving data 5. To resume the transfer, the Master re-asserts ut_rxenb 6. The Slave samples low ut_rxenb and starts driving valid data 7. The Master drives ut_txenb high one before the expected end of the current cell if the Slave has no more cell to transfer 8. The Slave de-asserts ut_rxclav to indicate that no new cell is available 9. 14 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 1 3 6 4 8 9 ut_rclk ut_rclav ut_renb ut_rsoc ut_rdat Z ut_rprty Z 2 7 5 Figure 8: Single Cell Transfer ­ Cell Level Transfer Cell Level Transfer ­ Back to Back Cells If the Master keeps ut_rxenb asserted at the end of a cell transfer 1 and if the Slave has a new cell to send, the Slave keeps ut_rxclav asserted 2 and immediately drives the new cell asserting ut_rxsoc to indicate the start of a new cell 3. 1 2 3 ut_rxclk ut_rxclav ut_rxenb ut_rxsoc ut_rxdat ut_rxprty Cell N Cell N+1 Figure 9: Back to Back Cells Transfer ­ Cell Level Transfer Note: If the Master keeps ut_rxenb asserted at the end of a packet and if the Slave does not have a new cell available, the Slave de-asserts ut_rxclav and the data of the bus ut_rxdat are invalid. 15 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 6.3 Utopia Interface MPHY Transmit (L2) When operating in MPHY mode, the Master checks, (Typically in a round robin fashion) the status of all the Slave ports. Two options are defined by the Utopia standard: · Polled status indication with all the PHY ports using a shared single CLAV signal to report their status to the Master · Direct status indication with one CLAV implemented per PHY port or per Utopia group. In MPHY mode only one transmit PHY port is selected at a time for data transfers but the Master continuously polls the status of the Slave's other PHY ports. The multiplexer west interface implements the second approach, using direct status indication. MPHY Operation with Direct Status For each PHY port, a status signal ut_txclav is permanently available. The Utopia Bus then supports up to four PHY ports, each using one CLAV signal (Slave port ut_txclav_dir(n). For each port independently, ut_txclav_dir(n) is asserted when enough space is available for a complete cell in the port FIFO 1 and ut_txclav_dir(n) is de-asserted when the corresponding port FIFO cannot receive the subsequent cell 2. Status signals and cell transfers are independent of each other for each port. No address information is needed to obtain status information. Address information must be valid only for selecting a PHY port prior to one or multiple cell transfers. To select a port, the Master deasserts ut_txenb 3, puts address port on ut_txaddr(4:0) 4, the port is selected by the Slave when ut_txenb goes low (Re-asserted by the Master) 5. 1 5 4 2 ut_txclk ut_txclav_dir(3) ut_txclav_dir(2) ut_txclav_dir(1) ut_txclav_dir(0) ut_txaddr x n m x x ut_txenb ut_txsoc ut_txdat ut_txprty Port m Port n 3 Figure 10: MPHY Transmit ­ Direct Status Indication As defined for single CLAV Utopia Transmit, the Master can pause a transfer and implicitly reselect a PHY port. 16 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 6.4 Utopia Interface MPHY Receive (L2) When operating in MPHY mode, the Master checks, (Typically in a round robin fashion) the status of all the Slave ports. Two options are defined by the Utopia standard: · Polled status indication with all the PHY ports using a signal CLAV signal to report their status to the Master · Direct status indication with one CLAV implemented per PHY port or per Utopia group. In MPHY mode only one receive PHY port is selected at a time for data transfers but the Master can continuously polls the status of the Slave PHY ports. MPHY Operation with Direct Status For each PHY port, a status signal ut_rxclav_dir(n) is permanently available. For each port independently, ut_rxclav_dir(n) is asserted when the corresponding PHY port has a cell available in its FIFO 1 and ut_rxclav_dir(n) is de-asserted when the corresponding port FIFO cannot transmit a complete cell to the Master 2. Status signals and cell transfers are independent of each other for each port. No address information is needed to obtain status information. Address information must be valid only for selecting a PHY port prior to one or multiple cell transfers. To select a port, the Master deasserts ut_rxenb 3, puts address port on ut_rxaddr(4:0) 4, the port is selected by the Slave when ut_rxenb goes low (Re-asserted by the Master) 5. 4 2 3 1 ut_rxclk ut_rxaddr(4:0) x n x m x ut_rxclav_dir(3) ut_rxclav_dir(2) ut_rxclav_dir(1) ut_rxclav_dir(0) ut_rxenb ut_rxsoc ut_rxdat ut_rxprty Port n Port m 5 Figure 11: MPHY Receive ­ Direct Status Indication 17 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 7 Core Management and Error Handling On Egress, the Core is designed to handle and report Utopia errors such as Parity error or wrong cell length. Errored cells are discarded with an error status indication provided to the user PHY application. When an errored cell is received on the Utopia interface, the Core discards the complete cell and provides a cell discard indication to the User PHY application (Signal eg_err(n) asserted) 1 together with a cell discard status (Signal eg_err_stat(1:0) 2. Note: eg_err is routed to the corresponding wtx_err and erx_err respectively (see Figure 4). 1 ff_eg_clk(0) ff_eg_cav(0) ff_eg_rdy(0) ff_eg_dval(0) ff_eg_soc(0) ff_eg_data(0) 000A 000B 000C 000D 000E ff_eg_err(0) ff_eg_err_stat(0) Cell N+2 Cell N 2 Figure 12: Cell Discard Indication Table 9: Error Status Word Bit Coding Error Status Bit Name Description 0 PARITY_ERR Valid when wtx/etx_err is asserted. If set to one indicates that a cell is discarded with a parity error decoded by the Core. 1 LENGTH_ERR Valid when wtx/etx_err is asserted. If set to one indicates that a cell is discarded with a cell length error detected on the Utopia interface. The signals are sampled on the corresponding clocks from the west interface: · erx_. sampled with wrxclk (west receive clock) · wtx_. sampled with wtxclk (west transmit clock) 18 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 8 Complexity and Performance Summary 8.1 Timing Parameters Definition ut_tclk ut_rclk tco ut_rxdat, ut_rxsoc ut_rxprty, ut_rxenb ut_rxclav, ut_txclav Figure 13: Tco Timing Parameter Definition ut_tclk ut_rclk tsu ut_txdat, ut_txsoc ut_txprty, ut_txaddr ut_rxaddr, ut_txenb ut_rxenb Figure 14: Tsu Timing Parameter Definition 19 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 8.2 Eclipse Implementation Table 10: Eclipse Implementation Summary Selected Options FIFO depth Utopia Interface MPHY (Ports) 8 Bit 2 Ingress per port Cells RAM Blocks odd 512 per port Parity Egress 512 Implementation 1428 12 Table 11: 8-Bit Utopia Interface Timing Characteristics QL6250-PQ208 QL6250-PQ208 typ Max Unit Parameter -5 -6 tco 7.5 9.5 7.0 ns tsu 2.5 3.2 2.4 ns wrxclk 46 66 MHz wtxclk 48 69 MHz erxclk 45 62 MHz etxclk 45 62 MHz minimum reset time 50 ns Note: QL6250 QL6250 with timing model "worst" at 25 degrees used. 20 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 9 Device Pinout 9.1 Signals Overview The table summarizes all signals. If less than 4 ports are implemented, the port numbers N vary from 0 to maximum port available. Signals Description wrxclk, wrxclav, wrxenb*, wrxdat, wrxsoc, wrxaddr West Utopia L2 Receive Interface. wtxclk, wtxclav, wtxenb*, wtxdata, wtxsoc, wtxaddr West Utopia L2 Transmit Interface. wtx_err, wtx_err_stat West Interface error indication (sampled with wtxclk). erxclk[N], erxclav[N], erxenb[N]*, erxsoc[N], erxdataN[7:0] East Utopia L1 Receive Interface. Port N (N=0.3) etxclk[N], etxclav[N], etxenb[N]*, etxsoc[N], etxdataN[7:0] East Utopia L1 Transmit Interface. Port N (N=0.3) Note: the data port names are not indexed, instead, explicitly named erxdata0. erxdata3 each consisting of 8 pins. Note: the data port names are not indexed, instead, explicitly named erxdata0. erxdata3 each consisting of 8 pins. Unused etxdatN[] signals of non-existing ports should be left open. erx_err[0], erx_err_stat[1:0] East Interface error indication Port 0 (sampled with wrxclk). erx_err[1], erx_err_stat[3:2] East Interface error indication Port 1 (sampled with wrxclk). erx_err[2], erx_err_stat[5:4] East Interface error indication Port 2 (sampled with wrxclk). erx_err[3], erx_err_stat[7:6] East Interface error indication Port 3 (sampled with wrxclk). prty_en, cellsize, waddr Configuration Pins to be board wired. Usual values for waddr are between 0 and 3. reset Active high device reset GND Ground VCC Device Power 3.3 V clk(x) unused clock inputs should be tied to GND IOCTRL(x) VCCIO(x) IO Power 3.3 V INREF(x) connect to GND 21 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 Signals Description PLLRST(x) connect to GND or VCC PLLOUT(x) connect to GND or VCC VCCPLL(x) GNDPLL(x) TCK, TRSTB JTAG signals. connect to GND TMS, TDI JTAG signals. connect to VCC TDO JTAG signal. leave open iov nc not connected. should be left open *: active low signal 22 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 9.2 280 Pin FPBGA Pinout Table Pin Function Pin Function Pin Function Pin Function Pin Function A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 F1 F2 F3 F4 F5 F15 F16 F17 F18 F19 G1 G2 G3 G4 G5 G15 G16 G17 G18 G19 H1 H2 H3 H4 H5 H15 H16 H17 H18 H19 J1 J2 J3 J4 J5 J15 J16 J17 J18 J19 K1 K2 K3 K4 K5 K15 K16 K17 K18 K19 L1 L2 L3 L4 L5 L15 L16 L17 L18 L19 M1 M2 M3 M4 M5 M15 M16 M17 M18 M19 N1 N2 N3 N4 N5 N15 N16 N17 N18 N19 P1 P2 P3 P4 P5 P15 P16 P17 P18 P19 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 PLLOUT3 GNDPLL0 cellsize[7] reset etxdat2[0] IOCTL etxdat2[1] etxdat2[2] etxdat2[3] etxclk[1] erxdat1[1] erxdat1[2] erxdat1[3] IOCTL erxdat1[4] erxdat1[5] erxdat1[6] PLLRST1 GND PLLRST0 GND etxdat2[4] etxdat2[5] etxdat2[6] INREF etxdat2[7] etxdat3[0] TMS erxclk[1] erxdat1[7] erxclav[1] IOCTL erxenb[1] erxprty[1] erxsoc[1] VCCPLL1 GNDPLL1 PLLOUT0 etxdat3[1] VCCPLL0 etxdat3[2] etxdat3[3] VCCIO IOCTL etxdat3[4] etxdat3[5] VCCIO erxclk[0] VCCIO waddr[0] waddr[1] waddr[2] VCCIO waddr[3] waddr[4] cellsize[0] cellsize[1] I/O I/O etxdat3[6] etxdat3[7] prty_en I/O I/O I/O etxclk[0] cellsize[2] cellsize[3] cellsize[4] INREF cellsize[5] cellsize[6] erxdat0[7] erxclav[0] erxenb[0] erxprty[0] I/O I/O VCCIO I/O GND VCC VCC VCC VCC GND GND VCC VCC GND GND erxsoc[0] VCCIO INREF IOCTL INREF IOCTL I/O I/O GND VCC IOCTL etxdat1[0] etxdat1[1] etxdat1[2] I/O I/O IOCTL I/O VCC VCC etxdat1[3] etxdat1[4] etxdat1[5] etxdat1[6] I/O I/O I/O I/O VCC VCC VCC etxdat1[7] etxclav[1] etxenb[1] I/O I/O VCCIO I/O GND VCC etxdat0[1] VCCIO etxprty[1] etxsoc[1] VCC TCK I/O I/O GND GND etxdat0[2] erxdat1[0] etxdat0[3] TRSTB I/O I/O VCCIO I/O VCC GND etxdat0[4] VCCIO etxdat0[5] etxdat0[6] I/O I/O I/O I/O VCC VCC INREF etxdat0[7] etxclav[0] etxenb[0] IOCTL I/O I/O 23 I/O VCC VCC etxprty[0] etxsoc[0] IOCTL IOCTL I/O I/O IOCTL INREF VCC GND erxdat0[0] erxdat0[1] erxdat0[2] erxdat0[3] I/O I/O VCCIO I/O GND GND VCC VCC GND GND VCC VCC VCC VCC GND erxdat0[4] VCCIO erxdat0[5] erxdat0[6] I/O I/O wtx_err wtx_err_stat[0] wtx_err_stat[1] IOCTL wtxaddr[0] wtxaddr[1] wtxaddr[2] wtxaddr[3] PLLIN1 wrxaddr[2] wrxaddr[3] wrxaddr[4] wrxclav[0] wrxclav[1] VCCPLL2 wrxdat[0] wrxdat[1] wtxaddr[4] wtxclav[0] VCCPLL3 wtxclav[1] VCCIO INREF wtxdat[0] wtxdat[1] VCCIO wtxclk VCCIO wrxdat[2] wrxdat[3] IOCTL VCCIO wrxdat[4] (Floating) PLLRST2 wrxdat[5] PLLOUT2 GNDPLL3 GND wtxdat[2] wtxdat[3] IOCTL wtxdat[4] wtxdat[5] wtxdat[6] clk(1) wrxclk wrxdat[6] wrxdat[7] INREF wrxenb wrxprty wrxsoc GNDPLL2 GND GND PLLRST3 wtxdat[7] wtxenb wtxprty wtxsoc wrxaddr[0] wrxaddr[1] TDI PLLIN2 erx_err[0] erx_err_stat[0] erx_err_stat[1] IOCTL erx_err[1] erx_err_stat[2] erx_err_stat[3] etxdat0[0] PLLOUT1 MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 9.3 280 Pin FPBGA Device Diagram erxdat1[6] A19 GND A18 erxdat 1[ 5] erxdat1[4] A17 A16 A15 erx dat1[2] erxdat1[1] etx clk[ 1] etx dat2[3] etxdat 2[ 2] et xdat2[1] A13 A12 A11 A10 A9 A8 A7 I/O I/O I/O IOCTL I/O I/O I/O G NDPLL0 PLLOUT3 B18 B17 etxdat 3[ 0] et xdat2[7] etxdat 2[ 6] et xdat2[5] etxdat2[4] B8 B7 B5 B4 I/O I/O IOCTL I/O I/O I/O GCLK/I erxsoc[ 1] B19 PLLRST1 I/O erxdat 1[ 3] A14 erxprty[ 1] erxenb[1] erxc a v[ 1] l erxdat1[7] erxclk[ 1] B16 B15 B14 B12 B11 B10 B9 I/O GCLK/I TMS PLLOUT0 GNDPLL1 VCCPLL1 I/O cellsiz e[1] cellsize[0] w addr[ 4] I/O w addr[3] B13 I/O IOCTL I/O w addr[ 2] waddr[1] waddr[0] etxdat 2[ 0] reset A5 A4 A6 A2 A1 B3 B2 B1 I/O I/O INREF I/O I/O I/O GND PLLRST0 et xdat3[4] et xdat3[3] etxdat3[2] C7 C6 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 I/O I/O I/O VCCIO I/O I/O I/O VCCIO GCLK/I VCCIO I/O erxprty [0] erx enb[ 0] erxclav[ 0] erxdat 0[ 7] c els ize[6] l c ellsiz e[ 5] c ells ize[4] c ellsiz e[ 3] cellsize[2] D18 D17 D16 D15 D14 D12 D11 D10 D9 D8 D7 D6 I/O I/O I/O I/O I/O I/O I/O GCLK/I I/O I/O I/O C5 etxc lk[0] D19 I/O INREF I/O A3 etxdat 3[ 5] erxclk[ 0] B6 I/O D13 c ells z e[7] i I/O IOCTL VCCIO C4 C3 et xdat3[1] C2 C1 I/O I/O VCCPLL0 I/O prty_en et xdat3[7] etxdat3[6] D5 D4 D3 D2 D1 I/O I/O I/O I/O I/O erxsoc[ 0] E19 E18 E17 IOCTL INREF VCCIO etxdat 1[ 2] et xdat1[1] E16 E15 E14 E13 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E2 E1 I/O GND GND VCC VCC GND GND VCC VCC VCC VCC GND I/O VCCIO I/O I/O F3 F2 F1 etxdat1[0] F17 F16 F15 F19 F18 I/O I/O I/O IOCTL etxdat 1[ 6] et xdat1[5] etxdat1[4] G19 G18 G17 G16 G15 I/O I/O I/O I/O VCC et xenb[1] etxc lav[ 1] etxdat1[7] VCC et xdat 1[ 3] QuickLogic F5 F4 GND I/O G5 VCC G4 I/O IOCTL INREF G3 G2 I/O IOCTL I/O G1 I/O H19 H18 H17 H16 H15 H5 H4 H3 H2 H1 I/O I/O I/O VCC VCC VCC I/O I/O I/O I/O etxsoc[ 1] etxprty[ 1] J19 J18 J16 J15 J5 J4 J3 J2 J1 I/O I/O VCCIO I/O VCC GND I/O VCCIO I/O I/O et xdat0[3] erxdat1[0] et xdat 0[ 2] et xdat 0[ 1] J17 K19 K18 K17 K16 K15 K5 K4 K3 K2 K1 TRSTB I/O I/O I/O GND GND I/O I/O TCK VCC etxdat 0[ 6] et xdat0[5] L19 L18 I/O et xenb[0] et xdat 0[ 4] L17 L16 L15 L5 L4 L3 L2 L1 I/O VCCIO I/O GND VCC I/O VCCIO I/O I/O etxc lav[ 0] etxdat0[7] M16 M15 M5 M4 M3 M2 M1 VCC VCC I/O I/O I/O I/O N2 N1 M19 M18 I/O I/O N19 N18 M17 I/O INREF etxs oc [0] N17 IOCTL IOCTL I/O erxdat 0[ 3] erxdat0[2] erxdat0[1] P19 P18 P17 I/O I/O I/O erxdat 0[ 6] erxdat0[5] pASIC et xprty[ 0] N16 N15 I/O VCC N5 N4 N3 VCC I/O I/O P4 P3 I/O IOCTL erxdat 0[ 0] P16 QL6325-6PT280C QL6325-6PT280C P15 I/O GND erxdat 0[ 4] P5 VCC P2 INREF IOCTL I/O P1 I/O R19 R18 R17 R16 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 I/O I/O VCCIO I/O GND VCC VCC VCC VCC GND GND VCC VCC G ND GND I/O VCCIO I/O I/O wrxdat[ 1] w rxdat[0] wrxclav[ 1] w rx clav[0] w rx addr[4] w rxaddr[3] wrxaddr[ 2] w txaddr[3] wt xaddr[ 2] w txaddr[1] w txaddr[0] T19 T18 T16 T15 T14 T13 T12 T11 T10 T9 T8 T7 I/O I/O I/O I/O GCLK/I I/O I/O I/O w rxdat[ 3] w rxdat[2] wt xdat[ 1] I/O T17 I/O VCCPLL2 I/O wrxdat[ 5] U19 wrxdat[ 4] U18 V19 GND V18 U17 U16 TDO I/O w rxs oc I/O PLLRST2 wrxprty w rxenb V17 V16 V15 GNDPLL2 I/O I/O U15 U14 W 19 W 18 W17 W 16 I/O I/O T3 T2 T1 I/O IOCTL I/O I/O I/O I/O I/O wtx dat[0] wtx clav[1] wt xclav[0] wt xaddr[ 4] U12 U11 U10 U9 U8 VCCIO GCLK/I VCCIO I/O I/O INREF VCCIO I/O VCCPLL3 I/O w rxdat[ 7] V14 w rxdat[6] wrxc lk w txdat[6] wt xdat[ 5] wtx dat[4] w txdat[2] V13 V12 V11 V9 V8 V7 I/O INREF I/O W15 wt x_err T4 I/O V10 erx_err_s tat[1]erx_err_st at [0] erx_err[0] W14 W 13 I/O IOCTL I/O U6 U5 wt xdat[ 3] V6 V5 I/O I/O IOCTL I/O w rx addr[1] HW CLK GCLK/I I/O U7 T5 I/O VCCIO IOCTL I/O et xdat0[0] erx_err_stat[ 3]erx_err_s tat[2] erx_err[ 1] PLLOUT1 I/O U13 wt xclk wt x_err_stat[ 1] tx_err_s tat[0] w T6 wrxaddr[0] w txs oc wt xprty U4 V4 GND wtxenb U2 V2 U1 I/O V1 w txdat [7] W12 W11 W 10 W9 W8 W7 W6 W5 W4 I/O GCLK/I TDI I/O I/O I/O I/O I/O 24 V3 I/O I/O Figure 15: 280 Pin Bottom View U3 W3 G NDPLL3 PLLOUT2 W2 I/O PLLRST3 W1 GND MS2M18x Utopia Level 2 to 1 Multiplexer Device Datasheet Version 1.0 - July 2001 10 References · · · ATM Forum, Utopia Level 1, af-phy-0017.000, 1994 ATM Forum, Utopia Level 2, af-phy-0039.000, 1995 Quicklogic, Eclipse Family Datasheet (Preliminary, 8/24/2000) 11 Contact MorethanIP Tel : +49 (0) 89 3219599 0 FAX : +49 (0) 89 3219599 1 E-Mail : info@morethanip.com Internet : www.morethanip.com QuickLogic Corp. Tel : 408 990 4000 (US) : + 44 1932 57 9011 (Europe) : + 49 89 930 86 170 (Germany) : + 852 8106 9091 (Asia) : + 81 45 470 5525 (Japan) E-mail : info@quicklogic.com Internet : www.quicklogic.com 25