MPE603EEC/D 603TM EG7655 2328B - Datasheet Archive

 

MPE603EEC/D (Motorola Order Number) 5/1999 Rev. 1 Freescale Semiconductor, Inc. TM Advance Information EC603e TM Embedded RISC

 

Freescale Semiconductor, Inc. MPE603EEC/D MPE603EEC/D (Motorola Order Number) 5/1999 Rev. 1 Freescale Semiconductor, Inc. TM Advance Information EC603e TM Embedded RISC Microprocessor (PID6) Hardware Specifications The EC603e microprocessor from Motorola is an implementation of the PowerPCTM family of reduced instruction set computing (RISC) microprocessors. The EC603e microprocessor for embedded systems is functionally equivalent to the MPC603e with the exception of the floating-point unit which is not supported on the EC603e microprocessor. The EC603e microprocessor is implemented in both a 2.5-volt version (PID 0007t EC603e microprocessor, abbreviated as PID7t) and a 3.3-volt version (PID 0006 EC603e microprocessor, abbreviated as PID6). This document describes the pertinent physical characteristics of the PID6. For functional characteristics of the processor, refer to the MPC603e & EC603e RISC Microprocessors User's Manual. This document contains the following topics: Topic Page Section 1.1, "Overview" Section 1.2, "Features" Section 1.3, "General Parameters" Section 1.4, "Electrical and Thermal Characteristics" Section 1.5, "Pin Assignments" Section 1.6, "Pinout Listings" Section 1.7, "Package Description" Section 1.8, "System Design Information" Section 1.9, "Document Revision History" Section 1.10, "Ordering Information" 2 3 4 4 14 16 20 24 30 30 The PowerPC name, the PowerPC logotype, PowerPC 603, and PowerPC 603e are trademarks of International Business Machines Corporation, used by Motorola under license from International Business Machines Corporation. FLOTHERM is a registered trademark of Flomerics Ltd., UK This document contains information on a new product under development by Motorola and IBM. Motorola and IBM reserve the right to change or discontinue this product without notice. © Motorola Inc., 1999. All rights reserved. Portions hereof © International Business Machines Corporation, 1991­1999. All rights reserved. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. To locate any published errata or updates for this document, refer to the website at http://www.mot.com/ SPS/PowerPC/. 1.1 Overview Freescale Semiconductor, Inc. The PID6 implementation of the EC603e microprocessor is a low-power implementation of the PowerPC microprocessor family of reduced instruction set computer (RISC) microprocessors. The PID6 implements the 32-bit portion of the PowerPC architecture specification, which provides 32-bit effective addresses, and integer data types of 8, 16, and 32 bits. For 64-bit PowerPC microprocessors, the PowerPC architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. The PID6 provides four software controllable power-saving modes. Three of the modes (the nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of power consumed by the processor. The fourth is a dynamic power management mode that causes the functional units in the PID6 to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware. The PID6 is a superscalar processor capable of issuing and retiring as many as three instructions per clock. Instructions can execute out of order for increased performance; however, the PID6 makes completion appear sequential. The PID6 integrates four execution units-an integer unit (IU), a branch processing unit (BPU), a load/store unit (LSU), and a system register unit (SRU). The ability to execute five instructions in parallel and the use of simple instructions with rapid execution times yield high efficiency and throughput for PID6­based systems. Most integer instructions execute in one clock cycle. The PID6 provides independent on-chip, 16-Kbyte, four-way set-associative, physically addressed caches for instructions and data, as well as on-chip instruction and data memory management units (MMUs). The MMUs contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (DTLB and ITLB) that provide support for demand-paged virtual memory address translation and variable-sized block translation. The TLBs and caches use a least-recently used (LRU) replacement algorithm. The PID6 also supports block address translation through the use of two independent instruction and data block address translation (IBAT and DBAT) arrays of four entries each. Effective addresses are compared simultaneously with all four entries in the BAT array during block translation. In accordance with the PowerPC architecture, if an effective address hits in both the TLB and BAT array, the BAT translation takes priority. The PID6 has a selectable 32- or 64-bit data bus and a 32-bit address bus. The PID6 interface protocol allows multiple masters to compete for system resources through a central external arbiter. The PID6 provides a three-state coherency protocol that supports the exclusive, modified, and invalid cache states. This protocol is a compatible subset of the MESI (modified/exclusive/shared/invalid) four-state protocol and operates coherently in systems that contain four-state caches. The PID6 supports single-beat and burst data transfers for memory accesses, and supports memory-mapped I/O. The PID6 uses an advanced, 3.3-V CMOS process technology and maintains full interface compatibility with TTL devices. 2 EC603e Microprocessor Hardware Specifications (PID6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. 1.2 Features This section summarizes features of the PID6's implementation of the PowerPC architecture. Major features of the PID6 are as follows: · Freescale Semiconductor, Inc. · · · · · High-performance, superscalar microprocessor - As many as three instructions issued and retired per clock - As many as five instructions in execution per clock - Single-cycle execution for most instructions Four independent execution units and one register file - BPU featuring static branch prediction - A 32-bit IU - LSU for data transfer between data cache and GPRs - SRU that executes condition register (CR), special-purpose register (SPR) instructions, and integer add/compare instructions - Thirty-two GPRs for integer operands High instruction and data throughput - Zero-cycle branch capability (branch folding) - Programmable static branch prediction on unresolved conditional branches - Instruction fetch unit capable of fetching two instructions per clock from the instruction cache - A six-entry instruction queue that provides lookahead capability - Independent pipelines with feed-forwarding that reduces data dependencies in hardware - 16-Kbyte data cache-four-way set-associative, physically addressed; LRU replacement algorithm - 16-Kbyte instruction cache-four-way set-associative, physically addressed; LRU replacement algorithm - Cache write-back or write-through operation programmable on a per page or per block basis - BPU that performs CR lookahead operations - Address translation facilities for 4-Kbyte page size, variable block size, and 256-Mbyte segment size - A 64-entry, two-way set-associative ITLB - A 64-entry, two-way set-associative DTLB - Four-entry data and instruction BAT arrays providing 128-Kbyte to 256-Mbyte blocks - Software table search operations and updates supported through fast-trap mechanism - 52-bit virtual address; 32-bit physical address Facilities for enhanced system performance - A 32- or 64-bit split-transaction external data bus with burst transfers - Support for one-level address pipelining and out-of-order bus transactions Integrated power management - Low-power 3.3-volt design - Internal processor/bus clock multiplier that provides 1/1, 1.5/1, 2/1, 2.5/1, 3/1, 3.5/1, and 4/1 ratios - Three power saving modes: doze, nap, and sleep - Automatic dynamic power reduction when internal functional units are idle In-system testability and debugging features through JTAG boundary-scan capability EC603e Microprocessor Hardware Specifications (PID6) For More Information On This Product, Go to: www.freescale.com 3 Freescale Semiconductor, Inc. 1.3 General Parameters The following list provides a summary of the general parameters of the PID6. Technology Die size Transistor count Logic design Package Power supply 0.5 µ CMOS, four-layer metal 11.67 mm x 8.4 mm (98 mm2) 2.6 million Fully-static Surface mount 240-pin ceramic quad flat pack (CQFP) or 255-pin ceramic ball grid array (CBGA) 3.3 ± 5% V dc Freescale Semiconductor, Inc. 1.4 Electrical and Thermal Characteristics This section provides the AC and DC electrical specifications and thermal characteristics for the PID6. 1.4.1 DC Electrical Characteristics The tables in this section describe the PID6 DC electrical characteristics. Table 1 provides the absolute maximum ratings. Table 1. Absolute Maximum Ratings Characteristic Symbol Value Unit Core supply voltage Vdd ­0.3 to 4.0 V PLL supply voltage AVdd ­0.3 to 4.0 V I/O supply voltage OVdd ­0.3 to 4.0 V Input voltage Vin ­0.3 to 5.5 V Storage temperature range Tstg ­55 to 150 °C Notes: 1. Functional operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. Caution: Vin must not exceed OVdd by more than 2.5 V at any time including during power-on reset. 3. Caution: OVdd must not exceed Vdd/AVdd by more than 2.5 V at any time including during power-on reset. 4. Caution: Vdd/AVdd must not exceed OVdd by more than 0.4 V at any time including during power-on reset. 4 EC603e Microprocessor Hardware Specifications (PID6) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Table 2 provides the recommended operating conditions for the PID6. Table 2. Recommended Operating Conditions Characteristic Symbol Value Unit Core supply voltage Vdd 3.3 ± 165mv V PLL supply voltage AVdd 3.3 ± 165mv V I/O supply voltage OVdd 3.3 ± 165mv V Input voltage Vin ­0.3 to 5.5 V Die-junction temperature Tj 0 to 105 °C Note: Freescale Semiconductor, Inc. 1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not guaranteed. Table 3 provides the packages thermal characteristics for the PID6. Table 3. Package Thermal Characteristics Characteristic Symbol Value Rating Wire-bond CQFP package die junction-to-case thermal resistance (typical) JC 2.2 °C/W Wire-bond CQFP package die junction-to-lead thermal resistance (typical) JB 18.0 °C/W CBGA package die junction-to-case thermal resistance (typical) JC 0.08 °C/W CBGA package die junction-to-ball thermal resistance (typical) JB 2.8 °C/W Note: Refer to Section 1.8, "System Design Information," for more details about thermal management. Table 4 provides the DC electrical characteristics for the PID6. Table 4. DC Electrical Specifications At recommended operating conditions. See Table 2 Characteristic Symbol Min Max Unit Input high voltage (all inputs except SYSCLK) VIH 2.0 5.5 V Input low voltage (all inputs except SYSCLK) VIL -0.3 0.8 V SYSCLK input high voltage CVIH 2.4 5.5 V SYSCLK input low voltage CVIL -0.3 0.4 V Input leakage current, Vin = 3.465 V Iin - 10 µA 1 Iin - 245 µA 1 ITSI - 10 µA 1 ITSI - 245 µA 1 VOH 2.4 - V 1 Vin = 5.5 V Hi-Z (off-state) leakage current, Vin = 3.465 V Vin = 5.5 V Output high voltage, IOH = ­9 mA EC603e Microprocessor Hardware Specifications (PID6) For More Information On This Product, Go to: www.freescale.com Notes 5 Freescale Semiconductor, Inc. Table 4. DC Electrical Specifications (Continued) At recommended operating conditions. See Table 2 Characteristic Symbol Min Max Unit Notes Output low voltage, IOL = 14 mA VOL - 0.4 V Capacitance, Vin = 0 V, f = 1 MHz (excludes TS, ABB, DBB, and ARTRY) Cin - 10.0 pF 2 Capacitance, Vin = 0 V, f = 1 MHz (for TS, ABB, DBB, and ARTRY) Cin - 15.0 pF 2 Notes: 1. Excludes test signals (LSSD_MODE, L1_TSTCLK, L2_TSTCLK) and JTAG signals. 2. Capacitance is periodically sampled rather than 100% tested. Table 5 provides the power consumption for the PID6. Freescale Semiconductor, Inc. Table 5. Power Consumption At recommended operating conditions. See Table 2 Processor (CPU) Frequency CPU Clock: SYSCLK Unit 100 MHz Notes 133.33 MHz Full-On Mode (DPM Enabled) Typical 3.2 4.2 W 1, 3 Max. 4.0 5.3 W 1, 2 Typical 1.0 1.3 W 1, 2 Typical 70 85 mW 1, 2 Typical 40 50 mW 1, 2 5 6 mW 1, 2 3 mW 1, 2 Doze Mode Nap Mode Sleep Mode Sleep Mode-PLL Disabled Typical Sleep Mode-PLL and SYSCLK Disabled Typical 3 Notes: 1. These values apply for all valid bus ratios (PLL_CFG[0­3] settings). The values do not include I/O supply power (OVdd) or PLL supply power (AVdd). OVdd power is system dependent, but is typically