RS-232 RS232 MB811171622A-100 MPC821B MPC823 MPC850 MPC860B MPC860SAR MPC801 - Datasheet Archive

 

Motorola Semiconductor Israel Ltd. MICROPROCESSOR & MEMORY TECHNOLOGIES GROUP MPC8XXFADS Revision ENG & Revision PILOT

 

MOTOROLA Motorola Semiconductor Israel Ltd. MICROPROCESSOR & MEMORY TECHNOLOGIES GROUP MPC8XXFADS Revision ENG & Revision PILOT User's Manual AUTHOR: YAIR LIEBMAN - MSIL ISSUE 0.1 - Release 15,1,98 ISSUE 0.0 - Draft 22,7,97 6 SIX SIGMA MOTOROLA MPC8XXFADS - User's Manual TABLE OF CONTENTS 1 1·1 1·2 1·3 1·4 1·5 1·6 1·7 1·8 1·9 2 2·1 2·2 2·3 2·3·1 2·3·2 2·3·3 2·3·4 2·3·5 2·3·6 2·4 2·4·1 2·4·2 2·4·3 2·4·4 2·4·5 2·4·6 2·4·7 2·4·8 2·4·9 3 3·1 3·2 3·2·1 3·2·2 3·2·3 3·2·4 3·2·5 3·2·6 3·2·7 3·2·8 3·2·9 3·2·10 3·2·11 3·2·12 3·2·13 3·2·14 3·2·15 General Information Introduction MPC8XX Family Support Abbreviations' List Related Documentation Revision ENG to Revision PILOT Changes Changes to This Document from Previous Issue (Draft 0.0) SPECIFICATIONS MPC8XXFADS Features MPC8XXFADS Goals Hardware Preparation and Installation INTRODUCTION UNPACKING INSTRUCTIONS HARDWARE PREPARATION ADI Port Address Selection Clock Source Selection Power-On Reset Source Selection VDDL Source Selection Keep Alive Power Source Selection Debug Mode Indication Source Selection INSTALLATION INSTRUCTIONS Host Controlled Operation Debug Port Controller For Target System Stand Alone Operation +5V Power Supply Connection P7: +12V Power Supply Connection ADI Installation Host computer to MPC8XXFADS Connection Terminal to MPC8XXFADS RS-232 RS-232 Connection Memory Installation OPERATING INSTRUCTIONS INTRODUCTION CONTROLS AND INDICATORS ABORT Switch SW1 SOFT RESET Switch SW2 HARD RESET - Switches SW1 & SW2 DS1 - Software Options Switch GND Bridges ETH ON - LD1 IRD ON - LD2 RS232 RS232 Port 1 ON - LD3 RS232 RS232 Port 2 ON - LD4 Ethernet RX Indicator - LD5 Ethernet TX Indicator - LD6 Ethernet JABB Indicator - LD7 Ethernet CLSN Indicator LD8 Ethernet PLR Indicator - LD9 Ethernet LIL Indicator - LD10 1 1 1 1 1 2 2 2 4 5 6 6 6 6 8 8 8 9 9 9 9 9 10 11 12 12 13 13 13 14 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 16 16 16 Release 0.1 MPC8XXFADS - User's Manual TABLE OF CONTENTS 3·2·16 3·2·17 3·2·18 3·2·19 3·2·20 3·2·21 3·2·22 3·3 3·4 3·4·1 4 4·1 4·1·1 4·1·2 4·1·3 4·1·4 4·1·5 4·1·6 4·1·6·1 4·1·6·2 4·1·6·3 4·2 4·3 4·4 4·5 4·6 4·6·1 4·6·2 4·6·3 4·6·4 4·7 4·8 4·8·1 4·8·1·1 4·8·2 4·9 4·9·1 4·9·2 4·9·2·1 4·9·3 4·9·3·1 4·10 4·10·1 4·11 4·11·1 4·11·2 4·11·3 4·11·4 5V Indicator - LD11 RUN Indicator - LD12 AUXILARY Indicator LD13 FLASH ON - LD14 DRAM ON - LD15 SDRAM ON - LD16 PCMCIA ON - LD17 MEMORY MAP MPC Registers' Programming Memory Controller Registers Programming Functional Description Reset & Reset - Configuration Keep Alive Power-On Reset Regular Power - On Reset Manual Soft Reset Manual Hard Reset MPC Internal Sources Reset Configuration Power - On Reset Configuration Hard Reset Configuration Soft Reset Configuration Local Interrupter Clock Generator Buffering Chip - Select Generator DRAM DRAM 16 Bit Operation DRAM Performance Figures Refresh Control Variable Bus-Width Control Flash Memory SIMM Synchronous Dram SDRAM Programming SDRAM Initializing Procedure SDRAM Refresh Communication Ports Ethernet Port Infra-Red Port Infra-Red Port Rate Range Selection RS232 RS232 Ports RS-232 RS-232 Ports' Signal Description PCMCIA Port PCMCIA Power Control Board Control & Status Register - BCSR BCSR Disable Protection Logic BCSR0 - Hard Reset Configuration Register BCSR1 - Board Control Register 1 BCSR2 - Board Control / Status Register - 2 16 17 17 17 17 17 17 17 18 19 29 29 29 29 29 29 29 30 30 30 30 31 31 31 32 32 33 33 34 35 37 39 40 41 41 42 42 42 43 43 43 44 46 46 47 47 48 52 Release 0.1 MPC8XXFADS - User's Manual TABLE OF CONTENTS 4·11·5 4·11·6 4·12 4·12·1 4·12·1·1 4·12·2 4·12·3 4·12·3·1 4·12·3·2 4·12·3·3 4·12·3·4 4·12·3·5 4·12·3·6 4·13 4·13·1 4·13·2 4·13·3 5 5·1 5·1·1 5·1·2 5·1·3 5·1·4 5·1·5 5·1·6 5·1·7 5·1·8 5·1·9 5·2 5·3 5·3·1 5·3·2 5·3·3 APPENDIX A A·1 APPENDIX B B·1 B·2 B·2·1 B·3 B·3·1 BCSR3 - Board Control / Status Register 3 BCSR4 - Board Control / Status Register 4 Debug Port Controller MPC8XXFADS As Debug Port Controller For Target System Debug Port Connection - Target System Requirements Debug Port Control / Status Register Standard MPCXXX Debug Port Connector Pin Description VFLS(0:1) HRESET* SRESET* DSDI - Debug-port Serial Data In DSCK - Debug-port Serial Clock DSDO - Debug-port Serial Data Out Power 5V Bus 3.3V Bus 12V Bus Support Information Interconnect Signals P1 ADI - Port Connector PA2, PB2 - RS232 RS232 Ports' Connectors P3 - Ethernet Port Connector PCMCIA Port Connector P5 - External Debug Port Controller Input Interconnect. P6 - 5V Power Connector P7 - 12V Power Connector P8 - Serial Ports' Expansion Connector PD1 - PD4 - Daughter Boards' Connectors Interconnect Signals MPC8XXFADS Part List Programmable Logic Equations U2 - Debug Port Controller U11 - Board Control & Status Register U22 - Auxiliary Board Control ADI I/F ADI Port Signal Description ADI Installation INTRODUCTION IBM-PC/XT/AT to MPC8XXFADS Interface ADI Installation in IBM-PC/XT/AT SUN-4 to MPC8XXFADS Interface ADI Installation in the SUN-4 55 58 60 61 62 62 64 64 64 64 64 65 65 65 67 67 67 68 68 68 69 69 70 73 74 74 74 74 100 104 105 133 174 191 191 193 193 193 193 194 195 Release 0.1 MPC8XXFADS - User's Manual LIST OF FIGURES FIGURE 1-1 FIGURE 2-1 FIGURE 2-2 FIGURE 2-3 FIGURE 2-4 FIGURE 2-5 FIGURE 2-6 FIGURE 2-7 FIGURE 2-8 FIGURE 2-9 FIGURE 2-10 FIGURE 2-11 FIGURE 3-1 FIGURE 4-1 FIGURE 4-2 FIGURE 4-3 FIGURE 4-4 FIGURE 4-5 FIGURE 4-6 FIGURE 4-7 FIGURE 4-8 FIGURE 4-1 FIGURE A-1 FIGURE B-1 FIGURE B-2 FIGURE B-3 MPC8XXFADS Motherboard Block Diagram MPC8XXFADS Top Side Part Location diagram Configuration Dip-Switch - DS2 J1 - VFLS / FRZ Selection Host Controlled Operation Scheme Debug Port Controller For Target System Operation Scheme Stand Alone Configuration P6: +5V Power Connector P7: +12V Power Connector P1 - ADI Port Connector PA2, PB2 - RS-232 RS-232 Serial Port Connectors Memory SIMM Installation DS1 - Description Refresh Scheme DRAM Address Lines' Switching Scheme Flash Memory SIMM Architecture SDRAM Connection Scheme RS232 RS232 Serial Ports' Connector PCMCIA Port Configuration Debug Port Controller Block Diagram Standard Debug Port Connector MPC8XXFADS Power Scheme ADI Port Connector Physical Location of jumper JG1 and JG2 JG1 Configuration Options ADI board for SBus 5 7 8 9 10 11 12 12 13 13 14 14 15 35 37 38 40 43 45 61 64 66 191 194 194 195 Release MPC8XXFADS - User's Manual LIST OF TABLES TABLE 1-1. TABLE 3-1. TABLE 3-2. TABLE 3-3. TABLE 3-4. TABLE 3-5. TABLE 3-6. TABLE 3-7. TABLE 3-8. TABLE 3-9. TABLE 4-1. TABLE 4-2. TABLE 4-3. TABLE 4-4. TABLE 4-5. TABLE 4-6. TABLE 4-7. TABLE 4-8. TABLE 4-9. TABLE 4-10. TABLE 4-11. TABLE 4-12. TABLE 4-13. TABLE 4-14. TABLE 4-15. TABLE 4-16. TABLE 4-17. TABLE 4-18. TABLE 4-19. TABLE 4-20. TABLE 4-21. TABLE 4-22. TABLE 4-23. TABLE 4-24. TABLE 4-25. TABLE 4-26. TABLE 5-1 TABLE 5-2. TABLE 5-3. TABLE 5-4. TABLE 5-5. TABLE 5-6. TABLE 5-7. TABLE 5-8. TABLE 5-9. MPC8XXFADS Specifications MPC8XXADS Main Memory Map SIU REGISTERS' PROGRAMMING Memory Controller Initializations For 50Mhz UPMA Initializations for 60nsec DRAMs @ 50MHz UPMA Initializations for 60nsec EDO DRAMs @ 50MHz Memory Controller Initializations For 20Mhz UPMA Initializations for 60nsec EDO DRAMs @ 20MHz UPMB Initializations for MB811171622A-100 MB811171622A-100 upto 32MHz UPMB Initializations for MB811171622A-100 MB811171622A-100, 32+MHz - 50MHz MPC8XXFADS Chip Selects' Assignment Regular DRAM Performance Figures EDO DRAM Performance Figures DRAM ADDRESS CONNECTIONS Flash Memory Performance Figures Estimated SDRAM Performance Figures SDRAM's Mode Register Programming MPC8XX Family Comm. Ports BCSR0 Description BCSR1 Description PCCVCC(0:1) Encoding PCCVPP(0:1) Encoding BCSR2 Description Flash Presence Detect (4:1) Encoding DRAM Presence Detect (2:1) Encoding DRAM Presence Detect (4:3) Encoding EXTOOLI(0:3) Assignment MPC8XXFADS Daughter Boards' Revision Encoding BCSR3 Description Daughter Boards' ID Codes MPC8XXFADS Revision Number Conversion Table FLASH Presence Detect (7:5) Encoding BCSR4 Description Debug Port Control / Status Register DSCK Frequency Select Off-board Application Maximum Current Consumption P1 - ADI Port Interconnect Signals PA2, PB2 Interconnect Signals P3 - Ethernet Port Interconnect Signals P4 - PCMCIA Connector Interconnect Signals P5 - Interconnect Signals P6 - Interconnect Signals P7 - Interconnect Signals PD1 Interconnect Signals PD2 Interconnect Signals 2 18 19 20 22 23 23 26 27 28 32 34 34 36 39 39 41 42 48 50 51 52 53 53 54 54 54 55 56 56 57 57 58 63 63 66 68 69 70 70 73 74 74 75 80 Release 0.1 MPC8XXFADS - User's Manual LIST OF TABLES TABLE 5-10. TABLE 5-11. TABLE 5-12. PD3 Interconnect Signals PD4 Interconnect Signals MPC8XXFADS Part List 87 94 100 Release 0.1 MPC8XXFADS - User's Manual General Information 1 - General Information 1·1 Introduction This document is an operation guide for the MPC8XXFADS board. It contains operational, functional and general information about the FADS. The MPC8XXFADS is meant to serve as a platform for s/w and h/w development around the MPC8XX family processors. Using its on-board resources and its associated debugger, a developer is able to download his code, run it, set breakpoints, display memory and registers and connect his own proprietary h/w via the expansion connectors, to be incorporated to a desired system with the MPC8XX processor. This board could also be used as a demonstration tool, i.e., application s/w may be burnedA into its flash memory and ran in exhibitions etc`. 1·2 MPC8XX Family Support The MPC8XXFADS supports the following MPC8XX family members: o o MPC821B MPC821B o MPC823 MPC823 o MPC850 MPC850 o MPC860B MPC860B o MPC860SAR MPC860SAR B o 1·3 MPC801 MPC801 MPC860TB MPC860TB Abbreviations' List · FADSC - the MPC8XXFADS, the subject of this document. · UPM - User Programmable Machine · GPCM - General Purpose Chip-select Machine · GPL - General Purpose Line (associated with the UPM) · I/R - Infra-Red · BCSR - Board Control & Status Register. · ZIF - Zero Input Force · BGA - Ball Grid Array · SIMM - Single In-line Memory Module 1·4 Related Documentation · MPC8XX User's Manuals. · ADI Board Specification. A. Either on or off-board. B. Same Daughter Board. C. Not to be mistaken for the M683XX M683XX Family Ads 8 Release 0.1 MPC8XXFADS - User's Manual General Information 1·5 Revision ENG to Revision PILOT Changes The only electrical change between the two revisions is a bug correction in BCSR. This bug was irrelevant to ENG 0091A and up, boards. The rest, are production associated changes, which were meant to improve boards' reliability and manufacturability, such as changes in SMD pad sizes, drill sizes and so on and are of no interest to any user. 1·6 Changes to This Document from Previous Issue (Draft 0.0) 1) Daughter Board's for MPC821 MPC821, MPC860 MPC860, MPC860SAR MPC860SAR, MPC860T MPC860T, are identical. (1·2 on page 8) 2) Typo error in TABLE 3-1. "MPC8XXADS Main Memory Map" on page 25 was fixed: BCSR occupies 32KByte space rather than 16KByte as implied from this table. 3) Typo Error in TABLE 3-3. "Memory Controller Initializations For 50Mhz" on page 27 and in TABLE 3-6. "Memory Controller Initializations For 20Mhz" on page 30 was fixed: BR0 is set 02800001. Flash base address is 0x2800000, rather than 0x2200000. 4) Changed Daughter-Board Codes - MPC821 MPC821, MPC860/860SAR/860T MPC860/860SAR/860T share the same code now (0x22). See TABLE 4-20. "Daughter Boards' ID Codes" on page 63. 5) Mother Board revsion codes are changed: 0 is now reserved, ENG & PILOT share the same code - 1. See TABLE 4-18. "MPC8XXFADS Daughter Boards' Revision Encoding" on page 62. 6) Added BCSR4 functions' description for MPC821/860/860SAR/860T MPC821/860/860SAR/860T Daughter board, with MPC860T MPC860T. (TABLE 4-23. on page 65). 7) Changed Mach equations for U11. Bug correction (Irrelevant for ENG091 ENG091+ boards). See 5·3·2 "U11 - Board Control & Status Register" on page 140. 1·7 SPECIFICATIONS The MPC8XXFADS specifications are given in TABLE 1-1. TABLE 1-1. MPC8XXFADS Specifications CHARACTERISTICS SPECIFICATIONS Power requirements (no other boards attached) +5Vdc @ 1.7 A (typical), 3 A (maximum) +12Vdc - @1A. Microprocessor MPC8XX running upto @ 50 MHz Addressing Total address range: 4 GigaBytes Flash Memory Dynamic RAM Synchronous DRAM 2 MByte, 32 bits wide expandable to 8 MBytes 4 MByte, 32 bits wide EDO SIMM Support for up to 32 MByte, EDO or FPM SIMM 4 MBytes, organized as 1 Meg X 32 bit. Operating temperature 0OC - 30OC Storage temperature -25OC -25OC to 85OC Relative humidity 5% to 90% (non-condensing) A. The only implication of that bug is that ENG0001 ENG0001 - ENG0090 ENG0090 may not connect to MPC823FADSDB MPC823FADSDB of revision PILOT. ENG0091 ENG0091 and up may. 9 Release 0.1 MPC8XXFADS - User's Manual General Information TABLE 1-1. MPC8XXFADS Specifications CHARACTERISTICS Dimensions: Length Width Thickness 10 SPECIFICATIONS 9.173" (233 mm) 6.3" (160 mm) 0.063" (1.6 mm) Release 0.1 MPC8XXFADS - User's Manual General Information 1·8 MPC8XXFADS Features o 4 MByte, Unbuffered, Synchronous Dram On-Board. o 4 MByte EDO 60nsec delay DRAM SIMM. Support for 4 - 32 MByte FPM or EDO Dram SIMM, with Automatic Dram SIMM identification. 16 Bit Data-Bus Width Support. o 2 MByte Flash SIMM. Support for upto 8 MByte, 5V or 12V Programmable, with Automatic Flash SIMM identification. o Memory Disable Option for each local memory map slaves. o Board Control & Status Register - BCSR, Controlling Board's Operation. o Programmable Hard-Reset Configuration via BCSR. o 5V only PCMCIA Socket With Full Buffering, Power Control and Port Disable Option. Complies with PCMCIA 2.1+ Standard. o Module Enable Indications. o 10-Base-T Port On-Board, with Stand-By Mode. o Fast-IrDA (4MBps) Port with Stand-By Mode. o Dual RS232 RS232 port with Low-Power Option per each port. o On - Board Debug Port Controller with ADI I/F. o MPC8XXFADS Serving as Debug Station for Target System option. o Optional Hard-Reset Configuration Burned in FlashA. o External Tools' Identification Capability, via BCSR. o Soft / HardB Reset Push - Button o ABORT Push - Button o SingleC 5V Supply. o Reverse / Over Voltage Protection for Power Inputs. o 3.3V / 2V MPC Internal Logic Operation D, 3.3V MPC I/O Operation. o Power Indications for Each Power Bus. o Software Option Switch provides 16 S/W options via BCSR. A. Available only if supported also on the MPC8XX. B. Hard reset is applied by depressing BOTH Soft Reset & ABORT buttons. C. Unless a 12V supply is required for a PCMCIA card or for a 12V programmable Flash SIMM. D. Implemented on Daughter Board. 11 Release 0.1 MPC8XXFADS - User's Manual General Information FIGURE 1-1 MPC8XXFADS Motherboard Block Diagram SDRAM 4 MBytes DATA & ADDRESS BUFFERS FLASH SIMM. Reset, Interrupts & Clock 2 - 8MByte DRAM SIMM Dram Width & Size Logic 4 - 32 Mbyte Control & Status Register Fast IrDA Port DAUGHTER BOARD CONN. RS232 RS232 PORTS Debug Port Connector PORT CONTROLLER ADI PORT (*) (*) May be on a separate board. 1·9 PCMCIA Buffering & Control PCMCIA PORT EEST (ADI I/F) ETHERNET PORT DEBUG MPC8XXFADS Goals The MPC8XXFADS is meant to become a general platform for s/w and h/w development around the MPC8XX family. Using its on-board resources and its associated debugger, the developer is able to load his code, run it, set breakpoints, display memory and registers and connect his own proprietary h/w via the expansion connectors, to be incorporated to a system with the MPC. This board could also be used as a demonstration tool, i.e., application s/w may be programmed A into its flash memory and ran in exhibitions etc. A. Either on or off-board. 12 Release 0.1 MPC8XXFADS - User's Manual Hardware Preparation and Installation 2 - Hardware Preparation and Installation 2·1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation, and installation instructions for the MPC8XXFADS. 2·2 UNPACKING INSTRUCTIONS NOTE If the shipping carton is damaged upon receipt, request carrier's agent to be present during unpacking and inspection of equipment. Unpack equipment from shipping carton. Refer to packing list and verify that all items are present. Save packing material for storing and reshipping of equipment. CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY; STATIC DISCHARGE CAN DAMAGE CIRCUITS. 2·3 HARDWARE PREPARATION To select the desired configuration and ensure proper operation of the MPC8XXFADS board, changes of the Dip-Switch settings may be required before installation. The location of the switches, LEDs, DipSwitches, and connectors is illustrated in FIGURE 2-1. The board has been factory tested and is shipped with Dip-Switch settings as described in the following paragraphs. Parameters can be changed for the following conditions: · · MPC Clock Source · Power-On Reset Source. · MPC Keep Alive Power Source · MPC Internal Logic Supply Source · 13 ADI port address Debug Mode Indication Source Release 0.1 MPC8XXFADS - User's Manual Hardware Preparation and Installation FIGURE 2-1 MPC8XXFADS Top Side Part Location diagram 14 Release 0.1 MPC8XXFADS - User's Manual Hardware Preparation and Installation 2·3·1 ADI Port Address Selection The MPC8XXFADS can have eight possible slave addresses set for its ADI port, enabling up to eight MPC8XXFADS boards to be connected to the same ADI board in the host computer. The selection of the slave address is done by setting switches 1, 2 & 3 in the Dip-Switch - DS2. Switch 1 stands for the mostsignificant bit of the address and switch 3 stands for the least-significant bit. If the switch is in the 'ON' state, it stands for logical '1'. In FIGURE 2-2 DS1 is shown to be configured to address '0'. FIGURE 2-2 Configuration Dip-Switch - DS2 ON ADR2 ADR2 1 ADR1 2 ADR1 ADR0 3 ADR0 3 - 5 MHz Generator via EXTCLK 4 32.678 KHz Crystal Resonator DS2 Table 2-1 describes the switch settings for each slave address: Table 2-1 ADI Address Selection ADDRESS Switch 2 Switch 3 0 OFF OFF OFF 1 OFF OFF ON 2 OFF ON OFF 3 OFF ON ON 4 ON OFF OFF 5 ON OFF ON 6 ON ON OFF 7 2·3·2 Switch 1 ON ON ON Clock Source Selection Switch #4 on DS2 selects the clock source for the MPC. When it is in the 'ON' position while the FADS is powered-up, the on-board 32.768 KHz crystal resonatorA becomes the clock source and the PLL multiplication factor becomes 1:513. When switch #4 is in the 'OFF' position while the FADS is poweredup, the on-board 4BMHz clock generatorA becomes the clock source while the PLL multiplication factor becomes 1:5. 2·3·3 Power-On Reset Source Selection As there are differences between MPC revisions regarding the functionality of the Power-On Reset logic, A. Located on the Daughter-Board B. A 5MHz clock generator is packed as well. 15 Release 0.1 MPC8XXFADS - User's Manual Hardware Preparation and Installation it is therefore necessary to select different sources for Power-ON reset generation. The above selection is done on the Daughter Board and therefore, documented in the specific Daughter Board user's manual. 2·3·4 VDDL Source Selection This selection is done on the Daughter Board and therefore, documented in the specific Daughter Board user's manual. 2·3·5 Keep Alive Power Source Selection This selection is done on the Daughter Board and therefore, documented in the specific Daughter Board user's manual. 2·3·6 Debug Mode Indication Source Selection Jumper J1 selects between VFLS(0:1) signals and FRZ signal of the MPC as an indication for debug mode state. Since with the MPC8XXs, each of these signals has alternate function, it may be necessary to switch between the two sources, in favor of alternate function being used. When a jumper is positioned between pins 1 and 2 of J1 - VFLS(0:1) are selected towards the debug-port controller. When a jumper is placed between positions 2 - 3 of J1(2) - FRZ signal is selected. FIGURE 2-3 J1 - VFLS / FRZ Selection J1 1 VFLS(0:1) Selected 2·4 J1 1 FRZ Selected INSTALLATION INSTRUCTIONS When the MPC8XXFADS has been configured as desired by the user, it can be installed according to the required working environment as follows: · Host Controlled Operation · Debug Port Controller for Target System · Stand-Alone 2·4·1 Host Controlled Operation In this configuration the MPC8XXFADS is controlled by a host computer via the ADI through the debug port. This configuration allows for extensive debugging using on-host debugger. 16 Release 0.1 MPC8XXFADS - User's Manual Hardware Preparation and Installation FIGURE 2-4 Host Controlled Operation Scheme ADI Host Computer 37 Wire Flat Cable P1 P1 5V Power Supply P6 P6 2·4·2 Debug Port Controller For Target System This configuration resembles the previous, but here the local MPC is removed from its socket while the FADS is connected via a 10 lead Flat-Cable between P5 and a matching connector on a target system. WARNNING When connecting the FADS to a target system via P5 and a 10 lead flat-cable, the MPC MUST be REMOVED from its SOCKET. Otherwise, PERMANENT DAMAGE might be inflicted to either the Local MPC or to the Target MPC. With this mode of operation, all on-board modules are disabled and can not be accessed in anyway, except for the debug port controller. Also, all indications except for 5V power, 3.3V-Power A and RUN are darkened. All debugger commands and debugging features are available in this mode, including s/w download, breakpoints, etc`. The target system may be reset or interrupted by the debug port or reset by the FADS's RESET switches. It is the responsibility of the target system designer, to provide Power-On-Reset and HARD-Reset configurations, while SOFT-Reset configuration is provided by the debug-port controller. See also 4·12·1 "MPC8XXFADS As Debug Port Controller For Target System" on page 68. A. On Daughter Board. 17 Release 0.1 MPC8XXFADS - User's Manual Hardware Preparation and Installation FIGURE 2-5 Debug Port Controller For Target System Operation Scheme Target System 10 Wire 37 Wire ADI Host Computer Flat Cable Flat Cable P1 P1 P5 5V Power Supply P6 P6 MPC Removed From Socket 2·4·3 Stand Alone Operation In this mode, the FADS is not controlled by the host via the ADI/Debug port. It may connect to host via one of its other ports, e.g., RS232 RS232 port, I/R port, Ethernet port, etc`. Operating in this mode requires an application program to be programmed into the board`s Flash memory (while with the host controlled operation, no memory is required at all). 18 Release 0.1 MPC8XXFADS - User's Manual Hardware Preparation and Installation FIGURE 2-6 Stand Alone Configuration RS 23 2 Et he rn e t Host Computer I/R P1 5V Power Supply P6 2·4·4 P6 +5V Power Supply Connection The MPC8XXFADS requires +5 Vdc @ 5 A max, power supply for operation. Connect the +5V power supply to connector P6 as shown below: FIGURE 2-7 P6: +5V Power Connector +5V 1 GND 2 GND 3 P6 is a 3 terminal block power connector with power plug. The plug is designed to accept 14 to 22 AWG wires. It is recommended to use 14 to 18 AWG wires. To provide solid ground, two Gnd terminals are supplied. It is recommended to connect both Gnd wires to the common of the power supply, while VCC is connected with a single wire. NOTE 2·4·5 Since hardware applications may be connected to the MPC8XXFADS via the Daughter-Boards' expansion connectors PX1, PX2 PX3, PX4 or FADS's P8, the additional power consumption should be taken into consideration when a power supply is connected to the MPC8XXFADS. P7: +12V Power Supply Connection The MPC8XXFADS requires +12 Vdc @ 1 A max, power supply for the PCMCIA channel Flash programming capability or for 12V programmable Flash SIMM. The MPC8XXFADS can work properly without the +12V power supply, if there is no need to program either a 12V programmable PCMCIA flash card or a 12V programmable Flash SIMM. Connect the +12V power supply to connector P7 as shown below: 19 Release 0.1 MPC8XXFADS - User's Manual Hardware Preparation and Installation FIGURE 2-8 P7: +12V Power Connector +12V 1 GND 2 P7 is a 2 terminal block power connector with power plug. The plug is designed to accept 14 to 22 AWG wires. It is recommended to use 14 to 18 AWG wires. 2·4·6 ADI Installation For ADI installation on various host computers, refer to APPENDIX B - "ADI Installation" on page 200. 2·4·7 Host computer to MPC8XXFADS Connection The MPC8XXFADS ADI interface connector, P1, is a 37 pin, male, D type connector. The connection between the MPC8XXFADS and the host computer is by a 37 line flat cable, supplied with the ADI board. FIGURE 2-9 below shows the pin configuration of the connector. FIGURE 2-9 P1 - ADI Port Connector Gnd Gnd Gnd Gnd Gnd Gnd (+ 12 v) N.C. HOST_VCC HOST_VCC HOST_VCC HOST_ENABLE~ Gnd Gnd Gnd PD0 PD2 PD4 PD6 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 N.C D_C~ HST_ACK ADS_SRESET ADS_HRESET ADS_SEL2 ADS_SEL1 ADS_SEL0 HOST_REQ ADS_REQ ADS_ACK N.C. N.C. N.C. N.C. PD1 PD3 PD5 PD7 NOTE: Pin 26 on the ADI is connected to +12 v power supply, but it is not used in the MPC8XXFADS. 2·4·8 Terminal to MPC8XXFADS RS-232 RS-232 Connection A serial (RS232 RS232) terminal or any other RS232 RS232 equipment, may be connected to the RS-232 RS-232 connectors PA2 and PB2. The RS-232 RS-232 connectors is a 9 pin, female, Stacked D-type connector as shown in FIGURE 2-10. The connectors are arranged in a manner that allows for 1:1 connection with the serial port of an IBM-ATA or compatibles, i.e. via a flat cable. A. IBM-AT is a trademark of International Business Machines Inc. 20 Release 0.1 MPC8XXFADS - User's Manual Hardware Preparation and Installation FIGURE 2-10 PA2, PB2 - RS-232 RS-232 Serial Port Connectors CD TX 1 2 RX 3 DTR 4 5 GND 6 7 8 9 DSR RTS CTS N.C. NOTE: The RTS line (pin 7) is not connected on the MPC8XXFADS. 2·4·9 Memory Installation The MPC8XXFADS is supplied with two types of memory SIMM: · Dynamic Memory SIMM · Flash Memory SIMM. To avoid shipment damage, these memories are packed aside rather than being installed in their sockets. Therefore, they should be installed on site. To install a memory SIMM, it should be taken out of its package, put diagonally in its socket (no error can be made here, since the Flash socket has 80 contacts, while the DRAM socket has 72) and then twisted to a vertical position until the metal lock clips are locked. See FIGURE 2-11 "Memory SIMM Installation" below. CAUTION The memory SIMMs have alignment nibble near their # 1 pin. It is important to align the memory correctly before it is twisted, otherwise damage might be inflicted to both the memory SIMM and its socket. FIGURE 2-11 Memory SIMM Installation (1) (2) Memory SIMM Metal Lock Clip SIMM Socket 21 Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS 3 - OPERATING INSTRUCTIONS 3·1 INTRODUCTION This chapter provides necessary information to use the MPC8XXFADS in host-controlled and stand-alone configurations. This includes controls and indicators, memory map details, and software initialization of the board. 3·2 CONTROLS AND INDICATORS The MPC8XXFADS has the following switches and indicators. 3·2·1 ABORT Switch SW1 The ABORT switch is normally used to abort program execution, this by issuing a level 0 interrupt to the MPC. If the FADS is in stand alone mode, it is the responsibility of the user to provide means of handling the interrupt, since there is no resident debugger with the MPC8XXFADS. The ABORT switch signal is debounced, and can not be disabled by software. 3·2·2 SOFT RESET Switch SW2 The SOFT RESET switch SW2 performs Soft reset to the MPC internal modules, maintaining MPC's configuration (clocks & chip-selects) Dram and SDram contents. The switch signal is debounced, and it is not possible to disable it by software. At the end of the Soft Reset Sequence, the Soft Reset Configuration is sampled and becomes valid. 3·2·3 HARD RESET - Switches SW1 & SW2 When BOTH switches - SW1 and SW2 are depressed simultaneously, HARD reset is generated to the MPC. When the MPC is HARD reset, all its configuration is lost, including data stored in the DRAM or SDRAM and the MPC has to be re-initialized. At the end of the Hard Reset sequence, the Hard Reset Configuration stored in BCSR0 becomes valid. 3·2·4 DS1 - Software Options Switch DS1 is a 4-switches Dip-Switch. This switch is connected over EXTOLI(0:3) lines which are available at BCSR, S/W options may be manually selected, according to DS1 state. FIGURE 3-1 DS1 - Description ON EXTOLI0 Pulled to '1' 1 EXTOLI1 Pulled to '1' 2 EXTOLI1 Driven to '0' EXTOLI2 Pulled to '1' 3 EXTOLI2 Driven to '0' EXTOLI3 Pulled to '1' 4 EXTOLI3 Driven to '0' EXTOLI0 Driven to '0' DS1 3·2·5 GND Bridges There are 3 GND bridges on the MPC8XXFADS. They are meant to assist general measurements and 22 Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS logic-analyzer connection. Warning When connecting to a GND bridge, use only INSULATED GND clips. Failure in doing so, might result in permanent damage to the MPC8XXFADS. 3·2·6 ETH ON - LD1 When the yellow ETH ON led is lit, it indicates that the ethernet port transceiver - the MC68160 MC68160 EEST, is active. When it is dark, it indicates that the EEST is in power down mode, enabling the use of its associated SCC pins off-board via the expansion connectors. 3·2·7 IRD ON - LD2 When the yellow IRD ON led is lit, it indicates that the Infra-Red transceiver - the TFDS6000 TFDS6000, is active and enables communication via that medium. When it is dark, the I/R transceiver is in shutdown mode, enabling the use of its associated SCC pins off-board via the expansion connectors. 3·2·8 RS232 RS232 Port 1 ON - LD3 When the yellow RS232 RS232 Port 1 ON led is lit, it designates, that the RS232 RS232 transceiver connected to PA2, is active and communication via that medium is allowed. When darkened, it designates that the transceiver is in shutdown mode, so its associated MPC pins may be used off-board via the expansion connectors. 3·2·9 RS232 RS232 Port 2 ON - LD4 When the yellow RS232 RS232 Port 2 ON led is lit, it designates that the RS232 RS232 transceiver connected to PB2, is active and communication via that medium is allowed. When darkened, it designates, that the transceiver is in shutdown mode, so its associated MPC pins may be used off-board via the expansion connectors. 3·2·10 Ethernet RX Indicator - LD5 The green Ethernet Receive LED indicator blinks whenever the EEST is receiving data from one of the Ethernet port. 3·2·11 Ethernet TX Indicator - LD6 The green Ethernet Receive LED indicator blinks whenever the EEST is transmitting data via the Ethernet port. 3·2·12 Ethernet JABB Indicator - LD7 The red Ethernet TP Jabber LED indicator - JABB, lights whenever a jabber condition is detected on the TP ethernet port. 3·2·13 Ethernet CLSN Indicator LD8 The red Ethernet Collision LED indicator CLSN, blinks whenever a collision condition is detected on the ethernet port, i.e., simultaneous receive and transmit. 3·2·14 Ethernet PLR Indicator - LD9 The red Ethernet TP Polarity LED indicator - PLR, lights whenever the wires connected to the receiver input of the ethernet port are reversed. The LED is lit by the EEST, and remains on while the EEST has automatically corrected for the reversed wires. 3·2·15 Ethernet LIL Indicator - LD10 The yellow Ethernet Twisted Pair Link Integrity LED indicator - LIL, lights to indicate good link integrity on the TP port. The LED is off when the link integrity fails. 3·2·16 5V Indicator - LD11 The yellow 5V led, indicates the presence of the +5V supply at P6. 23 Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS 3·2·17 RUN Indicator - LD12 When the green RUN led - LD12 is lit, it indicates that the MPC is not in debug mode, i.e., VFLS0 & VFLS1 = 0 (or FRZ = 0, which ever selected by J1). 3·2·18 AUXILARY Indicator LD13 This indication has no dedicated function over the FADS. It is meant to provide some visibility for program behavior. It is controlled by the Signal Lamp bit in BCSR4. 3·2·19 FLASH ON - LD14 When the yellow FLASH ON led is lit, it indicates that the FLASH SIMM is enabled in the BCSR1 register. I.e., any access done to the CS0~ address space will hit the flash memory. When it is dark, the flash is disabled and CS0~ may be used off-board via the expansion connectors. 3·2·20 DRAM ON - LD15 When the yellow DRAM ON led is lit, it indicates the DRAM SIMM is enabled in BCSR1. Therefore, any access made to CS2~ (or CS3~) will hit on the DRAM. When it is dark, it indicates that either the DRAM is disabled in BCSR1, enabling the use of CS2~ and CS3~ off-board via the expansion connectors. 3·2·21 SDRAM ON - LD16 When the yellow SDRAM ON led is lit, it indicates the SDRAM is enabled in BCSR1. Therefore, any access made to CS4~ (will hit on the SDRAM. When it is dark, it indicates that either the SDRAM is disabled in BCSR1, enabling the use of CS4~ off-board via the expansion connectors. 3·2·22 PCMCIA ON - LD17 When the yellow PCMCIA ON led is lit, it indicates the following: 1) Address & strobe buffers are driven towards the PCMCIA card 2) Data buffers are driven to / from the PCMCIA card whenever CE1A~A or CE2A~B signals are asserted. 3) Card status lines are driven towards the MPC from the PCMCIA card. When it is dark, it indicates that all the above buffers are tri-stated and the pins associated with PCMCIA channel AC, may be used off-board via the expansion connectors. 3·3 MEMORY MAP All accesses to MPC8XXFADS's memories are controlled by the MPC's memory controller. Therefore, the memory map is reprogrammable to the desire of the user. After Hard Reset is performed by the debug station, the debugger checks to see the size, delay and type of the DRAM and FLASH SIMMs mounted on A. Connected to CE1B~ for MPC823FADSDB MPC823FADSDB. B. Connected to CE2B~ for MPC823FADSDB MPC823FADSDB. C. Or B for MPC823FADSDB MPC823FADSDB. 24 Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS board and initializes the chip-selects accordingly. The DRAM, SDRAM and the FLASH memory respond to all types of memory access i.e., user / supervisory, program / data and DMA. TABLE 3-1. MPC8XXADS Main Memory Map ADDESS RANGE Memory Type 00000000 - 003FFFFF 003FFFFF DRAM SIMM Port Size Device Type MB321Bxa08 MB322Bxa08 MC324Cxa00 MB328Cxa00 32 00400000 - 007FFFFF 007FFFFF 32 00800000 - 00FFFFFF 00FFFFFF 32 01000000 - 01FFFFFF 01FFFFFF 32 02000000 - 020FFFFF 020FFFFF Empty Space 02100000 - 02107FFF 02107FFF BCSR(0:4)b 02100000 - 02107FE3 02107FE3 BCSR0 2100004 - 02107FE7 02107FE7 BCSR1 2100008 - 02107FEB 02107FEB BCSR2 210000C 210000C - 02107FEF 02107FEF BCSR3 2100010 - 02107FF3 02107FF3 BCSR4 02108000 - 021FFFFF 021FFFFF Empty Space 02200000 - 02207FFF 02207FFF MPC Internal MAPd 02208000 - 027FFFFF 027FFFFF Empty Space 02800000 - 029FFFFF 029FFFFF Flash SIMM 32c 02A00000 02A00000 - 02BFFFFF 02BFFFFF 32 MCM29F020 MCM29F020 MCM29F040 MCM29F040 SM732A1000A SM732A1000A MCM29F080 MCM29F080 SM732A2000 SM732A2000 32 32 02C00000 02C00000 - 02FFFFFF 02FFFFFF 32 03000000 - 033FFFFF 033FFFFF SDRAM 03400000 - FFFFFFFF 32 Empty Space a. x [B,T] b. The device appears repeatedly in multiples of its size. E.g., BCSR0 appears at memory locations 2100000, 2100020, 2100040., while BCSR1 appears at 2100004, 2100024, 2100044. and so on. c. Only upper 16 bit (D0-D15 D0-D15) are in fact used. d. Refer to the relevant MPC User's Manual for complete description of the MPC internal memory map. 3·4 MPC Registers' Programming The MPC provides the following functions on the MPC8XXFADS: 1) 2) SDRAM Controller 3) 25 DRAM Controller Chip Select generator. Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS 4) UART for terminal or host computer connection. 5) Ethernet controller. 6) Infra-Red Port Controller 7) General Purpose I/O signals. The internal registers of the MPC must be programmed after Hard reset as described in the following paragraphs. The addresses and programming values are in hexadecimal base. For better understanding the of the following initializations refer to the MPC821 MPC821 or to the MPC860 MPC860 User's Manual for more information. TABLE 3-2. SIU REGISTERS' PROGRAMMING Register Init Value[hex] Description SIUMCR 01012440 Internal arbitration, External master arbitration priority - 0, External arbitration priority - 0, PCMCIA channel II pins - PCMCIA, Debug Port on JTAG port pins, FRZ/IRQ6~ - FRZ, debug register - locked, No parity for non-CS regions, DP(0:3)/ IRQ(3:6)~ pins - DP(0:3), reservation disabled, SPKROUT - Tri-stated, BS_A(0:3)~ and WE(0:3)~ are driven just on their dedicated pins, GPL_B5~ enabled, GPL_A/ B(2:3)~ function as GPLs. SYPCR FFFFFF88 FFFFFF88 Software watchdog timer count - FFFF, Bus-monitor timing FF, Bus-monitor Enabled, S/W watch-dog - Freeze, S/W watch-dog - disabled, S/W watch-dog (if enabled) causes NMI, S/W (if enabled) not prescaled. TBSCR 00C2 No interrupt level, reference match indications cleared, interrupts disabled, no freeze, time-base disabled. RTCSC 00C2 Interrupt request level - 0, 32768 Hz source, second interrupt disabled, Alarm interrupt disabled, Real-time clock - FREEZE, Real-time clock enabled. PISCR 0082 No level for interrupt request, Periodic interrupt disabled, clear status, interrupt disabled, FREEZE, periodic timer disabled. 3·4·1 Memory Controller Registers Programming The memory controller on the MPC8XXFADS is initialized to 50 MHz operation. I.e., registers' programming is based on 50 MHZ timing calculation except for refresh timer which is initialized to 16.67Mhz, the lowest frequency at which the FADS may wake up. Since the FADS may be made to wake-up at 25MHz A as well, the initializations are not efficient, since there are too many wait-states inserted. Therefore, additional set of initialization is provided to support efficient 25MHz operation. The reason for initializing the FADS for 50Mhz is to allow proper (although not efficient) FADS operation through all available FADS clock frequencies. A. The only parameter which is initialized to the start-up frequency, is the refresh rate, which would have been inadequate if initialized to 50Mhz while board is running at a lower frequency. Therefore, for best bus bandwidth availability, refresh rate should be adapted to the current system clock frequency. 26 Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS Warning Due to availability problems with few of the supported memory components, the below initializations were not tested with all parts. Therefore, the below initializations are liable to CHANGE, throughout the testing period. TABLE 3-3. Memory Controller Initializations For 50Mhz Register Device Type BR0 All Flash supported. OR0 Description 02800001 Base at 2800000, 32 bit port size, no parity, GPCM MCM29F020-90 MCM29F020-90 FFE00D34 FFE00D34 2MByte block size, all types access, CS early negate, 6 w.s., Timing relax MCM29F040-90 MCM29F040-90 SM732A1000A-9 SM732A1000A-9 FFC00D34 FFC00D34 4MByte block size, all types access, CS early negate, 6 w.s., Timing relax MCM29F080-90 MCM29F080-90 SM732A2000-9 SM732A2000-9 FF800D34 FF800D34 8MByte block size, all types access, CS early negate, 6 w.s., Timing relax MCM29F020-12 MCM29F020-12 FFE00D44 FFE00D44 2MByte block size, all types access, CS early negate, 8 w.s., Timing relax MCM29F040-12 MCM29F040-12 SM732A1000A-12 SM732A1000A-12 FFC00D44 FFC00D44 4MByte block size, all types access, CS early negate, 8 w.s., Timing relax MCM29F080-12 MCM29F080-12 SM732A2000-12 SM732A2000-12 BR1 SIMMs Init Value [hex] FF800D44 FF800D44 8MByte block size, all types access, CS early negate, 8 w.s., Timing relax BCSR 02100001 Base at 2100000, 32 bit port size, no parity, GPCM FFFF8110 FFFF8110 32 KByte block size, all types access, CS early negate, 1 w.s. 00000081 Base at 0, 32 bit port size, no parity, UPMA OR1 BR2 All Dram Supported OR2 MCM36100/200-60/70 MCM36100/200-60/70 FFC00800 FFC00800 4MByte block size, all types access, initial address multiplexing according to AMA. MCM36400/800-60/70 MCM36400/800-60/70 MT8/16D432/832X-6/7 MT8/16D432/832X-6/7 FF000800 FF000800 16MByte block size, all types access, initial address multiplexing according to AMA. MCM36200-60/70 MCM36200-60/70 00400081 Base at 400000, 32 bit port size, no parity, UPMA MCM36800-60/70 MCM36800-60/70 MT16D832X-6/7 MT16D832X-6/7 01000081 Base at 1000000, 32 bit port size, no parity, UPMA MCM36200-60/70 MCM36200-60/70 FFC00800 FFC00800 4MByte block size, all types access, initial address multiplexing according to AMA MCM36800-60/70 MCM36800-60/70 MT16D832X-6/7 MT16D832X-6/7 FF000800 FF000800 16MByte block size, all types access, initial address multiplexing according to AMA. MB811171622A-100 MB811171622A-100 030000C1 030000C1 Base at 3000000, on UPM B FFC00A00 FFC00A00 4 MByte block size, all types access, initial address multiplexing according to AMB. BR3 OR3 BR4 OR4 27 SIMMs Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS TABLE 3-3. Memory Controller Initializations For 50Mhz Register Device Type MPTPR All Dram Supported MAMR Description 0400 Divide by 16 (decimal) MB321BT08TASN60 MB321BT08TASN60 40A21114a 60A21114b C0A21114c refresh clock divided by 40a or 60b or C0c, periodic timer enabled, type 2 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MB322BT08TASN60 MB322BT08TASN60 20A21114a 30A21114b 60A21114c refresh clock divided by 20a or 30b or 60c, periodic timer enabled, type 2 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MB324CT00TBSN60 MB324CT00TBSN60 40B21114a 60B21114b C0B21114c refresh clock divided by 40a or 60b or C0c, periodic timer enabled, type 3 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MB328CT00TBSN60 MB328CT00TBSN60 MBMR SIMMs Init Value [hex] 20B21114a 30B21114b 60B21114c refresh clock divided by 20a or 30b or 60c, periodic timer enabled, type 3 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MB811171622A-100 MB811171622A-100 D0802114c 80802114 d refresh clock divided by D0 or 80, periodic timer enabled, type 0 address multiplexing scheme, 1 cycle disable timer, GPL4enabled, 1 loop read, 1 loop write, 4 beats refresh burst. a. Assuming 16.67 MHz BRGCLK. b. Assuming 25MHz BRGCLK c. For 50MHz BRGCLK d. Assuming 32MHz BRGCLK. 28 Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS TABLE 3-4. UPMA Initializations for 60nsec DRAMs @ 50MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C 0 8FFFEC24 8FFFEC24 8FFFEC24 8FFFEC24 8FAFCC24 8FAFCC24 8FAFCC24 8FAFCC24 C0FFCC84 C0FFCC84 33FFCC07 33FFCC07 1 0FFFEC04 0FFFEC04 0FFFEC04 0FFFEC04 0FAFCC04 0FAFCC04 0FAFCC04 0FAFCC04 00FFCC04 00FFCC04 X 2 0CFFEC04 0CFFEC04 08FFEC04 08FFEC04 0CAFCC00 0CAFCC00 0CAFCC00 0CAFCC00 07FFCC04 07FFCC04 X 3 00FFEC04 00FFEC04 00FFEC0C 00FFEC0C 11BFCC47 11BFCC47 03AFCC4C 03AFCC4C 3FFFCC06 3FFFCC06 X 4 00FFEC00 00FFEC00 03FFEC00 03FFEC00 X 0CAFCC00 0CAFCC00 FFFFCC85 FFFFCC85 5 37FFEC47 37FFEC47 00FFEC44 00FFEC44 X 03AFCC4C 03AFCC4C FFFFCC05 FFFFCC05 6 X 00FFCC08 00FFCC08 X 0CAFCC00 0CAFCC00 X 7 X 0CFFCC44 0CFFCC44 X 03AFCC4C 03AFCC4C X Contents @ Offset + 8 0CAFCC00 0CAFCC00 X 9 03FFEC00 03FFEC00 33BFCC4F 33BFCC4F X A 00FFEC44 00FFEC44 X X B 00FFCC00 00FFCC00 X X C 3FFFC847 3FFFC847 X D X X E X X F 29 00FFEC0C 00FFEC0C X X Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS TABLE 3-5. UPMA Initializations for 60nsec EDO DRAMs @ 50MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C 0 8FFBEC24 8FFBEC24 8FFFEC24 8FFFEC24 8FFFCC24 8FFFCC24 8FFFCC24 8FFFCC24 C0FFCC84 C0FFCC84 33FFCC07 33FFCC07 1 0FF3EC04 0FF3EC04 0FFBEC04 0FFBEC04 0FEFCC04 0FEFCC04 0FEFCC04 0FEFCC04 00FFCC04 00FFCC04 X 2 0CF3EC04 0CF3EC04 0CF3EC04 0CF3EC04 0CAFCC00 0CAFCC00 0CAFCC00 0CAFCC00 07FFCC04 07FFCC04 X 3 00F3EC04 00F3EC04 00F3EC0C 00F3EC0C 11BFCC47 11BFCC47 03AFCC4C 03AFCC4C 3FFFCC06 3FFFCC06 X 4 00F3EC00 00F3EC00 0CF3EC00 0CF3EC00 X 0CAFCC00 0CAFCC00 FFFFCC85 FFFFCC85 5 37F7EC47 37F7EC47 00F3EC4C 00F3EC4C X 03AFCC4C 03AFCC4C FFFFCC05 FFFFCC05 6 X 0CF3EC00 0CF3EC00 X 0CAFCC00 0CAFCC00 X 7 X 00F3EC4C 00F3EC4C X 03AFCC4C 03AFCC4C X Contents @ Offset + 8 0CF3EC00 0CF3EC00 0CAFCC00 0CAFCC00 X 9 00F3EC44 00F3EC44 33BFCC4F 33BFCC4F X A 03F3EC00 03F3EC00 X X B 3FF7EC47 3FF7EC47 X X C X X D X X E X X F X X TABLE 3-6. Memory Controller Initializations For 20Mhz Register BR0 30 Device Type All Flash supported. SIMMs Init Value [hex] 02800001 Description Base at 2800000, 32 bit port size, no parity, GPCM Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS TABLE 3-6. Memory Controller Initializations For 20Mhz Register OR0 Device Type Init Value [hex] Description FFE00D20 FFE00D20 2MByte block size, all types access, CS early negate, 2 w.s. MCM29F040-90 MCM29F040-90 SM732A1000A-9 SM732A1000A-9 FFC00D20 FFC00D20 4MByte block size, all types access, CS early negate, 2 w.s. MCM29F080-90 MCM29F080-90 SM732A2000-9 SM732A2000-9 FF800920 FF800920 8MByte block size, all types access, CS early negate, 2 w.s., Timing relax MCM29F020-12 MCM29F020-12 FFE00D30 FFE00D30 2MByte block size, all types access, CS early negate, 3 w.s. MCM29F040-12 MCM29F040-12 SM732A1000A-12 SM732A1000A-12 FFC00D30 FFC00D30 4MByte block size, all types access, CS early negate, 3 w.s. MCM29F080-12 MCM29F080-12 SM732A2000-12 SM732A2000-12 BR1 MCM29F020-90 MCM29F020-90 FF800930 FF800930 8MByte block size, all types access, CS early negate, 3 w.s. BCSR 02100001 Base at 2100000, 32 bit port size, no parity, GPCM FFFF8110 FFFF8110 32 KByte block size, all types access, CS early negate, 1 w.s. 00000081 Base at 0, 32 bit port size, no parity, UPMA OR1 BR2 All Dram Supported OR2 MB321/2BT08TASN60 MB321/2BT08TASN60 FFC00800 FFC00800 4MByte block size, all types access, initial address multiplexing according to AMA. MB324/8CT00TBSN60 MB324/8CT00TBSN60 FF000800 FF000800 16MByte block size, all types access, initial address multiplexing according to AMA. MB322BT08TASN60 MB322BT08TASN60 00400081 Base at 400000, 32 bit port size, no parity, UPMA MB328CT00TBSN60 MB328CT00TBSN60 01000081 Base at 1000000, 32 bit port size, no parity, UPMA MB322BT08TASN60 MB322BT08TASN60 FFC00800 FFC00800 4MByte block size, all types access, initial address multiplexing according to AMA MB328CT00TBSN60 MB328CT00TBSN60 FF000800 FF000800 16MByte block size, all types access, initial address multiplexing according to AMA. MB811171622A-100 MB811171622A-100 030000C1 030000C1 Base at 3000000, on UPM B. FFC00A00 FFC00A00 4MByte block size, all types access, initial address multiplexing according to AMB 0400 Divide by 16 (decimal) BR3a OR3 BR4 SIMMs OR4 MPTPR 31 All Dram Supported SIMMs Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS TABLE 3-6. Memory Controller Initializations For 20Mhz Register MAMR Device Type Init Value [hex] Description 60A21114 60A21114 refresh clock divided by 60, periodic timer enabled, type 2 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MB322BT08TASN60 MB322BT08TASN60 30A21114 30A21114 refresh clock divided by 30, periodic timer enabled, type 2 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MB324CT00TBSN60 MB324CT00TBSN60 60B21114 60B21114 refresh clock divided by 60, periodic timer enabled, type 3 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MB328CT00TBSN60 MB328CT00TBSN60 MBMR MB321BT08TASN60 MB321BT08TASN60 30B21114 30B21114 refresh clock divided by 30, periodic timer enabled, type 3 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MB811171622A-100 MB811171622A-100 42802114b refresh clock divided by 42, periodic timer enabled, type 0 address multiplexing scheme, 1 cycle disable timer, GPL4 enabled, 1 loop read, 1 loop write, 4 beats refresh burst. a. BR3 is not initialized for MB321xx or MB324xx EDO DRAM SIMMs. b. Assuming 16.67MHz BRGCLK 32 Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS TABLE 3-7. UPMA Initializations for 60nsec EDO DRAMs @ 20MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C 0 8FFFCC04 8FFFCC04 8FFFCC04 8FFFCC04 8FEFCC00 8FEFCC00 8FEFCC00 8FEFCC00 80FFCC84 80FFCC84 33FFCC07 33FFCC07 1 08FFCC00 08FFCC00 08FFCC08 08FFCC08 39BFCC47 39BFCC47 09AFCC48 09AFCC48 17FFCC04 17FFCC04 X 2 33FFCC47 33FFCC47 08FFCC08 08FFCC08 X 09AFCC48 09AFCC48 FFFFCC86 FFFFCC86 X 3 X 08FFCC08 08FFCC08 X 09AFCC48 09AFCC48 FFFFCC05 FFFFCC05 X 4 X 08FFCC00 08FFCC00 X 39BFCC47 39BFCC47 X 5 X 3FFFCC47 3FFFCC47 X X X 6 X X X X X 7 X X X X X Contents @ Offset + 8 X X 9 X X X A X X X B X X X C X X D X X E X X F 33 X X X Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS TABLE 3-8. UPMB Initializations for MB811171622A-100 MB811171622A-100 upto 32MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM 0 8 18 20 30 3C 0 0126CC04 0126CC04 0026FC04 0026FC04 0E26BC04 0E26BC04 0E26BC00 0E26BC00 1FF5FC84 1FF5FC84 7FFFFC07 7FFFFC07 1 0FB98C00 0FB98C00 10ADFC00 10ADFC00 01B93C00 01B93C00 10AD7C00 10AD7C00 FFFFFC04 FFFFFC04 X 2 1FF74C45 1FF74C45 F0AFFC00 F0AFFC00 1FF77C45 1FF77C45 F0AFFC00 F0AFFC00 FFFFFC84 FFFFFC84 X 3 X F1AFFC00 F1AFFC00 X F0AFFC00 F0AFFC00 FFFFFC05 FFFFFC05 X 4 X EFBBBC00 EFBBBC00 X E1BBBC04 E1BBBC04 X 5 1FE77C34a 1FF77C45 1FF77C45 X 1FF77C45 1FF77C45 X 6 EFAABC34 EFAABC34 X X X X 7 1FA57C35 1FA57C35 X X X X Contents @ Offset + 8 X X X 9 X X X A X X X B X X X C X X D X X E X X F X X a. MRS initialization. Uses Free space. 34 Release 0.1 MPC8XXFADS - User's Manual OPERATING INSTRUCTIONS TABLE 3-9. UPMB Initializations for MB811171622A-100 MB811171622A-100, 32+MHz - 50MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM 0 8 18 20 30 3C 0 1F07FC04 1F07FC04 1F07FC04 1F07FC04 1F27FC04 1F27FC04 1F07FC04 1F07FC04 1FF5FC84 1FF5FC84 7FFFFC07 7FFFFC07 1 EEAEFC04 EEAEFC04 EEAEFC04 EEAEFC04 EEAEBC00 EEAEBC00 EEAEBC00 EEAEBC00 FFFFFC04 FFFFFC04 X 2 11ADFC04 11ADFC04 10ADFC04 10ADFC04 01B93C04 01B93C04 10AD7C00 10AD7C00 FFFFFC04 FFFFFC04 X 3 EFBBBC00 EFBBBC00 F0AFFC00 F0AFFC00 1FF77C47 1FF77C47 F0AFFC00 F0AFFC00 FFFFFC04 FFFFFC04 X 4 1FF77C47 1FF77C47 F0AFFC00 F0AFFC00 X F0AFFC00 F0AFFC00 FFFFFC84 FFFFFC84 5 1FF77C34a F1AFFC00 F1AFFC00 X E1BBBC04 E1BBBC04 FFFFFC07 FFFFFC07 6 EFEABC34 EFEABC34 EFBBBC00 EFBBBC00 X 1FF77C47 1FF77C47 X 7 1FB57C35 1FB57C35 1FF77C47 1FF77C47 X X X Contents @ Offset + 8 X X X 9 X X X A X X X B X X X C X X D X X E X X F X X a. MRS initialization, Uses free space. 35 Release 0.1 MPC8XXFADS - User's Manual Functional Description 4 - Functional Description In this chapter the various modules combining the MPC8XXFADS are described to their design details. 4·1 Reset & Reset - Configuration There are several reset sources on the FADS: 1) Keep Alive Power-On ResetA 2) Regular Power On Reset 3) Manual Soft-Reset 4) Manual Hard-Reset 5) MPC Internal Sources. (See the appropriate Spec or U/M) 4·1·1 Keep Alive Power-On Reset The Keep Alive Power - On Reset logic resides on the daughter board this since the Keep Alive power bus is on that board and it also allows the use of the daughter board connected directly to a user's application. 4·1·2 Regular Power - On Reset The regular power on reset operates in the same manner as the keep alive power-on reset, using a similar device - the Seiko - S-8052ANY-NH-X S-8052ANY-NH-X with detection voltage of 2.595V to 2.805V. The reference voltage of this device is the MAIN VDDH bus of the MPC while the reset line assertedB, is the HRESET* line. When HRESET~ is asserted to the MPC, Hard-Reset configuration is made available to the MPC, via BCSR0. See 4·1·6·2 "Hard Reset Configuration" on page 37 and TABLE 4-9. "BCSR0 Description" on page 55. 4·1·3 Manual Soft Reset To support application development not around the debug port and resident debuggers, a soft reset pushbutton is provided. (SW2) Depressing that button, asserts the SRESET* pin of the MPC, generating a SOFT RESET sequence. When the SRESET~ line is asserted to the MPC, the Soft-Reset configuration is made available to the MPC, by the debug-port controller. See 4·1·6·3 "Soft Reset Configuration" on page 37. 4·1·4 Manual Hard Reset To support application development not around the debug port, a Hard-Reset push-button is providedC. When the Soft Reset push-button (SW2) is depressed in conjunction with the ABORT push-button (SW1), the HRESET* line is asserted, generating a HARD RESET sequence. The button sharing is for economy and board space saving and does not effect in any way, functionality. 4·1·5 MPC Internal Sources Since the HRESET* and SRESET* lines of the MPC are open-drain and the on-board reset logic drives these lines with open-drain gates, the correct operation of the internal reset sources of the MPC is facilitated. As a rule, an internal reset source asserts HRESET* and / or SRESET* for a minimum time of 512 system clocks. It is beyond the scope of this document to describe these sources, however Debug-Port Soft / Hard Resets which are part of the development systemD, are regarded as such. A. In fact generated on the daughter board. B. Again not directly. C. It is not a dedicated button. D. And therefore mentioned. 36 Release 0.1 MPC8XXFADS - User's Manual Functional Description 4·1·6 Reset Configuration During reset the MPC device samples the state of some external pins to determine its operation modes and pin configuration. There are 3 kinds of reset levels to the MPC each level having its own configuration sampled: 1) Power - On Reset configuration 2) Hard Reset configuration 3) Soft Reset Configuration. 4·1·6·1 Power - On Reset Configuration Just before PORESET* is negated by the external logic, the power-on reset configuration which include the MODCK(1:2) pins is sampled. These pins determine the clock operation mode of the MPC. Two clock modes are supported on the MPC8XXFADS: 1) 1:5 PLL operation via on-board clock generator. In this mode MODCK(1:2) are driven with '11' duringA power on reset. 2) 1:513 PLL operation via on-board clock generator. In this mode MODCK(1:2) are driven with '00'. during power-on reset. 4·1·6·2 Hard Reset Configuration During HARD reset sequence, when RSTCONF* pin is asserted, the MPC data bus state is sampled to acquire the MPC's hard reset configuration. The reset configuration word is driven by BCSR0 register, defaults of which are set during power-on reset. The BCSR0 drives half of the configuration word, i.e., data bits D(0:15) in which the reserved bits are designated RSRVxx. If the hard-reset configuration is to be changedB, BCSR0 may be written with new values, which become valid after HARD reset is applied to the MPC. On the FADS, the RSTCONF* line is always driven during HARD reset, i.e., no use is possible with the MPC's internal HARD reset configuration defaults. The system parameters to which BCSR0 defaults during power-on reset and are driven at hard-reset, are listed below: 1) Arbitration: internal arbitration is selected. 2) Interrupt Prefix: The internal default is interrupt prefix at 0xFFF00000. It is overridden to provide interrupt prefix at address 0, which is located within the DRAM. 3) Boot Disable: Boot is enabled. 4) Boot Port Size: 32 bit boot port size is selected. 5) Initial Internal Space Base: Immediately after HARD reset, the internal space is located at $FF000000 FF000000. 6) Debug pins configuration: PCMCIA port BC pins become PCMCIA port B pins. 7) Debug port pins configuration. Debug port pins are on the JTAG port. 8) External Bus Division Factor: 1:1 internal to external clocks' frequencies ratio is selected. 4·1·6·3 Soft Reset Configuration The rising edge of SRESET* is used to configure the development port. Before the negation of SRESET*, DSCKD is sampled to determine for debug-mode enable / disable. After SRESET* is negated, if debug A. The MODCK lines are in fact driven longer - by HRESET~ line. B. With respect the FADS's power-on defaults. C. Where they exist. 37 Release 0.1 MPC8XXFADS - User's Manual Functional Description mode was enabled, DSCK is sampled again for debug-mode entry / non-entry. DSDI is used to determine the debug port clock mode and is sampled after the negation of SRESET*. The Soft Reset configuration is provided by the debug-port controller via the ADI I/F. Option is given to enter debug mode directly or only after exception. 4·2 Local Interrupter The only external interrupt which is applied to the MPC via its interrupt controller is the ABORT (NMI), which is generated by a push-button. When this button is depressed, the NMI input to the MPC is asserted. The purpose of this type of interrupt, is to support the use of resident debuggers if any is made available to the FADS. All other interrupts to the MPC, are generated internally by the MPC's peripherals and by the debug port. To support external (off-board) generation of an NMI, the IRQ0* line which is routed as an NMI input, is driven by an open-drain gate. This allows for external h/w to also drive this line. If an external h/w indeed does so, it is compulsory that IRQ0* is driven by an open-drain (or open-collector) gate. Clock GeneratorA 4·3 There are 2 ways to clock the MPC on the MPC8XXFADS: 1) 3 - 5MHz Clock generatorB connected to CLK4IN input. 1:5 PLL mode. 2) 32.768 KHz crystal resonatorB via EXTAL-XTAL pair of the MPC, 1:513 initial PLL multiplication factor. The selection between the above modes is done using Dip-switch (DS2 / 4) with dual functionality: it is responsible to the combination driven to the MODCK lines during power-on reset and to the connection of the appropriate capacitor between MPC's XFC and VDDSYN lines to match the PLL's multiplication factor. When 1:5 mode is selected, a capacitor of 5nF is connected, while when 1:513 mode is selected a 0.68µF capacitor is connected parallel to it via a TMOS gate. The capacitors' values are calculated to support a wider range of multiplication factors as possible. When mode (2) above is selected, the output of the clock generator is gated from EXTCLK input and driven to '0' constantly so that a jitter-free system clock is generated. On-board logic is clocked by the MPC's CLKOUT coming from the Daughter board. This clock is multiplexed with the debug port's clock generator, so that on-board logic is always clocked, even when the MPC is removed from its socketC. 4·4 Buffering As the FADS meant to serve also as a hardware development platform, it is necessary to buffer the MPC from the local bus, so the MPC's capacitive drive capability is not wasted internally and remains available for user's off-board applications via the expansion connectors. Buffers are provided for address and strobeD lines while transceivers are provided for data. Since the capacitive load over dram's address lines mightE exceed 200 pF, the dram address lines are separately buff- D. DSCK is configured at hard-reset to reside on the JTAG port. A. Although this module resides on the DAUGHTER boards, it is described here, as it is common to all MPC8XX supported. B. Located On the Daughter Board. C. When the FADS serves a debug station for target system. D. If necessary. E. Depended on dram SIMM's internal structure. 38 Release 0.1 MPC8XXFADS - User's Manual Functional Description ered. Use is done with 74LCX 74LCX buffers which are 3.3V operated and are 5V tolerant. This type of buffers reduces noise on board due to reduced transitions' amplitude. To further reduce noise and reflections, series resistors are placed over dram's address and strobe lines. The data transceivers open only if there is an access to a validA B board address or during Hard - Reset configuration C. That way data conflicts are avoided in case an off-board memory is read, provided that it is not mapped to an address valid on board. It is the users' responsibility to avoid such errors. 4·5 Chip - Select Generator The memory controller of the MPC is used as a chip-select generator to access on-boardD memories, saving board's area reducing cost, power consumption and increasing flexibility. To enhance off-board application development, memory modules (including the BCSRx) may be disabled via BCSR1 E in favor of an external memory connected via the expansion connectors. That way, a CS line may be used off-board via the expansion connectors, while its associated local memory is disabled. When a CS region is disabled via BCSR1, the local data transceivers do not open during access to that region, avoiding possible F contention over data lines. The MPC's chip-selects assignment to the various memories / registers on the FADS are as shown in TABLE 4-1. "MPC8XXFADS Chip Selects' Assignment" below: TABLE 4-1. MPC8XXFADS Chip Selects' Assignment Chip Select: Assignment CS0* Flash Memory CS1* BCSR CS2* DRAM Bank 1 CS3* DRAM Bank 2a CS4* SDRAM CS(5-7)* Unused, user available a. If exists. 4·6 DRAM The MPC8XXFADS is provided with 4 MBytes of 60nsec delay EDO Dram SIMM. Support is given to any 5V powered FPM / EDO Dram SIMM configured as 1M X32 upto 2 X 4M X 32, with 60 nsec or 70nsec delay. All dram configurations are supported via the Board Control & Status Register (BCSR), i.e., DRAM size (4M to 32M) and delay (60 / 70 nsec) are read from BCSR2 and the associated registers (including the A. An address which covered in a Chip-Select region. B. Except for SDRAM, which is Unbuffered. C. To allow a configuration word stored in Flash memory become active. D. And off-board. See further. E. After the BCSR is removed from the local memory map, there is no way to access it but to re-apply power to the FADS. F. During read cycles. 39 Release 0.1 MPC8XXFADS - User's Manual Functional Description UPM) are programmed accordingly. Dram timing control is performed by UPMA of the MPC via CS2 (and CS3 for a dual-bank SIMM) region(s), i.e., RAS and CAS signals' generation, during normalA access as well as during refresh cycles and the necessary address multiplexingB are performed using UPMA. CS2* and CS3* signals are buffered from the DRAM and each is split to 2 to overcome the capacitive load over the Dram SIMM RAS lines. The DRAM module may enabled / disabled at any time by writing the DRAMEN~ bit in BCSR1. See TABLE 4-10. "BCSR1 Description" on page 57. 4·6·1 DRAM 16 Bit Operation To enhance evaluation capabilities, support is given to Dram with 16-bit and 32-bit data bus width. That way users can tailor dram configuration, to get best fit to their application requirements. When the DRAM is in 16 bit mode, half of it can not be used, i.e., the memory portion that is connected to data lines D(16:31). To configure the DRAM for 16 bit data bus width operation, the following steps should be taken: 1) Set the Dram_Half_Word bit in BCSR1 to Half-Word. See TABLE 4-10. "BCSR1 Description" on page 57 2) The Port Size bits of BR2~ (and of BR3~ for a 2-bank DRAM simm) should be set to 16 bits. 3) The AM bits in OR2 register should be set to 1/2 of the nominal single-bank DRAM simm volume or to 1/4 of the nominal dual-bank DRAM simm volume. If a Dual-Bank DRAM simm is being used: 4) The Base-Address bits in BR3 register should be set to DRAM_BASE + 1/4 Nominal_Volume, that is, if a contiguous block of DRAM is desired. 5) The AM bits of OR3 register, should be set to 1/4 Nominal_Volume. If the above is executed out of running code, than this code should not reside on the DRAM while executing, otherwise, erratic behavior is likely to be demonstrated, resulting in a system crash. 4·6·2 DRAM Performance Figures The projected performance figures for the dram are shown in TABLE 4-2. "Regular DRAM Performance A. Normal i.e.: Single Read, Single Write, Burst Read & Burst Write. B. Taking into account support for narrower bus widths. 40 Release 0.1 MPC8XXFADS - User's Manual Functional Description Figures" on page 41 and in TABLE 4-3. "EDO DRAM Performance Figures" on page 41. TABLE 4-2. Regular DRAM Performance Figures Number of System Clock Cycles System Clock Frequency [MHz] 50 DRAM Delay [nsec] 25 60 70 60 70 Single Read 6 6 3 4 Single Write 4 4 3 3 Burst Read 6,2,3,2 6,3,2,3 3,2,2,2 4,2,2,2 Burst Write 4,2,2,2 4,2,2,2 3,1,2,2 3,2,2,2 ab ab ab Refresh 21 25 13 13a b a. Four-beat refresh burst. b. Not including arbitration overhead. TABLE 4-3. EDO DRAM Performance Figures Number of System Clock Cycles System Clock Frequency [MHz] 50 DRAM Delay [nsec] 25 60 70 60 70 Single Read 6 6 3 4 Single Write 4 4 2 3 Burst Read 6,2,2,2 6,3,2,2 3,1,1,1 4,1,2,2 Burst Write 4,2,2,2 4,2,2,2 2,1,1,1 3,2,2,2 ab ab ab Refresh 21 25 13 13a b a. Four-beat refresh burst. b. Not including arbitration overhead. 4·6·3 Refresh Control The refresh to the dram is a CAS before RAS refresh, which is controlled by UPMA as well. The refresh logic is clocked by the MPC's BRG clock which is not influenced by the MPC's low-power divider. 41 Release 0.1 MPC8XXFADS - User's Manual Functional Description FIGURE 4-1 Refresh Scheme BRG Clock PTP PTB UPMB DRAM BANKS As seen in FIGURE 4-1 "Refresh Scheme" above, the BRG clock is twice divided: once by the PTP (Periodic Timer Prescaler) and again by another prescaler - the PTA, dedicated for each UPM. If there are more than one dram banks, than refresh cycles are performed for consecutive banks, therefore, refresh should be made faster. The formula for calculation of the PTA is given below: PTA = Refresh_Period X Number_Of_Beats_Per_Refresh_Cycle Number_Of_Rows_To_Refresh X T_BRG X MPTPR X Number_Of_Banks Where: · PTA - Periodic Timer A filed in MAMR. The value of the 2'nd divider. · Refresh_Period is the time (usually in msec) required to refresh a dram bank · Number_Of_Beats_Per_Refresh_Cycle: using the UPM looping capability, it is possible to perform more than one refresh cycle per refresh burst (in fact upto 16). · Number_Of_Rows_To_Refresh: the number of rows in a dram bank · T_BRG: the cycle time of the BRG clock · MPTPR: the value of the periodic timer prescaler (2 to 64) · Number_Of_Banks: number of dram banks to refresh. If we take for example a MCM36200 MCM36200 SIMM which has the following data: · Refresh_Period = 16 msec · Number_Of_Beats_Per_Refresh_Cycle: on the FADS it is 4. · Number_Of_Rows_To_Refresh = 1024 · T_BRG = 20 nsec (system clock @ 50 Mhz) · MPTPR arbitrarily chosen to be 16 · Number_Of_Banks = 2 for that SIMM If we assign the figures to the PTA formula we get the value of PTA should be 97 decimal or 61 hex. 4·6·4 Variable Bus-Width Control Since a port's width determines its address lines' connection scheme, i.e., the number of address lines required for byte-selection varies (1 for 16-bit port and 2 for 32-bit port) according to the port's width, it is necessary to change address connections to a memory port if its width is to be changed. E.g.: if a certain memory is initially configured as a 32-bit port, the list significant address line which is connected to that memory's A0 line should be the MPC's A29. Now, if that port is to be reconfigured as a 16-bit port, the LS address line becomes A30. If a linearA address scheme is to be maintained, all address lines connected to that memory are to be shifted one bit, this obviously involves extensive multiplexing (passive or active). If linear addressing 42 Release 0.1 MPC8XXFADS - User's Manual Functional Description scheme is not a must, than only minimal multiplexing is required to support variable port width. In TABLE 4-4. "DRAM ADDRESS CONNECTIONS" below, the FADS's dram address connection scheme is presented: TABLE 4-4. DRAM ADDRESS CONNECTIONS Width 16 - Bit Depth Dram ADD 32 - Bit Depth 4M 1M 4M 1M A0 BA29 BA29 BA29 BA29 A1 BA28 BA28 BA28 BA28 A2 BA27 BA27 BA27 BA27 A3 BA26 BA26 BA26 BA26 A4 BA25 BA25 BA25 BA25 A5 BA24 BA24 BA24 BA24 A6 BA23 BA23 BA23 BA23 A7 BA22 BA22 BA22 BA22 A8 BA21 BA21 BA21 BA21 A9 BA20 BA20 BA20 BA30 A10 BA19 BA30 As can seen from the table above, most of the address lines remain fixed while only 2 lines (the shaded cells) need switching. The switching scheme is shown in FIGURE 4-2 "DRAM Address Lines' Switching Scheme" on page 44. The switches on that figure are implemented by active multiplexers controlled by the BCSR1/Dram_Half_Word* bit. A. Consequent addresses lead to adjacent memory cells 43 Release 0.1 MPC8XXFADS - User's Manual Functional Description FIGURE 4-2 DRAM Address Lines' Switching Scheme DRAM BA(21:29) A(0:8) BA20 A9 BA30 BA19 A10 BA30 4·7 Flash Memory SIMM The MPC8XXFADS is provided with 2Mbyte of 90 nsec flash memory SIMM - the MCM29020 MCM29020 by Motorola. Support is given also to 4MBytes MCM29F040 MCM29F040, 8 MBytes MCM29F080 MCM29F080, 4 MBytes SM73218 SM73218 and to 8 MBytes SM73228 SM73228 by Smart Technology. The Motorola SIMMs are internally composed of 1, 2 or 4 banks of 4 Am29F040 Am29F040 compatible devices, while the Smart SIMMs are arranged as 1 or 2 banks of four 28F008 28F008 devices by Intel. The flash SIMM resides on an 80 pin SIMM socket. To minimize use of MPC's chip-select lines, only one chip-select line (CS0~) is used to select the flash as a whole, while distributing chip-select lines among the internal banks is done via on-board programmable 44 Release 0.1 MPC8XXFADS - User's Manual Functional Description logic, according to the Presence-Detect lines of the Flash SIMM inserted to the FADS. FIGURE 4-3 Flash Memory SIMM Architecture Flash Presence-Detect Lines ADD F_CS1~ M29F040 M29F040 or 1M X8 M29F040 M29F040 or 1M X 8 M29F040 M29F040 or 1M X 8 F_CS2~ M29F040 M29F040 or 1M X 8 M29F040 M29F040 or 1M X 8 M29F040 M29F040 or 1M X 8 M29F040 M29F040 or 1M X 8 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 CS0~ M29F040 M29F040 or 1M X 8 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 FADS's Logic F_CS3~ F_CS4~ DATA MCM29F020 MCM29F020 SM73218 SM73218 MCM29F040 MCM29F040 SM73228 SM73228 MCM29F080 MCM29F080 The access time of the Flash memory provided with the FADS is 90 nsec, however, 120 nsec devices may be used as well. Reading the delay section of the Flash SIMM Presence-Detect lines, the debugger establishes (via OR0) the correct number of wait-states (considering 50MHz system clock frequency). The Motorola SIMMs are built of AMD's Am29F0X0 Am29F0X0 devices which are 5V programmable, i.e., there is no need for external programming voltage and the flash may be written almostA as a regular memory. The SMART parts however, require 12V ± 0.5% programming voltage to be applied for programming. If on-boards programming of such device is required, a 12V supply needs to be connected to the FADS (P7). Otherwise, for normalB Flash operation, 12V supply is not required. The control over the flash is done using the GPCM and a dedicated CS0~ region, controlling the whole bank. During hard - reset initializations, the debugger reads the Flash Presence-Detect lines via BCSR2 and decides how to program BR0 & OR0 registers, within which the size and the delay of the region are determined. The performance of the flash memory is shown in TABLE 4-5. "Flash Memory Performance Figures" A. A manufacturer specific dedicated programming algorithm should be implemented during flash programming. B. I.e., Read-Only. 45 Release 0.1 MPC8XXFADS - User's Manual Functional Description below: TABLE 4-5. Flash Memory Performance Figures Number of System Clock Cycles System Clock Frequency [MHz] 50 25 Flash Delay [nsec] 90 120 90 120 Read / Writea Access [Clocks] 8 10 4 5 a. The figures in the table refer to the actual write access. The write operation continues internally and the device has to be polled for operation completion. The Flash module may disabled / enabled at any time by writing '1' / '0' the FlashEn~ bit in BCSR1. 4·8 Synchronous Dram To enhance performance, especially in higher operation frequencies - 4 MBytes of SDRAM is provided on board. The SDRAM is unbuffered from the MPC bus and is configured as 2 X 512K X 32. Use is done with two MB811171622A-100 MB811171622A-100 chips by Fujitsu or compatibles. To enhance performance, the SDRAM is unbuffered from the MPC, saving the delay associated with address and data buffers. Since only 2 memory chips are involved, it does not adversely effect overall system performance. The SDRAM does not reside on a SIMM but is soldered directly to the FADS pcb. The SDRAM may be enabled / disabled at any time by writing 1 / 0 to the SDRAMEN bit in BCSR1. See TABLE 4-10. "BCSR1 Description" on page 57. The SDRAM's timing is controlled by UPMB via its assigned CS (See TABLE 4-1. "MPC8XXFADS Chip Selects' Assignment" on page 39) line. Unlike a regular dram the synchronous dram has a CS input in addition to the RAS and CAS signals. The sdram connection scheme is shown in FIGURE 4-4 "SDRAM Connection Scheme" on page 47. The SDRAM's performance figures, are shown in TABLE 4-6. "Estimated SDRAM Performance Figures": TABLE 4-6. Estimated SDRAM Performance Figures Number of System Clock Cycles System Clock Frequency [MHz] 25a 50 Single Read 5 3 Single Write 3+1b 2 + 1b Burst Read 5,1,1,1 3,1,1,1 Burst Write 3,1,1,1 + 1b 2,1,1,1 + 1b Refresh 21 c 13 b a. In fact upto 32MHz. b. One additional cycle for RAS precharge c. 4-beat Refresh Burst, not including arbitration overhead. 46 Release 0.1 MPC8XXFADS - User's Manual Functional Description FIGURE 4-4 SDRAM Connection Scheme CS4 CS GPL1 GPL2 GPL3 A10 GPL0 (A11) A(20:21) A(22:29) SDRAMEN SYSCLK CS RAS RAS CAS CAS W W A11 A11 A10 A10 A(9:8) A(9:8) A(7:0) A(7:0) CKE CKE CLK CLK BS0_B DQMU DQMU BS1_B DQML DQML DQ(15:0) DQ(15:0) D(0:15) BS2_B BS3_B D(16:31) 4·8·1 SDRAM Programming After power-up, the sdram needs to be initialized by means of programming, to establish its mode of operation. The Sdram is programmed by issuing a Mode Register Set command. During that command, data is passed to the Mode Register through the Sdram's address lines. This command is fully supported by the UPM by means of a dedicated Memory Address Register and the UPM command run option. Mode Register programming values are shown in TABLE 4-7. "SDRAM's Mode Register Programming" 47 Release 0.1 MPC8XXFADS - User's Manual Functional Description below: TABLE 4-7. SDRAM's Mode Register Programming Value @ Frequency SDRAM Option Burst Length Burst Type CAS Latency Write Burst Length 4·8·1·1 50MHz 25MHz 4 4 Sequential Sequential 2 1 Burst Burst SDRAM Initializing Procedure After Power-up the SDRAM needs to be initialized in a certain manner, described below: 1) UPMB should be programmed with values described in TABLE 3-8. "UPMB Initializations for MB811171622A-100 MB811171622A-100 upto 32MHz" on page 34 or in TABLE 3-9. "UPMB Initializations for MB811171622A-100 MB811171622A-100, 32+MHz - 50MHz" on page 35. 2) Memory controller's MPTPR, MBMR, OR4 and BR4 registers should be programmed according to TABLE 3-6. "Memory Controller Initializations For 20Mhz" on page 30 or TABLE 3-3. "Memory Controller Initializations For 50Mhz" on page 27. 3) MAR should be set with proper value (0x48 for upto 32MHz or 0x88 for 32 - 50 MHz) 4) MCR should be written with 0x80808105 to run the MRS command programmed in locations 5 - 8 of UPMB. 5) MBMR's TLFB field should be changed to 8, to constitute 8-beat refresh Bursts. 6) MCR should be written with 0x80808130 to run the refresh sequence (8 refresh cycles are performed now) 7) MBMR's TLFB field should be restored to 4, to provide 4-beat refresh Bursts for normal operation. The SDRAM is initialized and ready for operation. 4·8·2 SDRAM Refresh The SDRAM is refreshed using its auto-refresh mode. I.e., using UMPB's periodic timer, a burst of four auto-refresh commands is issued to the SDRAM every 62.4 µsec, so that all 2048 SDRAM rows are refreshed within specified 32.8 msec. 48 Release 0.1 MPC8XXFADS - User's Manual Functional Description 4·9 Communication Ports Since the FADS platform is meant to serve all the MPC8XX family, it only contains modules that are common to all family members. The various communication ports for the present and future family members are shown in TABLE 4-8. "MPC8XX Family Comm. Ports" below: TABLE 4-8. MPC8XX Family Comm. Ports Family Member - MPC Comm. Port 801 823 821 860 860SAR 860SAR 860T SCC1 Uart, IrDA USB 3 +Enet 3 +Enet 3 +Enet 3 +Enet SCC2 Uart, IrDA 3 +Enet, Fast IrDA 3 +IrDA 3 +Enet, IrDA 3 +Enet, IrDA 3 +Enet, IrDA SCC3 3 +Enet 3 +Enet 3 +Enet SCC4 3 +Enet 3 +Enet 3 +Enet SMC1 3 Uart 3 Uart 3 Uart 3 Uart 3 Uart SMC2 3 TDM Only 3 Uart 3 Uart 3 Uart 3 Uart SPIa 3 3 3 3 3 3 I2 C a 3 3 3 3 3 3 Fast Enet Utopia 3 3 a. This is an interchip protocol and therefore will not be supported for evaluation. As can be seen from the above table the Ethernet, I/R and Uart (RS232 RS232) support are common to allA family members. Therefore, the FADS is equipped with 2 port of RS232 RS232, each with independent enable via BCSR and an IRDA transceiver, supporting Fast IRDA. 4·9·1 Ethernet Port An Ethernet port with T.P. (10-Base-T) I/F is provided on the MPC8XXFADS. The comm. port over which this port resides, is determined according to the MPC typeB. Use is done with the MC68160 MC68160 EEST 10-baseT transceiver, used also with the MPC8XXFADS. To allow alternative use of the Ethernet's SCC pins, they appear at the expansion connectors over the daughter-board and over the Comm. Ports expansion connector (P8) of the this board, while the Ethernet transceiver may be Disabled / Enabled at any time by writing '1' / '0' to the EthEn~ bit in BCSR1. 4·9·2 Infra-Red Port An infra-Red communication port is provided with the FADS - the Temic's TFDS 6000 integrated transceiver, which incorporates both the receiver and transmitter optical devices with the translating logic and supports Fast IrDA (upto 4 Mbps). The comm. port over which this port resides, is determined according A. Except for the MPC801 MPC801 which does not have Ethernet support. B. I.e., routing is done on the daughter board. 49 Release 0.1 MPC8XXFADS - User's Manual Functional Description B to the MPC type . To allow alternative use of the I/R's SCC or its pins, the infra-red transceiver may be disabled / enabled at any time, by writing '1' / '0' to the IrdEn~ bit in BCSR1, while all pins appear on the daughter-board expansion connector, as well as on P8 of this board. 4·9·2·1 Infra-Red Port Rate Range Selection The TFDS6000 TFDS6000 has 2 bit-rate ranges: 1) 9600 Bps to 1.2 MBps 2) 1.2 MBps to 4 MBps. Selection between the 2 ranges is determined by the state of the transceiver's TX input on the falling edge of IrdEn~. When TX input is LOW at least 200 nsec before the falling edge of IrdEn~, then, the LOWER range is selected. If TX is HIGH for that period of time, then, the HIGHER range is selected. 4·9·3 RS232 RS232 Ports To assist user's applications and to provided convenient communication channels with both a terminal and a host computer, two identical RS232 RS232 ports are provided on the FADS. The MPC's communication ports to which these RS232 RS232 ports is routed, is established according to the type of MPC residing on the daughter board. Use is done with MC145707 MC145707 transceivers which generates RS232 RS232 levels internally using a single 5V supply and are equipped with OE and shutdown mode. When the RS232EN1 RS232EN1 or RS232EN2 RS232EN2 bits in BCSR1 are asserted (low), the associated transceiver is enabled. When negated, the associated transceiver enters standby mode, in which the receiver outputs are tri-stated, enabling use of the associated port's pins, off-board via the expansion connectors. Use is done with 9 pins, female D-Type stacked connector, configured to be directly (via a flat cable) connected to a standard IBM-PC like RS232 RS232 connector. FIGURE 4-5 RS232 RS232 Serial Ports' Connector DCD TX 1 2 TX 3 DTR 4 5 GND 4·9·3·1 6 7 8 9 DSR RTS CTS N.C. RS-232 RS-232 Ports' Signal Description In the list below, the directions 'I', 'O', and 'I/O' are relative to the FADS board. (I.e. 'I' means input to the FADS) · CD ( O ) - Data Carrier Detect. This line is always asserted by the FADS. · TX ( O ) - Transmit Data. · RX ( I ) - Receive Data. · DTR ( I ) - Data Terminal Ready. This signal may be used by the software on the FADS to detect if a terminal is connected to the FADS board. · DSRA ( O ) - Data Set Ready. This line is always asserted by the FADS. · RTS ( I ) - Request To Send. This line is not connected in the FADS. · CTS ( O ) - Clear To Send. This line is always asserted by the FADS. A. Since there are only 3 RS232 RS232 transmitters in the device, DSR is connected to CD. 50 Release 0.1 MPC8XXFADS - User's Manual Functional Description 4·10 PCMCIA PortA To enhance PCMCIA i/f development, a dedicated PCMCIA port is provided on the FADS. Support is given to 5V only PC-Cards, PCMCIA standard 2.1+ compliant. All the necessary control signals are generated by the MPC itself. To protect MPC signals from external hazards, and to provide sufficient drive capability, a set of buffers and latches is provided over PC-Card's address, data & strobe lines. To conform with the design spirit of the FADS, i.e., making as much as possible MPC resources available for external application development, input buffers are provided for input control signals, controlled by the PCC_EN~ bit in BCSR1, so the PCMCIA port may be Disabled / Enabled at any time, by writing '1' / '0' to that bit. When the PCMCIA channel is disabled, its associated pins are available for off-board use via the expansion connectors. A loudspeaker is provided on board and connected to SPKROUT line of the MPC. The speaker is buffered from the MPC and low-pass filtered. When the PCC_EN~ bit in BCSR1 is negated (high) the speaker buffer is tri-stated so the SPKROUT signal of the MPC may be used for alternate function. Since it is not desirableB to apply control signals to unpowered PC-Card, the strobe / data signal buffers / transceivers are tri-stated and may be driven only when the PC-Card is powered. The block diagram of the PCMCIA port is shown in FIGURE 4-6 "PCMCIA Port Configuration" on page 52. A. As the MPC801 MPC801 does not have a PCMCIA port, this port is not operational with an MPC801 MPC801 daughter board. B. This since the PC-Card might have protection diodes on its inputs, which will force down input signals regardless of their driven level. 51 Release 0.1 MPC8XXFADS - User's Manual Functional Description FIGURE 4-6 PCMCIA Port Configuration PCMCIA SOCKET PCCVCC Power Logic LTC1315 LTC1315 or equiv. PCMCIA POWER CONTROL From BCSR PCCVPP 1 1 1 5V 12V D[8:15] Data_A[15:8] D[0:7] Data_A[7:0] 8 8 8 8 OE From BCSR 1 PCMCIA_EN R/W 1 CE1_A(B) CE1 1 CE2_A(B) CE2 1 1 WE/PGM WE/PGM OE 2 IORD,IOWR 1 OE RESET_A(B) 1 MPC8XX IORD,IOWR RESET POE_A(B) 1 1 2 1 Transparent latch with OE A[6:31] Address_A[25:0] 26 1 1 buffer with OE On Daughter - Board 1 1 REG REG ALE_A(B) VDD OE 26 1 VDD WAIT_A(B), IOIS16 IOIS16_A(B) 2 2 RDY/BSY_A(B), BVD(1:2)_A(B) 3 VDD VDD 3 5 CD(1:2)_A(B),VS(1:2)_A(B) 4 4 1 52 SPKROUT LPF Release 0.1 MPC8XXFADS - User's Manual Functional Description 4·10·1 PCMCIA Power Control To support hot-insertion A the socket's power is controlled via a dedicated PCMCIA power controller the LTC1315 LTC1315 made by LINEAR TECHNOLOGY. This device, controlled by BCSR1, switches 12V VPP for card programming and controls gates of external MOSFET transistors, through which the PC Card VCC is switched. When a card is inserted while the channel is enabled via BCSR1, i.e., both of the CD(1:2)* (Card Detect) lines are asserted (low), the status of the voltage select lines VS(1:2)* should be read to determine the PC Card's operation voltage level according to which, PCCVCC(0:1) bits in BCSR1 should be set, to drive the correct VCC (5V) to the PC-Card. When a card is being removed from the socket while the channel is enabled via BCSR1, the negation of CD1~ and CD2~ may be sensed by the MPC and power supply to the card may be cut. WARNNING Any application S/W handling the PCMCIA channel must check the Voltage-Sense lines before Power is applied to the PC-Card. Otherwise, if 5V power is applied to a 3.3V-Only card, permanent damage will be inflicted to the PC-Card. 4·11 Board Control & Status Register - BCSR Most of the hardware options on the MPC8XXFADS are controlled or monitored by the BCSR, which is a 32B bit wide read / write register file. The BCSR is accessed via the MPC's CS1 region and in fact includes 5 registers: BCSR0 to BCSR4. Since the minimum block size for a CS region is 32KBytes, BCSR0 BCSR4 are multiply duplicated within that region. See also TABLE 3-1. "MPC8XXADS Main Memory Map" on page 25. The following functions are controlled / monitored by the BCSR: 1) MPC's Hard Reset Configuration. 2) Flash Module Enable / Disable 3) Dram Module Enable / Disable 4) Dram port width - 32 bit / 16 bit. 5) SDRAM Module Enable / Disable. 6) Ethernet port Enable / Disable. 7) Infra-Red port Enable / Disable. 8) RS232 RS232 port 1 Enable / Disable. 9) RS232 RS232 port 2 Enable / Disable. 10) BCSR Enable / Disable. 11) Hard Reset Configuration Source - BCSR0 / FlashC Memory 12) PCMCIA control which include: · Channel Enable / Disable. A. I.e., card insertion when the FADS is powered B. In fact only the upper 16 bits - D(0:15) are used, but the BCSR is mapped as a 32 bit wide register and should be accessed as such. C. Provided that support is provided also within the MPC. 53 Release 0.1 MPC8XXFADS - User's Manual Functional Description · PC Card VCC appliance. · PC Card VPP appliance. 13) USBA Port Enable or UtopiaB Port Enable or 100-Base-TC Port Enable 14) USB Power Control. 15) Video Port Enable 16) Video Port Clock Select 17) Ethernet Port Control. 18) Dram Type / Size and Delay Identification. 19) Flash Size / Delay Identification. 20) External (off-board) tools identification or S/W option selection switch - DS1 status. 21) Daughter Board ID. 22) Mother Board Revision code 23) Daughter Board Revision code Since all of the FADS's modules are controlled by the BCSR and since they may be disabled in favor of external hardware, the enable signals for these modules are presented at both the daughter board connector and at the expansion connector over the daughter board, so that off- board hardware may be mutually exclusive enabled with on-board modules. 4·11·1 BCSR Disable Protection Logic The BCSR itself may be disabled in favor of off-board logic. To avoid accidental disable of the BCSR, an event from which only power re-appliance recovers, protection logic is provided: The BCSR_EN~ bit resides on BCSR1. This bit wakes-up active (low) during power-up and may not be changedD unless BCSR_EN_PROTECT~ bit in BCSR3 is written with '1' previously. After the BCSR_EN_PROTECT~ is written with '1' to unprotect the BCSR_EN~ bit there is only one shot at disabling the BCSR, since, immediately after any write to BCSR1, BCSR_EN_PROTECT~ is re-activated and BCSR_EN~ is re-protected and the disabling procedure has to be repeated if desired. 4·11·2 BCSR0 - Hard Reset Configuration Register BCSR0 is located at offset 0 on BCSR space. It may be read or written at any timeE. BCSR0 gets its defaults upon MAINF Power-On reset. During Hard-Reset data contained in BCSR0 is driven on the data bus to provide the Hard-Reset configuration for the MPC, this, if the Flash_Configuration_Enable~ bit in BCSR1 is not active. BCSR0 may be written at any time to change the Hard-Reset configuration of the MPC. The new values become valid when the next Hard-Reset is issued to the MPC regardless of the Hard-Reset source. The description of BCSR0 bits is shown in TABLE 4-9. "BCSR0 Description" on page A. For the MPC823 MPC823 daughter board B. For the MPC860SAR MPC860SAR daughter board C. For the MPC860T MPC860T daughter board D. It may be written but will not be influenced. E. Provided that BCSR is not disabled. F. I.e., when VDDH to the MPC is powered. 54 Release 0.1 MPC8XXFADS - User's Manual Functional Description 55. TABLE 4-9. BCSR0 Description BIT MNEMONIC PON DEF. FUNCTION ATT 0 ERB External Arbitration. When '0' during Hard-Reset, Arbitration is performed internally. When '1' during Hard-Reset, Arbitration is performed externally. 0 R,W 1 IP Interrupt Prefix. When '0' during Hard-Reset, Interrupt prefix set to 0xFFF00000, if '1' Interrupt Prefix set to 0. 0 R,W 2 Reserved Implementeda 0 R,W 3 BDIS Boot Disable. When '0' during Hard-Reset, CS0~ region is enabled for boot. When '1', CS0~ region is disabled for boot. 0 R,W 4-5 BPS(0:1) Boot Port Size. Determines the port size for CS0~ at boot. '00' - 32 bit, '01' 8 bit, '10' - 16 bit, '11' - reserved. '00' R,W 6 Reserved Implementeda 0 R,W 7-8 ISB(0:1) Initial Space Base. Value during Hard-Reset determines the initial base address of the internal MPC memory map. When '00' - initial space at 0, when '01' - initial space at 0x00F00000, when '10' - initial space at 0xFF000000, when '11' - initial space at 0xFFF00000. '10' R,W 9 - 10 DBGC(0:1) Debug Pins Configuration. Value during Hard-Reset determines the function of the PCMCIA channel II pins. When '00' - these pins function as PCMCIA channel II pins, when '01' - they serve as Watch-Points,'10' - Reserved, when '11' - they become show-cycle attribute pins, e.g., VFLS, VF. '11' R,W 11-12 DBPC(0:1) Debug Port Pins Configuration. Value during Hard-Reset determines the location of the debug port pins. When '00' - debug port pins are on the JTAG port, when '01' - debug port non-existent, '10' - Reserved, when '11' debug port is on PCMCIA channel II pins. '00' R,W 13 - 14 EBDF(0:1)b External Bus Division Factor. Value during Hard Reset determines the factor upon which the CLKOUT of the MPC external bus, is divided with respect to its internal MPC clock. When '00' - CLKOUT is GCLK2 divided by 1, when '01', CLKOUT is GCLK2 divided by 2. '00' R,W 15 Reserved Implementeda. '0' R,W 16 - 31 Reserved Un-Implemented - - a. May be read and written as any other fields and are presented at their associated data pins during Hard-Reset. b. Applicable for MPC's revision A or above. Otherwise have no influence. 4·11·3 BCSR1 - Board Control Register 1 The BCSR1 serves as a control register on the FADS. It is accessed at offset 4 from BCSR base address. It may be read or written at any time A. BCSR1 gets its defaults upon Power-On reset. Most of BCSR1 pins are available at the daughter board connectors and on the expansion connectors residing over the A. Provided that BCSR is not disabled. 55 Release 0.1 MPC8XXFADS - User's Manual Functional Description daughter boards, providing visibility towards daughter boards' and external logic. BCSR1 fields are de- 56 Release 0.1 MPC8XXFADS - User's Manual Functional Description scribed in TABLE 4-10. "BCSR1 Description" on page 57. TABLE 4-10. BCSR1 Descriptiona BIT MNEMONIC PON DEF Function ATT. 0 FLASH_EN Flash Enable. When this bit is active (low), the Flash memory module is enabled on the local memory map. When in-active, the Flash memory is removed from the local memory map and CS0~, to which the Flash memory is connected may be used off-board via the expansion connectors. 0 R,W 1 DRAM_EN Dram Enable. When this bit is active (low), the DRAM module is enabled on the local memory map. When in-active, the DRAM is removed from the local memory map and CS2~ and CS3~b, to which the DRAM is connected may be used off-board via the expansion connectors. 0 R,W 2 ETHEN Ethernet Port Enable. When asserted (low) the EEST connected to SCC1 is enabled. When negated (high) that EEST is in standby mode, while all its system i/f signals are tri-stated. 1 R,W 3 IRDEN Infra-Red Port Enable. When asserted (low), the Infra-Red transceiver, connected to SCC2 is enabled. When negated, the Infra-Red transceiver is put in shutdown mode. And SCC2 pins are available for off-board use via the expansion connectors. 1 R,W 4 FLASH_CFG_EN Flash Configuration Enable. When this bit is asserted (low): (A) - the Hard-Reset configuration held in BCSR0 is NOT driven on the data bus during Hard-Reset and (B) - configuration data held at the 1'st word of the flash memory is driven to the data bus during Hard-Reset. c 1 R,W 5 CNT_REG_EN_P ROTECT Control Register Enable Protect. When this bit is active (low) the BCSR_EN bit in that register can not be written. When in-active, BCSR_EN may be written to remove the BCSR from the memory map. After any write to BCSR1 this bit becomes active again. This bit is a read-onlyd bit on that register. 0 R 6 BCSR_EN BCSR Enable. When this bit is active (low) the Board Control & Status Register is enabled on the local memory map. When inactive, the BCSR may not be read or written and its associated CS1~ is available for off-board use via the expansion connectors. This bit may be written with '1' only if CNT_REG_EN_PROTECT bit is negated (1). When the BCSR is disabled it still continues to configure the board according the last data held in it even during Hard-Reset. 0 R,W 7 RS232EN RS232EN_1 RS232 RS232 port 1 Enable. When asserted (low) the RS232 RS232 transceiver for port 1, is enabled. When negated, the RS232 RS232 transceiver for port 1, is in standby mode and the relevant MPC communication port pins are available for offboard use via the expansion connectors. 1 R,W 8 PCCEN PC Card Enable. When asserted (low), the on-board PCMCIA channel is enabled, i.e., address and strobe buffers are enabled to / from the card. When negated, all buffers to / from the PCMCIA channel are disabled allowing off-board use of its associated lines. 1 R,W 57 Release 0.1 MPC8XXFADS - User's Manual Functional Description TABLE 4-10. BCSR1 Descriptiona BIT MNEMONIC PON DEF Function ATT. 9 PCCVCC0 Pc Card VCC Select 0. These signal in conjunction with PCCVCC1 determine the voltage applied to the PCMCIA card's VCC. Possible values are 0 / 3.3 / 5 V. For the encoding of these lines and their associated voltages see TABLE 4-11. "PCCVCC(0:1) Encoding" on page 59 . 0 R,W 10 - 11 PCCVPP(0:1) PC Card VPP. These signals determine the voltage applied to the PCMCIA card's VPP. Possible values are 0 / 5 / 12 V. For the encoding of these lines and their associated voltages see TABLE 4-12. "PCCVPP(0:1) Encoding" on page 59. '11' R,W 12 Dram_Half_Word Dram Half Word. When this bit is active (low) and the steps listed in 4·6·1 "DRAM 16 Bit Operation" on page 40, are taken, the DRAM becomes 16 bit wide. When inactive the DRAM is 32 bit wide. 1 R,W 13 RS232EN RS232EN_2 RS232 RS232 port 2 Enable. When asserted (low) the RS232 RS232 transceiver for port 2, is enabled. When negated, the RS232 RS232 transceiver for port 2, is in standby mode and the relevant MPC communication port pins are available for offboard use via the expansion connectors. 1 R,W 14 SDRAMEN SDRAM Enable. When this bit is active (high), the SDRAM module is enabled on the local memory map. When in-active, the DRAM is place in low-power mode, in fact removed from the local memory map, allowing its associated CS line, to be used off-board via the expansion connectors. 1 R,W 15 PCCVCC1 Pc Card VCC Se