TSPC860 TS68EN360 BADDR28 BADDR29 BADDR30 IOIS16 MIL-STD-883 MIL-PRF-38535 - Datasheet Archive

 

· PowerPC® Single Issue Integer Core · Precise Exception Model · Extensive System Development Support

 

Features · PowerPC® Single Issue Integer Core · Precise Exception Model · Extensive System Development Support · · · · · · · · · · · ­ On-chip Watchpoints and Breakpoints ­ Program Flow Tracking ­ On-chip Emulation (Once) Development Interface High Performance (Dhrystone 2.1: 52 MIPS at 50 MHz, 3.3V, 1.3 Watts Total Power) Low Power (< 241 mW at 25 MHz, 2.4V Internal, 3.3V I/O-core, Caches, MMUs, I/O) MPC8XX PowerPC System Interface, Including a Periodic Interrupt Timer, a Bus Monitor, and Real-time Clocks Single Issue, 32-bit Version of the Embedded PowerPC Core (Fully Compatible with Book 1 of the PowerPC Architecture Definition) with 32 x 32-bit Fixed Point Registers ­ Embedded PowerPC Performs Branch Folding, Branch Prediction with Conditional Prefetch, without Conditional Execution ­ 4-Kbyte Data Cache and 4-Kbyte Instruction Cache, Each with an MMU ­ Instruction and Data Caches are Two-way, Set Associative, Physical Address, 4 Word Line Burst, Least Recently Used (LRU) Replacement, Lockable On-line Granularity ­ MMUs with 32 Entry TLB, Fully Associative Instruction and Data TLBs ­ MMUs Support Multiple Page Sizes of 4 KB, 16 KB, 256 KB, 512 KB and 8 MB; 16 Virtual Address Spaces and 8 Protection Groups ­ Advanced On-chip Emulation Debug Mode Up to 32-bit Data Bus (Dynamic Bus Sizing for 8- and 16-bit) 32 Address Lines Fully Static Design VCC = +3.3V ± 5% fmax = 66 MHz (80 MHz (TBC) Military Temperature Range: -55°C < TC < +125°C PD = 0.75 W Typical at 66 MHz 32-bit Quad Integrated Power QUICCTM Communication Controller TSPC860 TSPC860 Description The TSPC860 TSPC860 PowerPC QUad Integrated Communication Controller (Power QUICCTM) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in communications and networking systems. The Power QUICC (pronounced "quick") can be described as a PowerPC-based derivative of the TS68EN360 TS68EN360 (QUICCTM). The CPU on the TSPC860 TSPC860 is a 32-bit PowerPC implementation that incorporates memory management units (MMUs) and instruction and data caches. The communications processor module (CPM) of the TS68EN360 TS68EN360 QUICC has been enhanced with the addition of a Two-wire Interface (TWI) compatible with protocols such as I2C. Moderate to high digital signal processing (DSP) functionality has been added to the CPM. The memory controller has been enhanced, enabling the TSPC860 TSPC860 to support any type of memory, including high performance memories and newer dynamic random access memories (DRAMs). Overall system functionality is completed with the addition of a PCMCIA socket controller supporting up to two sockets and a real-time clock. PBGA 357 ZP suffix Rev. 2129A­HIREL­08/02 1 Screening/Quality This product will be manufactured in full compliance with: · According to Atmel Standards General Description The TSPC860 TSPC860 is functionally composed of three major blocks: · A 32-bit PowerPC Core with MMUs and Caches · A System Interface Unit · A Communications Processor Module Figure 1. Block Diagram View of the TSPC860 TSPC860 4 or 16 KB I-Cache Embedded PowerPC Core Instruction Bus SYSTEM INTERFACE UNIT I-MMU Memory Controller Unified Bus Bus Interface Unit System Functions 4 or 8 KB D-Cache Load/store BUS Parallel I/O Baud Rate Generators Parallel Interface Port SCC1 SCC2 4 Timers Interrupt Controller PCMCIA Interface Dual-Port RAM 32-bit RISC µController and Program ROM 16 Serial DMA and Virtual IDMA MAC Timer SCC3 SCC4 Time Slot Assigner 2 Real Time Clock D-MMU SMC1 SMC2 SPI TWI Serial Interface TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Main Features The Following is a List of the TSPC860 TSPC860's Important Features: · Fully Static Design · Four Major Power Saving Modes · 357 OMPAC Ball Grid Array Packaging (Plastic) · 32-bit Address and Data Busses · Flexible Memory Management · 4-Kbyte Physical Address, Two-way, Set-associative Data Cache · 4-Kbyte Physical Address, Two-way, Set-associative Instruction Cache · Eight-bank Memory Controller ­ Glueless Interface to SRAM, DRAM, EPROM, FLASH and Other Peripherals ­ · Byte Write Enables and Selectable Parity Generation ­ 32-bit Address Decodes With Bit Masks System Interface Unit ­ Clock Synthesizer ­ Power Management ­ Reset Controller ­ PowerPC Decrementer And Time Base ­ Real-time Clock Register ­ Hardware Bus Monitor and Software Watchdog Timer ­ · Periodic Interrupt Timer ­ IEEE 1149.1 JTAG Test Access Port Communications Processor Module ­ Embedded 32-bit RISC Controller Architecture for Flexible I/O ­ Interfaces to PowerPC Core Through On-chip Dual-port Ram And Virtual DMA Channel Controller ­ Continuous Mode Transmission And Reception On All Serial Channels ­ Serial DMA Channels For Reception And Transmission On All Serial Channels ­ I/O registers with Open-drain and Interrupt Capability ­ Memory-memory and Memory-I/O Transfers with Virtual DMA Functionality 3 2129A­HIREL­08/02 ­ ­ Four Hardware Serial Communications Controller Channels Supporting the Protocols ­ Two Hardware Serial Management Channels - Management for BRI Devices as General Circuit Interface Controller Multiplexed Channels - Low-speed UART operation ­ Hardware Serial Peripheral Interfaces ­ Two-wire Interface (TWI) ­ Time-slot Assigner ­ Port Supports Centronics Interfaces and Chip-to-chip ­ Four Independent Baud Rate Generators and Four Input Clock Pins for Supplying Clocks to SMC and SCC Serial Channels ­ 4 Protocols Supported by ROM or Downloadable Microcode and Include, but Limited to, the Digital Portion of: - Ethernet/IEEE 802.3 CS/CDMA - HDLC2/SDLC and HDLC bus - Apple Talk - Signaling System #7 (RAM Microcode Only) - Universal Asynchronous Receiver Transmitter (UART) - Synchronous UART - Binary Synchronous (BiSync) Communications - Totally Transparent - Totally Transparent with CRC - Profibus (RAM Microcode Option) - Asynchronous HDLC - DDCMP - V.14 (RAM Microcode Option) - X.21 (RAM Microcode Option) - V.32bis Datapump Filters - IrDA Serial Infrared - Basis Rate ISDN (BRI) in Conjunction with SMC Channels - Primary Rate ISDN (MH Version Only) Four Independent 16-bit timers Which Can Be Interconnected as Two 32-bit Timers TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Pin Assignment Plastic Ball Grid Array Figure 2. Pin Assignment: Top View W PD10 PD8 PD3 PD9 PD6 PA0 PB14 PD15 PD4 PA1 PC5 PC4 PD11 PC6 PA2 PB15 PD12 PA4 PB17 PA3 VDDL PB19 PA5 PB18 PB16 HRESET TEXP EXTCLK EXTAL PA7 PC8 PA6 PC7 MODCK2 BADDR28 BADDR28 BADDR29 BADDR29 VDDL PB22 PC9 PA8 PB20 PC10 PA9 PB23 PB21 PC11 PB24 PA10 PB25 IRQ7 D0 D4 D1 D2 D3 D5 VDDL D6 D7 D29 DP2 CLKOUT IPA3 M_Tx_EN IRQ0 D13 D27 D10 D14 D18 D20 D24 D28 DP1 DP3 DP0 N/C VSSSYN1 D23 D11 D16 D19 D21 D26 D30 IPA5 IPA4 IPA2 N/C VSSSYN D17 D9 D15 D22 D25 D31 IPA6 IPA0 IPA1 IPA7 XFC VDDSYN V PD14 PD13 U PD5 IRQ1 D8 T PD7 VDDH D12 R VDDH WAIT_B WAIT_A PORESET KAPWR VDDH P GND VDDL RSTCONF SRESET XTAL GND N M L OP0 AS OP1 MODCK1 K GND BADDR30 BADDR30 IPB6 ALEA IRQ4 J IPB5 IPB1 IPB2 ALEB M_COL IRQ2 IPB0 IPB7 IPB4 IPB3 H VDDL M_MDIO TDI TCK TRST TMS TDO PA11 PB26 PC12 PA12 VDDL PB27 PC13 PA13 PB29 PB28 PC14 PA14 PC15 A8 N/C N/C A15 A19 A25 PB30 PA15 PB31 A3 A9 A12 A16 A20 A24 A26 TSIZ1 BSA1 A0 A1 A4 A6 A10 A13 A17 A21 A23 A22 TSIZ0 BSA3 M_CRS WE2 GPLA2 CS5 A2 A5 A7 A11 A14 A27 A29 A30 A28 A31 18 17 16 15 14 13 12 11 10 9 G BR GND IRQ6 VDDL TS CS3 GND BI F VDDH VDDH IRQ3 BURST E BG BB D A18 BSA0 GPLA0 N/C CS6 CS2 GPLA5 BDIP TEA C WE0 GPLA1 GPLA3 CS7 CS0 TA GPLA4 CE1A WR GPLB4 B A 19 Signal Descriptions VDDL BSA2 8 7 WE1 WE3 CS4 CE2A CS1 6 5 4 3 2 1 This section describes the signals on the TSPC860 TSPC860. 5 2129A­HIREL­08/02 Figure 3. TSPC860 TSPC860 External Signals 6 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Figure 4. TSPC860 TSPC860 Signals and Pin Numbers (Part 1) 7 2129A­HIREL­08/02 Figure 5. TSPC860 TSPC860 Signals and Pin Numbers (Part 2) 8 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 System Bus Signals The TSPC860 TSPC860 system bus consists of all signals that interface with the external bus. Many of these signals perform different functions, depending on how the user assigns them. The following input and output signals are identified by their abbreviation. Each signal's pin number can be found in Figure 4 and Figure 5. Table 1. Signal Descriptions Name Reset Number Type Description A(0-31) Hi-Z See Figure 2 Bidirectional Three-state Address Bus - Provides the address for the current bus cycle. A0 is the most-significant signal. The bus is output when an internal master starts a transaction on the external bus. The bus is input when an external master starts a transaction on the bus. TSIZ0 REG Hi-Z B9 Bidirectional Three-state Transfer Size 0 - When accessing a slave in the external bus, used (together with TSIZ1) by the bus master to indicate the number of operand bytes waiting to be transferred in the current bus cycle. TSIZ0 is an input when an external master starts a bus transaction. Register - When an internal master initiates an access to a slave controlled by the PCMCIA interface, REG is output to indicate which space in the PCMCIA card is accessed. TSIZ1 Hi-Z C9 Bidirectional Three-state Transfer Size 1 - Used (with TSIZ0) by the bus master to indicate the number of operand bytes waiting to be transferred in the current bus cycle. The TSPC860 TSPC860 drives TSIZ1 when it is bus master. TSIZ1 is input when an external master starts a bus transaction. RD/WR Hi-Z B2 Bidirectional Three-state Read/Write - Driven by the bus master to indicate the direction of the bus's data transfer. A logic one indicates a read from a slave device and a logic zero indicates a write to a slave device. The TSPC860 TSPC860 drives this signal when it is bus master. Input when an external master initiates a transaction on the bus. BURST Hi-Z F1 Bidirectional Three-state Burst Transaction - Driven by the bus master to indicate that the current initiated transfer is a burst. The TSPC860 TSPC860 drives this signal when it is bus master. This signal is input when an external master initiates a transaction on the bus. BDIP GPL_B5 See Section "Signal States During Hardware Reset" on page 28 D2 Bidirectional Three-state Burst Data in Progress - When accessing a slave device in the external bus, the master on the bus asserts this signal to indicate that the data beat in front of the current one is the one requested by the master. BDIP is negated before the expected last data beat of the burst transfer. General-Purpose Line B5-Used by the memory controller when UPMB takes control of the slave access. TS Hi-Z F3 Bidirectional Active Pull-up Transfer Start - Asserted by the bus master to indicate the start of a bus cycle that transfers data to or from a slave device. Driven by the master only when it has gained the ownership of the bus. Every master should negate this signal before the bus relinquish. TS requires the use of an external pull-up resistor. The TSPC860 TSPC860 samples TS when it is not the external bus master to allow the memory controller/PCMCIA interface to control the accessed slave device. It indicates that an external synchronous master initiated a transaction. 9 2129A­HIREL­08/02 Table 1. Signal Descriptions (Continued) Name Reset Number Type TA Hi-Z C2 Bidirectional Active Pull-up Transfer Acknowledge - Indicates that the slave device addressed in the current transaction accepted data sent by the master (write) or has driven the data bus with valid data (read). This is an output when the PCMCIA interface or memory controller controls the transaction. The only exception occurs when the memory controller controls the slave access by means of the GPCM and the corresponding option register is instructed to wait for an external assertion of TA. Every slave device should negate TA after a transaction ends and immediately three-state it to avoid bus contention if a new transfer is initiated addressing other slave devices. TA requires the use of an external pull-up resistor. TEA Hi-Z D1 Open-drain Transfer Error Acknowledge - Indicates that a bus error occurred in the current transaction. The TSPC860 TSPC860 asserts TEA when the bus monitor does not detect a bus cycle termination within a reasonable amount of time. Asserting TEA terminates the bus cycle, thus ignoring the state of TA. TEA requires the use of an external pull-up resistor. BI Hi-Z E3 Bidirectional Active Pull-up Burst Inhibit - Indicates that the slave device addressed in the current burst transaction cannot support burst transfers. It acts as an output when the PCMCIA interface or the memory controller takes control of the transaction. BI requires the use of an external pull-up resistor. RSV IRQ2 See Section "Signal States During Hardware Reset" on page 28 H3 Bidirectional Three-state Reservation - The TSPC860 TSPC860 outputs this three-state signal in conjunction with the address bus to indicate that the core initiated a transfer as a result of a stwcx. or lwarx. Interrupt Request 2 - One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. KR/RETRY IRQ4 SPKROUT See Section "Signal States During Hardware Reset" on page 28 K1 Bidirectional Three-state Kill Reservation - This input is used as a part of the memory reservation protocol, when the TSPC860 TSPC860 initiated a transaction as the result of a stwcx. instruction. Retry - This input is used by a slave device to indicate it cannot accept the transaction. The TSPC860 TSPC860 must relinquish mastership and reinitiate the transaction after winning in the bus arbitration. Interrupt Request 4 ­ One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal that is sent to the interrupt controller is the logical AND of this line (if defined as IRQ4) and DP1/IRQ4 (if defined as IRQ4). SPKROUT - Digital audio wave form output to be driven to the system speaker. CR IRQ3 Hi-Z F2 Input Cancel Reservation - This input is used as a part of the storage reservation protocol. Interrupt Request 3 - One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of CR/IRQ3 (if defined as IRQ3) and DP0/IRQ3 if defined as IRQ3. 10 Description TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 1. Signal Descriptions (Continued) Name Reset Number Type Description D(0-31) Hi-Z (Pulled Low if RSTCONF pulled down) See Figure 2 Bidirectional Three-state Data Bus - This bidirectional three-state bus provides the generalpurpose data path between the TSPC860 TSPC860 and all other devices. The 32-bit data path can be dynamically sized to support 8-, 16-, or 32-bit transfers. D0 is the MSB of the data bus. DP0 IRQ3 Hi-Z V3 Bidirectional Three-state Data Parity 0 - Provides parity generation and checking for D(0-7) for transfers to a slave device initiated by the TSPC860 TSPC860. The parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves sitting on the external bus. Parity generation and checking is not supported for external masters. Interrupt Request 3 - One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of DP0/IRQ3 (if defined as IRQ3) and CR/IRQ3 (if defined as IRQ3). DP1 IRQ4 Hi-Z V5 Bidirectional Three-state Data Parity 1 - Provides parity generation and checking for D(8-15) for transfers to a slave device initiated by the TSPC860 TSPC860. The parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. Parity generation and checking is not supported for external masters. Interrupt Request 4 - One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of this line (if defined as IRQ4) and KR/IRQ4/SPKROUT (if defined as IRQ4). DP2 IRQ5 Hi-Z W4 Bidirectional Three-state Data Parity 2 - Provides parity generation and checking for D(1623) for transfers to a slave device initiated by the TSPC860 TSPC860. The parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. Parity generation and checking is not supported for external masters. Interrupt Request 5 - One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. DP3 IRQ6 Hi-Z V4 Bidirectional Three-state Data Parity 3 - Provides parity generation and checking for D(2431) for transfers to a slave device initiated by the TSPC860 TSPC860. The parity function can be defined independently for each one of the addressed memory banks (if controlled by the memory controller) and for the rest of the slaves on the external bus. Parity generation and checking is not supported for external masters. Interrupt Request 6 - One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of this line (if defined as IRQ6) and the FRZ/IRQ6 (if defined as IRQ6). BR Hi-Z G4 Bidirectional Bus Request - Asserted low when a possible master is requesting ownership of the bus. When the TSPC860 TSPC860 is configured to work with the internal arbiter, this signal is configured as an input. When the TSPC860 TSPC860 is configured to work with an external arbiter, this signal is configured as an output and asserted every time a new transaction is intended to be initiated (no parking on the bus). 11 2129A­HIREL­08/02 Table 1. Signal Descriptions (Continued) Name Number Type BG Hi-Z E2 Bidirectional Bus Grant - Asserted low when the arbiter of the external bus grants the bus to a specific device. When the TSPC860 TSPC860 is configured to work with the internal arbiter, BG is configured as an output and asserted every time the external master asserts BR and its priority request is higher than any internal sources requiring a bus transfer. However, when the TSPC860 TSPC860 is configured to work with an external arbiter, BG is an input. BB Hi-Z E1 Bidirectional Active Pull-up Bus Busy - Asserted low by a master to show that it owns the bus. The TSPC860 TSPC860 asserts BB after the arbiter grants it bus ownership and BB is negated. FRZ IRQ6 See Section "Signal States During Hardware Reset" on page 28 G3 Bidirectional Freeze - Output asserted to indicate that the core is in debug mode. Interrupt Request 6 - One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. Note that the interrupt request signal sent to the interrupt controller is the logical AND of FRZ/IRQ6 (if defined as IRQ6) and DP3/IRQ6 (if defined as IRQ6). IRQ0 Hi-Z V14 Input Interrupt Request 0 - One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. IRQ1 Hi-Z U14 Input Interrupt Request 1 - One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. IRQ7 Hi-Z W15 Input Interrupt Request 7 - One of eight external inputs that can request (by means of the internal interrupt controller) a service routine from the core. CS(0-5) High C3, A2, D4, E4, A4, B4 Output Chip Select - These outputs enable peripheral or memory devices at programmed addresses if they are appropriately defined. CS0 can be configured to be the global chip-select for the boot device. CS6 CE1_B High D5 Output Chip Select 6 - This output enables a peripheral or memory device at a programmed address if defined appropriately in the BR6 and OR6 in the memory controller. Card Enable 1 Slot B - This output enables even byte transfers when accesses to the PCMCIA Slot B are handled under the control of the PCMCIA interface. CS7 CE2_B 12 Reset Description High C4 Output Chip Select 7 - This output enables a peripheral or memory device at a programmed address if defined appropriately in the BR7 and OR7 in the memory controller. Card Enable 2 Slot B - This output enables odd byte transfers when accesses to the PCMCIA Slot B are handled under the control of the PCMCIA interface. TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 1. Signal Descriptions (Continued) Name Reset Number Type Description WE0 BS_B0 IORD High C7 Output Write Enable 0 - Output asserted when a write access to an external slave controlled by the GPCM is initiated by the TSPC860 TSPC860. WE0 is asserted if D(0-7) contains valid data to be stored by the slave device. Byte Select 0 on UPMB - Output asserted under control of the UPMB, as programmed by the user. In a read or write transfer, the line is only asserted if D(0-7) contains valid data. IO Device Read - Output asserted when the TSPC860 TSPC860 starts a read access to a region controlled by the PCMCIA interface. Asserted only for accesses to a PC card I/O space. WE1 BS_B1 IOWR High A6 Output Write Enable 1 - Output asserted when the TSPC860 TSPC860 initiates a write access to an external slave controlled by the GPCM. WE1 is asserted if D(8-15) contains valid data to be stored by the slave device. Byte Select 1 on UPMB - Output asserted under control of the UPMB, as programmed by the user. In a read or write transfer, the line is only asserted if D(8-15) contains valid data. I/O Device Write - This output is asserted when the TSPC860 TSPC860 initiates a write access to a region controlled by the PCMCIA interface. IOWR is asserted only if the access is to a PC card I/O space. WE2 BS_B2 PCOE High B6 Output Write Enable 2 - Output asserted when the TSPC860 TSPC860 starts a write access to an external slave controlled by the GPCM. WE2 is asserted if D(16-23) contains valid data to be stored by the slave device. Byte Select 2 on UPMB - Output asserted under control of the UPMB, as programmed by the user. In a read or write transfer, BS_B2 is asserted only D(16-23) contains valid data. PCMCIA Output Enable - Output asserted when the TSPC860 TSPC860 initiates a read access to a memory region under the control of the PCMCIA interface. WE3 BS_B3 PCWE High A5 Output Write Enable 3 - Output asserted when the TSPC860 TSPC860 initiates a write access to an external slave controlled by the GPCM. WE3 is asserted if D(24-31) contains valid data to be stored by the slave device. Byte Select 3 on UPMB - Output asserted under control of the UPMB, as programmed by the user. In a read or write transfer, BS_B3 is asserted only if D(24-31) contains valid data. PCMCIA Write Enable - Output asserted when the TSPC860 TSPC860 initiates a write access to a memory region under control of the PCMCIA interface. BS_A(0-3) High D8, C8, A7, B8 Output Byte Select 0 to 3 on UPMA - Outputs asserted under requirement of the UPMB, as programmed by the user. For read or writes, asserted only if their corresponding data lanes contain valid data: BS_A0 for D(0-7), BS_A1 for D(8-15), BS_A2 for D(16-23), BS_A3 for D(24-31) 13 2129A­HIREL­08/02 Table 1. Signal Descriptions (Continued) Name Reset Number Type GPL_A0 GPL_B0 High D7 Output General-Purpose Line 0 on UPMA - This output reflects the value specified in the UPMA when an external transfer to a slave is controlled by the UPMA. General-Purpose Line 0 on UPMB - This output reflects the value specified in the UPMB when an external transfer to a slave is controlled by the UPMB. OE GPL_A1 GPL_B1 High C6 Output Output Enable - Output asserted when the TSPC860 TSPC860 initiates a read access to an external slave controlled by the GPCM. General-Purpose Line 1 on UPMA - This output reflects the value specified in the UPMA when an external transfer to a slave is controlled by UPMA. General-Purpose Line 1 on UPMB - This output reflects the value specified in the UPMB when an external transfer to a slave is controlled by UPMB. GPL_A(2-3) GPL_B(2-3) CS(2-3) High B5, C5 Output General-Purpose Line 2 and 3 on UPMA - These outputs reflect the value specified in the UPMA when an external transfer to a slave is controlled by UPMA. General-Purpose Line 2 and 3 on UPMB - These outputs reflect the value specified in the UPMB when an external transfer to a slave is controlled by UPMB. Chip Select 2 and 3 - These outputs enable peripheral or memory devices at programmed addresses if they are appropriately defined. The double drive capability for CS2 and CS3 is independently defined for each signal in the SIUMCR. UPWAITA GPL_A4 Hi-Z C1 Bidirectional User Programmable Machine Wait A - This input is sampled as defined by the user when an access to an external slave is controlled by the UPMA. General-Purpose Line 4 on UPMA - This output reflects the value specified in the UPMA when an external transfer to a slave is controlled by UPMA. UPWAITB GPL_B4 Hi-Z B1 Bidirectional User Programmable Machine Wait B - This input is sampled as defined by the user when an access to an external slave is controlled by the UPMB. General-Purpose Line 4 on UPMB - This output reflects the value specified in the UPMB when an external transfer to a slave is controlled by UPMB. GPL_A5 High D3 Output General-Purpose Line 5 on UPMA - This output reflects the value specified in the UPMA when an external transfer to a slave is controlled by UPMA. This signal can also be controlled by the UPMB. PORESET Hi-Z R2 Input Power on Reset - When asserted, this input causes the TSPC860 TSPC860 to enter the power-on reset state. RSTCONF Hi-Z P3 Input Reset Configuration - The TSPC860 TSPC860 samples this input while HRESET is asserted. If RSTCONF is asserted, the configuration mode is sampled in the form of the hard reset configuration word driven on the data bus. When RSTCONF is negated, the TSPC860 TSPC860 uses the default configuration mode. Note that the initial base address of internal registers is determined in this sequence. HRESET Low N4 Open-drain Hard Reset - Asserting this open drain signal puts the TSPC860 TSPC860 in hard reset state. 14 Description TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 1. Signal Descriptions (Continued) Name Reset Number Type Description SRESET Low P2 Open-drain XTAL Analog Driving P1 Analog Output EXTAL Hi-Z N1 Analog Input (3.3V only) This line is one of the connections to an external crystal for the internal oscillator circuitry. XFC Analog Driving T2 Analog Input External Filter Capacitance - This input is the connection pin for an external capacitor filter for the PLL circuitry. CLKOUT High until SPLL locked, then oscillating W3 Output EXTCLK Hi-Z N2 Input (3.3V only) TEXP High N3 Output Timer Expired - This output reflects the status of PLPRCR[TEXPS]. ALE_A Low K2 Output Address Latch Enable A - This output is asserted when TSPC860 TSPC860 initiates an access to a region under the control of the PCMCIA interface to socket A. CE1_A High B3 Output Card Enable 1 Slot A - This output enables even byte transfers when accesses to PCMCIA Slot A are handled under the control of the PCMCIA interface. CE2_A High A3 Output Card Enable 2 Slot A - This output enables odd byte transfers when accesses to PCMCIA Slot A are handled under the control of the PCMCIA interface. WAIT_A Hi-Z R3 Input Wait Slot A - This input, if asserted low, causes a delay in the completion of a transaction on the PCMCIA controlled Slot A. WAIT_B Hi-Z R4 Input Wait Slot B - This input, if asserted low, causes a delay in the completion of a transaction on the PCMCIA controlled Slot B. IP_A(0-1) Hi-Z T5, T4 Input Input Port A 0-1 - The TSPC860 TSPC860 monitors these inputs that are reflected in the PIPR and PSCR of the PCMCIA interface. IP_A2 IOIS16 IOIS16_A Hi-Z U3 Input Input Port A 2 - The TSPC860 TSPC860 monitors these inputs; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. I/O Device A is 16-Bits Ports Size - The TSPC860 TSPC860 monitors this input when a transaction under the control of the PCMCIA interface is initiated to an I/O region in socket A of the PCMCIA space. IP_A(3-7) Hi-Z W2, U4, U5, T6, T3 Input Input Port A 3-7 - The TSPC860 TSPC860 monitors these inputs; their values and changes are reported in the PIPR and PSCR of the PCMCIA interface. Soft Reset - Asserting this open drain line puts the TSPC860 TSPC860 in soft reset state. This output is one of the connections to an external crystal for the internal oscillator circuitry. Clock Out - This output is the clock system frequency. External Clock - This input is the external input clock from an external source. 15 2129A­HIREL­08/02 Table 1. Signal Descriptions (Continued) Name Reset Number Type ALE_B DSCK/AT1 See Section "Signal States During Hardware Reset" on page 28 J1 Bidirectional Three-state Address Latch Enable B - This output is asserted when the TSPC860 TSPC860 initiates an access to a region under the control of the PCMCIA socket B interface. Development Serial Clock - This input is the clock for the debug port interface. Address Type 1 - The TSPC860 TSPC860 drives this bidirectional three-state line when it initiates a transaction on the external bus. When the transaction is initiated by the core, it indicates if the transfer is for user or supervisor state. This signal is not used for transactions initiated by external masters. IP_B(0-1) IWP(0-1) VFLS(0-1) See Section "Signal States During Hardware Reset" on page 28 H2, J3 Bidirectional Input Port B 0-1 - The TSPC860 TSPC860 senses these inputs; their values and changes are reported in the PIPR and PSCR of the PCMCIA interface. Instruction Watchpoint 0-1 - These outputs report the detection of an instruction watchpoint in the program flow executed by the core. Visible History Buffer Flushes Status - The TSPC860 TSPC860 outputs VFLS(0-1) when program instruction flow tracking is required. They report the number of instructions flushed from the history buffer in the core. IP_B2 IOIS16 IOIS16_B AT2 Hi-Z J2 Bidirectional Three-state Input Port B 2 - The TSPC860 TSPC860 senses this input; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. I/O Device B is 16- Bits Port Size - The TSPC860 TSPC860 monitors this input when a PCMCIA interface transaction is initiated to an I/O region in socket B in the PCMCIA space. Address Type 2 - The TSPC860 TSPC860 drives this bidirectional three-state signal when it initiates a transaction on the external bus. If the core initiates the transaction, it indicates if the transfer is instruction or data. This signal is not used for transactions initiated by external masters. IP_B3 IWP2 VF2 See Section "Signal States During Hardware Reset" on page 28 G1 Bidirectional Input Port B 3 - The TSPC860 TSPC860 monitors this input; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. Instruction Watchpoint 2 - This output reports the detection of an instruction watchpoint in the program flow executed by the core. Visible Instruction Queue Flush Status - The TSPC860 TSPC860 outputs VF2 with VF0/VF1 when instruction flow tracking is required. VFn reports the number of instructions flushed from the instruction queue in the core. IP_B4 LWP0 VF0 Hi-Z G2 Bidirectional Input Port B 4 - The TSPC860 TSPC860 monitors this input; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. Load/Store Watchpoint 0 - This output reports the detection of a data watchpoint in the program flow executed by the core. Visible Instruction Queue Flushes Status - The TSPC860 TSPC860 outputs VF0 with VF1/VF2 when instruction flow tracking is required. VFn reports the number of instructions flushed from the instruction queue in the core. 16 Description TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 1. Signal Descriptions (Continued) Name Reset Number Type Description IP_B5 LWP1 VF1 Hi-Z J4 Bidirectional Input Port B 5 - The TSPC860 TSPC860 monitors this input; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. Load/Store Watchpoint 1 - This output reports the detection of a data watchpoint in the program flow executed by the core. Visible Instruction Queue Flushes Status - The TSPC860 TSPC860 outputs VF1 with VF0 and VF2 when instruction flow tracking is required. VFn reports the number of instructions flushed from the instruction queue in the core. IP_B6 DSDI AT0 Hi-Z K3 Bidirectional Three-state Input Port B 6 - The TSPC860 TSPC860 senses this input and its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. Development Serial Data Input - Data input for the debug port interface. Address Type 0 - The TSPC860 TSPC860 drives this bidirectional three-state line when it initiates a transaction on the external bus. If high (1), the transaction is the CPM. If low (0), the transaction initiator is the CPU. This signal is not used for transactions initiated by external masters. IP_B7 PTR AT3 Hi-Z H1 Bidirectional Three-state Input Port B 7 - The TSPC860 TSPC860 monitors this input; its value and changes are reported in the PIPR and PSCR of the PCMCIA interface. Program Trace - To allow program flow tracking, the TSPC860 TSPC860 asserts this output to indicate an instruction fetch is taking place. Address Type 3 - The TSPC860 TSPC860 drives the bidirectional three-state signal when it starts a transaction on the external bus. When the core initiates a transfer, AT3 indicates whether it is a reservation for a data transfer or a program trace indication for an instruction fetch. This signal is not used for transactions initiated by external masters. OP(0-1) Low L4, L2 Output OP2 MODCK1 STS Hi-Z L1 Bidirectional Output Port 2 - This output is generated by the TSPC860 TSPC860 as a result of a write to the PGCRB register in the PCMCIA interface. Mode Clock 1 - Input sampled when PORESET is negated to configure PLL/clock mode. Special Transfer Start - The TSPC860 TSPC860 drives this output to indicate the start of an external bus transfer or of an internal transaction in show-cycle mode. OP3 MODCK2 DSDO Hi-Z M4 Bidirectional Output Port 3 - This output is generated by the TSPC860 TSPC860 as a result of a write to the PGCRB register in the PCMCIA interface. Mode Clock 2 - This input is sampled at the PORESET negation to configure the PLL/clock mode of operation. Development Serial Data Output - Output data from the debug port interface. Output Port 0-1 - The TSPC860 TSPC860 generates these outputs as a result of a write to the PGCRA register in the PCMCIA interface. 17 2129A­HIREL­08/02 Table 1. Signal Descriptions (Continued) Name Reset Number Type BADDR30 BADDR30 REG Hi-Z K4 Output Burst Address 30 - This output duplicates the value of A30 when the following is true: · An internal master in the TSPC860 TSPC860 initiates a transaction on the external bus. · An asynchronous external master initiates a transaction. · A synchronous external master initiates a single beat transaction. The memory controller uses BADDR30 BADDR30 to increment the address lines that connect to memory devices when a synchronous external master or an internal master initiates a burst transfer. Register - When an internal master initiates an access to a slave under control of the PCMCIA interface, this signal duplicates the value of TSIZ0/REG. When an external master initiates an access, REG is output by the PCMCIA interface (if it must handle the transfer) to indicate the space in the PCMCIA card being accessed. BADDR(2829) Hi-Z M3 M2 Output Burst Address - Outputs that duplicate A(28-29) values when one of the following occurs: · An internal master in the TSPC860 TSPC860 initiates a transaction on the external bus. · An asynchronous external master initiates a transaction. · A synchronous external master initiates a single beat transaction. The memory controller uses these signals to increment the address lines that connect to memory devices when a synchronous external or internal master starts a burst transfer. AS Hi-Z L3 Input Address Strobe - Input driven by an external asynchronous master to indicate a valid address on A(0-31). The TSPC860 TSPC860 memory controller synchronizes AS and controls the memory device addressed under its control. PA[15] RXD1 Hi-Z C18 Bidirectional General-Purpose I/O Port A Bit 15 - Bit 15 of the general-purpose I/O port A. RXD1 - Receive data input for SCC1. PA[14] TXD1 D17 Bidirectional (Optional: Open-drain) General-Purpose I/O Port A Bit 14 - Bit 14 of the general-purpose I/O port A. TXD1 - Transmit data output for SCC1. TXD1 has an open-drain capability. PA[13] RXD2 E17 Bidirectional General-Purpose I/O Port A Bit 13 - Bit 13 of the general-purpose I/O port A. RXD2 - Receive data input for SCC2. PA[12] TXD2 F17 Bidirectional (Optional: Open-drain) General-Purpose I/O Port A Bit 12 - Bit 12 of the general-purpose I/O port A. TXD2 - Transmit data output for SCC2. TXD2 has an open-drain capability. PA[11] L1TXDB G16 Bidirectional (Optional: Open-drain) General-Purpose I/O Port A Bit 11 - Bit 11 of the general-purpose I/O port A. L1TXDB - Transmit data output for the serial interface TDM port B. L1TXDB has an open-drain capability. PA[10] L1RXDB J17 Bidirectional General-Purpose I/O Port A Bit 10 - Bit 10 of the general-purpose I/O port A. L1RXDB - Receive data input for the serial interface TDM port B. 18 Description TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 1. Signal Descriptions (Continued) Name Number Type PA[9] L1TXDA K18 Bidirectional (Optional: Open-drain) General-Purpose I/O Port A Bit 11 - Bit 9 of the general-purpose I/O port A. L1TXDA - Transmit data output for the serial interface TDM port A. L1TXDA has an open-drain capability. PA[8] L1RXDA L17 Bidirectional General-Purpose I/O Port A Bit 8 - Bit 8 of the general-purpose I/O port A. L1RXDA - Receive data input for the serial interface TDM port A. PA[7] CLK1 TIN1 L1RCLKA BRGO1 M19 Bidirectional General-Purpose I/O Port A Bit 7 - Bit 7 of the general-purpose I/O port A. CLK1 - One of eight clock inputs that can be used to clock SCCs and SMCs. TIN1 - Timer 1 external clock. L1RCLKA - Receive clock for the serial interface TDM port A. BRGO1 - Output clock of BRG1. PA[6] CLK2 TOUT1 BRGCLK1 M17 Bidirectional General-Purpose I/O Port A Bit 6 - Bit 6 of the general-purpose I/O port A. CLK2 - One of eight clock inputs that can be used to clock SCCs and SMCs. TOUT1 - Timer 1 output. BRGCLK1 - One of two external clock inputs of the BRGs. PA[5] CLK3 TIN2 L1TCLKA BRGO2 N18 Bidirectional General-Purpose I/O Port A Bit 5 - Bit 5 of the general-purpose I/O port A. CLK3 - One of eight clock inputs that can be used to clock SCCs and SMCs. TIN2 - Timer 2 external clock input. L1TCLKA - Transmit clock for the serial interface TDM port A. BRGO2 - Output clock of BRG2. P19 Bidirectional General-Purpose I/O Port A Bit 4 - Bit 4 of the general-purpose I/O port A. CLK4 - One of eight clock inputs that can be used to clock SCCs and SMCs. TOUT2 - Timer 2 output. PA[3] CLK5 TIN3 BRGO3 P17 Bidirectional General-Purpose I/O Port A Bit 3 - Bit 3 of the general-purpose I/O port A. CLK5 - One of eight clock inputs that can be used to clock SCCs and SMCs. TIN3 - Timer 3 external clock input. BRGO3 - Output clock of BRG3. PA[2] CLK6 TOUT3 L1RCLKB BRGCLK2 R18 Bidirectional General-Purpose I/O Port A Bit 2 - Bit 2 of the general-purpose I/O port A. CLK6 - One of eight clock inputs that can be used to clock the SCCs and SMCs. TOUT3 - Timer 3 output. L1RCLKB - Receive clock for the serial interface TDM port B. BRGCLK2 - One of the two external clock inputs of the BRGs. PA[4] CLK4 TOUT2 Reset Hi-Z Description 19 2129A­HIREL­08/02 Table 1. Signal Descriptions (Continued) Name Number Type PA[1] CLK7 TIN4 BRGO4 T19 Bidirectional General-Purpose I/O Port A Bit 1 - Bit 1 of the general-purpose I/O port A. CLK7 - One of eight clock inputs that can be used to clock SCCs and SMCs. TIN4 - Timer 4 external clock input. BRGO4 - BRG4 output clock. PA[0] CLK8 TOUT4 L1TCLKB U19 Bidirectional General-Purpose I/O Port A Bit 0 - Bit 0 of the general-purpose I/O port A. CLK8 - One of eight clock inputs that can be used to clock SCCs and SMCs. TOUT4 - Timer 4 output. L1TCLKB - Transmit clock for the serial interface TDM port B. PB[31] SPISEL REJECT1 C17 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 31 - Bit 31 of the general-purpose I/O port B. SPISEL - SPI slave select input. REJECT1 - SCC1 CAM interface reject pin. PB[30] SPICLK RSTRT2 C19 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 30 - Bit 30 of the general-purpose I/O port B. SPICLK - SPI output clock when it is configured as a master or SPI input clock when it is configured as a slave. RSTRT2 - SCC2 serial CAM interface output signal that marks the start of a frame. PB[29] SPIMOSI E16 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 29 - Bit 29 of the general-purpose I/O port B. SPIMOSI - SPI output data when it is configured as a master or SPI input data when it is configured as a slave. PB[28] SPIMISO BRGO4 D19 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 28 - Bit 29 of the general-purpose I/O port B. SPIMISO - SPI input data when the TSPC860 TSPC860 is a master; SPI output data when it is a slave. BRGO4 - BRG4 output clock. E19 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 27 - Bit 27 of the general-purpose I/O port B. I2CSDA - TWI serial data pin. Bidirectional; should be configured as an open-drain output. BRGO1 - BRG1 output clock. PB[26] I2CSCL BRGO2 F19 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 26 - Bit 26 of the general-purpose I/O port B. I2CSCL - TWI serial clock pin. Bidirectional; should be configured as an open-drain output. BRGO2 - BRG2 output clock. PB[25] SMTXD1 J16 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 25 - Bit 25 of the general-purpose I/O port B. SMTXD1 - SMC1 transmit data output. PB[24] SMRXD1 J18 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 24 - Bit 24 of the general-purpose I/O port B. SMRXD1 - SMC1 receive data input. PB[27] I2CSDA BRGO1 20 Reset Hi-Z Description TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 1. Signal Descriptions (Continued) Name Number Type PB[23] SMSYN1 SDACK1 K17 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 23 - Bit 23 of the general-purpose I/O port B. SMSYN1 - SMC1 external sync input. SDACK1 - SDMA acknowledge 1 output that is used as a peripheral interface signal for IDMA emulation, or as a CAM interface signal for Ethernet. PB[22] SMSYN2 SDACK2 L19 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 22 - Bit 22 of the general-purpose I/O port B. SMSYN2 - SMC2 external sync input. SDACK2 - SDMA acknowledge 2 output that is used as a peripheral interface signal for IDMA emulation, or as a CAM interface signal for Ethernet. PB[21] SMTXD2 L1CLKOB K16 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 21 - Bit 21 of the general-purpose I/O port B. SMTXD2 - SMC2 transmit data output. L1CLKOB - Clock output from the serial interface TDM port B. PB[20] SMRXD2 L1CLKOA L16 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 20 - Bit 20 of the general-purpose I/O port B. SMRXD2 - SMC2 receive data input. L1CLKOA - Clock output from the serial interface TDM port A. PB[19] RTS1 L1ST1 N19 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 19 - Bit 19 of the general-purpose I/O port B. RTS1 - Request to send modem line for SCC1. L1ST1 - One of four output strobes that can be generated by the serial interface. PB[18] RTS2 L1ST2 N17 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 18 - Bit 18 of the general-purpose I/O port B. RTS2 - Request to send modem line for SCC2. L1ST2 - One of four output strobes that can be generated by the serial interface. P18 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 17 - Bit 17 of the general-purpose I/O port B. L1RQB - D - channel request signal for the serial interface TDM port B. L1ST3 - One of four output strobes that can be generated by the serial interface. PB[16] L1RQA L1ST4 N16 Bidirectional (Optional: Open-drain) General-Purpose I/O Port B Bit 16 - Bit 16 of the general-purpose I/O port B. L1RQA - D-channel request signal for the serial interface TDM port A. L1ST4 - One of four output strobes that can be generated by the serial interface. PB[15] BRGO3 R17 Bidirectional General-Purpose I/O Port B Bit 15 - Bit 15 of the general-purpose I/O port B. BRGO3 - BRG3 output clock. PB[17] L1RQB L1ST3 Reset Hi-Z Description 21 2129A­HIREL­08/02 Table 1. Signal Descriptions (Continued) Name Number Type PB[14] RSTRT1 U18 Bidirectional General-Purpose I/O Port B Bit 14 - Bit 14 of the general-purpose I/O port B. RSTRT1 - SCC1 serial CAM interface outputs that marks the start of a frame. PC[15] DREQ0 RTS1 L1ST1 D16 Bidirectional General-Purpose I/O Port C Bit 15 - Bit 15 of the general-purpose I/O port C. DREQ0 - IDMA channel 0 request input. RTS1 - Request to send modem line for SCC1. L1ST1 - One of four output strobes that can be generated by the serial interface. PC[14] DREQ1 RTS2 L1ST2 D18 Bidirectional General-Purpose I/O Port C Bit 14 - Bit 14 of the general-purpose I/O port C. DREQ1 - IDMA channel 1 request input. RTS2 - Request to send modem line for SCC2. L1ST2 - One of four output strobes that can be generated by the serial interface. PC[13] L1RQB L1ST3 E18 Bidirectional General-Purpose I/O Port C Bit 13 - Bit 13 of the general-purpose I/O port C. L1RQB - D-channel request signal for the serial interface TDM port B. L1ST3 - One of four output strobes that can be generated by the serial interface. PC[12] L1RQA L1ST4 F18 Bidirectional General-Purpose I/O Port C Bit 12 - Bit 12 of the general-purpose I/O port C. L1RQA - D-channel request signal for the serial interface TDM port A. L1ST4 - One of four output strobes that can be generated by the serial interface. PC[11] CTS1 J19 Bidirectional General-Purpose I/O Port C Bit 11 - Bit 11 of the general-purpose I/O port C. CTS1 - Clear to send modem line for SCC1. K19 Bidirectional General-Purpose I/O Port C Bit 10 - Bit 10 of the general-purpose I/O port C. CD1 - Carrier detect modem line for SCC1. TGATE1 - Timer 1/timer 2 gate signal. PC[9] CTS2 L18 Bidirectional General-Purpose I/O Port C Bit 9 - Bit 9 of the general-purpose I/O port C. CTS2 - Clear to send modem line for SCC2. PC[8] CD2 TGATE2 M18 Bidirectional General-Purpose I/O Port C Bit 8 - Bit 8 of the general-purpose I/O port C. CD2 - Carrier detect modem line for SCC2. TGATE2 - Timer 3/timer 4 gate signal. PC[10] CD1 TGATE1 22 Reset Hi-Z Description TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 1. Signal Descriptions (Continued) Name Number Type PC[7] CTS3 L1TSYNCB SDACK2 M16 Bidirectional General-Purpose I/O Port C Bit 7 - Bit 7 of the general-purpose I/O port C. CTS3 - Clear to send modem line for SCC3. L1TSYNCB - Transmit sync input for the serial interface TDM port B. SDACK2 - SDMA acknowledge 2 output that is used as a peripheral interface signal for IDMA emulation or as a CAM interface signal for Ethernet. PC[6] CD3 L1RSYNCB R19 Bidirectional General-Purpose I/O Port C Bit 6 - Bit 6 of the general-purpose I/O port C. CD3 - Carrier detect modem line for SCC3. L1RSYNCB - Receive sync input for the serial interface TDM port B. PC[5] CTS4 L1TSYNCA SDACK1 T18 Bidirectional General-Purpose I/O Port C Bit 5 - Bit 5 of the general-purpose I/O port C. CTS4 - Clear to send modem line for SCC4. L1TSYNCA - Transmit sync input for the serial interface TDM port A. SDACK1 - SDMA acknowledge 1output that is used as a peripheral interface signal for IDMA emulation or as a CAM interface signal for Ethernet. PC[4] CD4 L1RSYNCA T17 Bidirectional General-Purpose I/O Port C Bit 4 - Bit 4 of the general-purpose I/O port C. CD4 - Carrier detect modem line for SCC4. L1RSYNCA - Receive sync input for the serial interface TDM port A. PD[15] L1TSYNCA U17 Bidirectional General-Purpose I/O Port D Bit 15 - Bit 15 of the general-purpose I/O port D. L1TSYNCA - Input transmit data sync signal to the TDM channel A. PD[14] L1RSYNCA V19 Bidirectional General-Purpose I/O Port D Bit 14 - Bit 14 of the general-purpose I/O port D. L1RSYNCA - Input receive data sync signal to the TDM channel A. PD[13] L1TSYNCB V18 Bidirectional General-Purpose I/O Port D Bit 13 - Bit 13 of the general-purpose I/O port D. L1TSYNCB - Input transmit data sync signal to the TDM channel B. R16 Bidirectional General-Purpose I/O Port D Bit 12 - Bit 12 of the general-purpose I/O port D. L1RSYNCB - Input receive data sync signal to the TDM channel B. PD[11] RXD3 T16 Bidirectional General-Purpose I/O Port D Bit 11 - Bit 11 of the general-purpose I/O port D. RXD3 - Receive data for serial channel 3. PD[10] TXD3 W18 Bidirectional General-Purpose I/O Port D Bit 10 - Bit 10 of the general-purpose I/O port D. TXD3 - Transmit data for serial channel 3. PD[9] RXD4 V17 Bidirectional General-Purpose I/O Port D Bit 9 - Bit 9 of the general-purpose I/O port D. RXD4 - Receive data for serial channel 4. PD[12] L1RSYNCB Reset Hi-Z Description 23 2129A­HIREL­08/02 Table 1. Signal Descriptions (Continued) Name Reset Number Type Description PD[8] TXD4 W17 Bidirectional General-Purpose I/O Port D Bit 8 - Bit 8 of the general-purpose I/O port D. TXD4 - Transmit data for serial channel 4. PD[7] RTS3 T15 Bidirectional General-Purpose I/O Port D Bit 7 - Bit 7 of the general-purpose I/O port D. RTS3 - Active low request to send output indicates that SCC3 is ready to transmit data. PD[6] RTS4 V16 Bidirectional General-Purpose I/O Port D Bit 6 - Bit 6 of the general-purpose I/O port D. RTS4 - Active low request to send output indicates that SCC4 is ready to transmit data. PD[5] REJECT2 U15 Bidirectional General-Purpose I/O Port D Bit 5 - Bit 5 of the general-purpose I/O port D. REJECT2 - This input to SCC2 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match. PD[4] REJECT3 U16 Bidirectional General-Purpose I/O Port D Bit 4 - Bit 4 of the general-purpose I/O port D. REJECT3 - This input to SCC3 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match. PD[3] REJECT4 W16 Bidirectional General-Purpose I/O Port D Bit 3 - Bit 3 of the general-purpose I/O port D. REJECT4 - This input to SCC4 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match. TCK DSCK H16 Input Provides clock to scan chain logic or for the development port logic. Should be tied to Vcc if JTAG or development port are not used. TMS Pulled up G18 Input Controls the scan chain test mode operations. Should be tied to power through a pull-up resistor if unused. TDI DSDI Pulled up (HiZ on rev 0 to rev A.3) H17 Input Input serial data for either the scan chain logic or the development port and determines the operating mode of the development port at reset. TDO DSDO 24 Hi-Z (Pulled up on rev 0 to rev A.3) Low G17 Output Output serial data for either the scan chain logic or for the development port. TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 1. Signal Descriptions (Continued) Name Reset Number Type Description TRST Pulled up G19 Input Reset for the scan chain logic. If JTAG is not used, connect TRST to ground. If JTAG is used, connect TRST to PORESET. In case PORESET logic is powered by the keep-alive power supply (KAPWR), connect TRST to PORESET through a diode (anode connected to TRST and cathode to PORESET). SPARE[1-4] Hi-Z B7, H18, V15, H4 No-connect See Figure 4 Power Power Supply Active Pull-up Buffers Spare signals - Not used on current chip revisions. Leave unconnected. VDDL - Power supply of the internal logic. VDDH - Power supply of the I/O buffers and certain parts of the clock control. VDDSYN - Power supply of the PLL circuitry. KAPWR - Power supply of the internal OSCM, RTC, PIT, DEC, and TB. VSS - Ground for circuits, except for the PLL circuitry. VSSSYN, VSSSYN1 - Ground for the PLL circuitry. Active pull-up buffers are a special variety of bidirectional three-state buffer with the following properties: · When enabled as an output and driving low, they behave as normal output drivers (that is, the pin is constantly driven low). · When enabled as an output and driving high, drive high until an internal detection circuit determines that the output has reached the logic high threshold and then stop driving (that is, the pin switches to high-impedance). · When disabled as an output or functioning as an input, it should not be driven. Due to the behavior of the buffer when being driven high, a pull-up resistor is required externally to function as a `bus keep' for these shared signals in periods when no drivers are active and to keep the buffer from oscillating when the buffer is driving high, because if the voltage ever dips below the logic high threshold while the buffer is enabled as an output, the buffer will reactivate. Further, external logic must not attempt to drive these signals low while active pull-up buffers are enabled as outputs, because the buffers will reactivate and drive high, resulting in a buffer fight and possible damage to the TSPC860 TSPC860, to the system, or to both. Figure 6 compares three-state buffers and active pull-up buffers graphically in general terms. It makes no implication as to which edges trigger which events for any particular signal. 25 2129A­HIREL­08/02 Figure 6. Three-State Buffers and Active Pull-Up Buffers 1 Drive high on one edge 2 Switch to Hi-Z on later edge 3 Pull-up resistor maintains logic high state 3 Three-state buffer 1 2 3 5 Active pull-up buffer 1 2 Note: 1 Drive high on one edge 2 Switch to Hi-Z when threshold voltage (Voh+margin) is reached 3 Pull-up resistor maintains logic high state 4 Disable buffer as output 5 Pull-up resistor maintains logic high state; other driver can drive signal 4 Events 1 and 4 can be in quick succession. Table 2 summarizes when active pull-up drivers are enabled as outputs. Table 2. Active Pull-Up Resistors Enabled as Outputs Signal Description TS, BB When the TSPC860 TSPC860 is the external bus master throughout the entire bus cycle. BI When the TSPC860 TSPC860's memory controller responds to the access on the external bus, throughout the entire bus cycle. TA When the TSPC860 TSPC860's memory controller responds to the access on the external bus, then: · For chip-selects controlled by the GPCM set for external TA, the TSPC860 TSPC860's TA buffer is not enabled as an output. · For chip-selects controlled by the GPCM set to terminate in n wait-states, TA is enabled as an output on cycle (n-1) and driven high, then is driven low on cycle n, terminating the bus transaction. External logic can drive TA at any point before this, thus terminating the cycle early. [For example, assume the GPCM is programmed to drive TA after 15 cycles. If external logic drives TA before 14 clocks have elapsed then the TA will be accepted by the TSPC860 TSPC860 as a cycle termination.] · For chip-selects controlled by the UPM, the TA buffer is enabled as an output throughout the entire bus cycle. The purpose of active pull-up buffers is to allow access to zero wait-state logic that drives a shared signal on the clock cycle immediately following a cycle in which the signal is driven by the TSPC860 TSPC860. In other words, it eliminates the need for a bus turnaround cycle. Internal Pull-up and Pull- The TMS and TRST pins have internal pull-up resistors. TSPC860 TSPC860 devices from Rev 0 to Rev A.3 (masks xE64C and xF84C) have an internal pull-up resistor on TCK/DSCK down Resistors but no internal pull-up resistor on TDI/DSDI. This was corrected on Rev B and later; on these chips, the internal pull-up resistor was removed from TCK/DSCK and an internal pull-up resistor was added to TDI/DSDI. If RSTCONF is pulled down, during hardware reset (initiated by HRESET or PORESET), the data bus D[0-31] is pulled down with internal pull-down resistors. These internal pull-down resistors are to provide a logic-zero default for these pins when programming the hard reset configuration word. These internal pull-down resistors are disconnected after HRESET is negated. No other pins have internal pull-ups or pull-downs. 26 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Resistance values for internal pull-up and pull-down resistors are not specified because their values may vary due to process variations and shrinks in die size, and they are not tested. Typical values are on the order of 5 K but can vary by approximately a factor of 2. Recommended Basic Pin Connections Reset Configuration Some external pin configuration is determined at reset by the hard reset configuration word. Thus, some decisions as to system configuration (for example, location of BDM pins) should be made before required application of pull-up and pull-down resistors can be determined. RSTCONF should be grounded if the hard reset configuration word is used to configure the TSPC860 TSPC860 or should be connected to VCC if the default configuration is used. Pull-up resistors may not be used on D[0-31] to set the hard reset configuration word, as the values of the internal pull-down resistors are not specified or guaranteed. To change a data bus signal from its default logic low state during reset, actively drive that signal high. MODCK[1-2] must be used to determine the default clocking mode for the TSPC860 TSPC860. After hardware reset, the MODCK[1-2] pins change function and become outputs. Thus, if these alternate functions are also desired, then the MODCK[1-2] configuration should be set with three-state drivers that turn off after HRESET is negated; however, if MODCK[1-2] pins' alternate output functions are not used in the system, they can be configured with pull-up and pull-down resistors. Signals with open-drain buffers and active pull-up buffers (HRESET, SRESET, TEA, TS, TA, BI, and BB) must have external pull-up resistors. These signals include the following: Some other input signals do not absolutely require a pull-up resistor, as they may be actively driven by external logic. However, if they are not used externally, or if the external logic connected to them is not always actively driving, they may need external pullup resistors to hold them negated. These signals include the following: · PORESET · AS · CR/IRQ3 · KR/RETRY/IRQ4/SPKROUT (if configured as KR/RETRY or IRQ4) · Any IRQx (if configured as IRQx) · BR (if the TSPC860 TSPC860's internal bus arbiter is used) · BG (if an external bus arbiter is used) 27 2129A­HIREL­08/02 JTAG and Debug Ports TCK/DSCK or ALE_B/DSCK/AT1 (depending on the configuration of the DSCK function) should be connected to ground through a pull-down resistor to disable Debug Mode as a default. When required, a debug mode controller tool externally drives this signal high actively to put the TSPC860 TSPC860 into debug mode. Two pins need special attention, depending on the version of TSPC860 TSPC860 used. · For TSPC860 TSPC860 rev B and later, TDI/DSDI should be pulled up to VCC to keep it from oscillating when unused. · For TSPC860 TSPC860 rev A.3 and earlier, TCK/DSCK should be connected to ground if it is configured for its DSCK function, as stated above. However, for these versions of the TSPC860 TSPC860, the pull-down resistor must be strong (for example, 1 k to overcome the internal pull-up resistor. To allow application of any version of processor, perform both of the above actions. Unused Inputs In general, pull-up resistors should be used on any unused inputs to keep them from oscillating. For example, if PCMCIA is not used, the PCMCIA input pins (WAIT_A, WAIT_B, IP_A[0-8], IP_B[0-8]) should have external pull-up resistors. However, unused pins of port A, B, C, or D can be configured as outputs, and, if they are configured as outputs they do not require external terminations. Unused Outputs Unused outputs can be left unterminated. Signal States During Hardware Reset During hardware reset (HRESET or PORESET), the signals of the TSPC860 TSPC860 behave as follows: · The bus signals are high-impedance. · The port I/O signals are configured as inputs, and are therefore high-impedance. · The memory controller signals are driven to their inactive state. However, some signal functions are determined by the reset configuration. When HRESET is asserted, these signals immediately begin functioning as determined by the reset configuration and are either high-impedance or are drive to their inactive state accordingly. The behavior of these signals is shown in Table 12. Table 3. Signal States during Hardware Reset Signal Behavior BDIP/GPL_B5 BDIP: high impedance GPL_B5: high RSV/IRQ2 RSV: high IRQ2: high impedance KR/RETRY/IRQ4/SPKROUT FRZ/IRQ6 ALE_B/DSCK/AT1 IP_B[0-1]/IWP[0-1]/VFLS[0-1] 28 KR/RETRY/IRQ4: high impedance SPKROUT: low FRZ: low IRQ6: high impedance ALE_B: low DSCK/AT1: high impedance IP_B[0-1]: high impedance IWP[0-1]: high VFLS[0-1]: low TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 3. Signal States during Hardware Reset (Continued) Signal Behavior IP_B3/IWP2/VF2 IP_B3: high impedance IWP2: high VF2: low IP_B4/LWP0/VF0 IP_B4: high impedance LWP0: high VF0: low IP_B5/LWP1/VF1 IP_B5: high impedance LWP1: high; VF1: low Scope This drawing describes the specific requirements for the microcontroller TSPC860 TSPC860, in compliance with MIL-STD-883 MIL-STD-883 class Q or Atmel standard screening. Applicable Documents 1. MIL-STD-883 MIL-STD-883: Test methods and procedures for electronics. 2. MIL-PRF-38535 MIL-PRF-38535 appendix A: General specifications for microcircuits. Requirements General The microcircuits are in accordance with the applicable documents and as specified herein. Design and Construction Terminal Connections The terminal connections shall be as shown in the general description. Lead Material and Finish Lead material and finish shall be as specified on page 87. Package The macrocircuits are packaged in 357-lead Plastic Ball Grid Array (BGA) packages. The precise case outlines are described at the end of the specification. 29 2129A­HIREL­08/02 Absolute Maximum Ratings Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Table 4. Absolute Maximum Rating for the TSPC860 TSPC860 Parameter Symbol Min Max Unit I/O Supply Voltage VDDH -0.3 4.0 V Internal Supply Voltage VDDL -0.3 4.0 V Backup Supply Voltage KAPWR -0.3 4.0 V PLL Supply Voltage VDDSYN -0.3 4.0 V VIN -0.3 5.8 V TSTG -55 +150 °C Input Voltage Storage Temperature Range Table 5. Thermal Characteristics Rating Environnement Junction to Ambient (1) Natural Convection Single layer board (1s) Four layer board (2s2p) Air Flow (200 ft/min) Symbol RJA (2) RJMA (3) Rev A Rev B, C, D Unit 31 40 °C/W 20 25 Junction to Board Junction to Case Junction to Package Top(6) Air Flow (20 ft/min) Notes: 30 32 RJMA 16 21 8 15 RJC Natural Convection 26 RJB (5) RJMA Four layer board (2s2p) (4) Single layer board (1s) 5 7 JT 1 2 2 3 1. Junction temperature is a function on on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 G38-87 and JEDEC JESD51-2 JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8 JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature. For exposed pad packages where the pad would be expected to be soldered, junction to case thermal resistance is a simlated value from the junction to the exposed pas without contact resistance. 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2 JESD51-2. TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 6. Power Dissipation (PD)(3) Frequency Typical(1) Maximum(2) Unit 25 450 550 mW 40 700 850 mW 50 870 1050 mW 33 375 TBD mW 50 575 TBD mW 66 750 TBD mW D.3 and D.4 (1:1 Mode) 50 656 735 mW 66 TBD TBD mW D.3 and D.4 (2:1 Mode) 66 722 762 mW 80 851 909 mW Die Revision A.3 and Previous B.1 and C.1 Note: 1. Typical power dissipation is measured at 3.3V. 2. Maximum power dissipation is measured at 3.65V. 3. Values in Table 6 represent VDDL-based power dissipation and do not include I/O power dissipation over VDDH. I/O power dissipation varies widely by application due to buffer current, depending on external circuitry. 31 2129A­HIREL­08/02 Electrical Characteristics General Requirements All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below. DC Electrical Specifications Table 7. DC Electrical Specification VCC = 3.3 ± 5% VDC, GND = 0 VDC, -55°C Tc 125°C Characteristic Symbol Min Max Unit Operating Voltage VDDH, VDDL, KAPWR, VDDSYN 3.135 3.465 V KAPWR (powerdown mode) 2.0 3.6 V KAPWR (all other operating modes) VDDH - 0.4 VDDH V Input High Voltage (all inputs except EXTAL and EXTCLK) VIH 2.0 5.5 V Input Low Voltage VIL GND 0.8 V VIHC 0.7 * (VCC) VCC + 0.3 V Input Leakage Current, VIN = 5.5V (Except TMS, TRST, DSCK and DSDI pins) IIN - 100 µA Input Leakage Current, VIN = 3.6V (Except TMS, TRST, DSCK and DSDI pins) IIN - 10 µA Input Leakage Current, VIN = 0V (Except TMS, TRST, DSCK and DSDI pins) IIN - 10 µA VOH 2.4 - V EXTAL, EXTCLK Input High Voltage Output High Voltage, IOH = -2.0 mA, VDDH = 3.0V Except XTAL, XFC, and Open drain pins 32 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 7. DC Electrical Specification (Continued) VCC = 3.3 ± 5% VDC, GND = 0 VDC, -55°C Tc 125°C Characteristic Symbol IOL = 2.0 mA V Cin - 20 pF TXD1/PA14 TXD1/PA14, TXD2/PA12 TXD2/PA12 IOL = 8.9 mA 0.5 BDIP/GPL_B(5), BR, BG, FRZ/IRQ6, CS(0:5), CS(6)/CE(1)_B, CS(7)/CE(2)_B, WE0/BS_B0/IORD, WE1/BS_B1/IOWR, WE2/BS_B2/PCOE, WE3/BS_B3/PCWE, BS_A(0:3), GPL_A0/GPL_B0, OE/GPL_A1/GPL_B1, GPL_A(2:3)/GPL_B(2:3)/CS(2:3), UPWAITA/GPL_A4, UPWAITB/GPL_B4, GPL_A5, ALE_A, CE1_A, CE2_A, ALE_B/DSCK/AT1, OP(0:1), OP2/MODCK1/STS, OP3/MODCK2/DSDO, BADDR(28:30) IOL = 7.0 mA - A(0:31), TSIZ0/REG, TSIZ1, D(0:31), DP(0:3)/IRQ(3:6), RD/WR, BURST, RSV/IRQ2, IP_B(0:1)/IWP(0:1)/VFLS(0:1), IP_B2/IOIS16 B2/IOIS16_B/AT2, IP_B3/IWP2/VF2, IP_B4/LWP0/VF0, IP_B5/LWP1/VF1, IP_B6/DSDI/AT0, IP_B7/PTR/AT3, RXD1 /PA15 /PA15, RXD2/PA13 RXD2/PA13, L1TXDB/PA11 L1TXDB/PA11, L1RXDB/PA10 L1RXDB/PA10, L1TXDA/PA9, L1RXDA/PA8, TIN1/L1RCLKA/BRGO1/CLK1/PA7, BRGCLK1/TOUT1/CLK2/PA6, TIN2/L1TCLKA/BRGO2/CLK3/PA5, TOUT2/CLK4/PA4, TIN3/BRGO3/CLK5/PA3, BRGCLK2/L1RCLKB/TOUT3/CLK6/PA2, TIN4/BRGO4/CLK7/PA1, L1TCLKB/TOUT4/CLK8/PA0, RRJCT1/SPISEL/PB31 RRJCT1/SPISEL/PB31, SPICLK/PB30 SPICLK/PB30, SPIMOSI/PB29 SPIMOSI/PB29, BRGO4/SPIMISO/PB28 BRGO4/SPIMISO/PB28, BRGO1/I2CSDA/PB27 BRGO1/I2CSDA/PB27, BRGO2/I2CSCL/PB26 BRGO2/I2CSCL/PB26, SMTXD1/PB25 SMTXD1/PB25, SMRXD1/PB24 SMRXD1/PB24, SMSYN1/sdack1/PB23, SMSYN2/sdack2/PB22, SMTXD2/L1CLKOB/PB21 SMTXD2/L1CLKOB/PB21, SMRXD2/L1CLKOA/PB20 SMRXD2/L1CLKOA/PB20, L1ST1/RTS1/PB19 L1ST1/RTS1/PB19, L1ST2/RTS2/PB18 L1ST2/RTS2/PB18, L1ST3/L1RQB/PB17 L1ST3/L1RQB/PB17, L1ST4/L1RQA/PB16 L1ST4/L1RQA/PB16, BRGO3/PB15 BRGO3/PB15, RSTRT1/PB14 RSTRT1/PB14, L1ST1/RTS1/DREQ0/PC15 L1ST1/RTS1/DREQ0/PC15, L1ST2/RTS2/DREQ1/PC14 L1ST2/RTS2/DREQ1/PC14, L1ST3/L1RQB/PC13 L1ST3/L1RQB/PC13, L1ST4/L1RQA/PC12 L1ST4/L1RQA/PC12, CTS1/PC11 CTS1/PC11, TGATE1/CD1/PC10 TGATE1/CD1/PC10, CTS2/PC9, TGATE2/CD2/PC8, CTS3/SDACK2/L1TSYNCB/PC7, CD3/L1RSYNCB/PC6, CTS4/SDACK1/L1TSYNCA/PC5, CD4/L1RSYNCA/PC4, PD15/L1TSYNCA PD15/L1TSYNCA, PD14/L1RSYNCA PD14/L1RSYNCA, PD13/L1TSYNCB PD13/L1TSYNCB, PD12/L1RSYNCB PD12/L1RSYNCB, PD11/RXD3 PD11/RXD3, PD10/TXD3 PD10/TXD3, PD9/RXD4, PD8/TXD4, PD5/RRJCT2, PD6/RTS4, PD7/RTS3, PD4/RRJCT3, PD3 IOL = 5.3 mA Unit CLKOUT IOL = 3.2 mA Max VOL Output Low Voltage Min TS, TA, TEA, BI, BB, HRESET, SRESET Input Capacitance 33 2129A­HIREL­08/02 AC Electrical Specifications Control Timing Figure 7. AC Electrical Specifications Control Timing Diagram 2.0V 2.0V 0.8V 0.8V CLKOUT A B 2.0V OUTPUTS 2.0V 0.8V 0.8V A B 2.0V 2.0V 0.8V OUTPUTS 0.8V C D 2.0V 2.0V 0.8V 0.8V INPUTS C D 2.0V 2.0V 0.8V INPUTS 0.8V A. Maxi mu m Output Delay Speci ficat ion C. Minim um input Setup Tim e Specification B. Minim um Out put Hold Tim e D. Minim um input Hold Tim e Specification The timing for the TSPC860 TSPC860 bus shown assumes a 50 pF load for maximum delays and a 0 pF load for minimum delays. For loads other than 50 pF, maximum delays can be derated by 1 ns per 10 pF. 34 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 8. Bus Operation Timings 33 MHz 40 MHz 50 MHz 66 MHz Unit Num Characteristic Min Max Min Max Min Max Min Max B1 CLKOUT Period 30.30 30.30 25 30.30 20 30.30 15.15 30.30 ns B1a EXTCLK to CLKOUT Phase Skew (EXTCLK > 15 MHz and MF 2) -0.90 0.90 -0.90 0.90 -0.90 0.90 -0.90 0.90 ns B1b EXTCLK to CLKOUT Phase Skew (EXTCLK > 10 MHz and MF < 10) -2.30 2.30 -2.30 2.30 -2.30 2.30 -2.30 2.30 ns B1c CLKOUT Phase Jitter (EXTCLK > 15 MHz and MF 2)(1) -0.60 0.60 -0.60 0.60 -0.60 0.60 -0.60 0.60 ns B1d CLKOUT Phase Jitter -2 2 -2 2 -2 2 -2 2 ns B1e CLKOUT Frequency Jitter (MF < 10) ­ 0.50 ­ 0.50 ­ 0.50 ­ 0.50 % B1f CLKOUT Frequency Jitter (10 < MF < 500) ­ 2 ­ 2 ­ 2 ­ 2 % B1g CLKOUT Frequency Jitter (MF > 500) ­ 3 ­ 3 ­ 3 ­ 3 % ­ 0.50 ­ 0.50 ­ 0.50 ­ 0.50 % (2) B1h Frequency Jitter on EXTCLK B2 CLKOUT pulse width low 12.12 ­ 10 ­ 8 ­ 6.06 ­ ns B3 CLKOUT width high 12.12 ­ 10 ­ 8 ­ 6.06 ­ ns B4 CLKOUT rise time(3) ­ 4 ­ 4 ­ 4 ­ 4 ns ­ 4 ­ 4 ­ 4 ­ 4 ns (3) B5 CLKOUT fall time B7 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) Invalid 7.58 ­ 6.25 ­ 5 ­ 3.80 ­ ns B7a CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3), BDIP, PTR Invalid 7.58 ­ 6.25 ­ 5 ­ 3.80 ­ ns B7b CLKOUT to BR, BG, FRZ, VFLS(0:1), VF(0:2), IWP(0:2), LWP(0:1), STS Invalid(4) 7.58 ­ 6.25 ­ 5 ­ 3.80 ­ ns B8 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3) valid 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns B8a CLKOUT to TSIZ(0:1), REG, RSV, AT(0:3), BDIP, PTR valid 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns B8b CLKOUT to BR, BG, VFLS(0:1), VF(0:2), IWP(0:2), FRZ, LWP(0:1), STS valid(4) 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns B9 CLKOUT to A(0:31), BADDR(28:30), RD/WR, BURST, D(0:31), DP(0:3), TSIZ(0:1), REG, RSV, AT(0:3), PTR High Z 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns B11 CLKOUT to TS, BB assertion 7.58 13.58 6.25 12.25 5 11 3.80 11.29 ns B11a CLKOUT to TA, BI assertion (when driven by the Memory Controller or PCMCIA I/F) 2.50 9.25 2.50 9.25 2.50 9.25 2.50 9.75 ns B12 CLKOUT to TS, BB negation 7.58 14.33 6.25 13 5 11.75 3.80 8.54 ns B12a CLKOUT to TA, BI negation (when driven by the Memory Controller or PCMCIA interface) 2.50 11 2.50 11 2.50 11 2.50 9 ns B13 CLKOUT to TS, BB High Z 7.58 21.58 6.25 20.25 5 19 3.80 14.04 ns 35 2129A­HIREL­08/02 Table 8. Bus Operation Timings (Continued) 33 MHz 40 MHz 50 MHz 66 MHz Unit Num Characteristic Min Max Min Max Min Max Min Max B13a CLKOUT to TA, BI High Z (when driven by the Memory Controller or PCMCIA interface) 2.50 15 2.50 15 2.50 15 2.50 15 ns B14 CLKOUT to TEA assertion 2.50 10 2.50 10 2.50 10 2.50 9 ns B15 CLKOUT to TEA High Z 2.50 15 2.50 15 2.50 15 2.50 15 ns B16 TA, BI valid to CLKOUT (Setup Time) 9.75 ­ 9.75 ­ 9.75 ­ 6 ­ ns B16a TEA, KR, RETRY, CR valid to CLKOUT (Setup Time) 10 ­ 10 ­ 10 ­ 4.50 ­ ns B16b BB, BG, BR, valid to CLKOUT (setup time)(5) 8.50 ­ 8.50 ­ 8.50 ­ 4 ­ ns B17 CLKOUT to TA, TEA, BI, BB, BG, BR valid (Hold Time) 1 ­ 1 ­ 1 ­ 2 ­ ns B17a CLKOUT to KR, RETRY, CR valid (Hold Time) 2 ­ 2 ­ 2 ­ 2 ­ ns B18 D(0:31), DP(0:3) valid to CLKOUT Rising Edge (Setup Time)(6) 6 ­ 6 ­ 6 ­ 6 ­ ns B19 CLKOUT Rising Edge to D(0:31), DP(0:3) valid (Hold Time)(6) 1 ­ 1 ­ 1 ­ 2 ­ ns B20 D(0:31), DP(0:3) valid to CLKOUT Falling Edge (Setup Time)(7) 4 ­ 4 ­ 4 ­ 4 ­ ns B21 CLKOUT Falling Edge to D(0:31), DP(0:3) valid (Hold Time)(7) 2 ­ 2 ­ 2 ­ 2 ­ ns B22 CLKOUT Rising Edge to CS asserted -GPCM- ACS = 00 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns B22a CLKOUT Falling Edge to CS asserted -GPCM- ACS = 11, TRLX = 0, EBDF = 0 ­ 8 ­ 8 ­ 8 ­ 8 ns B22b CLKOUT Falling Edge to CS asserted -GPCM- ACS = 11, TRLX = 0, EBDF = 0 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns B22c CLKOUT Falling Edge to CS asserted -GPCM- ACS = 11, TRLX = 0, EBDF = 1 10.86 17.99 8.88 16 7 14.13 5.18 12.31 ns B23 CLKOUT Rising Edge to CS negated -GPCM- Read Access, -GPCM- write access, ACS = `00', TRLX = `0' & CSNT = `0' 2 8 2 8 2 8 2 2 ns B24 A(0:31) and BADDR(28:30) to CS asserted -GPCM- ACS = 10, TRLX = 0 5.58 ­ 4.25 ­ 3 ­ 1.79 ­ ns B24a A(0:31) and BADDR(28:30) to CS asserted -GPCM- ACS = 11, TRLX = 0 13.15 ­ 10.5 ­ 8 ­ 5.58 ­ ns B25 CLKOUT Rising Edge to OE, WE(0:3) asserted ­ 9 ­ 9 ­ 9 ­ 9 ns B26 CLKOUT Rising Edge to OE negated 2 9 2 9 2 9 2 9 ns B27 A(0:31) and BADDR(28:30) to CS asserted -GPCM- ACS = 10, TRLX = 1 35.88 ­ 29.25 ­ 23 ­ 16.94 ­ ns B27a A(0:31) and BADDR(28:30) to CS asserted -GPCM- ACS = 11, TRLX = 1 43.45 ­ 35.50 ­ 28 ­ 20.73 ­ ns 36 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 8. Bus Operation Timings (Continued) 33 MHz 40 MHz 50 MHz 66 MHz Unit Num Characteristic B28 CLKOUT rising edge to WE(0:3) negated GPCM write access CSNT = 0 B28a CLKOUT falling Edge to WE(0:3) negated -GPCM- write access TRLX = 0, CSNT = 1, EBDF = 0 B28b Min Max Min Max Min Max Min Max ­ 9 ­ 9 ­ 9 ­ 9 ns 7.58 14.33 6.25 13 5 11.75 3.8 10.54 ns CLKOUT falling edge to CS negated -GPCM- write access TRLX = `0', CSNT = `1', ACS = 11, EBDF = 0 ­ 14.33 ­ 13 ­ 11.75 ­ 10.54 ns B28c CLKOUT Falling Edge to WE(0:3) negated -GPCM- write access TRLX = `0', CSNT = `1' write access TRLX = 0, CSNT = 1, EBDF = 1 10.86 17.99 8.88 16 7 14.13 5.18 12.31 ns B28d CLKOUT Falling Edge to CS negated -GPCM- write access TRLX = `0', CSNT = `1', ACS = 10, or ACS = `11', EBDF = 1 ­ 17.99 ­ 16 ­ 14.13 ­ 12.31 ns B29 WE (0:3) negated to DP (0:3) High-Z -GPCM- write access, CSNT = 0, EBDF = 0 5.58 ­ 4.25 ­ 3 ­ 1.79 ­ ns B29a WE(0:3) negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `0', CSNT = 1', EBDF = 0 13.15 ­ 10.5 ­ 8 ­ 5.58 ­ ns B29b CS negated to D(0:31), DP(0:3) High Z -GPCM- write access, ACS = `00', TRLX = `0' & CSNT = `0' 5.58 ­ 4.25 ­ 3 ­ 1.79 ­ ns B29c CS negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `0', CSNT = `1', ACS = `11,', EBDF = 0 13.15 ­ 10.5 ­ 8 ­ 5.58 ­ ns B29d WE(0:3) negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `1', CSNT = `1', EBDF = 0 43.45 ­ 35.5 ­ 28 -­ 20.73 ­ ns B29e CS negated to D (0:31), DP(0:3) High Z -GPCM- write access, TRLX = 1, CSNT = 1, ACS = 10, or ACS = 11 EBDF = 0 43.45 ­ 35.5 ­ 28 ­ 29.73 ­ ns B29f WE(0:3) negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `0', CSNT = `1', EBDF = 1 8.86 ­ 6.8 ­ 5 ­ 3.48 ­ ns B29g CS negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `0', CSNT = `1', ACS = `10' or ACS = '11', EBDF = 1 8.86 ­ 6.8 ­ 5 ­ 3.48 ­ ns B29h WE(0:3) negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `1', CSNT = `1', EBDF = 1 38.67 ­ 31.38 ­ 24.50 ­ 17.83 ­ ns B29i CS negated to D(0:31), DP(0:3) High Z -GPCM- write access, TRLX = `1', CSNT = `1', ACS = `10' or ACS = '11 ', EBDF = 1 38.67 ­ 31.38 ­ 24.50 ­ 17.83 ­ ns B30 CS, WE(0:3) negated to A(0:31), BADDR(28:30) invalid -GPCM- write access(8) 5.58 ­ 4.25 ­ 3 ­ 1.79 ­ 37 2129A­HIREL­08/02 Table 8. Bus Operation Timings (Continued) 33 MHz 40 MHz 50 MHz 66 MHz Unit Num Characteristic B30a Min Max Min Max Min Max Min Max WE(0:3) negated to A(0:31), BADDR(28:30) invalid -GPCM- write access, TRLX = '0', CSNT = '1'. CS negated to A(0:31) invalid GPCM write access, TRLX = '0', CSNT = '1', ACS = 10, ACS = 11, EBDF = 0 13.15 ­ 10.50 ­ 8 ­ 5.58 ­ ns B30b WE(0:3) negated to A(0:31), BADDR(28:30) invalid -GPCM- write access, TRLX = '1', CSNT = '1'. CS negated to A(0:31) invalid -GPCM- write access, TRLX = '1', CSNT = '1', ACS = 10, ACS = '1 1', EBDF = 0 43.45 ­ 35.50 ­ 28 ­ 20.73 ­ ns B30c WE(0:3) negated to A(0:31), BADDR(28:30) invalid -GPCM- write access, TRLX = '0', CSNT = '1'. CS negated to A(0:31) invalid -GPCM- write access, TRLX = '0', CSNT = '1', ACS = 10, ACS = '11', EBDF = 1 8.36 ­ 6.38 ­ 4.50 ­ 2.68 ­ ns B30d WE(0:3) negated to A(0:31), BADDR(28:30) invalid -GPCM- write access, TRLX = '1', CSNT = '1'. CS negated to A(0:31) invalid -GPCM- write access, TRLX = '1', CSNT = '1', ACS = 10,ACS = '11', EBDF = 1 38.67 ­ 31.38 ­ 24.50 ­ 17.83 ­ ns B31 CLKOUT Falling Edge to CS valid - as requested by control bit CST4 in the corresponding word in the UPM 1.5 6 1.50 6 1.50 6 1.50 6 ns B31a CLKOUT Falling Edge to CS valid - as requested by control bit CST1 in the corresponding word in the UPM 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns B31b CLKOUT Rising Edge to CS valid - as requested by control bit CST2 in the corresponding word in the UPM 1.50 8 1.50 8 1.50 8 1.50 8 ns B31c CLKOUT Rising Edge to CS valid - as requested by control bit CST3 in the corresponding word in the UPM 7.58 14.33 6.25 13 5 11.75 3.80 10.04 ns B31d CLKOUT Falling Edge to CS valid - as requested by control bit CST1 in the corresponding word in the UPM, EBDF = 1 13.26 17.99 11.28 16 9.40 14.13 7.58 12.31 ns B32 CLKOUT Falling Edge to BS valid - as requested by control bit BST4 in the corresponding word in the UPM 1.50 6 1.50 6 1.50 6 1.50 6 ns B32a CLKOUT Falling Edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 0 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns 38 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 8. Bus Operation Timings (Continued) 33 MHz 40 MHz 50 MHz 66 MHz Unit Num Characteristic Min Max Min Max Min Max Min Max B32b CLKOUT Rising Edge to BS valid - as requested by control bit BST2 in the corresponding word in the UPM 1.50 8 1.50 8 1.50 8 1.50 8 ns B32c CLKOUT Rising Edge to BS valid - as requested by control bit BST3 in the corresponding word in the UPM 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns B32d CLKOUT Falling Edge to BS valid - as requested by control bit BST1 in the corresponding word in the UPM, EBDF = 1 13.26 17.99 11.28 16 9.40 14.13 7.58 12.31 ns B33 CLKOUT Falling Edge to GPL valid - as requested by control bit GxT4 in the corresponding word in the UPM 1.50 6 1.50 6 1.50 6 1.50 6 ns B33a CLKOUT Rising Edge to GPL valid - as requested by control bit GxT3 in the corresponding word in the UPM 7.58 14.33 6.25 13 5 11.75 3.80 10.54 ns B34 A(0:31), BADDR(28:30), and D(0:31) to CS valid as requested by control bit CST4 in the corresponding word in the UPM 5.58 ­ 4.25 ­ 3 ­ 1.79 ­ ns B34a A(0:31), BADDR(28:30), and D(0:31) to CS valid as requested by control bit CST1 in the corresponding word in the UPM 13.15 ­ 10.50 ­ 8 ­ 5.58 ­ ns B34b A(0:31), BADDR(28:30), and D(0:31) to CS valid as requested by control bit CST2 in the corresponding word in the UPM 20.73 ­ 16.75 ­ 13 ­ 9.36 ­ ns B35 A(0:31), BADDR(28:30), and D(0:31) to BS valid as requested by control bit BST4 in the corresponding word in the UPM 5.58 ­ 4.25 ­ 3 ­ 1.79 ­ ns B35a A(0:31), BADDR(28:30), and D(0:31) to BS valid as requested by control bit BST1 in the corresponding word in the UPM 13.15 ­ 10.50 ­ 8 ­ 5.58 ­ ns B35b A(0:31), BADDR(28:30), and D(0:31) to BS valid as requested by control bit BST2 in the corresponding word in the UPM 20.73 ­ 16.75 ­ 13 ­ 9.36 ­ ns B36 A(0:31), BADDR(28:30), and D(0:31) to GPL valid as requested by control bit GxT4 in the corresponding word in the UPM 5.58 ­ 4.25 ­ 3 ­ 1.79 ­ ns B37 UPWAIT valid to CLKOUT Falling Edge(9) 6 ­ 6 ­ 6 ­ 6 ­ ns B38 CLKOUT Falling Edge to UPWAIT valid(9) 1 ­ 1 ­ 1 ­ 1 ­ ns (10) B39 AS valid to CLKOUT Rising Edge 7 ­ 7 ­ 7 ­ 7 ­ ns B40 A(0:31), TSIZ(0:1), RD/WR, BURST, valid to CLKOUT Rising Edge. 7 ­ 7 ­ 7 ­ 7 ­ ns 39 2129A­HIREL­08/02 Table 8. Bus Operation Timings (Continued) 33 MHz 40 MHz 50 MHz 66 MHz Unit Num Characteristic B41 B42 B43 Notes: Min Max Min Max Min Max Min Max TS valid to CLKOUT Rising Edge (SetUp Time). 7 ­ 7 ­ 7 ­ 7 ­ ns CLKOUT Rising Edge to TS Valid (Hold Time). 2 ­ 2 ­ 2 ­ 2 ­ ns AS negation to Memory Controller Signals ­ TBD ­ TBD ­ TBD ­ TBD ns Negation 1. Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value. 2. If the rate of change of the frequency of EXTAL is slow (i.e. it does not jump between the minimum and maximum values in one cycle) or the frequency of the jitter is fast (i.e. it does not stay at an extreme value for a long time) then the maximum allowed jitter on EXTAL can be up to 2% 3. The timings specified in B4 and B5 are based on full strength clock. 4. The timing for BR output is relevant when the PC860 PC860 is selected to work with the external bus arbiter. The timing for BG output is relevant when the PC860 PC860 is selected to work with internal bus arbiter. 5. The timing required for BR input is relevant when the TSPC860 TSPC860 is selected to work with internal bus arbiter. The timing for BG input is relevant when the TSPC860 TSPC860 is selected to work with internal bus arbiter. 6. The D (0:31) and DP (0:3) input timings B20 and B21 refer to the rising edge of the CLKOUT in which the TA input signal is asserted. 7. The D (0:31) and DP (0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only for read accesses controlled by chip-selects under control of the UPM in the Memory Controller, for data beats where DLT3 = 1 in the UPM RAM words. (This is only the cases where data is latched on the falling edge of CLKOUT). 8. The timing B30 refers to CS when ACS = 00 and to WE (0:3) when CSNT = 0 9. The signal UPWAIT is considered asynchronous to the CLKOUT and synchronized internally. The timings specified in B37 and B38 are specified to enable the freeze of the UPM output signals as described in Figure 22. 10. The AS signal is considered asynchronous to the CLKOUT. The timing B39 is specified in order to allow the behavior specified in Figure 25. Figure 8. External Clock Timing CLKOUT B1 B3 B1 B4 40 B2 B5 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Figure 9. Synchronous Output Signals Timing CLKOUT B8 B7 B9 Output Signals B8a B7a B9 Output Signals B8b B7b Output Signals Figure 10. Synchronous Active Pull-up and Open Drain Output Signals Timing CLKOUT B13 B11 B12 B11a B12a TS, BB B13a TA, BI B14 B15 TEA 41 2129A­HIREL­08/02 Figure 11. Synchronous Input Signals Timing CLKOUT B16 B17 TA, BI B16a B17a TEA, KR, RETRY, CR B16b B17 BB, BG, BR Figure 12. Input Data Timing in Normal Case CLKOUT B16 B17 TA B18 B19 D[0:31], DP[0:3] Figure 13. Input Data Timing when controlled by UPM in the Memory Controller CLKOUT TA B20 B21 D[0:31], DP[0:3] 42 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Figure 14. External Bus Read Timing (GPCM Controlled ­ ACS = `00') CLKOUT B11 B12 TS B8 A[0:31] B22 B23 CSx B25 B26 OE B28 WE[0:3] B19 B18 D[0:31], DP[0:3] Figure 15. External Bus Read Timing (GPCM Controlled ­ TRLX = `0' ACS = `10') CLKOUT B11 B12 TS B8 A[0:31] B23 B22a CSx B24 B25 B26 OE B18 B19 D[0:31], DP[0:3] 43 2129A­HIREL­08/02 Figure 16. External Bus Read Timing (GPCM Controlled ­ TRLX = `0' ACS = `11') CLKOUT B11 B12 TS B8 B22b A[0:31] B23 B22c CSx B25 B24a B26 OE B18 B19 D[0:31], DP[0:3] Figure 17. External Bus Read Timing (GPCM Controlled ­ TRLX = `1', ACS = `10', ACS = `11') CLKOUT B11 B12 TS B8 A[0:31] B23 B22a CSx B27 OE B26 B27a B22b B22c B18 B19 D[0:31], DP[0:3] 44 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Figure 18. External Bus Write Timing (GPCM controlled ­ TRLX = `0', CSNT = `0') CLKOUT B11 B12 TS B8 B30 A[0:31] B22 B23 CSx B25 B28 WE[0:3] B26 B29b OE B29 B8 B9 D[0:31], DP[0:3] Figure 19. External Bus Write Timing (GPCM controlled ­ TRLX = `0', CSNT = `1') CLKOUT B11 B12 TS B8 B30a B30c A[0:31] B22 B23 B28b B28d CSx B25 B29c B29g WE[0:3] B26 B29a B29f OE B28a B28c B8 B9 D[0:31], DP[0:3] 45 2129A­HIREL­08/02 Figure 20. External Bus Write Timing (GPCM controlled ­ TRLX = `1', CSNT = `1') CLKOUT B11 B12 TS B8 B30b B30d A[0:31] B22 B23 B28b B28d CSx B25 B29e B29i WE[0:3] B26 B29d B29h OE B29b B8 B28a B28c B9 D[0:31], DP[0:3] 46 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Figure 21. External Bus Timing (UPM Controlled Signals) CLKOUT B8 A[0:31] B31a B31d B31 B31c B31b CSx B34 B34a B34b B32a B32d B32 B32c B32b BS_A[0:3], BS_B[0:3] B35 B36 B35a B33a B35b B33 GPL_A[0:5], GPL_B[0:5] Figure 22. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] 47 2129A­HIREL­08/02 Figure 23. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing CLKOUT B37 UPWAIT B38 CSx BS_A[0:3], BS_B[0:3] GPL_A[0:5], GPL_B[0:5] Figure 24. Synchronous External Master Access Timing ­ GPCM handled ACS = `00' CLKOUT B41 B42 TS B40 A[0:31], TSIZ[0:1], R/W, BURST B22 CSx 48 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Figure 25. Asynchronous External Master Memory Access Timing (GPCM Controlled ­ ACS = '00') CLKOUT B39 AS B40 A[0:31], TSIZ[0:1], R/W B22 CSx Figure 26. Asynchronous External Master ­ Control Signals Negation Time AS B43 CSx, WE[0:3], OE, GPLx, BS[0:3] Table 9. Interrupt Timing(2) All Frequencies Num Characteristic(1) I39 Min Max Unit IRQx Valid to CLKOUT Rising Edge (Set Up Time) 6 ­ ns I40 IRQx Hold Time After CLKOUT 2 ­ ns I41 IRQx Pulse Width Low 3 ­ ns I42 IRQx Pulse Width High 3 ­ ns I43 IRQx Edge to Edge Time 4XTCLOCKOUT ­ ­ Notes: 1. The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being defined as level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference to the CLKOUT. 2. The timings I41, I42 and I43 are specified to allow the correct function of the IRQ lines detection circuitry, and has no direct relation with the total system interrupt latency that the TSPC860 TSPC860 is able to support. Figure 27. Interrupt Detection Timing for External Level Sensitive Lines CLKOUT I39 I40 IRQx 49 2129A­HIREL­08/02 Figure 28. Interrupt Detection Timing for External Edge Sensitive Lines CLKOUT I41 I42 IRQx I43 I43 Table 10. PCMCIA Timing 33 MHz Num Characteristic P44 50 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit A(0:31), REG valid to PCMCIA Strobe asserted(1) 20.73 ­ 16.75 ­ 13 ­ 9.36 ­ ns P45 A(0:31), REG valid to ALE negation(1) 28.30 ­ 23 ­ 18 ­ 13.15 ­ ns P46 CLKOUT to REG valid 7.58 15.58 6.25 14.25 5 13 3.79 11.84 ns P47 CLKOUT to REG Invalid 8.58 ­ 7.25 ­ 6 ­ 4.84 ­ ns P48 CLKOUT to CE1, CE2 asserted 7.58 15.58 6.25 14.25 5 13 3.79 11.84 P49 CLKOUT to CE1, CE2 negated 7.58 15.58 6.25 14.25 5 13 3.79 11.84 P50 CLKOUT to PCOE, IORD, PCWE, IOWR assert time P51 CLKOUT to PCOE, IORD, PCWE, IOWR negate time P52 CLKOUT to ALE assert time P53 CLKOUT to ALE negate time ns ns 11 2 11 7.58 15.58 6.25 14.25 5 13 3.79 11.04 ns ­ 15.58 ­ 14.25 ­ 13 ­ 11.84 ns 5.58 ­ 4.25 ­ 3 ­ 1.79 ­ ns 8 ­ 8 ­ 8 ­ 8 ­ ns 2 CLKOUT rising edge to WAITA and WAITB invalid(1) 1. PSST = 1. Otherwise add PSST times cycle time. 2. PSHT = 1. Otherwise add PSHT times cycle time. ­ 2 ­ 2 ­ 2 ­ ns (1) PCWE, IOWR negated to D(0:31) invalid P55 WAITA and WAITB valid to CLKOUT rising edge(1) Notes: 11 2 P54 P56 11 ns These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the PCMCIA current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL timer expiration. 50 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Figure 29. PCMCIA Access Cycles Timing External Bus Read CLKOUT TS P44 A[0:31] P46 P45 P47 REG P48 P49 CE1/CE2 P50 P51 P53 P52 PCOE, IORD P52 ALE B18 B19 D[0:31] 51 2129A­HIREL­08/02 Figure 30. PCMCIA Access Cycles Timing External Bus Write CLKOUT TS P44 A[0:31] P46 P45 P47 REG P48 P49 CE1/CE2 P50 P51 P53 P52 B18 P54 B19 PCOE, IOWR P52 ALE D[0:31] Figure 31. PCMCIA Wait Signals Detection Timing CLKOUT P55 P56 WAITx Table 11. PCMCIA Port Timing 33 MHz Num Characteristic P57 CLKOUT to OPx Valid P58 HRESET negated to OPx drive(1) P59 P60 Note: 52 40 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit ­ 19 ­ 19 ­ 19 ­ 19 ns 25.73 ­ 21.75 ­ 18 ­ 14.36 ­ ns IP_Xx valid to CLKOUT Rising Edge 5 ­ 5 ­ 5 ­ 5 ­ ns CLKOUT Rising Edge to IP_Xx invalid 1. OP2 and OP3 only. 1 ­ 1 ­ 1 ­ 1 ­ ns TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Figure 32. PCMCIA Output Port Timing CLKOUT P57 Output Signals HRESET P58 OP2, OP3 Figure 33. PCMCIA Input Port Timing CLKOUT P59 P60 Input Signals Table 12. Debug Port Timing All Frequencies Num Characteristic Min Max Unit P61 DSCK Cycle Time 3xTCLOCKOUT ­ ­ P62 DSCK Clock Pulse Width 1.25xTCLOCKOUT ­ ­ P63 DSCK Rise and Fall Times 0 3 ns P64 DSDI Input Data Setup Time 8 ­ ns P65 DSDI Data Hold Time 5 ­ ns P66 DSCK Low to DSDO Data Valid 0 15 ns P67 DSCK Low to DSDO Invalid 0 2 ns 53 2129A­HIREL­08/02 Figure 34. Debug Port Clock Input Timing CLKOUT P59 P60 Input Signals Figure 35. Debug Port Timings DSCK D64 D65 DSDI D66 D67 DSDO 54 TSPC860 TSPC860 2129A­HIREL­08/02 TSPC860 TSPC860 Table 13. RESET Timing 33 MHz Num Characteristic R69 40 MHz 50 MHz 66 MHz Min Max Min Max Min Max Min Max Unit CLKOUT to HRESET high impedance ­ 20 ­ 20 ­ 20 ­ 20 ns R70 CLKOUT to SRESET high impedance ­ 20 ­ 20 ­ 20 ­ 20 ns R71 RSTCONF pulse width 515.15 ­ 425 340 ­ 257.58 ­ ns R72 ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ R73 Configuration Data to HRESET rising edge set up time 504.55 ­ 425 ­ 350 ­ 277.27 ­ ns R74 Configuration Data to RSTCONF rising edge set up time 350 ­ 350 ­ 350 ­ 350 ­ ns R75 Configuration Data hold ti