MPC860ADS RS-232 RS232 MPC860 MC68160 MP860 -25OC SM732A1000A SM732A2000 U11/65 - Datasheet Archive

 

Motorola Semiconductor Israel Ltd. MICROPROCESSOR & MEMORY TECHNOLOGIES GROUP MPC860ADS Revision - B User's Manual ISSUE 0.1-

 

MOTOROLA Motorola Semiconductor Israel Ltd. MICROPROCESSOR & MEMORY TECHNOLOGIES GROUP MPC860ADS MPC860ADS Revision - B User's Manual ISSUE 0.1- ENG DRAFT 8/24/95 ISSUE 1.1a - ENG Release 3/22/96 ISSUE 1.2a - PILOT Release 5/14/96 ISSUE 1.3a - A Release 5/16/96 ISSUE 1.4a - B Release 2/11/97 SIX SIGMA 6 MOTOROLA MPC860ADS MPC860ADS, Revision B - User's Manual TABLE OF CONTENTS 1 1·1 1·2 1·3 1·4 1·5 1·6 1·7 1·8 2 2·1 2·2 2·3 2·3·1 2·3·2 2·3·2·1 2·3·3 2·3·4 2·3·5 2·4 2·4·1 2·4·2 2·4·3 2·4·4 2·4·5 2·4·6 2·4·7 2·4·8 2·4·9 3 3·1 3·2 3·2·1 3·2·2 3·2·3 3·2·4 3·2·5 3·2·6 3·2·7 3·2·8 3·2·9 3·2·10 3·2·11 3·2·12 3·2·13 3·2·14 3·2·15 3·2·16 Release 1.4a General Information Introduction Abbreviations' List Related Documentation SPECIFICATIONS MPC860ADS MPC860ADS Features Revision A to Revision B Changes Revision Pilot to Revision A Changes Revision ENG to Revision PILOT Changes Hardware Preparation and Installation INTRODUCTION UNPACKING INSTRUCTIONS HARDWARE PREPARATION ADI Port Address Selection Clock Source Selection Clock Generator Replacement - U17 Power-On Reset Source Selection VDDL Source Selection Keep Alive Power Source Selection INSTALLATION INSTRUCTIONS Host Controlled Operation Debug Port Controller For Target System Stand Alone Operation +5V Power Supply Connection P8: +12V Power Supply Connection ADI Installation Host computer to MPC860ADS MPC860ADS Connection Terminal to MPC860ADS MPC860ADS RS-232 RS-232 Connection Memory Installation OPERATING INSTRUCTIONS INTRODUCTION CONTROLS AND INDICATORS SOFT RESET Switch SW1 ABORT Switch SW2 HARD RESET - Switches SW1 & SW2 DS2 - Software Options Switch J4 Power Bridge GND Bridges RUN Indicator - LD1 FLASH ON - LD2 DRAM ON - LD3 ETH ON - LD4 Ethernet RX Indicator - LD5 Ethernet TX Indicator - LD6 Ethernet JABB Indicator - LD7 IRD ON - LD8 Ethernet CLSN Indicator LD9 Ethernet PLR Indicator - LD10 1 1 1 1 1 3 5 5 5 8 8 8 8 10 10 10 11 12 12 13 13 13 14 15 15 16 16 16 17 18 18 18 18 18 18 18 19 19 19 19 19 19 19 19 19 20 20 20 i MPC860ADS MPC860ADS, Revision B - User's Manual TABLE OF CONTENTS 3·2·17 3·2·18 3·2·19 3·2·20 3·2·21 3·2·22 Ethernet LIL Indicator - LD11 RS232 RS232 Port 1 ON - LD12 PCMCIA ON - LD13 RS232 RS232 Port 2 ON - LD14 5V Indicator - LD15 3.3V Indicator - LD16 3·3 MEMORY MAP 3·4 Programming The MPC Registers 3·4·1 Memory Controller Registers Programming 4 Functional Description 4·1 MPC860 MPC860 4·2 Reset & Reset - Configuration 4·2·1 Keep Alive Power-On Reset 4·2·2 Main Power - On Reset 4·2·3 Manual Soft Reset 4·2·4 Manual Hard Reset 4·2·5 MPC Internal Sources 4·2·6 Reset Configuration 4·2·6·1 Power - On Reset Configuration 4·2·6·2 Hard Reset Configuration 4·2·6·3 Soft Reset Configuration 4·3 Local Interrupter 4·4 Clock Generator 4·4·1 SPLL Support 4·5 Buffering 4·6 Chip - Select Generator 4·7 DRAM 4·7·1 DRAM 16 Bit Operation 4·7·2 DRAM Performance Figures 4·7·3 Refresh Control 4·7·4 Variable Bus-Width Control 4·8 Flash Memory 4·9 Ethernet Port 4·10 Infra - Red Port 4·11 RS232 RS232 Ports 4·11·1 RS-232 RS-232 Port 1 or 2 Signal Description 4·12 PCMCIA Port 4·12·1 PCMCIA Power Control 4·13 LCD Port 4·14 Board Control & Status Register - BCSR 4·14·1 BCSR Disable Protection Logic 4·14·2 BCSR0 - Hard Reset Configuration Register 4·14·3 BCSR1 - Board Control Register 4·14·4 BCSR2 - Board Status Register - 1 4·14·5 BCSR3 - Auxiliary Control / Status Register 4·15 Debug Port Controller 4·15·1 MPC860ADS MPC860ADS As Debug Port Controller For Target System 4·15·1·1 Debug Port Connection - Target System Requirements Release 1.4a 20 20 20 20 20 20 21 21 22 35 35 35 35 35 35 36 36 36 36 36 37 37 37 38 38 38 39 39 40 41 42 43 44 45 45 45 46 46 46 48 48 48 50 51 53 56 56 57 ii MPC860ADS MPC860ADS, Revision B - User's Manual TABLE OF CONTENTS 4·15·2 4·15·3 4·15·3·1 4·15·3·2 4·15·3·3 4·15·3·4 4·15·3·5 4·15·3·6 4·16 4·16·1 4·16·2 4·16·3 4·16·4 4·16·5 5 5·1 5·1·1 5·1·2 5·1·3 5·1·4 5·1·5 5·1·6 5·1·6·1 5·1·7 5·1·8 5·1·9 5·1·10 5·2 APPENDIX A A·1 A·2 A·3 APPENDIX B B·1 APPENDIX C C·1 C·2 C·2·1 C·3 C·3·1 Release 1.4a Debug Port Control / Status Register Standard MPCXXX Debug Port Connector Pin Description VFLS(0:1) HRESET* SRESET* DSDI - Debug-port Serial Data In DSCK - Debug-port Serial Clock DSDO - Debug-port Serial Data Out Power 5V Bus 3.3V Bus 2V Bus 12V Bus Keep Alive Power Support Information Interconnect Signals P1 ADI - Port Connector P2 - Ethernet Port Connector P3 - RS232 RS232 Ports' Connectors PCMCIA Port Connector P5 - External Debug Port Controller Input Interconnect. P6, P9, P10 & P12 Expansion and Logic Analyzer Connectors. Connecting Application Boards to the Expansion Connectors P7 - 5V Power Connector P8 - 12V Power Connector P11 - LCD Connector P13 - QUADS Compatible Communication Connector MPC860ADS MPC860ADS Part List Programmable Logic Equations U7 - Debug Port Controller U10 - Auxiliary Board Control U11 - Board Control & Status Register ADI I/F ADI Port Signal Description ADI Installation INTRODUCTION IBM-PC/XT/AT to MPC860ADS MPC860ADS Interface ADI Installation in IBM-PC/XT/AT SUN-4 to MPC860ADS MPC860ADS Interface ADI Installation in the SUN-4 57 59 59 59 59 60 60 60 60 62 62 62 62 62 63 63 63 64 64 65 67 68 68 89 90 90 90 95 101 102 128 145 177 177 179 179 179 179 180 181 iii MPC860ADS MPC860ADS, Revision B - User's Manual LIST OF FIGURES FIGURE 1-1 FIGURE 2-1 FIGURE 2-2 FIGURE 2-3 FIGURE 2-4 FIGURE 2-5 FIGURE 2-6 FIGURE 2-7 FIGURE 2-8 FIGURE 2-9 FIGURE 2-10 FIGURE 2-11 FIGURE 2-12 FIGURE 2-13 FIGURE 2-14 FIGURE 3-1 FIGURE 4-1 FIGURE 4-2 FIGURE 4-3 FIGURE 4-4 FIGURE 4-5 FIGURE 4-6 FIGURE 4-7 FIGURE 4-8 FIGURE 5-1 FIGURE B-1 FIGURE C-1 FIGURE C-2 FIGURE C-3 iv MPC860ADS MPC860ADS Block Diagram MPC860ADS MPC860ADS Top Side Part Location diagram Configuration Dip-Switch - DS1 U17 Power Sources Power-On Reset Source Selection VDDL Source Selection Keep Alive Power Source Selection Host Controlled Operation Scheme Debug Port Controller For Target System Operation Scheme Stand Alone Configuration P7: +5V Power Connector P8: +12V Power Connector P1 - ADI Port Connector P3 - RS-232 RS-232 Serial Port Connector Memory SIMM Installation DS2 - Description Refresh Scheme DRAM Address Lines' Switching Flash Memory SIMM Architecture RS232 RS232 Serial Port 1 or 2 Connector PCMCIA Port Configuration Debug Port Controller Block Diagram Standard Debug Port Connector MPC860ADS MPC860ADS Power Scheme Expansion Connector Assembly ADI Port Connector Physical Location of jumper JG1 and JG2 JG1 Configuration Options ADI board for SBus 4 9 10 11 12 12 13 13 14 15 15 16 16 17 17 18 41 43 43 45 47 56 59 61 70 177 180 180 181 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual LIST OF TABLES TABLE 1-1. TABLE 3-1. TABLE 3-2. TABLE 3-3. TABLE 3-4. TABLE 3-5. TABLE 3-6. TABLE 3-7. TABLE 3-8. TABLE 3-9. TABLE 3-10. TABLE 3-11. TABLE 3-12. TABLE 4-1. TABLE 4-2. TABLE 4-3. TABLE 4-4. TABLE 4-5. TABLE 4-6. TABLE 4-7. TABLE 4-8. TABLE 4-9. TABLE 4-10. TABLE 4-11. TABLE 4-12. TABLE 4-13. TABLE 4-14. TABLE 4-15. TABLE 4-16. TABLE 4-17. TABLE 4-18. TABLE 5-1 TABLE 5-2 TABLE 5-3 TABLE 5-4. TABLE 5-5. TABLE 5-6. TABLE 5-7. TABLE 5-8. TABLE 5-9. TABLE 5-10. TABLE 5-11. TABLE 5-12. TABLE 5-13. Release 1.4a MPC860ADS MPC860ADS Specifications MPC860ADS MPC860ADS Main Memory Map SIU REGISTERS' PROGRAMMING Memory Controller Initializations For 50Mhz UPMA Initializations for 60nsec DRAMs @ 50MHz UPMA Initializations for 70nsec DRAMs @ 50MHz UPMA Initializations for 60nsec EDO DRAMs @ 50MHz UPMA Initializations for 70nsec EDO DRAMs @ 50MHz Memory Controller Initializations For 25Mhz UPMA Initializations for 60nsec DRAMs @ 25MHz UPMA Initializations for 70nsec DRAMs @ 25MHz UPMA Initializations for 60nsec EDO DRAMs @ 25MHz UPMA Initializations for 70nsec EDO DRAMs @ 25MHz Regular DRAM Performance Figures EDO DRAM Performance Figures DRAM ADDRESS CONNECTIONS Flash Memory Performance Figures BCSR0 Description BCSR1 Description PCCVPP(0:1) Assignment BCSR2 Description Flash Presence Detect (4:1) Encoding DRAM Presence Detect (2:1) Encoding DRAM Presence Detect (4:3) Encoding EXTOOLI(0:3) Assignment BCSR3 Description MPC860ADS MPC860ADS Revision Number Conversion Table FLASH Presence Detect (7:5) Encoding Debug Port Control / Status Register DSCK Frequency Select Off-board Application Maximum Current Consumption P1 - ADI Port Interconnect Signals P2 - Ethernet Port Interconnect Signals PA3 or PB3 - Interconnect Signals P4 - PCMCIA Connector Interconnect Signals P5 - Interconnect Signals P6 - Interconnect Signals P9 - Interconnect Signals P10 - Interconnect Signals P12 - Interconnect Signals P7 - Interconnect Signals P8 - Interconnect Signals P13 - Interconnect Signals MPC860ADS MPC860ADS Part List 1 21 22 23 25 26 27 28 28 31 32 33 34 40 40 42 44 49 50 51 52 52 53 53 53 54 54 55 58 59 61 63 64 64 65 68 70 75 81 86 89 90 91 95 v MPC860ADS MPC860ADS, Revision B - User's Manual General Information 1 - General Information 1·1 Introduction This document is an operation guide for the MPC860ADS MPC860ADS board. It contains operational, functional and general information about the ADS. The MPC860ADS MPC860ADS is meant to serve as a platform for s/w and h/w development around the MPC860 MPC860. Using its on-board resources and its associated debugger, a developer is able to load his code, run it, set breakpoints, display memory and registers and connect his own proprietary h/w via the expansion connectors, to be incorporated to a desired system with the PowerQUICC. This board could also be used as a demonstration tool, i.e., application s/w may be burnedA into its flash memory and ran in exhibitions etc`. 1·2 Abbreviations' List · PowerQUICC - PowerPC-based QUad Integrated Communications Controller, the MPC860 MPC860 · · · · · · · · UPM - User Programmable Machine GPCM - General Purpose Chip-select Machine GPL - General Purpose Line (associated with the UPM) I/R - Infra-Red MPCADS - the MPC860ADS MPC860ADS, the subject of this document. BSCR - Board Control & Status Register. ZIF - Zero Input Force BGA - Ball Grid Array 1·3 Related Documentation · · · MPC860 MPC860 User's Manual. MC68160 MC68160 Data Sheet. ADI Board Specification. 1·4 SPECIFICATIONS The MPC860ADS MPC860ADS specifications are given in TABLE 1-1. TABLE 1-1. MPC860ADS MPC860ADS Specifications CHARACTERISTICS SPECIFICATIONS Power requirements (no other boards attached) +5Vdc @ 1.7 A (typical), 3 A (maximum) +12Vdc - @1A. Microprocessor MP860 MP860 @ 50 MHz Addressing Total address range: 4 GigaBytes Flash Memory Dynamic RAM 2 MByte, 32 bits wide expandable to 8 MBytes 4 MByte, 36 bits wide SIMM (32 bit data, 4 bit parity) option to use higher density SIMM, up to 32 MByte A. Either on or off-board. Release 1.4a 1 MPC860ADS MPC860ADS, Revision B - User's Manual General Information TABLE 1-1. MPC860ADS MPC860ADS Specifications (Continued) CHARACTERISTICS SPECIFICATIONS Operating temperature 0OC - 30OC Storage temperature -25OC -25OC to 85OC Relative humidity 5% to 90% (non-condensing) Dimensions: Height Depth Thickness 9.173 inches (233 mm) 7.08 inches (180 mm) 0.063 inches (1.6 mm) 2 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual General Information 1·5 MPC860ADS MPC860ADS Features t MPC860 MPC860, running upto 50 MHz, mounted on ZIF BGA socket. t 4 MBytes of 60-nsec EDO DRAM, support is given to various types of DRAM varying from 4MByte configured as 1M X 32, upto 32MByte configured as 8M X 32. t Automatic Dram SIMM identification. t 2 MByte Flash SIMM. Support for upto 8 MByte. t Automatic Flash SIMM identification. t Memory Disable Option for all local memory map slaves. t Board Control & Status Register - BCSR, Controlling Board's Operation. t Programmable Hard-Reset Configuration via BCSR. t T.P. Ethernet port via MC68160 MC68160 - EEST on SCC1 with Standby Mode. t Infra-Red Transceiver on SCC2 with Shutdown Option. t 5V-only PCMCIA Socket With Full Buffering, Power Control and Port Disable Option. Complies with PCMCIA 2.1+ Standard. t Module Enable Indications. t RS232 RS232 port on SMC1 with Low-Power Option. t RS232 RS232 port on SMC2 with Low-Power Option. t On - Board Debug Port Controller with ADI I/F. t MPC860ADS MPC860ADS Serving as Debug Station for Target System option. t Debug Clock Frequency Control - support for 10 / 5 / 2.5 / 1.25 MHz debug clock, SW programmable. t Optional Hard-Reset Configuration Burned in FlashA. t All MPC Pins Available At Expansion & Logic Analyzer Connectors. t External Tools' Identification Capability, via BCSR. t Soft / Hard Reset Push - Button t ABORT Push - Button t SingleB 5V Supply. t Reverse / Over Voltage Protection for Power Inputs. t 3.3V / 2V MPC Internal Logic Operation, 3.3V MPC I/O Operation. A. Available only if supported also on-chip. B. Unless a 12V supply is required for a PCMCIA card. Release 1.4a 3 MPC860ADS MPC860ADS, Revision B - User's Manual General Information t External Keep Alive Power Source Option. t Power Indications for Each Power Bus. t Software Option Switch provides 16 S/W options via BCSR. FIGURE 1-1 MPC860ADS MPC860ADS Block Diagram Expansion & Logic - Analyzer Connectors DATA & ADDRESS BUFFERS FLASH Mem. 2 - 8MByte Reset, Interrupts & Clock Control & Status Register EEST Debug Port Connector PCMCIA Buffering & Control PCMCIA PORT RS232 RS232 PORT Infra-Red Port MPC860 MPC860 ETHERNET PORT 1 DRAM 4 - 32 Mbyte Dram Width & Size Logic DEBUG PORT CONTROLLER (ADI I/F) ADI PORT 4 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual General Information 1·6 Revision A to Revision B Changes 1) Added restraining resistors over Dram SIMM address lines and Flash SIMM strobe lines. Existing restraining resistors, over dram strobe lines, which were glued-in with revision A, are introduced into the PCB. 2) Fixed support for SM732A1000A SM732A1000A and SM732A2000 SM732A2000 by Smart. 3) Added 2'nd RS232 RS232 port over SMC2, with its own dedicated Enable bit in BCSR1. 4) RS232 RS232 connector is replaced with a stacked connector block, to support both RS232 RS232 ports. 5) Added 4 pull-up resistors over the MSB of each Byte of Dram data lines. This allows for normal FPM / EDO discrmination. 6) Additional support for external tools: DS1/4 state replaces GND in P9(D20), BRS_EN2~ replaces GND in P12(B22) and N.C. in P13(C6). Since ready made tools for previous revisions might have connected these signals to GND, both are protected with series resistors. 7) Revision field in BCSR3 was changed to '0011'. 1·7 Revision Pilot to Revision A Changes 1) DS2 which on PILOT revision was connected on SP2 with blue wires, is now integrated into the PCB, located nearby SP2. 2) UA38 which on revision PILOT was glued and connected with blue-wires, is now integrated into the PCB. Gate allocation within UA38, is different from revision PILOT, to provide better PCB routing. 3) Revision code in BCSR is changed to 2. 4) Added optional RA21 (0 ohm) and CA7 (0.01µF) for 10-Base-T interface network. 5) Some SMD pads were enlarged to assist manufacturing. 1·8 Revision ENG to Revision PILOT Changes 1) Added support for ads to function as debug station: · Added independent 20MHz clock generator for debug port controller · Added MUX (U38) so that internal logic is clocked by the above generator · Removed pervious debug clock logic, derived from CLKOUT of the MPC. · Added signal named CHINS~ (CHip-In-Socket, active-low) which is connected to one of the MPC's GND pins (isolated from GND layer). This signal controls the above mux and the indication LEDs illumination. · Added pull-up resistors on the Chip-Select lines, to avoid possible data-bus contention when MPC is off-socket. · DRAMEN~ becomes active-low to allow buffer manipulation supporting LEDs darkness when MPC off-socket. Signal RUN becomes active-high from the same reason. (Sh. 1, 7, 8, 9, 11, 14) 2) Signals EXTM(1:4) changed to BADDR(28:30),AS~ correspondingly, to support future external master support. (Sh. 1, 11, 13) 3) MODCK0 renamed to MODCK2, to comply with MPC's spec convention. (Sh 1, 3, 13) 4) Signal BCLOS~, which was optional for data buffers' enable logic, is found redundant and removed from ADS logic. Renamed to GPL4A~. (Sh 1, 2, 3, 12) Release 1.4a 5 MPC860ADS MPC860ADS, Revision B - User's Manual General Information 5) Added 3 Flash memory Presence Detect lines - F_PD(5:7) to BCSR (U11/65 U11/65:67) (ENG - U10) to support varying flash memory delays. (Sh 3, 4, 11) 6) Added support for SMART flash simms: · 12V VPP connected to SIMM · BA10 connected also to the SIMM, to support 1M X 8 devices (Sh. 4) 7) BCSR power on reset logic was changed to support board's power-up recovery when keep-alive power remained active. (Sh. 3, 9) 8) Power-on reset logic changes: · KA power-on reset is not driven by U10 (ENG - U9) but directly to the MPC. · Added AC14 (U23) powered by KAPWR to support this. (AC14's s-t is required for mach connection due to slow rise time of PORST~) · D3 and R12 powered from KAPWR from the same reason. · Added option for PON reset by main 3.3V bus. (J1) (Sh. 3, 9) 9) BA9 and BA10 are connected to U10 (ENG - U9) instead of BA11 and BA12, for flash bank selection. Bug correction. (Sh. 3) 10) Renewed support for 32Khz crystal: · CLK4IN is gated (UA38), so when working with 32768 Hz crystal, CLK4IN is driven constantly to '0'. This, to avoid clock jitter with this mode of operation. · Parallel resistor increased to 20M. (Sh. 7) 11) PLL's XFC capacitors were changed to reflect parameter changes. Lower MF range capacitor is changed to 5nF to cover 1:5 to 1:10 MF range, while higher MF range capacitor was changed to 0.68uF to cover 1:458A to 1:1220B 1220B MF range (Sh. 7) 12) PCMCIA power controller is changed to LTC1315 LTC1315 (by Linear Technologies): · PCCVPPG~ signal and indication are removed, not supported by this device · VPP selection code is changed. · DRAMEN no longer controls power to the dram. · Old 12V voltage pump remains as contingency for possible unavailability of the device, although the device switching outputs drive 12V. R55, R56 & R59 are therefore not assembled. (Sh. 3, 9) 13) Added ADS board revision tag in BCSR. 14) Added signals RS_EN~ and ETHEN~ to P13 - Quads Compatible connector, for tool designer benefit. (Sh. 16) A. Lowest MF allowed with 32768 Hz crystal, due to 15MHz minimal PLL frequency. B. Highest MF allowed with 32768 Hz crystal, considering 40MHz rated MPC. 6 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual General Information 15) Added 4-switches dip-switch - DS2, connected over EXTOLI(0:3) lines, to provide s/w option selection capability. Release 1.4a 7 MPC860ADS MPC860ADS, Revision B - User's Manual Hardware Preparation and Installation 2 - Hardware Preparation and Installation 2·1 INTRODUCTION This chapter provides unpacking instructions, hardware preparation, and installation instructions for the MPC860ADS MPC860ADS. 2·2 UNPACKING INSTRUCTIONS NOTE If the shipping carton is damaged upon receipt, request carrier's agent to be present during unpacking and inspection of equipment. Unpack equipment from shipping carton. Refer to packing list and verify that all items are present. Save packing material for storing and reshipping of equipment. CAUTION AVOID TOUCHING AREAS OF INTEGRATED CIRCUITRY; STATIC DISCHARGE CAN DAMAGE CIRCUITS. 2·3 HARDWARE PREPARATION To select the desired configuration and ensure proper operation of the MPC860ADS MPC860ADS board, changes of the Dip-Switch settings may be required before installation. The location of the switches, LEDs, Dip-Switches, and connectors is illustrated in FIGURE 2-1. The board has been factory tested and is shipped with DipSwitch settings as described in the following paragraphs. Parameters can be changed for the following conditions: · ADI port address · MPC Clock Source · Power-On Reset Source. · MPC Keep Alive Power Source · MPC Internal Logic Supply Source 8 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Hardware Preparation and Installation FIGURE 2-1 MPC860ADS MPC860ADS Top Side Part Location diagram Release 1.4a 9 MPC860ADS MPC860ADS, Revision B - User's Manual Hardware Preparation and Installation 2·3·1 ADI Port Address Selection The MPC860ADS MPC860ADS can have eight possible slave addresses set for its ADI port, enabling up to eight MPC860ADS MPC860ADS boards to be connected to the same ADI board in the host computer. The selection of the slave address is done by setting switches 1, 2 & 3 in the Dip-Switch - DS1. Switch 1 stands for the mostsignificant bit of the address and switch 3 stands for the least-significant bit. If the switch is in the 'ON' state, it stands for logical '1'. In FIGURE 2-2 DS1 is shown to be configured to address '0'. FIGURE 2-2 Configuration Dip-Switch - DS1 ON ADR2 ADR2 1 ADR1 2 ADR1 ADR0 3 ADR0 3 - 5 MHz Generator via CLK4IN 4 32.678 KHz Crystal Resonator DS1 Table 2-1 describes the switch settings for each slave address: Table 2-1 ADI Address Selection ADDRESS Switch 2 Switch 3 0 OFF OFF OFF 1 OFF OFF ON 2 OFF ON OFF 3 OFF ON ON 4 ON OFF OFF 5 ON OFF ON 6 ON ON OFF 7 2·3·2 Switch 1 ON ON ON Clock Source Selection Switch #4 on DS1 selects the clock source for the MPC. When it is in the 'ON' position while the ADS is powered-up, the on-board 32.768 KHz crystal resonator becomes the clock source and the PLL multiplication factor becomes 1:513. When switch #4 is in the 'OFF' position while the ADS is powered-up, the on-board 4AMHz clock generator (U17) becomes the clock source while the PLL multiplication factor becomes 1:5. 2·3·2·1 Clock Generator Replacement - U17 When replacing U17 with another clock generator it should be noticed that there are 2 supply level available at U17: 1) 5V supply at pin 14. A. A 5MHz clock generator is provided as well. 10 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Hardware Preparation and Installation 2) 3.3V supply available at pin 11. FIGURE 2-3 U17 Power Sources 14 1 5V 3.3V GND 7 8 U17 From looking at FIGURE 2-3 "U17 Power Sources" above, we see that 5V oscillator may be used with 14 pins only form-factor while 3.3V oscillators may be used with 8 pins only form-factor. WARNING IF A 14 Pin Form-Factor, 3.3V Clock Generator is inserted to U17, PERMANENT DAMAGE Might Be Inflicted To The Device. WARNING Since the MPC clock input is NOT 5V FRIENDLY, any clock generator inserted to U17, MUST BE 3.3V compatible. If a 5V output clock generator is inserted to U17, PERMANENT DAMAGE might be inflicted to the MPC. 2·3·3 Power-On Reset Source Selection As there are differences between MPC revisions regarding the functionality of the Power-On Reset logic, it is therefore necessary to select different sources for Power-ON reset generation. J1 on the ADS is used to select Power-On Reset source: when a jumper is placed between positions 1 - 2 of J1, Power-On reset to the MPC is generated by the Keep-Alive power rail. I.e., When KAPWR goes below 2.005V - Power-On reset is generated. When a jumper is place between position 2 - 3 of J1, PowerOn reset to the MPC is generated from the MAIN 3.3V power rail. I.e, when the MAIN 3.3V power rail goes below 2.805V Power-On reset is generated. Release 1.4a 11 MPC860ADS MPC860ADS, Revision B - User's Manual Hardware Preparation and Installation FIGURE 2-4 Power-On Reset Source Selection J1 J1 1 1 KA Power Rail 2·3·4 MAIN Power Rail VDDL Source Selection J2 serves as a selector for VDDL - MPC internal logic supply. When a jumper is placed between positions 1 - 2 of J2, VDDL is supplied with 3.3V. When a jumper is placed between positions 2 - 3 of J2, VDDL is supplied by 2V power source. The jumper on J2 is factory set between positions 1 - 2 to supply 3.3 to VDDL. FIGURE 2-5 VDDL Source Selection J2 1 VDDL - 3.3V 2·3·5 J2 1 VDDL - 2V Keep Alive Power Source Selection J3 selects the Keep Alive power source of the MPC. When a jumper is placed between positions 1 - 2 of J3, the Keep Alive power is fed from the main 3.3V bus. When an external power sourceA is to be connected to the Keep Alive power rail, it should be connected between positions 2 (the positive pole) and position 3 (GND) of J3. A. E.g., a battery. 12 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Hardware Preparation and Installation FIGURE 2-6 Keep Alive Power Source Selection J3 1 3.3V J3 3.3V 1 KAPWR KAPWR + GND GND - KAPWR From 3.3V 2·4 Ext. Power Supply KAPWR From Ext. Power Supply INSTALLATION INSTRUCTIONS When the MPC860ADS MPC860ADS has been configured as desired by the user, it can be installed according to the required working environment as follows: · Host Controlled Operation · Debug Port Controller for Target System · Stand-Alone 2·4·1 Host Controlled Operation In this configuration the MPC860ADS MPC860ADS is controlled by a host computer via the ADI through the debug port. This configuration allows for extensive debugging using on-host debugger. FIGURE 2-7 Host Controlled Operation Scheme ADI Host Computer 37 Wire Flat Cable P1 5V Power Supply P7 2·4·2 Debug Port Controller For Target System This configuration resembles the previous, but here the local MPC is removed from its socket while the ADS is connected via a 10 lead Flat-Cable between P5 and a matching connector on a target system. Release 1.4a 13 MPC860ADS MPC860ADS, Revision B - User's Manual Hardware Preparation and Installation WARNING When connecting the ADS to a target system via P5 and a 10 lead flat-cable, the MPC MUST be REMOVED from its SOCKET (U18). Otherwise, PERMANENT DAMAGE might be inflicted to either the Local MPC or to the Target MPC. With this mode of operation, all on-board modules are disabled and can not be accessed in any way, except for the debug port controller. Also, all indications except for 5V power, 3.3V power and RUN are darkened. All debugger commands and debugging features are available in this mode, including s/w download, breakpoints, etc`. The target system may be reset or interrupted by the debug port or reset by the ADS's RESET switches. It is the responsibility of the target system designer, to provide Power-On-Reset and HARD-Reset configurations, while SOFT-Reset configuration is provided by the debug-port controller. See also 4·15·1 "MPC860ADS MPC860ADS As Debug Port Controller For Target System" on page 56. FIGURE 2-8 Debug Port Controller For Target System Operation Scheme Target System 10 Wire 37 Wire ADI Host Computer Flat Cable Flat Cable P1 5V Power Supply P5 P7 MPC Removed From Socket 2·4·3 Stand Alone Operation In this mode, the board is not controlled by the host via the ADI/Debug port. It may connect to host via one of its other ports, e.g., RS232 RS232 port, I/R port, Ethernet port, etc`. Operating in this mode requires an application program to be programmed into the board`s Flash memory (while with the host controlled operation, no memory is required at all). 14 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Hardware Preparation and Installation FIGURE 2-9 Stand Alone Configuration Et he rn RS et 23 2 Host Computer I/R P2 P3 5V Power Supply P7 2·4·4 +5V Power Supply Connection The MPC860ADS MPC860ADS requires +5 Vdc @ 5 A max, power supply for operation. Connect the +5V power supply to connector P7 as shown below: FIGURE 2-10 P7: +5V Power Connector +5V 1 GND 2 GND 3 P7 is a 3 terminal block power connector with power plug. The plug is designed to accept 14 to 22 AWG wires. It is recommended to use 14 to 18 AWG wires. To provide solid ground, two Gnd terminals are supplied. It is recommended to connect both Gnd wires to the common of the power supply, while VCC is connected with a single wire. 2·4·5 NOTE Since hardware applications may be connected to the MPC860ADS MPC860ADS using the expansion connectors P6, P9, P10, P12 or P13, the additional power consumption should be taken into consideration when a power supply is connected to the MPC860ADS MPC860ADS. P8: +12V Power Supply Connection The MPC860ADS MPC860ADS requires +12 Vdc @ 1 A max, power supply for the PCMCIA channel Flash programming capability. The MPC860ADS MPC860ADS can work properly without the +12V power supply, if there is no need to program a 12V programmable PCMCIA flash card. Connect the +12V power supply to connector P6 as shown below: Release 1.4a 15 MPC860ADS MPC860ADS, Revision B - User's Manual Hardware Preparation and Installation FIGURE 2-11 P8: +12V Power Connector +12V 1 GND 2 P8 is a 2 terminal block power connector with power plug. The plug is designed to accept 14 to 22 AWG wires. It is recommended to use 14 to 18 AWG wires. 2·4·6 ADI Installation For ADI installation on various host computers, refer to APPENDIX C - "ADI Installation" on page 179. 2·4·7 Host computer to MPC860ADS MPC860ADS Connection The MPC860ADS MPC860ADS ADI interface connector, P1, is a 37 pin, male, D type connector. The connection between the MPC860ADS MPC860ADS and the host computer is by a 37 line flat cable, supplied with the ADI board. FIGURE 2-12 below shows the pin configuration of the connector. FIGURE 2-12 P1 - ADI Port Connector Gnd Gnd Gnd Gnd Gnd Gnd (+ 12 v) N.C. HOST_VCC HOST_VCC HOST_VCC HOST_ENABLE~ Gnd Gnd Gnd PD0 PD2 PD4 PD6 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 N.C D_C~ HST_ACK ADS_SRESET ADS_HRESET ADS_SEL2 ADS_SEL1 ADS_SEL0 HOST_REQ ADS_REQ ADS_ACK N.C. N.C. N.C. N.C. PD1 PD3 PD5 PD7 NOTE: Pin 26 on the ADI is connected to +12 v power supply, but it is not used in the MPC860ADS MPC860ADS. 2·4·8 Terminal to MPC860ADS MPC860ADS RS-232 RS-232 Connection A serial (RS232 RS232) terminal or any other RS232 RS232 equipment, may be connected to the RS-232 RS-232 connector P3. The RS-232 RS-232 connector is a 9 pin, female, D-type connector as shown in FIGURE 2-13. The connector is arranged in a manner that allows for 1:1 connection with the serial port of an IBM-ATA or compatibles, i.e. via a flat cable. A. IBM-AT is a trademark of International Business Machines Inc. 16 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Hardware Preparation and Installation FIGURE 2-13 P3 - RS-232 RS-232 Serial Port Connector CD TX 1 2 RX DTR 3 4 5 GND 6 7 8 9 DSR RTS CTS N.C. NOTE: The RTS line (pin 7) is not connected on the MPC860ADS MPC860ADS. 2·4·9 Memory Installation The MPC860ADS MPC860ADS is supplied with two types of memory SIMM: · EDO DRAM SIMM · Flash Memory SIMM. To avoid shipment damage, these memories are packed aside rather than being installed in their sockets. Therefore, they should be installed on site. To install a memory SIMM, it should be taken out of its package, put diagonally in its socket (no error can be made here, since the Flash socket has 80 contacts, while the DRAM socket has 72) and then twisted to a vertical position until the metal lock clips are locked. See FIGURE 2-14 "Memory SIMM Installation" below. CAUTION The memory SIMMs have alignment nibble near their # 1 pin. It is important to align the memory correctly before it is twisted, otherwise damage might be inflicted to both the memory SIMM and its socket. FIGURE 2-14 Memory SIMM Installation (1) (2) Memory SIMM Metal Lock Clip SIMM Socket Release 1.4a 17 MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS 3 - OPERATING INSTRUCTIONS 3·1 INTRODUCTION This chapter provides necessary information to use the MPC860ADS MPC860ADS in host-controlled and stand-alone configurations. This includes controls and indicators, memory map details, and software initialization of the board. 3·2 CONTROLS AND INDICATORS The MPC860ADS MPC860ADS has the following switches and indicators. 3·2·1 SOFT RESET Switch SW1 The SOFT RESET switch SW1 performs Soft reset to the MPC internal modules, maintaining MPC's configuration (clocks & chip-selects) and dram contents. The switch signal is debounced, and it is not possible to disable it by software. At the end of the Soft Reset Sequence, the Soft Reset Configuration is sampled and becomes valid. 3·2·2 ABORT Switch SW2 The ABORT switch is normally used to abort program execution, this by issuing a level 0 interrupt to the MPC. If the ADS is in stand alone modeA, it is the responsibility of the user to provide means of handling the interrupt, since there is no resident debugger with the MPC860ADS MPC860ADS. The ABORT switch signal is debounced, and can not be disabled by software. 3·2·3 HARD RESET - Switches SW1 & SW2 When BOTH switches - SW1 and SW2 are depressed simultaneously, HARD reset is generated to the MPC. When the MPC is HARD reset, all its configuration is lost, including data stored in the DRAM and the MPC has to be re-initialized. At the end of the Hard Reset sequence, the Hard Reset Configuration stored in BCSR0 becomes valid. 3·2·4 DS2 - Software Options Switch DS2 is a 4-switches Dip-Switch, mounted over SP2. This switch is connected over EXTOLI(0:3) lines, and since EXTOLI(0:3) lines are available at BCSR, S/W options may be manually selected, according to DS2 state. FIGURE 3-1 DS2 - Description ON EXTOLI0 Pulled to '1' 1 EXTOLI1 Pulled to '1' 2 EXTOLI1 Driven to '0' EXTOLI2 Pulled to '1' 3 EXTOLI2 Driven to '0' EXTOLI3 Pulled to '1' 4 EXTOLI3 Driven to '0' EXTOLI0 Driven to '0' DS2 A. I.e., detached from a debug station. 18 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS 3·2·5 J4 Power Bridge J4 is a soldered jumper, which is in series with the 3.3V power bus. This jumper may be removedA if current measurements on the 3.3V bus are to be performed. Warning There are also GND bridges on board, which physically resemble J4. Do not mistake J4 to be a GND jumper, otherwise, permanent damage might be inflicted to the MPC860ADS MPC860ADS. 3·2·6 GND Bridges There are 4 GND bridges on the MPC860ADS MPC860ADS. They are meant to assist general measurements and logicanalyzer connection. Warning When connecting to a GND bridge, use only INSULATED GND clips. Failure in doing so, might result in permanent damage to the MPC860ADS MPC860ADS. 3·2·7 RUN Indicator - LD1 When the green RUN led - LD1 is lit, it indicates that the MPC is not in debug mode, i.e., VFLS0 & VFLS1 = 0. It is important to remember, that if the VFLS(0:1) pins are programmed for alternative use rather than function as VFLS lines, this indication is meaningless. 3·2·8 FLASH ON - LD2 When the yellow FLASH ON led is lit, it indicates that the FLASH module is enabled in the BCSR1 register. I.e., any access done to the CS0~ address space will hit the flash memory. When it is dark, the flash is disabled and CS0~ may be used off-board via the expansion connectors. 3·2·9 DRAM ON - LD3 When the yellow DRAM ON led is lit, it indicates the DRAM is enabled in BCSR1. Therefore, any access made to CS1~ (or CS2~) will hit on the DRAM. When it is dark, it indicates that either the DRAM is disabled in BCSR1, enabling the use of CS1~ and CS2~ off-board via the expansion connectors. 3·2·10 ETH ON - LD4 When the yellow ETH ON led is lit, it indicates that the ethernet port transceiver - the MC68160 MC68160 EEST, connected to SCC1 is active. When it is dark, it indicates that the EEST is in power down mode, enabling the use of SCC1 pins off-board via the expansion connectors. 3·2·11 Ethernet RX Indicator - LD5 The green Ethernet Receive LED indicator blinks whenever the EEST is receiving data from one of the Ethernet port. 3·2·12 Ethernet TX Indicator - LD6 The green Ethernet Receive LED indicator blinks whenever the EEST is transmitting data via the Ethernet port. 3·2·13 Ethernet JABB Indicator - LD7 The red Ethernet TP Jabber LED indicator - JABB, lights whenever a jabber condition is detected on the TP ethernet port. A. By a skilled technician only. Release 1.4a 19 MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS 3·2·14 IRD ON - LD8 When the yellow IRD ON led is lit, it indicates that the Infra-Red transceiver - the TFDS3000 TFDS3000, connected to SCC2, is active and enables communication via that medium. When it is dark, the I/R transceiver is in shutdown mode, enabling the use of SCC2 pins off-board via the expansion connectors. 3·2·15 Ethernet CLSN Indicator LD9 The red Ethernet Collision LED indicator CLSN, blinks whenever a collision condition is detected on the ethernet port, i.e., simultaneous receive and transmit. 3·2·16 Ethernet PLR Indicator - LD10 The red Ethernet TP Polarity LED indicator - PLR, lights whenever the wires connected to the receiver input of the ethernet port are reversed. The LED is lit by the EEST, and remains on while the EEST has automatically corrected for the reversed wires. 3·2·17 Ethernet LIL Indicator - LD11 The yellow Ethernet Twisted Pair Link Integrity LED indicator - LIL, lights to indicate good link integrity on the TP port. The LED is off when the link integrity fails. 3·2·18 RS232 RS232 Port 1 ON - LD12 When the yellow RS232 RS232 ON led is lit, it designates that the RS232 RS232 transceiver connected to SMC1, is active and communication via that medium (through PA3) is allowed. When dark, it designates that the transceiver is in shutdown mode, so SMC1 pins may be used off-board via the expansion connectors. 3·2·19 PCMCIA ON - LD13 When the yellow PCMCIA ON led is lit, it indicates the following: 1) Address & strobe buffers are driven towards the PCMCIA card 2) Data buffers may be driven to / from the PCMCIA card depending on the CE1A~ and CE2A~ signals and transfer direction. 3) Card status lines are driven towards the MPC from the PCMCIA card. When it is dark, it indicates that all the above buffers are tri-stated and the pins associated with PCMCIA channel A, may be used off-board via the expansion connectors. 3·2·20 RS232 RS232 Port 2 ON - LD14 When the yellow RS232 RS232 Port 2 ON led is lit, it designates that the RS232 RS232 transceiver connected to SMC2, is active and communication via that medium (through PB3) is allowed. When dark, it designates that the transceiver is in shutdown mode, so SMC2 pins may be used off-board via the expansion connectors. 3·2·21 5V Indicator - LD15 The yellow 5V led, indicates the presence of the +5V supply at P7. 3·2·22 3.3V Indicator - LD16 The yellow 3.3V led indicates that the 3.3V power bus is powered 20 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS 3·3 MEMORY MAP All accesses to MPC860ADS MPC860ADS's memory slaves are controlled by the MPC's memory controller. Therefore, the memory map is reprogrammable to the desire of the user. After Hard Reset is performed by the debug station, the debugger checks to see the size, delay and type of the DRAM and FLASH memory mounted on board and initializes the chip-selects accordingly. The DRAM and the FLASH memory respond to all types of memory access i.e., user / supervisory, program / data and DMA. TABLE 3-1. MPC860ADS MPC860ADS Main Memory Map ADDESS RANGE Memory Type 00000000 - 003FFFFF 003FFFFF DRAM SIMM 00400000 - 007FFFFF 007FFFFF DRAM SIMM 00800000 - 00FFFFFF 00FFFFFF DRAM SIMM 01000000 - 01FFFFFF 01FFFFFF DRAM SIMM 02000000 - 020FFFFF 020FFFFF Empty Space 02100000 - 02103FFF 02103FFF BCSR(0:3)a 02104000 - 021FFFFF 021FFFFF Empty Space 02200000 - 02207FFF 02207FFF MPC Internal MAPc 02208000 - 027FFFFF 027FFFFF Empty Space 02800000 - 029FFFFF 029FFFFF Flash SIMM Port Size Device Type MCM36100 MCM36100 MCM36200 MCM36200 MCM36400 MCM36400 MCM36800 MCM36800 32 MCM36200 MCM36200 MCM36400 MCM36400 MCM36800 MCM36800 32 MCM36400 MCM36400 MCM36800 MCM36800 32 MCM36800 MCM36800 32 32b 32 MCM29F020 MCM29F020 02A00000 02A00000 - 02BFFFFF 02BFFFFF MCM29F040 MCM29F040 SM732A1000A SM732A1000A MCM29F080 MCM29F080 SM732A2000 SM732A2000 32 MCM29F040 MCM29F040 SM732A1000A SM732A1000A MCM29F080 MCM29F080 SM732A2000 SM732A2000 32 MCM29F080 MCM29F080 SM732A2000 SM732A2000 32 02C00000 02C00000 - 02FFFFFF 02FFFFFF a. The device appears repeatedly in multiples of its size. E.g., BCSR0 appears at memory locations 2100000, 2100010, 2100020., while BCSR1 appears at 2100004, 2100014, 2100024. and so on. b. Only upper 16 bit are in fact used. c. Refer to the MPC860 MPC860 User's Manual for complete description of the MPC internal memory map. 3·4 Programming The MPC Registers The MPC provides the following functions on the MPC860ADS MPC860ADS: 1) DRAM Controller 2) Chip Select generator. 3) UART for terminal or host computer connection. 4) Ethernet controller. 5) Infra-Red Port Controller 6) General Purpose I/O signals. Release 1.4a 21 MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS The internal registers of the MPC must be programmed after Hard reset as described in the following paragraphs. The addresses and programming values are in hexadecimal base. For better understanding the of the following initializations refer to the MPC860 MPC860 User's Manual for more information. TABLE 3-2. SIU REGISTERS' PROGRAMMING Register Init Value[hex] Description SIUMCR 01632440 Internal arbitration, External master arbitration priority - 0, External arbitration priority - 0, PCMCIA channel II pins - debug pins, Debug Port on JTAG port pins, FRZ/IRQ6~ - IRQ6~, debug register - locked, No parity for non-CS regions, DP(0:3)/IRQ(3:6)~ pins - DP(0:3), reservation disabled, SPKROUT - Tri-stated, BS_A(0:3)~ and WE(0:3)~ are driven just on their dedicated pins, GPL_B5~ enabled, GPL_A/B(2:3)~ function as GPLs. SYPCR FFFFFF88 FFFFFF88 Software watchdog timer count - FFFF, Bus-monitor timing FF, Bus-monitor Enabled, S/W watch-dog - Freeze, S/W watch-dog - disabled, S/W watch-dog (if enabled) causes NMI, S/W (if enabled) not prescaled. TBSCR 00C2 No interrupt level, reference match indications cleared, interrupts disabled, no freeze, time-base disabled. RTCSC 01C2 Interrupt request level - 1, 32768 Hz source, second interrupt disabled, Alarm interrupt disabled, Real-time clock - FREEZE, Real-time clock disabled. PISCR 0082 No level for interrupt request, Periodic interrupt disabled, clear status, interrupt disabled, FREEZE, periodic timer disabled. 3·4·1 Memory Controller Registers Programming The memory controller on the MPC860ADS MPC860ADS is initialized to 50 MHz operation. I.e., registers' programming is based on 50 MHZ timing calculation except for refresh timer which is initialized to 16.67Mhz, the lowest frequency at which the ADS may wake up. Since the ADS may be made to wake-up at 25MHzA as well, the initializations are not efficient, since there are too many wait-states inserted. Therefore, additional set of initialization is provided to support efficient 25MHz operation. The reason for initializing the ADS for 50Mhz is to allow proper (although not efficient) ADS operation through all available ADS clock operation frequencies. A. The only parameter which is initialized to the start-up frequency, is the refresh rate, which would have been inadequate if initialized to 50Mhz while board is running at a lower frequency. Therefore, for best bus bandwidth availability, refresh rate should be adapted to the current system clock frequency. 22 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS Warning Due to availability problems with few of the supported memory components, the below initializations were not tested with all parts. Therefore, the below initializations are liable to CHANGE, throughout the testing period. TABLE 3-3. Memory Controller Initializations For 50Mhz Register Device Type BR0 All Flash supported. OR0 Description 02800001 Base at 2800000, 32 bit port size, no parity, GPCM MCM29F020-90 MCM29F020-90 FFE00D34 FFE00D34 2MByte block size, all types access, CS early negate, 6 w.s., Timing relax MCM29F040-90 MCM29F040-90 SM732A1000A-9 SM732A1000A-9 FFC00D34 FFC00D34 4MByte block size, all types access, CS early negate, 6 w.s., Timing relax MCM29F080-90 MCM29F080-90 SM732A2000-9 SM732A2000-9 FF800D34 FF800D34 8MByte block size, all types access, CS early negate, 6 w.s., Timing relax MCM29F020-12 MCM29F020-12 FFE00D44 FFE00D44 2MByte block size, all types access, CS early negate, 8 w.s., Timing relax MCM29F040-12 MCM29F040-12 SM732A1000A-12 SM732A1000A-12 FFC00D44 FFC00D44 4MByte block size, all types access, CS early negate, 8 w.s., Timing relax MCM29F080-12 MCM29F080-12 SM732A2000-12 SM732A2000-12 FF800D44 FF800D44 8MByte block size, all types access, CS early negate, 8 w.s., Timing relax BR1 BCSR 02100001 Base at 2100000, 32 bit port size, no parity, GPCM OR1 BCSR FFFF8110 FFFF8110 32 KByte block size, all types access, CS early negate, 1 w.s. BR2 All Dram Supported 00000081 Base at 0, 32 bit port size, no parity, UPMA OR2 MCM36100/200-60/70 MCM36100/200-60/70 FFC00800 FFC00800 4MByte block size, all types access, initial address multiplexing according to AMA. MCM36400/800-60/70 MCM36400/800-60/70 MT8/16D432/832X-6/7 MT8/16D432/832X-6/7 FF000800 FF000800 16MByte block size, all types access, initial address multiplexing according to AMA. MCM36200-60/70 MCM36200-60/70 00400081 Base at 400000, 32 bit port size, no parity, UPMA MCM36800-60/70 MCM36800-60/70 MT16D832X-6/7 MT16D832X-6/7 01000081 Base at 1000000, 32 bit port size, no parity, UPMA MCM36200-60/70 MCM36200-60/70 FFC00800 FFC00800 4MByte block size, all types access, initial address multiplexing according to AMA MCM36800-60/70 MCM36800-60/70 MT16D832X-6/7 MT16D832X-6/7 FF000800 FF000800 16MByte block size, all types access, initial address multiplexing according to AMA. 0400 Divide by 16 (decimal) BR3 OR3 MPTPR Release 1.4a All Dram Supported SIMMs Init Value [hex] SIMMs SIMMs 23 MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS TABLE 3-3. Memory Controller Initializations For 50Mhz Register Device Type Init Value [hex] Description MCM36100-60/70 MCM36100-60/70 40A21114a 60A21114b C0A21114c refresh clock divided by 40a or 60b or C0c, periodic timer enabled, type 2 address multiplexing scheme, 2 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MCM36200-60/70 MCM36200-60/70 20A21114a 30A21114b 60A21114c refresh clock divided by 20a or 30b or 60c, periodic timer enabled, type 2 address multiplexing scheme, 2 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MCM36400-60/70 MCM36400-60/70 MT8D432X-6/7 MT8D432X-6/7 40B21114a 60B21114b C0B21114c refresh clock divided by 40a or 60b or C0c, periodic timer enabled, type 3 address multiplexing scheme, 2 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MCM36800-60/70 MCM36800-60/70 MT16D832-6/7 MT16D832-6/7 MAMR 20B21114a 30B21114b 60B21114c refresh clock divided by 20a or 30b or 60c, periodic timer enabled, type 3 address multiplexing scheme, 2 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. a. Assuming 16.67 MHz BRGCLK. b. Assuming 25MHz BRGCLK c. For 50MHz BRGCLK 24 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS TABLE 3-4. UPMA Initializations for 60nsec DRAMs @ 50MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C 0 8FFFEC24 8FFFEC24 8FFFEC24 8FFFEC24 8FAFCC24 8FAFCC24 8FAFCC24 8FAFCC24 C0FFCC84 C0FFCC84 33FFCC07 33FFCC07 1 0FFFEC04 0FFFEC04 0FFFEC04 0FFFEC04 0FAFCC04 0FAFCC04 0FAFCC04 0FAFCC04 00FFCC04 00FFCC04 X 2 0CFFEC04 0CFFEC04 08FFEC04 08FFEC04 0CAFCC00 0CAFCC00 0CAFCC00 0CAFCC00 07FFCC04 07FFCC04 X 3 00FFEC04 00FFEC04 00FFEC0C 00FFEC0C 11BFCC47 11BFCC47 03AFCC4C 03AFCC4C 3FFFCC06 3FFFCC06 X 4 00FFEC00 00FFEC00 03FFEC00 03FFEC00 X 0CAFCC00 0CAFCC00 FFFFCC85 FFFFCC85 5 37FFEC47 37FFEC47 00FFEC44 00FFEC44 X 03AFCC4C 03AFCC4C FFFFCC05 FFFFCC05 6 X 00FFCC08 00FFCC08 X 0CAFCC00 0CAFCC00 X 7 X 0CFFCC44 0CFFCC44 X 03AFCC4C 03AFCC4C X Contents @ Offset + 8 0CAFCC00 0CAFCC00 X 9 03FFEC00 03FFEC00 33BFCC4F 33BFCC4F X A 00FFEC44 00FFEC44 X X B 00FFCC00 00FFCC00 X X C 3FFFC847 3FFFC847 X D X X E X X F Release 1.4a 00FFEC0C 00FFEC0C X X 25 MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS TABLE 3-5. UPMA Initializations for 70nsec DRAMs @ 50MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM 0 8 18 20 30 3C 0 8FFFCC24 8FFFCC24 8FFFCC24 8FFFCC24 8FAFCC24 8FAFCC24 8FAFCC24 8FAFCC24 E0FFCC84 E0FFCC84 33FFCC07 33FFCC07 1 0FFFCC04 0FFFCC04 0FFFCC04 0FFFCC04 0FAFCC04 0FAFCC04 0FAFCC04 0FAFCC04 00FFCC04 00FFCC04 X 2 0CFFCC04 0CFFCC04 0CFFCC04 0CFFCC04 0CAFCC00 0CAFCC00 0CAFCC00 0CAFCC00 00FFCC04 00FFCC04 X 3 00FFCC04 00FFCC04 00FFCC04 00FFCC04 11BFCC47 11BFCC47 03AFCC4C 03AFCC4C 0FFFCC04 0FFFCC04 X 4 00FFCC00 00FFCC00 00FFCC08 00FFCC08 X 0CAFCC00 0CAFCC00 7FFFCC06 7FFFCC06 5 37FFCC47 37FFCC47 0CFFCC44 0CFFCC44 X 03AFCC4C 03AFCC4C FFFFCC85 FFFFCC85 6 X 00FFEC0C 00FFEC0C X 0CAFCC00 0CAFCC00 FFFFCC05 FFFFCC05 7 X 03FFEC00 03FFEC00 X 03AFCC4C 03AFCC4C X Contents @ Offset + 8 0CAFCC00 0CAFCC00 X 9 00FFCC08 00FFCC08 33BFCC47 33BFCC47 X A 0CFFCC44 0CFFCC44 X X B 00FFEC04 00FFEC04 X X C 00FFEC00 00FFEC00 X D 3FFFEC47 3FFFEC47 X E X X F 26 00FFEC44 00FFEC44 X X Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS TABLE 3-6. UPMA Initializations for 60nsec EDO DRAMs @ 50MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C 0 8FFBEC24 8FFBEC24 8FFFEC24 8FFFEC24 8FFFCC24 8FFFCC24 8FFFCC24 8FFFCC24 C0FFCC84 C0FFCC84 33FFCC07 33FFCC07 1 0FF3EC04 0FF3EC04 0FFBEC04 0FFBEC04 0FEFCC04 0FEFCC04 0FEFCC04 0FEFCC04 00FFCC04 00FFCC04 X 2 0CF3EC04 0CF3EC04 0CF3EC04 0CF3EC04 0CAFCC00 0CAFCC00 0CAFCC00 0CAFCC00 07FFCC04 07FFCC04 X 3 00F3EC04 00F3EC04 00F3EC0C 00F3EC0C 11BFCC47 11BFCC47 03AFCC4C 03AFCC4C 3FFFCC06 3FFFCC06 X 4 00F3EC00 00F3EC00 0CF3EC00 0CF3EC00 X 0CAFCC00 0CAFCC00 FFFFCC85 FFFFCC85 5 37F7EC47 37F7EC47 00F3EC4C 00F3EC4C X 03AFCC4C 03AFCC4C FFFFCC05 FFFFCC05 6 X 0CF3EC00 0CF3EC00 X 0CAFCC00 0CAFCC00 X 7 X 00F3EC4C 00F3EC4C X 03AFCC4C 03AFCC4C X Contents @ Offset + 8 0CAFCC00 0CAFCC00 X 9 00F3EC44 00F3EC44 33BFCC4F 33BFCC4F X A 03F3EC00 03F3EC00 X X B 3FF7EC47 3FF7EC47 X X C X X D X X E X X F Release 1.4a 0CF3EC00 0CF3EC00 X X 27 MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS TABLE 3-7. UPMA Initializations for 70nsec EDO DRAMs @ 50MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM 0 8 18 20 30 3C 0 8FFBCC24 8FFBCC24 8FFFCC24 8FFFCC24 8FFFCC24 8FFFCC24 8FFFCC24 8FFFCC24 E0FFCC84 E0FFCC84 33FFCC07 33FFCC07 1 0FF3CC04 0FF3CC04 0FFBCC04 0FFBCC04 0FEFCC04 0FEFCC04 0FEFCC04 0FEFCC04 00FFCC04 00FFCC04 X 2 0CF3CC04 0CF3CC04 0CF3CC04 0CF3CC04 0CAFCC00 0CAFCC00 0CAFCC00 0CAFCC00 00FFCC04 00FFCC04 X 3 00F3CC04 00F3CC04 00F3CC0C 00F3CC0C 11BFCC47 11BFCC47 03AFCC4C 03AFCC4C 0FFFCC04 0FFFCC04 X 4 00F3CC00 00F3CC00 03F3CC00 03F3CC00 X 0CAFCC00 0CAFCC00 7FFFCC04 7FFFCC04 5 37F7CC47 37F7CC47 00F3CC44 00F3CC44 X 03AFCC4C 03AFCC4C FFFFCC86 FFFFCC86 6 X 00F3EC0C 00F3EC0C X 0CAFCC00 0CAFCC00 FFFFCC05 FFFFCC05 7 X 0CF3EC00 0CF3EC00 X 03AFCC4C 03AFCC4C X Contents @ Offset + 8 00F3EC4C 00F3EC4C 0CAFCC00 0CAFCC00 X 9 03F3EC00 03F3EC00 33BFCC47 33BFCC47 X A 00F3EC44 00F3EC44 X X B 00F3CC00 00F3CC00 X X C 33F7CC47 33F7CC47 X D X X E X X F X X TABLE 3-8. Memory Controller Initializations For 25Mhz Register BR0 28 Device Type All Flash supported. SIMMs Init Value [hex] 02800001 Description Base at 2800000, 32 bit port size, no parity, GPCM Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS TABLE 3-8. Memory Controller Initializations For 25Mhz Register OR0 Device Type Init Value [hex] Description MCM29F020-90 MCM29F020-90 FFE00D20 FFE00D20 2MByte block size, all types access, CS early negate, 2 w.s. MCM29F040-90 MCM29F040-90 SM732A1000A-9 SM732A1000A-9 FFC00D20 FFC00D20 4MByte block size, all types access, CS early negate, 2 w.s. MCM29F080-90 MCM29F080-90 SM732A2000-9 SM732A2000-9 FF800920 FF800920 8MByte block size, all types access, CS early negate, 2 w.s., Timing relax MCM29F020-12 MCM29F020-12 FFE00D30 FFE00D30 2MByte block size, all types access, CS early negate, 3 w.s. MCM29F040-12 MCM29F040-12 SM732A1000A-12 SM732A1000A-12 FFC00D30 FFC00D30 4MByte block size, all types access, CS early negate, 3 w.s. MCM29F080-12 MCM29F080-12 SM732A2000-12 SM732A2000-12 FF800930 FF800930 8MByte block size, all types access, CS early negate, 3 w.s. BR1 BCSR 02100001 Base at 2100000, 32 bit port size, no parity, GPCM OR1 BCSR FFFF8110 FFFF8110 32 KByte block size, all types access, CS early negate, 1 w.s. BR2 All Dram Supported 00000081 Base at 0, 32 bit port size, no parity, UPMA OR2 MCM36100/200-60/70 MCM36100/200-60/70 FFC00800 FFC00800 4MByte block size, all types access, initial address multiplexing according to AMA. MCM36400/800-60/70 MCM36400/800-60/70 MT8/16D432/832X-6/7 MT8/16D432/832X-6/7 FF000800 FF000800 16MByte block size, all types access, initial address multiplexing according to AMA. MCM36200-60/70 MCM36200-60/70 00400081 Base at 400000, 32 bit port size, no parity, UPMA MCM36800-60/70 MCM36800-60/70 MT16D832X-6/7 MT16D832X-6/7 01000081 Base at 1000000, 32 bit port size, no parity, UPMA MCM36200-60/70 MCM36200-60/70 FFC00800 FFC00800 4MByte block size, all types access, initial address multiplexing according to AMA MCM36800-60/70 MCM36800-60/70 MT16D832X-6/7 MT16D832X-6/7 FF000800 FF000800 16MByte block size, all types access, initial address multiplexing according to AMA. 0400 Divide by 16 (decimal) BR3a OR3 MPTPR Release 1.4a All Dram Supported SIMMs SIMMs 29 MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS TABLE 3-8. Memory Controller Initializations For 25Mhz Register MAMR Device Type Init Value [hex] Description MCM36100-60/70 MCM36100-60/70 60A01114 60A01114 refresh clock divided by 60, periodic timer enabled, type 2 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MCM36200-60/70 MCM36200-60/70 30A01114 30A01114 refresh clock divided by 30, periodic timer enabled, type 2 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MCM36400-60/70 MCM36400-60/70 MT8D432X-6/7 MT8D432X-6/7 60B01114 60B01114 refresh clock divided by 60, periodic timer enabled, type 3 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. MCM36800-60/70 MCM36800-60/70 MT16D832-6/7 MT16D832-6/7 30B01114 30B01114 refresh clock divided by 30, periodic timer enabled, type 3 address multiplexing scheme, 1 cycle disable timer, GPL4 disabled for data sampling edge flexibility, 1 loop read, 1 loop write, 4 beats refresh burst. a. BR3 is not initialized for 36100 or 36400 DRAM SIMMs. 30 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS TABLE 3-9. UPMA Initializations for 60nsec DRAMs @ 25MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C 0 0FFFCC04 0FFFCC04 0FFFCC24 0FFFCC24 0FAFCC24 0FAFCC24 0FAFCC04 0FAFCC04 80FFCC84 80FFCC84 33FFCC07 33FFCC07 1 08FFCC00 08FFCC00 08FFCC00 08FFCC00 08AFCC00 08AFCC00 08AFCC00 08AFCC00 13FFCC04 13FFCC04 X 2 33FFCC47 33FFCC47 03FFCC4C 03FFCC4C 3FBFCC47 3FBFCC47 01AFCC48 01AFCC48 FFFFCC87 FFFFCC87 X 3 X 08FFCC00 08FFCC00 X 08AFCC44 08AFCC44 FFFFCC05 FFFFCC05 X 4 X 03FFCC4C 03FFCC4C X 0FAFCC08 0FAFCC08 X 5 X 08FFCC00 08FFCC00 X 08AFCC44 08AFCC44 X 6 X 03FFCC4C 03FFCC4C X 0CAFCC08 0CAFCC08 X 7 X 08FFCC00 08FFCC00 X 38BFCC46 38BFCC46 X Contents @ Offset + 8 FFFFCC45 FFFFCC45 X 9 X X X A X X X B X X X C X X D X X E X X F Release 1.4a 33FFCC47 33FFCC47 X X 31 MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS TABLE 3-10. UPMA Initializations for 70nsec DRAMs @ 25MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM 0 8 18 20 30 3C 0 0FFFEC04 0FFFEC04 0FFFCC24 0FFFCC24 0FAFCC04 0FAFCC04 0FAFCC04 0FAFCC04 C0FFCC84 C0FFCC84 33FFCC07 33FFCC07 1 08FFEC04 08FFEC04 0FFFCC04 0FFFCC04 08AFCC00 08AFCC00 0CAFCC00 0CAFCC00 01FFCC04 01FFCC04 X 2 00FFEC00 00FFEC00 08FFCC00 08FFCC00 3FBFCC47 3FBFCC47 01AFCC4C 01AFCC4C 7FFFCC86 7FFFCC86 X 3 3FFFEC47 3FFFEC47 03FFCC4C 03FFCC4C X 0CAFCC00 0CAFCC00 FFFFCC05 FFFFCC05 X 4 X 08FFCC00 08FFCC00 X 01AFCC4C 01AFCC4C X 5 X 03FFCC4C 03FFCC4C X 0CAFCC00 0CAFCC00 X 6 X 08FFCC00 08FFCC00 X 01AFCC4C 01AFCC4C X 7 X 03FFCC4C 03FFCC4C X 0CAFCC00 0CAFCC00 X Contents @ Offset + 8 31BFCC43 31BFCC43 X 9 33FFCC47 33FFCC47 X X A X X X B X X X C X X D X X E X X F 32 08FFCC00 08FFCC00 X X Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS TABLE 3-11. UPMA Initializations for 60nsec EDO DRAMs @ 25MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset in UPM 0 8 18 20 30 3C 0 0FFBCC04 0FFBCC04 0FFBCC04 0FFBCC04 0FEFCC04 0FEFCC04 0FEFCC04 0FEFCC04 80FFCC84 80FFCC84 33FFCC07 33FFCC07 1 0CF3CC04 0CF3CC04 09F3CC0C 09F3CC0C 08AFCC04 08AFCC04 08AFCC00 08AFCC00 13FFCC04 13FFCC04 X 2 00F3CC00 00F3CC00 09F3CC0C 09F3CC0C 00AFCC00 00AFCC00 07AFCC48 07AFCC48 FFFFCC87 FFFFCC87 X 3 33F7CC47 33F7CC47 09F3CC0C 09F3CC0C 0FBFCC47 0FBFCC47 08AFCC48 08AFCC48 FFFFCC05 FFFFCC05 X 4 X 08F3CC00 08F3CC00 X 08AFCC48 08AFCC48 X 5 X 3FF7CC47 3FF7CC47 X 39BFCC47 39BFCC47 X 6 X X X X 7 X X X X Contents @ Offset + 8 X 9 X X A X X X B X X X C X X D X X E X X F Release 1.4a X X X 33 MPC860ADS MPC860ADS, Revision B - User's Manual OPERATING INSTRUCTIONS TABLE 3-12. UPMA Initializations for 70nsec EDO DRAMs @ 25MHz Cycle Type Single Read Burst Read Single Write Burst Write Refresh Exception Offset In UPM 0 8 18 20 30 3C 0 0FFBCC04 0FFBCC04 0FFBEC04 0FFBEC04 0FEFCC04 0FEFCC04 0FEFCC04 0FEFCC04 C0FFCC84 C0FFCC84 33FFCC07 33FFCC07 1 0CF3CC04 0CF3CC04 08F3EC04 08F3EC04 08AFCC04 08AFCC04 08AFCC00 08AFCC00 01FFCC04 01FFCC04 X 2 00F3CC00 00F3CC00 03F3EC48 03F3EC48 00AFCC00 00AFCC00 07AFCC4C 07AFCC4C 7FFFCC86 7FFFCC86 X 3 33F7CC47 33F7CC47 08F3CC00 08F3CC00 0FBFCC47 0FBFCC47 08AFCC00 08AFCC00 FFFFCC05 FFFFCC05 X 4 X 0FF3CC4C X 07AFCC4C 07AFCC4C X 5 X 08F3CC00 08F3CC00 X 08AFCC00 08AFCC00 X 6 X 0FF3CC4C X 07AFCC4C 07AFCC4C X 7 X 08F3CC00 08F3CC00 X 08AFCC00 08AFCC00 X Contents @ Offset + 8 37BFCC47 37BFCC47 X 9 X X X A X X X B X X X C X X D X X E X X F 34 3FF7CC47 3FF7CC47 X X Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description 4 - Functional Description In this chapter the various modules combining the MPC860ADS MPC860ADS are described to their design details. 4·1 MPC860 MPC860 The MPC860 MPC860 runs @ frequencies from 15A - 50 MHz and is buffered from the rest of the board's logic - this to allow for external hardware development via dedicated expansion connectors. P6, P9, P10 & P12. 4·2 Reset & Reset - Configuration There are several reset sources on the MPCADS: 1) Keep Alive Power-On Reset 2) Main Power On Reset 3) Manual Soft-Reset 4) Manual Hard-Reset 5) Debug Port Soft-Reset 6) Debug Port Hard-Reset 7) MPC Internal Sources. 4·2·1 Keep Alive Power-On Reset The Keep Alive Power - On Reset on the MPCADS is generated by a dedicated voltage detector made by Seiko the S-8051HN-CD-X S-8051HN-CD-X with detection voltage range of 1.795 to 2.005V. This voltage detector is connected to the Keep Alive power input of the MPC and during keep alive power-on or when there is a voltage drop of that input into the above range and J1 is set accordingly (see 2·3·3 "Power-On Reset Source Selection" on page 11), Power-On Reset is generated, i.e., PORESET* input of the MPC is asserted for a period of approximately 4 sec. When PORESET* is asserted to the MPC, the Power-On reset configuration is made available to MPC. See 4·2·6·1 "Power - On Reset Configuration" on page 36. 4·2·2 Main Power - On Reset The Main power on reset generates HARD reset and optionally PON reset, when the MAIN 3.3V bus is powered-on or there is a drop of voltage level over this bus. The reset is generated by a dedicated voltage detector made by Seiko the S-8052ANY-NH-X S-8052ANY-NH-X with detection voltage range of 2.595 to 2.805V. When regular power-on reset conditions exist, the HRESET* signal of the MPC is asserted for a period of approximately 4 sec. In addition, if J1 is set accordingly (see 2·3·3 "Power-On Reset Source Selection" on page 11), Power-On Reset is generated, i.e., PORESET* input of the MPC is asserted for a period of approximately 4 sec. When HRESET signal is asserted, the HARD reset configuration is made available to the MPC. See 4·2·6·2 "Hard Reset Configuration" on page 36. When PORESET* is asserted to the MPC, the Power-On reset configuration is made available to MPC. See 4·2·6·1 "Power - On Reset Configuration" on page 32. 4·2·3 Manual Soft Reset To support resident application development and debuggers, a soft reset push-button is provided. Depressing that button, asserts the SRESET* pin of the MPC, generating a SOFT RESET sequence. This A. The MPC's PLL minimal frequency is 15MHz. Below that, the Low-Power-Divider must be incorporated, during the operation of which, CLKOUT is no longer 50% duty-cycle, distorting UPM timing. Release 1.4a 35 MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description button is debounced to avoid spikes over the SRESET* line. When SRESET* is signal is asserted, the SOFT reset configuration is made available to the MPC. See 4·2·6·3 "Soft Reset Configuration" on page 37. 4·2·4 Manual Hard Reset To support resident application development, a hard reset push-button is providedA. When the soft reset push-button is depressed in conjunction with the ABORT push-button, the HRESET* line is asserted, generating a HARD RESET sequence. The button sharing is for economy and board space saving and does not effect functionality in any way. 4·2·5 MPC Internal Sources Since the HRESET* and SRESET* lines of the MPC are open-drain and the on-board reset logic drives these lines with open-drain gates, the correct operation of the internal reset sources of the MPC is facilitated. As a rule, an internal reset source will assert HRESET* and / or SRESET* for a minimum time of 512 system clocks. It is beyond the scope of this document to describe these sources, however Debug-Port Soft / Hard Resets which are part of the development support systemB, are regarded as such. 4·2·6 Reset Configuration During reset sequences to their kinds, the MPC device samples the state of some external pins to determine its operation modes and pin configuration. There are 3 kinds of reset levels to the MPC, each level having its own configuration sampled: 1) Power - On Reset configuration 2) Hard Reset configuration 3) Soft Reset Configuration. 4·2·6·1 Power - On Reset Configuration Just before PORESET* is negated by the external logic, the power-on reset configuration which include the MODCK(1:2) pins is sampled. These pins determine the clock operation mode of the MPC. Two clock modes are supported within the MPC860ADS MPC860ADS: 1) 1:5 PLL operation via on-board clock generator. In this mode MODCK(1:2) are driven with '11' duringC power on reset. 2) 1:513 PLL operation via on-board clock generator. In this mode MODCK(1:2) are driven with '00'. during power-on reset. 4·2·6·2 Hard Reset Configuration During HARD reset sequence, when RSTCONF* pin is asserted, the data bus state is sampled to acquire the MPC's hard reset configuration. The reset configuration word is driven by BCSR0 register, defaults of which are set during power-on reset. The BCSR0 drives the half configuration word, i.e., data bits D(0:15) in which the reserved bits are designated RSRVxx. If the hard-reset configuration is to be changed D, BCSR0 may be written with new values, which become valid after HARD reset is applied to the ADS. On the MPCADS, the RSTCONF* line is always driven during HARD reset, i.e., no use is possible with the MPC's internal HARD reset configuration defaults. To allow user programmable, full-word hard reset configuration, i.e., D(0:31) lines being driven during HARD reset, an option is provided for Flash memory driven hard reset configuration. I.e., the desired hard- A. It is not a dedicated button. B. And therefore mentioned. C. The MODCK lines are in fact driven longer - by HRESET~ line. D. With respect the ADS's power-on defaults. 36 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description reset configuration word is taken from the first word of the Flash memory. During hard-reset this word drives the data bus to set the desired configuration. To support this option, CS0~ of the MPC should be assertedA during HARD reset and the ADDRESS lines should be driven low. The selection of this option is done via BCSR1. See TABLE 4-6. "BCSR1 Description" on page 50. The system parameters to which BCSR0 defaults during power-on reset and are driven at hard-reset are listed below: 1) Arbitration: internal arbitration is selected. 2) Interrupt Prefix: The internal default is interrupt prefix at 0xFFF00000. It is overridden to provide interrupt prefix at address 0, which is located within the DRAM. 3) Boot Disable: Boot is enabled. 4) Boot Port Size: 32 bit boot port size is selected. 5) Initial Internal Space Base: Immediately after HARD reset, the internal space is located at $FF000000 FF000000. 6) Debug pins configuration: PCMCIA port B pins become debug support pinsB. 7) Debug port pins configuration. Debug port pins are on the JTAG port. 8) External Bus Division Factor: 1:1 internal to external clocks ratio is selected. 4·2·6·3 Soft Reset Configuration The rising edge of SRESET* is used to configure the development port. Before the negation of SRESET*, DSCKC is sampled to determine for debug-mode enable / disable. After SRESET* is negated, if debug mode was enabled, DSCK is sampled again for debug-mode entry / non-entry. DSDI is used to determine the debug port clock mode and is sampled after the negation of SRESET*.D The Soft Reset configuration is provided by the debug-port controller U7 via the ADI I/F. When an ADI bundle is connected, i.e., a debug station is connected, debug mode is always enabled, while immediate entry is determined by the debug station. When a bundle is not connected to the ADI port, or disconnected from the host computer, debug mode is disabled by means of pulling DSCK low via a pull-down resistor. 4·3 Local Interrupter The only external interrupt applied to the MPC via its interrupt controller is the ABORT (NMI), which is generated by a push-button - SW2. When this button is depressed, the NMI input to the MPC is asserted (low). The purpose of this type of interrupt, is support the use of resident debuggers if any is made available to the MPCADS. All other interrupts to the MPC, are generated internally by the MPC's peripherals and by the debug port. To support external (off-board) generation of an NMI, the IRQ0* line which drives the MPC's NMI, is driven by an open-drain gate. This allows for external h/w to also drive this line. If an external h/w indeed does so, it is compulsory that IRQ0* is driven by an open-drain (or open-collector) gate. 4·4 Clock Generator There are 2 ways to clock the MPC on the MPC860ADS MPC860ADS: 1) 3 - 5MHz Clock generator connected to CLK4IN input. 1:5 PLL mode. A. May be supported on future revisions of the MPC. B. I.e., AT, VF, VFLS. C. DSCK is configured at hard-reset to reside on the JTAG port. D. With parts from the MPC5XX family DSDI is sampled prior (3 system-clock cycles) to the negation of SRESET*, to determine the part's configuration source: internal (default) or external via data bus. Release 1.4a 37 MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description 2) 32.768 KHz crystal resonator via EXTAL-XTAL pair of the MPC, 1:513 initial PLL multiplication factor. The clock generator (1) above, is a 3.3V operated, or 5V operated with 3.3V compatible output. The selection between the above modes is done using switch #4 of DS1. See 2·3·2 "Clock Source Selection" on page 10. See also 4·2·6 "Reset Configuration" on page 36. DS1/4 has dual functionality: it is responsible to the combination driven to the MODCK lines during power-on reset and to the connection of the appropriate capacitor between XFC and VDDSYN lines to match the PLL's multiplication factor. When 1:5 mode is selected, a capacitor of 5nF is connected, while when 1:513 mode is selected a 0.68µF capacitor is connected parallel to it via a TMOS gate. The capacitors' values are calculated to support a wider range of multiplication factors as possible. When mode (2) above is selected, the output of the clock generator is gated from CLK4IN and driven to '0' constantly so that a jitter-free system clock is generated. 4·4·1 SPLL Support Since the SPLL requires quiet supplies, GNDSYN and GNDSYN1have a dedicated ground plane connected only in one point to the global ground plane of the ads. Bypassing capacitors pairs of 0.1µF and 0.01uF are connected as close as possible between VDDSYN and GNDSYN. VDDSYN is filtered from the digital supply using a LC filter with a double pole @ app. 500 hz to provide satisfactoryA attenuation of switching regulators noise over PLL supply lines. 4·5 Buffering As the MPCADS is meant to serve also as a hardware development platform, it is necessary to buffer the MPC from the local bus, so the MPC's capacitive drive capability is not wasted internally and remains available for user's off-board applications via the expansion connectors. Since the total capacitive load over the address lines of all local memory slaves is significant, two parallel sets of buffers are provided for address - a dedicated group for the Flash memory and PCMCIA (U29, U33 & U34) and a dedicated group for the DRAM (part of U30 and U32). Strobe lines are also buffered (U30, U35 & U37) while transceivers are provided for data (U39 - U42). The data transceivers open only if there is an access to a validB board address or during Hard - Reset configurationC. That way data conflicts are avoided in case an off-board memory is read, provided that it is not mapped to an address valid on board. It is the users' responsibility to avoid such errors. 4·6 Chip - Select Generator The memory controller of the MPC is used as a chip-select generator to access on-boardD memories, saving board's area reducing cost, power consumption and increasing flexibility. To enhance off-board application development, memory modules (including the BCSRx) may be disabled via BCSR1E in favor of an external memory connected via the expansion connectors. That way, a CS line may be used off-board via the expansion connectors, while its associated local memory is disabled. When a CS region is disabled via BCSR1, the local data transceivers are not open during access to that A. Approximately -45dB @ 5KHz. B. An address which is covered in a Chip-Select region and that CS region is enabled via BCSR1. C. To allow a configuration word stored in Flash memory become active. D. And off-board. See further. E. After the BCSR is removed from the local memory map, there is no way to access it but to remove and re-apply power to the ADS. 38 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description region, avoiding possibleA contention over data lines. The MPC's chip-selects assignment to the various memories / registers on the MPCADS are as follows: 1) CS0* - Flash memory 2) CS1* - BCSR 3) CS2* - DRAM Bank 1. 4) CS3* - DRAM Bank 2 (if exists). 5) CS(4:7)* - Unused, user available. 4·7 DRAM The MPC860ADS MPC860ADS is supplied with 4 MBytes of EDO DRAM, with access time of 60 nsec. Support is given to memory capacity from 4 MByte with no parity upto 32MByte with parity. Support is given to and only to the following devices made by Motorola: MCM36100AS60 MCM36100AS60, MCM36100AS70 MCM36100AS70, MCM36100ASG60 MCM36100ASG60, MCM36100ASG70 MCM36100ASG70 MCM36100ASH60 MCM36100ASH60, MCM36100ASH70 MCM36100ASH70, MCM36100ASHG60 MCM36100ASHG60, MCM36100ASHG70 MCM36100ASHG70, MCM36200AS60 MCM36200AS60, MCM36200AS70 MCM36200AS70, MCM36200ASG60 MCM36200ASG60, MCM36200ASG70 MCM36200ASG70, MCM36400AS60 MCM36400AS60, MCM36400AS70 MCM36400AS70, MCM36400ASG60 MCM36400ASG60, MCM36400ASG70 MCM36400ASG70, MCM36400ASH60 MCM36400ASH60, MCM36800S60 MCM36800S60, MCM36800S70 MCM36800S70, MCM36800SG60 MCM36800SG60, MCM36800SG70 MCM36800SG70. MCM36100ASH70 MCM36100ASH70, MCM36100ASHG60 MCM36100ASHG60, MCM36100ASHG70 MCM36100ASHG70 Also supported, are 5V EDO memory SIMMs made by Micron: MT8D132M-6X MT8D132M-6X (4 MByte), MT16D232M6X MT16D232M6X (8 MByte), MT8D432M-6X MT8D432M-6X (16Mbyte), MT16D832M-6X MT16D832M-6X (32 MByte), MT8D432M-7X MT8D432M-7X and MT16D832M6X MT16D832M6X. All dram configurations are supported via the Board Control & Status Register (BCSR), i.e., DRAM size (4M to 32M) and delay (60 / 70 nsec) are read from BCSR2 and the associated registers (including the UPM) are programmed accordingly. Dram timing control is performed by UPMA of the MPC via CS2 (and CS3 for 2-bank SIMM) region(s), i.e., RAS and CAS signals' generation, during normalB access as well as during refresh cycles and the necessary address multiplexingC are performed using UPM1. CS2* and CS3* signals are buffered from the DRAM and each split to 2 to overcome the capacitive load over the dram SIMM RAS lines. The programming of UPM1 and other associated registers to perform that task is described in 3·4·1 "Memory Controller Registers Programming" on page 22. The DRAM module may enabled / disabled at any time by writing the DRAMEN~ bit in BCSR1. See TABLE 4-6. "BCSR1 Description" on page 50. 4·7·1 DRAM 16 Bit Operation To enhance evaluation capabilities, support is given to 16-bit and 32-bit data bus width. That way users can tailor dram configuration, to get best fit to their application requirements. When the DRAM is in 16 bit mode, half of it is not used, i.e., memory portion that is connected to data lines D(16:31) is not used at all. To configure the DRAM for 16 bit data bus width operation, the following steps should be taken: 1) Set the Dram_Half_Word bit in BCSR1 to Half-Word. See TABLE 4-6. "BCSR1 Description" on page 50 2) The Port Size bits of BR2~ (and of BR3~ for a 2-bank DRAM simm) should be set to 16 bits. A. During read cycles. B. Normal i.e.: Single Read, Single Write, Burst Read & Burst Write. C. Taking into account support for narrower bus widths. Release 1.4a 39 MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description 3) The AM bits in OR2 register should be set to 1/2 of the nominal single-bank DRAM simm volume or to 1/4 of the nominal dual-bank DRAM simm volume. If a Dual-Bank DRAM simm is being used: 4) The Base-Address bits in BR3 register should be set to DRAM_BASE + 1/4 Nominal_Volume, that is, if a contiguous block of memory is desired. 5) The AM bits of OR3 register, should be set to 1/4 Nominal_Volume. If the above is executed out of running code, than this code should not reside on the DRAM while executing, otherwise, erratic behavior is likely to be demonstrated, resulting in a system crash. 4·7·2 DRAM Performance Figures The performance figures for the dram as reflected from the initializations given in 3·4·1 "Memory Controller Registers Programming" on page 22 are shown in TABLE 4-1. "Regular DRAM Performance Figures" on page 40 and in TABLE 4-2. "EDO DRAM Performance Figures" on page 40. TABLE 4-1. Regular DRAM Performance Figures Number of System Clock Cycles System Clock Frequency [MHz] 50 DRAM Delay [nsec] 25 60 70 60 70 Single Read 6 6 3 4 Single Write 4 4 3 3 Burst Read 6,2,3,2 6,3,2,3 3,2,2,2 4,2,2,2 Burst Write 4,2,2,2 4,2,2,2 3,1,2,2 3,2,2,2 Refresh 21a b 25a b 13a b 13a b a. Four-beat refresh burst. b. Not including arbitration overhead. TABLE 4-2. EDO DRAM Performance Figures Number of System Clock Cycles System Clock Frequency [MHz] 50 DRAM Delay [nsec] 25 60 70 60 70 Single Read 6 3 4 Single Write 4 4 2 3 Burst Read 6,2,2,2 6,3,2,2 3,1,1,1 4,1,2,2 Burst Write 4,2,2,2 4,2,2,2 3,1,1,1 3,2,2,2 Refresh 40 6 21a b 25a b 13a b 13a b Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description a. Four-beat refresh burst. b. Not including arbitration overhead. 4·7·3 Refresh Control The refresh to the dram is a CAS before RAS refresh, which is controlled by UPMA as well. The refresh logic is clocked by the BRG clock which is not influenced by the low-power divider. FIGURE 4-1 Refresh Scheme BRG Clock PTP PTA UPMA DRAM BANKS As seen in FIGURE 4-1 "Refresh Scheme" above, the BRG clock is twice divided: once by the PTP (Periodic Timer Prescaler) and again by another prescaler - the PTA, dedicated for each UPM. If there are more than one dram banks, than refresh cycles are performed for consecutive banks, therefore, refresh should be made faster. The formula for calculation of the PTA is given below: PTA = Refresh_Period X Number_Of_Beats_Per_Refresh_Cycle Number_Of_Rows_To_Refresh X T_BRG X MPTPR X Number_Of_Banks Where: · · · PTA - Periodic Timer A filed in MAMR. The value of the 2'nd divider. Refresh_Period is the time (usually in msec) required to refresh a dram bank Number_Of_Beats_Per_Refresh_Cycle: using the UPM looping capability, it is possible to perform more than one refresh cycle per refresh burst (in fact upto 16). · Number_Of_Rows_To_Refresh: the number of rows in a dram bank · T_BRG: the cycle time of the BRG clock · MPTPR: the value of the periodic timer prescaler (2 to 64) · Number_Of_Banks: number of dram banks to refresh. If we take for example a MCM36200 MCM36200 SIMM which has the following data: · Refresh_Period = 16 msec · Number_Of_Beats_Per_Refresh_Cycle: on the ADS it is 4. · Number_Of_Rows_To_Refresh = 1024 · T_BRG = 40 nsec (1/2 system clock @ 50 Mhz) · MPTPR arbitrarily chosen to be 8 · Number_Of_Banks = 2 for that SIMM If we assign the figures to the PTA formula we get the value of PTA should be 97 decimal or 61 hex. The programming of the appropriate registers and UPM's memory, controlling this function, is shown in 3·4·1 "Memory Controller Registers Programming" on page 22. Release 1.4a 41 MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description 4·7·4 Variable Bus-Width Control Since a port's width determines its address connections, i.e., the number of address lines required for byteselection varies (1 for 16-bit port and 2 for 32-bit port) according to the port's width, it is necessary to change address connections to a memory port if its width is to be changed. E.g.: if a certain memory is initially configured as a 32-bit port, the list significant address line which is connected to that memory's A0 line should be the MPC's ADD29 ADD29. Now, if that port is to be reconfigured as a 16-bit port, the LS address line becomes ADD30 ADD30. If a linearA address scheme is to be maintained, all address lines connected to that memory are to be shifted one bit, this obviously involves extensive multiplexing (passive or active). If linear addressing scheme is not a must, than only minimal multiplexing is required to support variable port width. In TABLE 4-3. "DRAM ADDRESS CONNECTIONS" below, the MPCADS's address connection scheme is presented: TABLE 4-3. DRAM ADDRESS CONNECTIONS Width 16 - Bit Depth Dram ADD 32 - Bit Depth 4M 1M 4M 1M A0 BA29 BA29 BA29 BA29 A1 BA28 BA28 BA28 BA28 A2 BA27 BA27 BA27 BA27 A3 BA26 BA26 BA26 BA26 A4 BA25 BA25 BA25 BA25 A5 BA24 BA24 BA24 BA24 A6 BA23 BA23 BA23 BA23 A7 BA22 BA22 BA22 BA22 A8 BA21 BA21 BA21 BA21 A9 BA20 BA20 BA20 BA30 A10 BA19 BA30 As can seen from the table above, most of the address lines remain fixed while only 2 lines (the shaded cells) need switching. The switching scheme is shown in FIGURE 4-2 "DRAM Address Lines' Switching" on page 43. The switches on that figure are implemented by active multiplexers controlled by the BCSR1/ Dram_Half_Word* bit. A. Consequent addresses lead to adjacent memory cells 42 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description FIGURE 4-2 DRAM Address Lines' Switching DRAM BA(21:29) A(0:8) BA20 A9 BA30 BA19 A10 BA30 4·8 Flash Memory The MPC860ADS MPC860ADS support Flash non-volatile memory SIMMs of the following types: MCM29F020 MCM29F020, MCM29F040 MCM29F040 and MCM29F080 MCM29F080, volume of which is 2Mbytes, 4Mbytes and 8Mbytes correspondingly. These devices are internally composed of 1, 2 or 4 banks of 4 Am29F040 Am29F040 devices. The flash SIMM (U15) resides on an 80 pin SIMM socket. Also supported are SMART's SM732A1000A SM732A1000A 4Mbytes (1Meg X 32) or SM732A2000 SM732A2000 (2 X 1Meg X 32). To minimize use of MPC's chip-select lines, only one chip-select line (CS0~) is used to select the flash as a whole, while distributing chip-select lines among the internal banks is done via on-board programmable logic, according to the Presence-Detect lines of the Flash SIMM inserted to the ADS. FIGURE 4-3 Flash Memory SIMM Architecture Flash Presence-Detect Lines ADD F_CS1~ M29F040 M29F040 or 1M X8 M29F040 M29F040 or 1M X 8 M29F040 M29F040 or 1M X 8 F_CS2~ M29F040 M29F040 or 1M X 8 M29F040 M29F040 or 1M X 8 M29F040 M29F040 or 1M X 8 M29F040 M29F040 or 1M X 8 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 CS0~ M29F040 M29F040 or 1M X 8 M29F040 M29F040 M29F040 M29F040 M29F040 M29F040 U09 F_CS3~ F_CS4~ DATA MCM29F020 MCM29F020 SM732A1000A SM732A1000A MCM29F040 MCM29F040 SM732A2000 SM732A2000 MCM29F080 MCM29F080 The access time of the Flash memory supplied with the ADS is 120 nsec, however, 90 nsec devices may Release 1.4a 43 MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description be used. Reading the delay section of the Flash SIMM Presence-Detect lines, the debugger establishes (via OR0) the correct number of wait-states (considering 50MHz system clock frequency). The Motorola parts which are built of MC29F0X0 MC29F0X0 devices are 5V programmable, i.e., there is no need for external programming voltage and the flash may be written almostA as a regular memory. The SMART parts however, require 12V ± 0.5% programming voltage to be applied. If on-boards programming of such device is required, a 12V supply needs to be connected to the ADS. See 2·4·5 "P8: +12V Power Supply Connection" on page 15. The control over the flash is done using the GPCM and a dedicated CS0~ region, controlling the whole bank. During hard - reset initializations, the debugger reads the Flash Presence-Detect lines via BCSR2 and decided how to program BR0 & OR0 in which the size and the delay of the region are determined. The performance of the flash memory is shown in TABLE 4-4. "Flash Memory Performance Figures" below: TABLE 4-4. Flash Memory Performance Figures Number of System Clock Cycles System Clock Frequency [MHz] 50 25 Flash Delay [nsec] 90 120 90 120 Read / Writea Access [Clocks] 8 10 4 5 a. The figures in the table refer to the actual write access. The write operation continues internally and the device has to be polled for completion. The programming of the associated registers is shown in 3·4·1 "Memory Controller Registers Programming" on page 22. The Flash module may disabled / enabled at any time by writing '1' / '0' the FlashEn~ bit in BCSR1. 4·9 Ethernet Port An Ethernet port with T.P. (10-Base-T) I/F is provided on the MPC860ADS MPC860ADS. This port resides over SCC1of the MPC. Use is done with Motorola's MC68160 MC68160 EEST (Enhanced Ethernet Serial Transceiver) to mediate between the SCC and the Ethernet medium. To allow external use of SCC1, its pins appear at the expansion connectors and the ethernet transceiver may be Disabled / Enabled at any time by writing '1' / '0' to the EthEn~ bit in BCSR1. The EEST is configured constantly to Twisted Pair I/F with automatic polarity correction enabled. There are few control lines which control the EEST function and are driven by MPC's parallel I/O lines: 1) TPSQEL~ - Twisted Pair Signal Quality Error Test Enable. This active-low signal enables testing of the internal TP collision detect circuitry after each transmit to the TP media. It is connected to PC6B of the MPC and should be driven to '1' during normal operation. A. A manufacturer specific dedicated programming algorithm should be implemented during flash programming. B. After Hard reset this line wakes-up as Tri-state. For proper operation it should be initialized as Output. 44 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description 2) TPFLDL~ - Twisted Pair Full Duplex Mode Select. This active low signal allows simultaneous transmit and receive over the twisted pair lines without indicated collision. This signal is connected to PC5B of the MPC and should be driven to '0' during normal operation. 3) ETHLOOP - Diagnostic Loopback. This active high signal puts the EEST in diagnostic loopback mode, regardless of the I/F type it is configured to. This line is connected to PC4B of the MPC and should be driven to '0' during normal operation. For additional information on the EEST refer to the "MC68160 MC68160 Technical Data" document. 4·10 Infra - Red Port An infra-red communication port is provided with the MPCADS - the Temic's TFDS 3000 integrated transceiver, which incorporates both the receiver and transmitter optical devices with the translating logic. This port resides on SCC2 of the MPC. This device conforms to the IRDA standard, which is supported by the MPC allowing for glueless connection between the TFDS3000 TFDS3000 and the MPC. To allow SCC2's off-board use, the infra-red transceiver may be disabled / enabled at any time, by writing '1' / '0' to the IrdEn~ bit in BCSR1. 4·11 RS232 RS232 Ports To assist user's applications and to provided convenient communication channel with a host computer, 2 RS232 RS232 ports are provided via SMC1 and SMC2 ports. Support is given upto 19200 baud rate via an RS232 RS232 transceiver. Use is done with MC145707 MC145707 transceiver which generates RS232 RS232 levels internally using a single 5V supply and is equipped with OE and shutdown mode. When either RS232EN RS232EN_1 bit or RS232EN RS232EN_2 bit in BCSR1 are asserted , their associated transceiver is enabled. When negated, the associated transceiver enters standby mode, in which the receiver outputs are tri-stated, enabling use of the associated SMC port pins, off-board via the expansion connectors. In order of saving board space, a stacked 9 pins, female D-Type connector is used, both configured to be directly (via a flat cable) connected to a standard IBM-PC like RS232 RS232 connector. FIGURE 4-4 RS232 RS232 Serial Port 1 or 2 Connector DCD TX RX DTR GND 4·11·1 1 2 3 4 5 6 7 8 9 DSR RTS CTS N.C. RS-232 RS-232 Port 1 or 2 Signal Description In the list below, the directions 'I', 'O', and 'I/O' are relative to the MPCADS board. (I.e. 'I' means input to the MPCADS) · · · · CD ( O ) - Data Carrier Detect. This line is always asserted by the MPCADS. TX ( O ) - Transmit Data. RX ( I ) - Receive Data. DTR ( I ) - Data Terminal Ready. This signal may be used by the software in the MPCADS to Release 1.4a 45 MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description · · · 4·12 detect if a terminal is connected to the MPCADS board. DSRA ( O ) - Data Set Ready. This line is always asserted by the MPCADS. RTS ( I ) - Request To Send. This line is not connected on the MPCADS. CTS ( O ) - Clear To Send. This line is always asserted by the MPCADS. PCMCIA Port To enhance PCMCIA i/f development, a dedicated PCMCIA port is provided with the MPCADS. Support is given to 5V only PC-Cards, PCMCIA standard 2.1+ compliant. All the necessary control signals are generated by the MPC itself. To protect MPC signals from external hazards, and to provide sufficient drive capability, a set of buffers and latches is provided over address, data & strobe lines. To conform with the design spirit of the ADS, i.e., making as much as possible MPC resources available for external application development, input buffers are provided for input control signals, controlled by the PCC_EN~ bit in BCSR1, so the PCMCIA port may be Disabled / Enabled at any time, by writing '1' / '0' to that bit. When the PCMCIA channel is disabled, its associated pins are available off-board via the expansion connectors. A loudspeaker (SK1) is provided on board and connected to SPKROUT line of the MPC. The speaker is buffered from the MPC and low-pass filtered. When the PCC_EN~ bit in BCSR1 is negated (high) the speaker buffer is tri-stated so the SPKROUT signal of the MPC may be used for alternate function. 4·12·1 PCMCIA Power Control To support hot-insertionB the socket's power is controlled via a dedicated PCMCIA power controller the LTC1315 LTC1315 made by LINEAR TECHNOLOGY. This device, controlled by BCSR1, switches 12V VPP for card programming and controls gates of external MOSFET transistors, through which the PC Card VCC is switched. When a card is inserted and the channel is enabled via BCSR1, i.e., both of the CD(1:2)* (Card Detect) lines are asserted (low), the status of the voltage select lines VS(1:2)* should be read to determine the PC Card's operation voltage level and then if the PC-Card is found to be 5V operated, the BCSR1 may be written to turn on power (5V only) to the PC Card's VCC. If a 3.3V card is inserted, power should never be switched-on. When a card is being removed from the socket while the channel is enabled via BCSR1, the negation of CD1~ and CD2~ is sensed by the MPC and power supply to the card may be cut. WARNING Any application S/W handling the PCMCIA channel must check the Voltage-Sense lines before Power is applied to the PC-Card. Otherwise if power is applied to a 3.3VOnly card, permanent damage might be inflicted to the PC-Card. The LTC1315 LTC1315 may control power and VPP for 2 PC-Cards. Since there is only one PCMCIA socket on the ADS, the power control lines for the 2'nd socket are used for optional 3.3V supply to the DRAM simm. When the DRMPD5 signal is connected to GND, the DRAM is powered with 3.3V VCC. 4·13 LCD Port The LCD connector is not used on the MPC860ADS MPC860ADS board but is documented for the sake of completeness. A. Since there are only 3 RS232 RS232 transmitters available, DSR will be connected to CD. B. I.e., card insertion when the MPCADS is powered 46 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description FIGURE 4-5 PCMCIA Port Configuration PCMCIA SOCKET PCCVCC Power Logic LTC1315 LTC1315 or equiv. PCMCIA POWER CONTROL From BCSR PCCVPP 1 1 1 5V 12V D[8:15] Data_A[15:8] D[0:7] Data_A[7:0] 8 8 8 8 OE From BCSR 1 PCMCIA_EN R/W 1 CE1_A CE1 1 CE2_A CE2 1 1 WE/PGM WE/PGM OE 2 IORD,IOWR 1 OE RESET_A 1 MPC860 MPC860 IORD,IOWR RESET buffer with OE POE_A A[6:31] 1 1 1 1 2 1 Transparent latch with OE Address_A[25:0] 26 1 1 REG REG ALE_A VDD OE 26 1 VDD WAIT_A, IOIS16 IOIS16_A 2 2 RDY/BSY_A, BVD(1:2)_A 3 VDD VDD 3 5 CD(1:2)_A,VS(1:2)_A, 4 4 1 Release 1.4a SPKROUT LPF 47 MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description 4·14 Board Control & Status Register - BCSR Most of the hardware options on the FADS are controlled or monitored by the BCSR, which is a 32A bit wide read / write register. The BCSR is accessed via the MPC's CS1 region and in fact includes 4 registers: BCSR0 to BCSR3. Since the minimum block size for a CS region is 32KBytes, BCSR0 - BCSR3 are multiply duplicated inside that region. See also 3·3 "MEMORY MAP" on page 21. The following functions are controlled / monitored by the BCSR: 1) MPC's Hard Reset Configuration. 2) Flash Module Enable / Disable 3) Dram Module Enable / Disable 4) Dram port width - 32 bit / 16 bit. 5) Ethernet port Enable / Disable. 6) Infra-Red port Enable / Disable. 7) RS232 RS232 port 1 Enable / Disable. 8) RS232 RS232 port 2 Enable / Disable. 9) BCSR Enable / Disable. 10) Hard_Reset Configuration Source - BCSR0 / FlashB Memory 11) PCMCIA control which include: · Channel Enable / Disable. · PC Card VCC appliance. · PC Card VPP appliance. 12) Dram Type / Size and Delay Identification. 13) Flash Size / Delay Identification. 14) External (off-board) tools identification or S/W option selection switch - DS2 status. Since most of the MPCADS's modules are controlled via the BCSR and since they may be disabled in favor of external hardware, the enable signals for these modules are presented at the expansion connector, so that off- board hardware may be exclusive-or enabled with on-board modules. 4·14·1 BCSR Disable Protection Logic The BCSR itself may be disabled in favor of off-board logic. To avoid accidental disable of the BCSR, an event from which only power down recovers, a protection logic is provided: The BCSR_EN~ bit resides on BCSR1. This bit wakes-up active (low) during power-up and may not be changedC unless BCSR_EN_PROTECT~ bit in BCSR3 is written with '1' previously. After the BCSR_EN_PROTECT~ is written with '1' to unprotect the BCSR_EN~ bit there is only one shot at disabling the BCSR, since, immediately after any write to BCSR1, BCSR_EN_PROTECT~ is re-activated and BCSR_EN~ is re-protected and the disabling procedure has to be repeated if desired. 4·14·2 BCSR0 - Hard Reset Configuration Register BCSR0 is located at offset 0 on BCSR space. It may be read or written at any timeD. BCSR0 gets its A. In fact only the upper 16 bits - D(0:15) are used, but the BCSR is mapped as a 32 bit wide register and should be accessed as such. B. Provided that support is provided also within the MPC. C. It may be written but will not be influenced. 48 Release 1.4a MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description defaults upon MAIN Power-On reset. During Hard-Reset data contained in BCSR0 is driven on the data bus to provide the Hard-Reset configuration for the MPC, this, if the Flash_Configuration_Enable~ bit in BCSR1 is not active. BCSR0 may be written at any time to change the Hard-Reset configuration of the MPC. The new values will become valid when Hard-Reset is issued to the MPC regardless of the HardReset source. The description of BCSR0 bits is shown in TABLE 4-5. "BCSR0 Description" on page 49. TABLE 4-5. BCSR0 Description PON BIT MNEMONIC FUNCTION ATT DEF. 0 ERB External Arbitration. When '0' during Hard-Reset, Arbitration is performed internally. When '1' during Hard-Reset, Arbitration is performed externally. 0 R,W 1 IP Interrupt Prefix. When '0' during Hard-Reset, Interrupt prefix set to 0xFFF00000, if '1' Interrupt Prefix set to 0. 0 R,W 2 Reserved Implementeda 0 R,W 3 BDIS Boot Disable. When '0' during Hard-Reset, CS0~ region is enabled for boot. When '1', CS0~ region is disabled for boot. 0 R,W 4-5 BPS(0:1) Boot Port Size. Determines the port size for CS0~ at boot. '00' - 32 bit, '01' 8 bit, '10' - 16 bit, '11' - reserved. '00' R,W 6 Reserved Implementeda 0 R,W 7-8 ISB(0:1) Initial Space Base. Value during Hard-Reset determines the initial base address of the internal MPC memory map. When '00' - initial space at 0, when '01' - initial space at 0x00F00000, when '10' - initial space at 0xFF000000, when '11' - initial space at 0xFFF00000. '10' R,W 9 - 10 DBGC(0:1) Debug Pins Configuration. Value during Hard-Reset determines the function of the PCMCIA channel II pins. When '00' - these pins function as PCMCIA channel II pins, when '01' - they serve as Watch-Points,'10' Reserved, when '11' - they become show-cycle attribute pins, e.g., VFLS, VF. '11' R,W 11-12 DBPC(0:1) Debug Port Pins Configuration. Value during Hard-Reset determines the location of the debug port pins. When '00' - debug port pins are on the JTAG port, when '01' - debug port non-existent, '10' - Reserved, when '11' debug port is on PCMCIA channel II pins. '00' R,W 13 - 14 EBDF(0:1)b External Bus Division Factor. Value during Hard Reset determines the factor upon which the CLKOUT of the MPC external bus, is divided with respect to its internal MPC clock. When '00' - CLKOUT is GCLK2 divided by 1, when '01', CLKOUT is GCLK2 divided by 2. '00' R,W 15 Reserved Implementeda. '0' R,W 16 - 31 Reserved Un-Implemented - - a. May be read and written as any other fields and are presented at their associated data pins during Hard-Reset. b. Applicable for MPC's revision A or above. Otherwise have no influence. D. Provided that BCSR is not disabled. Release 1.4a 49 MPC860ADS MPC860ADS, Revision B - User's Manual Functional Description 4·14·3 BCSR1 - Board Control Register The BCSR1 serves as main control register on the MPCADS. It is accessed at offset 4 from BCSR base address. It may be read or written at any timeA. BCSR1 gets its defaults upon Power-On reset. Most of BCSR1 pins are available at the expansion connectors, providing visibility towards external logic. BCSR1 fields are described in TABLE 4-6. "BCSR1 Description" on page 50. TABLE 4-6. BCSR1 Description PON BIT MNEMONIC Function ATT. DEF 0 FLASH_EN Flash Enable. When this bit is active (low), the Flash memory module is enabled on the local memory map. When in-active, the Flash memory is removed from the local memory map and CS0~, to which the Flash memory is connected may be used off-board via the expansion connectors. 0 R,W 1 DRAM_EN Dram Enable. When this bit is active (low), the DRAM module is enabled on the local memory map. When in-active, the DRAM is removed from the local memory map and CS2~ and CS3~a, to which the DRAM is connected may be used off-board via the expansion connectors. 1 R,W 2 ETHEN Ethernet Port Enable. When asserted (low) the EEST connected to SCC1 is enabled. When negated (high) that EEST is in standby mode, while all its system i/f signals are tri-stated. 1 R,W 3 IRDEN Infra-Red Port Enable. When asserted (low), the Infra-Red transceiver, connected to SCC2 is enabled. When negated, the Infra-Red transceiver is put in shutdown mode. And SCC2 pins are available for off-boar