MPC855T MPC855TUM/D - Datasheet Archive

 

Integrated Communications Microprocessor MPC855TUM/D Rev. 0, 2/2001 TM DigitalDNA, PowerQUICC, and PowerQUICC II are trademarks

 

MPC855T MPC855T User's Manual Integrated Communications Microprocessor MPC855TUM/D MPC855TUM/D Rev. 0, 2/2001 TM DigitalDNA, PowerQUICC, and PowerQUICC II are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. I2C is a registered trademark of Philips Semiconductors Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information in this document. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1­303­675­2140 or 1­800­441­2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3­20­1, Minami­Azabu. Minato­ku, Tokyo 106­8573 Japan. 81­3­3440­3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852­26668334 Technical Information Center: 1­800­521­6274 HOME PAGE: http://www.motorola.com/semiconductors Document Comments: FAX (512) 933-2625, Attn: RISC Applications Engineering World Wide Web Addresses: http://www.motorola.com/PowerPC http://www.motorola.com/NetComm http://www.motorola.com/ColdFire © Motorola Inc., 2001. All rights reserved. Part I-Overview MPC855T MPC855T Overview Memory Map Part II-PowerPC Microprocessor Module PowerPC Core PowerPC Core Register Set MPC855T MPC855T Instruction Set Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing Part III-PowerPC Microprocessor Module System Interface Unit Reset Part IV-Hardware Interface External Signals External Bus Interface Clocks and Power Control Memory Controller PCMCIA Interface IND I 1 2 II 3 4 5 6 7 8 9 III 10 11 IV 12 13 14 15 16 I 1 2 II 3 4 5 6 7 8 9 III 10 11 IV 12 13 14 15 16 Part I-Overview MPC855T MPC855T Overview Memory Map Part II-PowerPC Microprocessor Module PowerPC Core PowerPC Core Register Set MPC855T MPC855T Instruction Set Exceptions Instruction and Data Caches Memory Management Unit Instruction Execution Timing Part III-PowerPC Microprocessor Module System Interface Unit Reset Part IV-Hardware Interface External Signals External Bus Interface Clocks and Power Control Memory Controller PCMCIA Interface Part V-Communications Processor Module Communications Processor Module and Timers Communications Processor SDMA Channels and IDMA Emulation Serial Interface SCC Introduction SCC UART Mode SCC HDLC Mode SCC AppleTalk Mode SCC Asynchronous HDLC Mode and IrDA SCC BISYNC Mode SCC Ethernet Mode SCC Transparent Mode Serial Management Controllers Serial Peripheral Interface I2C Controller Parallel Interface Port Parallel I/O Ports CPM Interrupt Controller Part VI-Asynchronous Transfer Mode ATM Overview Buffer Descriptors and Connection Tables ATM Parameter RAM ATM Controller ATM Pace Control ATM Exceptions Interface Configuration UTOPIA Interface Fast Ethernet Controller Fast Ethernet Controller Part VII-System Debugging and Testing Support System Development and Debugging IEEE 1149.1 Test Access Port Byte Ordering Serial Communication Performance Register Quick Reference Guide Instruction Set Listings Serial ATM Glossary Index V 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VI 35 36 37 38 39 40 41 42 VII 43 VIII 43 44 45 A B C D F E 43 GLO I IND V 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VI 35 36 37 38 39 40 41 42 VII 43 VIII 43 44 45 A B C D F E 43 GLO IND I Part V-Communications Processor Module Communications Processor Module and Timers Communications Processor SDMA Channels and IDMA Emulation Serial Interface SCC Introduction SCC UART Mode SCC HDLC Mode SCC AppleTalk Mode SCC Asynchronous HDLC Mode and IrDA SCC BISYNC Mode SCC Ethernet Mode SCC Transparent Mode Serial Management Controllers Serial Peripheral Interface I2 C Controller Parallel Interface Ports Parallel I/O Ports CPM Interrupt Controller Part VI-Asynchronous Transfer Mode ATM Overview Buffer Descriptors and Connection Tables ATM Parameter RAM ATM Controller ATM Pace Controller ATM Exceptions Interface Configuration UTOPIA Interface Fast Ethernet Controller Fast Ethernet Controller Part VIII ­ System Debugging and Testing Support System Development and Debugging IEEE 1149.1 Test Access Port Byte Ordering Serial Communication Performance Register Quick Reference Guide Instruction Set Listings Serial ATM Glossary Index CONTENTS Paragraph Number Title Page Number Part I Overview Chapter 1 MPC855T MPC855T Overview 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Features . 1­1 Embedded PowerPC Core. 1­6 System Interface Unit (SIU) . 1­7 PCMCIA Controller. 1­8 Power Management . 1­8 Communications Processor Module (CPM) . 1­8 ATM Capabilities. 1­9 Software Compatibility Issues . 1­10 Chapter 2 Memory Map Part II PowerPC Microprocessor Module Chapter 3 The PowerPC Core 3.1 3.2 3.2.1 3.3 3.4 3.4.1 3.4.2 3.4.3 3.4.3.1 3.4.3.2 The MPC855T MPC855T Core as a PowerPC Implementation . 3­1 PowerPC Architecture Overview. 3­1 Levels of the PowerPC Architecture . 3­3 Features . 3­4 Basic Structure of the Core . 3­5 Instruction Flow. 3­6 Basic Instruction Pipeline . 3­7 Instruction Unit . 3­7 Branch Operations . 3­7 Dispatching Instructions . 3­9 Contents vii CONTENTS Paragraph Number 3.5 3.6 3.6.1 3.6.2 3.6.3 3.6.3.1 3.6.3.2 3.6.3.3 3.6.3.4 3.6.3.5 3.6.3.6 3.7 Title Page Number Register Set . 3­9 Execution Units. 3­9 Branch Processing Unit . 3­10 Integer Unit . 3­10 Load/Store Unit. 3­10 Executing Load/Store Instructions . 3­12 Serializing Load/Store Instructions . 3­12 Store Accesses . 3­12 Nonspeculative Load Instructions . 3­13 Unaligned Accesses . 3­13 Atomic Update Primitives . 3­14 The MPC855T MPC855T and the PowerPC Architecture. 3­14 Chapter 4 PowerPC Core Register Set 4.1 4.1.1 4.1.1.1 4.1.1.1.1 4.1.1.1.2 4.1.1.1.3 4.1.1.1.4 4.1.2 4.1.2.1 4.1.2.2 4.1.2.3 4.1.2.3.1 4.1.2.3.2 4.1.3 4.1.3.1 4.2 MPC855T MPC855T Register Implementation . 4­1 PowerPC Registers-User Registers . 4­2 PowerPC User-Level Register Bit Assignments . 4­2 Condition Register (CR) . 4­3 Condition Register CR0 Field Definition . 4­3 XER . 4­3 Time Base Registers . 4­4 PowerPC Registers-Supervisor Registers . 4­4 DAR, DSISR, and BAR Operation. 4­5 Unsupported Registers. 4­6 PowerPC Supervisor-Level Register Bit Assignments. 4­6 Machine State Register (MSR). 4­6 Processor Version Register. 4­8 MPC855T-Specific SPRs . 4­8 Accessing SPRs . 4­11 Register Initialization at Reset . 4­11 Chapter 5 MPC855T MPC855T Instruction Set 5.1 5.1.1 5.1.2 5.2 5.2.1 5.2.1.1 viii Operand Conventions. 5­1 Data Organization in Memory and Data Transfers. 5­1 Aligned and Misaligned Accesses . 5­1 Instruction Set Summary. 5­2 Classes of Instructions . 5­3 Definition of Boundedly Undefined . 5­4 MPC855T MPC855T User's Manual CONTENTS Paragraph Number 5.2.1.2 5.2.1.3 5.2.1.4 5.2.2 5.2.2.1 5.2.2.2 5.2.2.3 5.2.2.3.1 5.2.2.3.2 5.2.2.3.3 5.2.3 5.2.4 5.2.4.1 5.2.4.1.1 5.2.4.1.2 5.2.4.1.3 5.2.4.1.4 5.2.4.2 5.2.4.2.1 5.2.4.2.2 5.2.4.2.3 5.2.4.2.4 5.2.4.2.5 5.2.4.2.6 5.2.4.3 5.2.4.3.1 5.2.4.3.2 5.2.4.3.3 5.2.4.4 5.2.4.5 5.2.4.5.1 5.2.4.6 5.2.5 5.2.5.1 5.2.5.2 5.2.5.2.1 5.2.5.2.2 5.2.5.3 5.2.6 5.2.6.1 5.2.6.2 5.2.6.2.1 5.2.6.2.2 5.2.6.3 Title Page Number Defined Instruction Class . 5­4 Illegal Instruction Class . 5­4 Reserved Instruction Class . 5­5 Addressing Modes . 5­5 Memory Addressing . 5­5 Effective Address Calculation . 5­6 Synchronization . 5­6 Context Synchronization . 5­6 Execution Synchronization. 5­7 Instruction-Related Exceptions. 5­7 Instruction Set Overview . 5­7 PowerPC UISA Instructions . 5­8 Integer Instructions . 5­8 Integer Arithmetic Instructions. 5­8 Integer Compare Instructions . 5­9 Integer Logical Instructions. 5­10 Integer Rotate and Shift Instructions . 5­10 Load and Store Instructions . 5­11 Integer Load and Store Address Generation. 5­11 Register Indirect Integer Load Instructions . 5­12 Integer Store Instructions. 5­12 Integer Load and Store with Byte-Reverse Instructions. 5­13 Integer Load and Store Multiple Instructions. 5­13 Integer Load and Store String Instructions. 5­14 Branch and Flow Control Instructions. 5­14 Branch Instruction Address Calculation. 5­15 Branch Instructions. 5­15 Condition Register Logical Instructions. 5­16 Trap Instructions . 5­16 Processor Control Instructions. 5­17 Move to/from Condition Register Instructions. 5­17 Memory Synchronization Instructions-UISA . 5­17 PowerPC VEA Instructions . 5­19 Processor Control Instructions. 5­19 Memory Synchronization Instructions-VEA . 5­20 eieio Behavior. 5­20 isync Behavior . 5­20 Memory Control Instructions-VEA . 5­21 PowerPC OEA Instructions . 5­21 System Linkage Instructions. 5­22 Processor Control Instructions-OEA . 5­22 Move to/from Machine State Register Instructions. 5­22 Move to/from Special-Purpose Register Instructions. 5­22 Memory Control Instructions-OEA . 5­23 Contents ix CONTENTS Paragraph Number Title Page Number Chapter 6 Exceptions 6.1 6.1.1 6.1.2 6.1.2.1 6.1.2.2 6.1.2.3 6.1.2.4 6.1.2.5 6.1.2.6 6.1.2.6.1 6.1.2.7 6.1.2.8 6.1.2.9 6.1.2.10 6.1.2.11 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3 6.1.3.4 6.1.3.5 6.1.3.6 6.1.4 6.1.5 6.1.6 6.1.7 Exceptions. 6­2 Exception Ordering. 6­3 PowerPC-Defined Exceptions . 6­4 System Reset Interrupt (0x00100) . 6­5 Machine Check Interrupt (0x00200) . 6­5 DSI Exception (0x00300) . 6­6 ISI Exception (0x00400). 6­6 External Interrupt Exception (0x00500) . 6­6 Alignment Exception (0x00600) . 6­7 Integer Alignment Exceptions . 6­9 Program Exception (0x00700). 6­9 Decrementer Exception (0x00900). 6­10 System Call Exception (0x00C00) . 6­11 Trace Exception (0x00D00) . 6­12 Floating-Point Assist Exception . 6­12 Implementation-Specific Exceptions. 6­12 Software Emulation Exception (0x01000) . 6­12 Instruction TLB Miss Exception (0x01100). 6­13 Data TLB Miss Exception (0x01200). 6­13 Instruction TLB Error Exception (0x01300) . 6­14 Data TLB Error Exception (0x014000) . 6­15 Debug Exceptions (0x01C00­0x01F00) . 6­15 Implementing the Precise Exception Model. 6­16 Recoverability after an Exception. 6­17 Exception Latency . 6­18 Partially Completed Instructions . 6­21 Chapter 7 Instruction and Data Caches 7.1 7.2 7.3 7.3.1 7.3.1.1 7.3.1.2 7.3.1.2.1 7.3.1.2.2 7.3.1.2.3 x Instruction Cache Organization . 7-2 Data Cache Organization . 7-5 Cache Control Registers . 7-6 Instruction Cache Control Registers . 7-6 Reading Data and Tags in the Instruction Cache. 7-8 IC_CST Commands. 7-9 Instruction Cache Enable/Disable Commands . 7-9 Instruction Cache Load & Lock Cache Block Command . 7-10 Instruction Cache Unlock Cache Block Command . 7-11 MPC855T MPC855T User's Manual CONTENTS Paragraph Number 7.3.1.2.4 7.3.1.2.5 7.3.2 7.3.2.1 7.3.2.2 7.3.2.2.1 7.3.2.2.2 7.3.2.2.3 7.3.2.2.4 7.3.2.2.5 7.3.2.2.6 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.6 7.6.1 7.6.2 7.6.3 7.6.3.1 7.6.3.2 7.6.4 7.6.4.1 7.6.4.2 7.6.5 7.6.6 7.7 7.8 7.8.1 7.8.2 Title Page Number Instruction Cache Unlock All Command . 7-11 Instruction Cache Invalidate All Command . 7-11 Data Cache Control Registers. 7-11 Reading Data Cache Tags and Copyback Buffer . 7-14 DC_CST Commands . 7-15 Data Cache Enable/Disable Commands . 7-15 Data Cache Load & Lock Cache Block Command . 7-16 Data Cache Unlock Cache Block Command. 7-16 Data Cache Unlock All Command . 7-17 Data Cache Invalidate All Command . 7-17 Data Cache Flush Cache Block Command. 7-17 PowerPC Cache Control Instructions . 7-18 Instruction Cache Block Invalidate (icbi). 7-18 Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst) . 7-18 Data Cache Block Zero (dcbz) . 7-19 Data Cache Block Store (dcbst) . 7-19 Data Cache Block Flush (dcbf) . 7-19 Data Cache Block Invalidate (dcbi) . 7-20 Instruction Cache Operations. 7-20 Instruction Cache Hit . 7-22 Instruction Cache Miss . 7-22 Instruction Fetching on a Predicted Path . 7-23 Fetching Instructions from Caching-Inhibited Regions. 7-23 Updating Code and Memory Region Attributes . 7-23 Data Cache Operation . 7-24 Data Cache Load Hit. 7-25 Data Cache Read Miss. 7-25 Write-Through Mode. 7-26 Data Cache Store Hit in Write-Through Mode. 7-26 Data Cache Store Miss in Write-Through Mode . 7-26 Write-Back Mode . 7-26 Data Cache Store Hit in Write-Back Mode . 7-26 Data Cache Store Miss in Write-Back Mode . 7-26 Data Accesses to Caching-Inhibited Memory Regions . 7-27 Atomic Memory References. 7-27 Cache Initialization after Reset. 7-29 Debug Support . 7-29 Instruction and Data Cache Operation in Debug Mode. 7-29 Instruction and Data Cache Operation with a Software Monitor Debugger 7-30 Contents xi CONTENTS Paragraph Number Title Page Number Chapter 8 Memory Management Unit 8.1 8.2 8.3 8.3.1 8.3.2 8.3.3 8.4 8.5 8.6 8.7 8.7.1 8.7.2 8.7.3 8.8 8.8.1 8.8.2 8.8.3 8.8.4 8.8.5 8.8.6 8.8.7 8.8.8 8.8.9 8.8.10 8.8.11 8.8.12 8.8.12.1 8.8.12.2 8.8.12.3 8.8.12.4 8.8.12.5 8.8.13 8.9 8.10 8.10.1 8.10.1.1 8.10.2 8.10.3 8.10.4 xii Features . 8­1 PowerPC Architecture Compliance . 8­2 Address Translation . 8­3 Translation Disabled . 8­3 Translation Enabled . 8­3 TLB Operation. 8­5 Using Access Protection Groups . 8­6 Protection Resolution Modes. 8­7 Memory Attributes. 8­8 Translation Table Structure. 8­9 Level-One Descriptor . 8­12 Level-Two Descriptor. 8­13 Page Size. 8­13 Programming Model . 8­14 IMMU Control Register (MI_CTR) . 8­15 DMMU Control Register (MD_CTR) . 8­16 IMMU/DMMU Effective Page Number Register (Mx_EPN) . 8­17 IMMU Tablewalk Control Register (MI_TWC) . 8­18 DMMU Tablewalk Control Register (MD_TWC) . 8­19 IMMU Real Page Number Register (MI_RPN) . 8­19 DMMU Real Page Number Register (MD_RPN) . 8­21 MMU Tablewalk Base Register (M_TWB) . 8­22 MMU Current Address Space ID Register (M_CASID). 8­22 MMU Access Protection Registers (MI_AP/MD_AP) . 8­23 MMU Tablewalk Special Register (M_TW) . 8­23 MMU Debug Registers. 8­24 IMMU CAM Entry Read Register (MI_CAM). 8­24 IMMU RAM Entry Read Register 0 (MI_RAM0). 8­25 IMMU RAM Entry Read Register 1 (MI_RAM1). 8­26 DMMU CAM Entry Read Register (MD_CAM). 8­27 DMMU RAM Entry Read Register 0 (MD_RAM0). 8­28 DMMU RAM Entry Read Register 1 (MD_RAM1). 8­29 Memory Management Unit Exceptions . 8­30 TLB Manipulation . 8­30 TLB Reload. 8­31 Translation Reload Examples . 8­31 Locking TLB Entries . 8­32 Loading Locked TLB Entries . 8­33 TLB Invalidation. 8­33 MPC855T MPC855T User's Manual CONTENTS Paragraph Number Title Page Number Chapter 9 Instruction Execution Timing 9.1 9.1.1 9.1.2 9.1.3 9.1.4 9.1.5 9.1.6 9.1.7 9.2 9.2.1 9.2.2 9.2.3 Instruction Execution Timing Examples . 9­1 Data Cache Load with a Data Dependency . 9­1 Writeback Arbitration . 9­2 Private Writeback Bus Load . 9­3 Fastest External Load (Data Cache Miss). 9­3 A Full Completion Queue. 9­4 Branch Instruction Handling. 9­4 Branch Prediction . 9­5 Instruction Timing List . 9­6 Load/Store Instruction Timing. 9­7 String Instruction Latency . 9­8 Accessing Off-Core SPRs. 9­8 Part III Configuration and Reset Chapter 10 System Interface Unit 10.1 10.2 10.3 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.5 10.5.1 10.5.2 10.5.3 10.5.3.1 10.5.4 10.5.4.1 10.5.4.2 10.5.4.3 10.5.4.4 10.6 Features . 10­2 System Configuration and Protection . 10­2 Multiplexing SIU Pins . 10­4 Programming the SIU . 10­5 Internal Memory Map Register (IMMR). 10­5 SIU Module Configuration Register (SIUMCR). 10­6 System Protection Control Register (SYPCR) . 10­7 Transfer Error Status Register (TESR). 10­8 Register Lock Mechanism . 10­9 System Configuration . 10­11 Interrupt Structure. 10­11 Priority of Interrupt Sources . 10­13 SIU Interrupt Processing. 10­14 Nonmaskable Interrupts-IRQ0 and SWT. 10­14 Programming the SIU Interrupt Controller. 10­15 SIU Interrupt Pending Register (SIPEND). 10­15 SIU Interrupt Mask Register (SIMASK) . 10­17 SIU Interrupt Edge/Level Register (SIEL) . 10­18 SIU Interrupt Vector Register (SIVEC) . 10­19 The Bus Monitor . 10­20 Contents xiii CONTENTS Paragraph Number 10.7 10.7.1 10.8 10.8.1 10.9 10.9.1 10.9.2 10.9.3 10.10 10.10.1 10.10.2 10.10.3 10.10.4 10.11 10.11.1 10.11.2 10.11.3 10.12 10.12.1 10.12.2 Title Page Number The Software Watchdog Timer. 10­21 Software Service Register (SWSR) . 10­22 The PowerPC Decrementer. 10­23 Decrementer Register (DEC). 10­24 The PowerPC Timebase. 10­24 Timebase Register (TBU and TBL). 10­25 Timebase Reference Registers (TBREFA and TBREFB). 10­26 Timebase Status and Control Register (TBSCR) . 10­26 The Real-Time Clock. 10­27 Real-Time Clock Status and Control Register (RTCSC) . 10­28 Real-Time Clock Register (RTC) . 10­29 Real-Time Clock Alarm Register (RTCAL) . 10­29 Real-Time Clock Alarm Seconds Register (RTSEC). 10­30 The Periodic Interrupt Timer (PIT). 10­31 Periodic Interrupt Status and Control Register (PISCR) . 10­32 PIT Count Register (PITC) . 10­33 PIT Register (PITR). 10­33 General SIU Timers Operation . 10­34 Freeze Operation. 10­34 Low-Power Stop Operation . 10­34 Chapter 11 Reset 11.1 11.1.1 11.1.2 11.1.3 11.1.3.1 11.1.3.2 11.1.3.3 11.1.4 11.1.5 11.1.6 11.1.7 11.1.8 11.1.9 11.2 11.3 11.3.1 11.3.1.1 11.3.2 11.4 xiv Types of Reset. 11­1 Power-On Reset . 11­2 External Hard Reset . 11­2 Internal Hard Reset . 11­2 PLL Loss of Lock . 11­3 Software Watchdog Reset. 11­3 Checkstop Reset. 11­3 Debug Port Hard or Soft Reset . 11­3 JTAG Reset. 11­3 Power-On and Hard Reset Sequence . 11­4 External Soft Reset . 11­4 Internal Soft Reset . 11­4 Soft Reset Sequence. 11­5 Reset Status Register (RSR) . 11­5 MPC855T MPC855T Reset Configuration . 11­6 Hard Reset. 11­7 Hard Reset Configuration Word . 11­9 Soft Reset. 11­11 TRST and Power Mode Considerations . 11­11 MPC855T MPC855T User's Manual CONTENTS Paragraph Number Title Page Number Part IV The Hardware Interface Chapter 12 External Signals 12.1 12.2 12.3 12.4 12.4.1 12.4.1.1 12.4.2 12.4.3 12.4.4 12.5 System Bus Signals. 12­5 Active Pull-Up Buffers . 12­22 Internal Pull-Up and Pull-Down Resistors . 12­23 Recommended Basic Pin Connections . 12­23 Reset Configuration . 12­24 Bus Control Signals and Interrupts. 12­24 JTAG and Debug Ports . 12­24 Unused Inputs . 12­25 Unused Outputs. 12­25 Signal States during Reset . 12­25 Chapter 13 External Bus Interface 13.1 13.2 13.3 13.4 13.4.1 13.4.2 13.4.2.1 13.4.2.2 13.4.3 13.4.4 13.4.5 13.4.6 13.4.6.1 13.4.6.2 13.4.6.3 13.4.6.4 13.4.7 13.4.7.1 13.4.7.2 13.4.7.3 13.4.7.3.1 13.4.7.3.2 Features . 13­1 Bus Transfer Overview . 13­1 Bus Interface Signal Descriptions. 13­2 Bus Operations. 13­6 Basic Transfer Protocol . 13­6 Single-Beat Transfer . 13­7 Single-Beat Read Flow . 13­7 Single-Beat Write Flow . 13­10 Burst Transfers. 13­13 Burst Operations . 13­14 Alignment and Data Packing on Transfers . 13­23 Arbitration Phase . 13­26 Bus Request (BR) . 13­27 Bus Grant (BG). 13­27 Bus Busy (BB). 13­28 External Bus Parking . 13­30 Address Transfer Phase-Related Signals . 13­30 Transfer Start (TS) . 13­30 Address Bus . 13­31 Transfer Attributes. 13­31 Read/Write (RD/WR) . 13­31 Burst Indicator (BURST). 13­31 Contents xv CONTENTS Paragraph Number 13.4.7.3.3 13.4.7.3.4 13.4.7.3.5 13.4.8 13.4.8.1 13.4.8.2 13.4.8.3 13.4.8.4 13.4.9 13.4.9.1 13.4.10 13.4.10.1 Title Page Number Transfer Size (TSIZ). 13­31 Address Types (AT) . 13­31 Burst Data in Progress (BDIP) . 13­34 Termination Signals. 13­34 Transfer Acknowledge (TA). 13­34 Burst Inhibit (BI) . 13­34 Transfer Error Acknowledge (TEA). 13­34 Termination Signals Protocol . 13­34 Memory Reservation. 13­35 Kill Reservation (KR). 13­36 Bus Exception Control Cycles. 13­37 RETRY . 13­38 Chapter 14 Clocks and Power Control 14.1 14.2 14.2.1 14.2.1.1 14.2.1.2 14.2.2 14.2.2.1 14.2.2.2 14.2.2.3 14.2.2.4 14.3 14.3.1 14.3.1.1 14.3.1.2 14.3.1.3 14.3.1.4 14.3.1.5 14.3.2 14.3.3 14.4 14.4.1 14.4.2 14.4.3 xvi Features . 14­1 The Clock Module . 14­2 External Reference Clocks. 14­3 Off-Chip Oscillator Input (EXTCLK) . 14­4 Crystal Oscillator Support (EXTAL and XTAL) . 14­4 System PLL. 14­5 SPLL Reset Configuration. 14­6 SPLL Output Characteristics and Stability. 14­7 The System Phase-Locked Loop Pins (VDDSYN, VSSSYN, VSSSYN1, XFC) 14­7 Disabling the SPLL. 14­8 Clock Signals . 14­8 Clocks Derived from the SPLL Output . 14­9 The Internal General System Clocks (GCLK1C, GCLK2C, GCLK1, GCLK2) .14­10 Memory Controller and External Bus Clocks (GCLK1_50, GCLK2_50, CLKOUT). 14­11 CLKOUT Special Considerations: 1:2:1 Mode. 14­14 The Baud Rate Generator Clock (BRGCLK) . 14­14 The Synchronization Clock (SYNCCLK, SYNCCLKS) . 14­14 The PIT and RTC Clock (PITRTCLK) . 14­15 The Time Base and Decrementer Clock (TMBCLK). 14­16 Power Distribution . 14­16 I/O Buffer Power (VDDH) . 14­17 Internal Logic Power (VDDL). 14­18 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1) . 14­18 MPC855T MPC855T User's Manual CONTENTS Paragraph Number 14.4.4 14.5 14.5.1 14.5.2 14.5.3 14.5.4 14.5.5 14.5.6 14.5.7 14.5.7.1 14.5.7.2 14.5.7.3 14.5.8 14.6 14.6.1 14.6.2 Title Page Number Keep-Alive Power (KAPWR) . 14­18 Power Control (Low-Power Modes). 14­18 Normal High Mode. 14­21 Normal Low Mode. 14­21 Doze High Mode. 14­21 Doze Low Mode . 14­22 Sleep Mode . 14­23 Deep-Sleep Mode . 14­23 Power-Down Mode. 14­24 Software Initiation of Power-Down Mode, with Automatic Wake-up. 14­24 Maintaining the Real-Time Clock (RTC) During Shutdown or Power Failure .14­26 Register Lock Mechanism: Protecting SIU Registers in Power-Down Mode .14­26 TMIST: Facilitating Nesting of SIU Timer Interrupts. 14­27 Clock and Power Control Registers. 14­27 System Clock and Reset Control Register (SCCR) . 14­27 PLL, Low-Power, and Reset Control Register (PLPRCR). 14­29 Chapter 15 Memory Controller 15.1 15.2 15.3 15.3.1 15.3.2 15.3.3 15.3.4 15.3.5 15.3.6 15.3.7 15.3.8 15.3.9 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.4.5 15.4.6 15.4.7 Features . 15­1 Basic Architecture. 15­4 Chip-Select Programming Common to the GPCM and UPM . 15­6 Address Space Programming. 15­7 Register Programming Order. 15­7 Memory Bank Write Protection. 15­7 Address Type Protection. 15­7 8-, 16-, and 32-Bit Port Size Configuration. 15­7 Parity Configuration . 15­8 Memory Bank Protection Status . 15­8 UPM-Specific Registers . 15­8 GPCM-Specific Registers. 15­8 Register Descriptions . 15­9 Base Registers (BRx). 15­9 Option Registers (ORx) . 15­10 Memory Status Register (MSTAT) . 15­13 Machine A Mode Register/Machine B Mode Registers (MxMR) . 15­13 Memory Command Register (MCR) . 15­15 Memory Data Register (MDR) . 15­16 Memory Address Register (MAR) . 15­17 Contents xvii CONTENTS Paragraph Number 15.4.8 15.5 15.5.1 15.5.1.1 15.5.1.2 15.5.1.3 15.5.1.4 15.5.1.5 15.5.1.6 15.5.2 15.5.3 15.5.4 15.6 15.6.1 15.6.1.1 15.6.1.2 15.6.1.3 15.6.1.4 15.6.2 15.6.3 15.6.4 15.6.4.1 15.6.4.2 15.6.4.3 15.6.4.4 15.6.4.5 15.6.4.6 15.6.4.7 15.6.4.8 15.6.4.9 15.6.4.10 15.6.4.11 15.6.4.11.1 15.6.4.11.2 15.7 15.7.1 15.7.2 15.8 15.8.1 15.8.2 15.8.3 15.8.4 15.8.4.1 xviii Title Page Number Memory Periodic Timer Prescaler Register (MPTPR). 15­18 General-Purpose Chip-Select Machine (GPCM). 15­18 Timing Configuration . 15­19 Chip-Select Assertion Timing . 15­20 Chip-Select and Write Enable Deassertion Timing. 15­21 Relaxed Timing . 15­23 Output Enable (OE) Timing . 15­26 Programmable Wait State Configuration. 15­26 Extended Hold Time on Read Accesses . 15­26 Boot Chip-Select Operation. 15­28 External Asynchronous Master Support . 15­29 Special Case: Bursting with External Transfer Acknowledge: . 15­30 User-Programmable Machines (UPMs). 15­31 Requests . 15­32 Internal/External Memory Access Requests. 15­32 UPM Periodic Timer Requests . 15­33 Software Requests-MCR run Command. 15­33 Exception Requests. 15­33 Programming the UPM. 15­34 Control Signal Generation Timing . 15­34 The RAM Array. 15­37 RAM Words. 15­37 Chip-Select Signals (CSTx). 15­41 Byte-Select Signals (BSTx) . 15­42 General-Purpose Signals (GxTx, G0x). 15­43 Loop Control (LOOP). 15­44 Exception Pattern Entry (EXEN). 15­45 Address Multiplexing (AMX) . 15­45 Transfer Acknowledge and Data Sample Control (UTA, DLT3) . 15­50 Disable Timer Mechanism (TODT) . 15­51 The Last Word (LAST) . 15­51 The Wait Mechanism (WAEN) . 15­51 Internal and External Synchronous Masters . 15­51 External Asynchronous Masters . 15­52 Handling Devices with Slow or Variable Access Times . 15­53 Hierarchical Bus Interface Example . 15­54 Slow Devices Example . 15­54 External Master Support . 15­54 Synchronous External Masters . 15­54 Asynchronous External Masters . 15­55 Special Case: Address Type Signals for External Masters. 15­55 UPM Features Supporting External Masters . 15­55 Address Incrementing for External Synchronous Bursting Masters . 15­55 MPC855T MPC855T User's Manual CONTENTS Paragraph Number 15.8.4.2 15.8.4.3 15.8.5 15.8.5.1 15.8.5.2 15.9 15.9.1 15.9.2 Title Page Number Handshake Mechanism for Asynchronous External Masters . 15­56 Special Signal for External Address Multiplexer Control . 15­56 External Master Examples . 15­56 External Masters and the GPCM . 15­56 External Masters and the UPM. 15­58 Memory System Interface Examples . 15­63 Page-Mode DRAM Interface Example. 15­63 Page Mode Extended Data-Out Interface Example . 15­74 Chapter 16 PCMCIA Interface 16.1 16.2 16.2.1 16.2.2 16.2.3 16.2.4 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.3.5 16.3.6 16.4 16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 16.4.6 16.5 System Configuration . 16­1 PCMCIA Module Signal Definitions. 16­1 PCMCIA Cycle Control Signals. 16­3 PCMCIA Input Port Signals . 16­4 PCMCIA Output Port Signals (OP[0­4]) . 16­5 Other PCMCIA Signals . 16­5 Operation Description. 16­5 Memory-Only Cards . 16­5 I/O Cards. 16­6 Interrupts. 16­6 Power Control . 16­7 Reset and Three-State Control. 16­7 DMA . 16­7 Programming Model . 16­8 PCMCIA Interface Input Pins Register (PIPR) . 16­8 PCMCIA Interface Status Changed Register (PSCR) . 16­9 PCMCIA Interface Enable Register (PER) . 16­10 PCMCIA Interface General Control Register (PGCRx). 16­11 PCMCIA Base Registers 0­7 (PBR0­PBR7). 16­12 PCMCIA Option Register 0­7 (POR0­POR7) . 16­12 PCMCIA Controller Timing Examples . 16­16 Contents xix CONTENTS Paragraph Number Title Page Number Part V Communications Processor Module Chapter 17 Communications Processor Module and CPM Timers 17.1 17.2 17.2.1 17.2.2 17.2.2.1 17.2.2.2 17.2.2.3 17.2.2.4 17.2.2.5 17.2.2.6 17.2.3 17.2.3.1 17.2.4 17.2.4.1 17.2.4.2 17.2.4.3 17.2.4.4 17.2.5 Features . 17­2 CPM General-Purpose Timers. 17­4 Features. 17­5 CPM Timer Operation . 17­6 Timer Clock Source . 17­6 Timer Reference Count. 17­6 Timer Capture . 17­6 Timer Gating. 17­7 Cascaded Mode. 17­7 Timer 1 and SPKROUT. 17­8 CPM Timer Register Set. 17­8 Timer Global Configuration Register (TGCR). 17­8 Timer Mode Registers (TMR1­TMR4) . 17­9 Timer Reference Registers (TRR1­TRR4) . 17­10 Timer Capture Registers (TCR1­TCR4). 17­10 Timer Counter Registers (TCN1­TCN4) . 17­11 Timer Event Registers (TER1­TER4). 17­11 Timer Initialization Examples . 17­12 Chapter 18 Communications Processor 18.1 18.2 18.3 18.4 18.5 18.5.1 18.5.2 18.5.3 18.5.4 18.5.4.1 18.5.4.2 18.6 18.6.1 18.6.2 xx Features . 18­1 Communicating with the Core . 18­2 Communicating with the Peripherals. 18­2 CP Microcode Revision Number . 18­3 CP Register Set and CP Commands . 18­4 RISC Controller Configuration Register (RCCR) . 18­4 RISC Microcode Development Support Control Register (RMDS) . 18­5 CP Command Register (CPCR). 18­6 CP Commands . 18­7 CP Command Examples . 18­8 CP Command Execution Latency. 18­8 Dual-Port RAM. 18­8 System RAM and Microcode Packages. 18­10 The Buffer Descriptor (BD). 18­11 MPC855T MPC855T User's Manual CONTENTS Paragraph Number 18.6.3 18.7 18.7.1 18.7.2 18.7.3 18.7.3.1 18.7.3.2 18.7.4 18.7.5 18.7.6 18.7.7 18.7.8 Title Page Number Parameter RAM . 18­11 The RISC Timer Table. 18­12 RISC Timer Table Scan Algorithm . 18­13 The set timer Command. 18­13 RISC Timer Table Parameter RAM and Timer Table Entries . 18­13 RISC Timer Command Register (TM_CMD) . 18­14 RISC Timer Table Entries . 18­15 RISC Timer Event Register (RTER)/Mask Register (RTMR). 18­15 PWM Mode. 18­15 RISC Timer Initialization . 18­16 RISC Timer Interrupt Handling. 18­17 Using the RISC Timers to Track CP Loading . 18­17 Chapter 19 SDMA Channels and IDMA Emulation 19.1 19.1.1 19.1.2 19.2 19.2.1 19.2.2 19.2.3 19.2.4 19.3 19.3.1 19.3.2 19.3.3 19.3.3.1 19.3.3.2 19.3.3.3 19.3.4 19.3.4.1 19.3.4.2 19.3.5 19.3.6 19.3.6.1 19.3.6.2 19.3.7 19.3.7.1 19.3.7.2 19.3.7.2.1 SDMA Channels . 19­1 SDMA Transfers. 19­2 U-Bus Arbitration and the SDMA Channels . 19­2 SDMA Registers . 19­3 SDMA Configuration Register (SDCR) . 19­3 SDMA Status Register (SDSR) . 19­4 SDMA Mask Register (SDMR). 19­5 SDMA Address Register (SDAR) . 19­5 IDMA Emulation . 19­5 IDMA Features . 19­6 IDMA Parameter RAM . 19­6 IDMA Registers. 19­7 DMA Channel Mode Registers (DCMR) . 19­7 IDMA Status Registers (IDSR1 and IDSR2) . 19­8 IDMA Mask Registers (IDMR1 and IDMR2). 19­9 IDMA Buffer Descriptors (BD). 19­9 Function Code Registers-SFCR and DFCR. 19­11 Auto-Buffering and Buffer-Chaining . 19­12 IDMA CP Commands. 19­12 IDMA Channel Operation . 19­13 Activating an IDMA Channel. 19­13 Suspending an IDMA Channel . 19­13 IDMA Interface Signals-DREQ and SDACK. 19­13 IDMA Requests for Memory/Memory Transfers. 19­14 IDMA Requests for Peripheral/Memory Transfers . 19­14 Level-Sensitive Requests. 19­14 Contents xxi CONTENTS Paragraph Number 19.3.7.2.2 19.3.8 19.3.8.1 19.3.8.2 19.3.9 19.3.9.1 19.3.9.2 19.3.9.3 19.3.9.4 19.3.10 19.3.11 Title Page Number Edge-Sensitive Requests. 19­15 IDMA Transfers-Dual-Address and Single-Address . 19­15 Dual-Address (Dual-Cycle) Transfer . 19­15 Single-Address (Single-Cycle) Transfer (Fly-By). 19­16 Single-Buffer Mode on IDMA1-A Special Case . 19­18 IDMA1 Channel Mode Register (DCMR) (Single-Buffer Mode) . 19­19 IDMA1 Status Register (IDSR1) (Single-Buffer Mode). 19­19 IDMA1 Mask Register (IDMR1) (Single-Buffer Mode) . 19­20 Burst Timing (Single-Buffer Mode) . 19­20 External Recognition of an IDMA Transfer . 19­21 Interrupts During an IDMA Bus Transfer . 19­22 Chapter 20 Serial Interface 20.1 20.2 20.2.1 20.2.2 20.2.3 20.2.3.1 20.2.3.2 20.2.3.3 20.2.3.4 20.2.3.5 20.2.4 20.2.4.1 20.2.4.2 20.2.4.3 20.2.4.4 20.2.4.5 20.2.4.6 20.3 20.4 20.4.1 20.4.2 20.4.3 xxii SI Features . 20­3 The Time-Slot Assigner (TSA). 20­3 TSA Signals . 20­7 Enabling Connections to the TSA . 20­7 SI RAM. 20­7 Disabling and Reenabling the TSA . 20­8 TDMa Channel with Static Frames . 20­8 SI RAM Dynamic Changes . 20­8 TDMa Channel with Dynamic Frames. 20­10 Programming the SI RAM. 20­10 The SI Registers. 20­12 SI Global Mode Register (SIGMR) . 20­12 SI Mode Register (SIMODE) . 20­13 SI Clock Route Register (SICR). 20­20 SI Command Register (SICMR). 20­20 SI Status Register (SISTR) . 20­21 SI RAM Pointer Register (SIRP). 20­22 NMSI Configuration . 20­23 Baud Rate Generators (BRGs). 20­25 Baud Rate Generator Configuration Registers (BRGCn). 20­26 Autobaud Operation on the SCC UART . 20­27 UART Baud Rate Examples . 20­28 MPC855T MPC855T User's Manual CONTENTS Paragraph Number Title Page Number Chapter 21 Serial Communications Controller 21.1 21.2 21.2.1 21.2.2 21.2.3 21.2.4 21.3 21.4 21.4.1 21.4.2 21.4.3 21.4.4 21.4.4.1 21.4.4.2 21.4.5 21.4.5.1 21.4.6 21.4.7 21.4.7.1 21.4.7.2 21.4.7.3 21.4.7.4 21.4.7.5 21.4.8 Features . 21­2 SCC Registers . 21­3 General SCC Mode Register (GSMR). 21­3 Protocol-Specific Mode Register (PSMR) . 21­9 Data Synchronization Register (DSR). 21­9 Transmit-on-Demand Register (TODR). 21­9 SCC Buffer Descriptors (BDs) . 21­10 SCC Parameter RAM. 21­12 Function Code Registers (RFCR and TFCR) . 21­15 Handling SCC Interrupts . 21­15 SCC Initialization . 21­16 Controlling SCC Timing with RTS, CTS, and CD. 21­17 Synchronous Protocols . 21­17 Asynchronous Protocols . 21­20 Digital Phase-Locked Loop (DPLL) Operation. 21­21 Encoding Data with a DPLL. 21­23 Clock Glitch Detection . 21­24 Reconfiguring the SCC. 21­25 General Reconfiguration Sequence for the SCC Transmitter. 21­25 Reset Sequence for the SCC Transmitter . 21­26 General Reconfiguration Sequence for the SCC Receiver . 21­26 Reset Sequence for the SCC Receiver. 21­26 Switching Protocols . 21­26 Saving Power . 21­26 Chapter 22 SCC UART Mode 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 22.9 22.10 22.11 Features . 22­2 Normal Asynchronous Mode. 22­3 Synchronous Mode . 22­3 SCC UART Parameter RAM. 22­4 Data-Handling Methods: Character- or Message-Based . 22­5 Error and Status Reporting. 22­6 SCC UART Commands. 22­6 Multidrop Systems and Address Recognition. 22­7 Receiving Control Characters . 22­7 Hunt Mode (Receiver) . 22­9 Inserting Control Characters into the Transmit Data Stream. 22­9 Contents xxiii CONTENTS Paragraph Number 22.12 22.13 22.14 22.15 22.16 22.17 22.18 22.19 22.20 22.21 22.22 Title Page Number Sending a Break (Transmitter). 22­10 Sending a Preamble (Transmitter) . 22­10 Fractional Stop Bits (Transmitter) . 22­10 Handling Errors in the SCC UART Controller. 22­11 UART Mode Register (PSMR). 22­12 SCC UART Receive Buffer Descriptor (RxBD) . 22­14 SCC UART Transmit Buffer Descriptor (TxBD). 22­17 SCC UART Event Register (SCCE) and Mask Register (SCCM) . 22­18 SCC UART Status Register (SCCS). 22­20 SCC UART Programming Example. 22­21 S-Records Loader Application. 22­22 Chapter 23 SCC HDLC Mode 23.1 23.2 23.3 23.4 23.5 23.6 23.7 23.8 23.9 23.10 23.11 23.12 23.13 23.13.1 23.13.2 23.14 23.14.1 23.14.2 23.14.3 23.14.4 23.14.5 23.14.6 23.14.6.1 23.14.6.2 xxiv SCC HDLC Features. 23­2 SCC HDLC Channel Frame Transmission . 23­2 SCC HDLC Channel Frame Reception . 23­3 SCC HDLC Parameter RAM. 23­3 Programming the SCC HDLC Controller. 23­5 SCC HDLC Commands. 23­5 Handling Errors in the SCC HDLC Controller. 23­6 HDLC Mode Register (PSMR). 23­7 SCC HDLC Receive Buffer Descriptor (RxBD) . 23­8 SCC HDLC Transmit Buffer Descriptor (TxBD). 23­11 HDLC Event Register (SCCE)/HDLC Mask Register (SCCM) . 23­12 SCC HDLC Status Register (SCCS). 23­14 SCC HDLC Programming Examples . 23­14 SCC HDLC Programming Example #1. 23­14 SCC HDLC Programming Example #2. 23­16 HDLC Bus Mode with Collision Detection. 23­16 HDLC Bus Features. 23­19 Accessing the HDLC Bus . 23­19 Increasing Performance . 23­20 Delayed RTS Mode . 23­20 Using the Time-Slot Assigner (TSA) . 23­22 HDLC Bus Protocol Programming. 23­22 Programming GSMR and PSMR for the HDLC Bus Protocol . 23­22 HDLC Bus Controller Programming Example. 23­23 MPC855T MPC855T User's Manual CONTENTS Paragraph Number Title Page Number Chapter 24 SCC AppleTalk Mode 24.1 24.2 24.3 24.4 24.4.1 24.4.2 24.4.3 24.4.4 Operating the LocalTalk Bus . 24­1 Features . 24­2 Connecting to AppleTalk. 24­3 Programming the SCC in AppleTalk Mode. 24­3 Programming the GSMR . 24­3 Programming the PSMR. 24­4 Programming the TODR. 24­4 SCC AppleTalk Programming Example. 24­4 Chapter 25 SCC Asynchronous HDLC Mode and IrDA 25.1 25.2 25.3 25.4 25.5 25.6 25.7 25.8 25.9 25.9.1 25.9.2 25.10 25.11 25.12 25.13 25.13.1 25.13.2 25.13.3 25.14 25.15 25.16 25.17 Asynchronous HDLC Features . 25­1 Asynchronous HDLC Frame Transmission Processing . 25­2 Asynchronous HDLC Frame Reception Processing. 25­2 Transmitter Transparency Encoding. 25­3 Receiver Transparency Decoding . 25­3 Exceptions to RFC 1549 . 25­4 Asynchronous HDLC Channel Implementation. 25­5 Asynchronous HDLC Mode Parameter RAM. 25­5 Configuring GSMR and DSR for Asynchronous HDLC . 25­6 General SCC Mode Register (GSMR). 25­7 Data Synchronization Register (DSR). 25­7 Programming the Asynchronous HDLC Controller . 25­7 Asynchronous HDLC Commands . 25­7 Handling Errors in the Asynchronous HDLC Controller . 25­8 SCC Asynchronous HDLC Registers . 25­9 Asynchronous HDLC Event Register (SCCE)/Asynchronous HDLC Mask Register (SCCM) .25­9 SCC Asynchronous HDLC Status Register (SCCS) . 25­10 Asynchronous HDLC Mode Register (PSMR) . 25­11 SCC Asynchronous HDLC RxBDs . 25­11 SCC Asynchronous HDLC TxBDs . 25­13 Differences between HDLC and Asynchronous HDLC. 25­14 SCC Asynchronous HDLC Programming Example. 25­15 Contents xxv CONTENTS Paragraph Number Title Page Number Chapter 26 SCC BISYNC Mode 26.1 26.2 26.3 26.4 26.5 26.6 26.7 26.8 26.9 26.10 26.11 26.12 26.13 26.14 26.15 26.16 26.17 Features . 26­2 SCC BISYNC Channel Frame Transmission . 26­2 SCC BISYNC Channel Frame Reception. 26­3 SCC BISYNC Parameter RAM . 26­4 SCC BISYNC Commands . 26­5 SCC BISYNC Control Character Recognition . 26­6 BISYNC SYNC Register (BSYNC). 26­7 SCC BISYNC DLE Register (BDLE) . 26­8 Sending and Receiving the Synchronization Sequence . 26­9 Handling Errors in the SCC BISYNC . 26­9 BISYNC Mode Register (PSMR). 26­10 SCC BISYNC Receive BD (RxBD). 26­12 SCC BISYNC Transmit BD (TxBD). 26­13 BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM). 26­15 SCC Status Registers (SCCS). 26­16 Programming the SCC BISYNC Controller . 26­16 SCC BISYNC Programming Example . 26­17 Chapter 27 SCC Ethernet Mode 27.1 27.2 27.3 27.4 27.5 27.6 27.7 27.7.1 27.7.2 27.8 27.9 27.10 27.11 27.12 27.13 27.14 27.15 27.16 xxvi Ethernet on the MPC855T MPC855T . 27­2 Features . 27­3 Learning Ethernet on the MPC855T MPC855T. 27­4 Connecting the MPC855T MPC855T to Ethernet. 27­4 SCC Ethernet Channel Frame Transmission . 27­6 SCC Ethernet Channel Frame Reception. 27­7 The Content-Addressable Memory (CAM) Interface. 27­8 Serial CAM Interface. 27­8 Parallel CAM Interface. 27­9 SCC Ethernet Parameter RAM . 27­11 Programming the Ethernet Controller. 27­13 SCC Ethernet Commands . 27­13 SCC Ethernet Address Recognition. 27­14 Hash Table Algorithm. 27­16 Interpacket Gap Time . 27­16 Handling Collisions . 27­16 Internal and External Loopback. 27­17 Full-Duplex Ethernet Support. 27­17 MPC855T MPC855T User's Manual CONTENTS Paragraph Number 27.17 27.18 27.19 27.20 27.21 27.22 Title Page Number Handling Errors in the Ethernet Controller. 27­17 Ethernet Mode Register (PSMR) . 27­18 SCC Ethernet Receive Buffer Descriptor . 27­20 SCC Ethernet Transmit Buffer Descriptor. 27­22 SCC Ethernet Event Register (SCCE)/Mask Register (SCCM) . 27­24 SCC Ethernet Programming Example . 27­25 Chapter 28 SCC Transparent Mode 28.1 28.2 28.3 28.4 28.4.1 28.4.1.1 28.4.1.2 28.4.1.2.1 28.4.1.3 28.4.1.4 28.4.2 28.4.2.1 28.4.2.2 28.5 28.6 28.7 28.8 28.9 28.10 28.11 28.12 28.13 28.14 Features . 28­1 SCC Transparent Channel Frame Transmission Process. 28­2 SCC Transparent Channel Frame Reception Process. 28­2 Achieving Synchronization in Transparent Mode . 28­3 Synchronization in NMSI Mode. 28­3 In-Line Synchronization Pattern. 28­3 External Synchronization Signals. 28­4 External Synchronization Example . 28­4 Transparent Mode without Explicit Synchronization. 28­5 End of Frame Detection. 28­5 Synchronization and the TSA . 28­5 In-line Synchronization Pattern . 28­5 Inherent Synchronization. 28­6 CRC Calculation in Transparent Mode. 28­6 SCC Transparent Parameter RAM. 28­6 SCC Transparent Commands. 28­6 Handling Errors in the Transparent Controller . 28­7 Transparent Mode and the PSMR. 28­8 SCC Transparent Receive Buffer Descriptor (RxBD). 28­8 SCC Transparent Transmit Buffer Descriptor (TxBD) . 28­10 SCC Transparent Event Register (SCCE)/Mask Register (SCCM) . 28­11 SCC Status Register in Transparent Mode (SCCS). 28­12 SCC1 Transparent Programming Example. 28­13 Chapter 29 Serial Management Controllers (SMCs) 29.1 29.2 29.2.1 29.2.2 29.2.3 SMC Features. 29­2 Common SMC Settings and Configurations. 29­3 SMC Mode Registers (SMCMRn) . 29­3 SMC Buffer Descriptors (BDs) . 29­4 SMC Parameter RAM. 29­5 Contents xxvii CONTENTS Paragraph Number 29.2.3.1 29.2.4 29.2.4.1 29.2.4.2 29.2.4.3 29.2.4.4 29.2.4.5 29.2.5 29.2.6 29.3 29.3.1 29.3.2 29.3.3 29.3.4 29.3.5 29.3.6 29.3.7 29.3.8 29.3.9 29.3.10 29.3.11 29.3.12 29.3.13 29.4 29.4.1 29.4.2 29.4.3 29.4.4 29.4.5 29.4.6 29.4.7 29.4.8 29.4.9 29.4.10 29.4.11 29.4.12 29.4.13 29.5 29.5.1 29.5.2 29.5.2.1 29.5.2.1.1 29.5.3 xxviii Title Page Number SMC Function Code Registers (RFCR/TFCR) . 29­7 Disabling SMCs On-the-Fly . 29­7 SMC Transmitter Full Sequence . 29­8 SMC Transmitter Shortcut Sequence . 29­8 SMC Receiver Full Sequence . 29­8 SMC Receiver Shortcut Sequence. 29­8 Changing SMC Protocols . 29­9 Saving Power . 29­9 Handling Interrupts In the SMC . 29­9 SMC in UART Mode. 29­9 SMC UART Features. 29­10 SMC UART-Specific Parameter RAM . 29­10 SMC UART Channel Transmission Process . 29­11 SMC UART Channel Reception Process . 29­11 Data Handling Modes: Character- and Message-Oriented . 29­12 SMC UART Commands. 29­12 Sending a Break . 29­13 Sending a Preamble . 29­13 Handling Errors in the SMC UART Controller. 29­13 SMC UART Receive BD (RxBD). 29­14 SMC UART Transmit BD (TxBD) . 29­17 SMC UART Event Register (SMCE)/Mask Register (SMCM). 29­18 SMC UART Controller Programming Example . 29­19 SMC in Transparent Mode. 29­20 SMC Transparent Mode Features . 29­21 SMC Transparent-Specific Parameter RAM . 29­21 SMC Transparent Channel Transmission Process. 29­21 SMC Transparent Channel Reception Process . 29­22 Using SMSYN for Synchronization . 29­22 Using TSA for Synchronization . 29­23 SMC Transparent Commands. 29­25 Handling Errors in the SMC Transparent Controller. 29­26 SMC Transparent Receive BD (RxBD). 29­26 SMC Transparent Transmit BD (TxBD) . 29­27 SMC Transparent Event Register (SMCE)/Mask Register (SMCM). 29­29 SMC Transparent NMSI Programming Example. 29­29 SMC Transparent TSA Programming Example . 29­30 SMC in GCI Mode. 29­31 SMC GCI Parameter RAM. 29­32 Handling the GCI Monitor Channel . 29­32 SMC GCI Monitor Channel Transmission Process. 29­32 SMC GCI Monitor Channel Reception Process . 29­32 Handling the GCI C/I Channel . 29­33 MPC855T MPC855T User's Manual CONTENTS Paragraph Number 29.5.3.1 29.5.3.2 29.5.4 29.5.5 29.5.6 29.5.7 29.5.8 29.5.9 Title Page Number SMC GCI C/I Channel Transmission Process. 29­33 SMC GCI C/I Channel Reception Process . 29­33 SMC GCI Commands. 29­33 SMC GCI Monitor Channel RxBD . 29­33 SMC GCI Monitor Channel TxBD. 29­34 SMC GCI C/I Channel RxBD . 29­35 SMC GCI C/I Channel TxBD. 29­35 SMC GCI Event Register (SMCE)/Mask Register (SMCM). 29­36 Chapter 30 Serial Peripheral Interface (SPI) 30.1 30.2 30.3 30.3.1 30.3.2 30.3.3 30.4 30.4.1 30.4.1.1 30.4.1.2 30.4.2 30.4.3 30.5 30.5.1 30.6 30.7 30.7.1 30.7.1.1 30.7.1.2 30.8 30.9 30.10 Features . 30­2 SPI Clocking and Signal Functions . 30­2 Configuring the SPI Controller. 30­3 The SPI as a Master Device. 30­3 The SPI as a Slave Device . 30­5 The SPI in Multi-master Operation . 30­5 SPI Registers. 30­7 SPI Mode Register (SPMODE) . 30­7 SPI Transfers with Different Clocking Modes . 30­8 SPI Examples with Different SPMODE[LEN] Values . 30­9 SPI Event/Mask Registers (SPIE/SPIM) . 30­10 SPI Command Register (SPCOM) . 30­10 SPI Parameter RAM . 30­11 Receive/Transmit Function Code Registers (RFCR/TFCR) . 30­12 SPI Commands. 30­13 The SPI Buffer Descriptor (BD) Table. 30­13 SPI Buffer Descriptors (BDs) . 30­13 SPI Receive BD (RxBD) . 30­14 SPI Transmit BD (TxBD) . 30­15 SPI Master Programming Example . 30­16 SPI Slave Programming Example. 30­17 Handling Interrupts in the SPI . 30­18 Chapter 31 I2C Controller 31.1 31.2 31.3 31.3.1 I2C Features . 31­2 I2C Controller Clocking and Signal Functions. 31­2 I2C Controller Transfers . 31­3 I2C Master Write (Slave Read). 31­3 Contents xxix CONTENTS Paragraph Number 31.3.2 31.3.3 31.3.4 31.4 31.4.1 31.4.2 31.4.3 31.4.4 31.4.5 31.5 31.6 31.7 31.7.1 31.7.1.1 31.7.1.2 Title Page Number I2C Loopback Testing. 31­4 I2C Master Read (Slave Write). 31­4 I2C Multi-Master Considerations . 31­5 I2C Registers. 31­6 I2C Mode Register (I2MOD). 31­6 I2C Address Register (I2ADD). 31­7 I2C Baud Rate Generator Register (I2BRG). 31­7 I2C Event/Mask Registers (I2CER/I2CMR). 31­8 I2C Command Register (I2COM). 31­8 I2C Parameter RAM . 31­9 I2C Commands . 31­11 I2C Buffer Descriptor (BD) Tables .