MPC8260 - Datasheet Archive

 

Order Number: MPC8260 Rev 2.0, 10/2000 Application Note MPC8260 IDMA Timing Diagram Motorola NetComm, Austin 1.0 Introduction All

 

Semiconductor Products Sector Order Number: MPC8260 MPC8260 Rev 2.0, 10/2000 Application Note MPC8260 MPC8260 IDMA Timing Diagram Motorola NetComm, Austin 1.0 Introduction All the timing diagrams are generated based on the simulations. The MPC8260 MPC8260 provides four general-purpose independent DMA (IDMA) channels which supports memory-to-memory or peripheral-to/from-memory transfers. All the the timing diagrams are for single-address fly-by mode. For dual address mode, a brief discussion is provided. The timing diagrams are organized as followings: 1.1 Fly-by, SDRAM-to-Peripheral, Peripheral-to-SDRAM 1.2 Fly-by, GPCM-to-Peripheral, Peripheral-to-GPCM 1.3 Fly-by, UPM-to-Peripheral, Peripheral-to-UPM 1.4 Fly-by, 60x slave-to-Peripheral, Peripheral-to 60x slave 1.5 Dual Address mode 1.6 DREQ 1.7 DONE This document contains information on a new product under development by Motorola. Motorola reserves the right to change or discontinue this product without notice. © Motorola, Inc., 2000. All rights reserved. IDMA Timing Diagram All the timing diagrams are based on 60x bus access when MPC8260 MPC8260 is in 60x compatible mode. The timings are very similar for 60x bus access in single MPC8260 MPC8260 mode and local bus access. Please refer to Application Note SDRAM Timing Diagram for IDMA programming. 2 IDMA Timing Diagram 1.1 SDRAM-to-Peripheral, Peripheral-to-SDRAM Fly-by Mode 1.1.1 IDMA Fly-by, SDRAM-to-Peripheral, Single Beat with Page Miss/Hit CLKIN ADDR addr1 addr2 DATA D0 D1 TS ALE PSDAMUX AACK ABB DBB DACK TA CS SDRAS SDCAS WE DQM Page Miss Page Hit Figure 1 SDRAM-Peripheral Fly-by 3 IDMA Timing Diagram 1.1.2 IDMA Fly-by, SDRAM-to-Peripheral, Burst with Page Miss CLKIN ADDR addr DATA D0 D1 D2 D3 TS ALE PSDAMUX AACK ABB DBB DACK TA CS SDRAS SDCAS WE DQM PSDMR[ACTTORW] = 011, PSDMR[CL]=2 Figure 2 SDRAM-to-Peripheral Burst, Page Missed 4 IDMA Timing Diagram 1.1.3 IDMA Fly-by, SDRAM-to-Peripheral, Burst with Page Hit CLKIN ADDR DATA addr D0 D1 D2 D3 TS ALE PSDAMUX AACK ABB DBB DACK TA CS SDRAS SDCAS WE DQM PSDMR[ACTTORW] = 011, PSDMR[CL]=2 Figure 3 SDRAM-to-Peripheral Fly-by, Page Hit 5 IDMA Timing Diagram 1.1.4 IDMA Fly-by, Peripheral-to-SDRAM, Single Beat with Page Miss/Hit CLKIN ADDR addr1 addr2 DATA D0 D1 TS ALE PSDAMUX AACK ABB DBB DACK TA CS SDRAS SDCAS WE DQM Page Miss Page Hit PSDMR[ACTTORW] = 011, PSDMR[CL]=2 Figure 4 Peripheral-to-SDRAM, Single Beat 6 IDMA Timing Diagram 7 IDMA Timing Diagram 1.1.5 IDMA Fly-by, Peripheral-to-SDRAM, Burst with Page Miss CLKIN ADDR DATA addr D0 D1 D2 D3 TS ALE PSDAMUX AACK ABB DBB DACK TA CS SDRAS SDCAS WE DQM PSDMR[ACTTORW] = 011, PSDMR[CL]=2 Figure 5 Peripheral-to-SDRAM Burst, Page Missed 8 IDMA Timing Diagram 1.1.6 IDMA Fly-by, Peripheral-to-SDRAM, Burst with Page Hit CLKIN ADDR DATA addr D0 D1 D2 D3 TS ALE PSDAMUX AACK ABB DBB DACK TA CS SDRAS SDCAS WE DQM PSDMR[ACTTORW] = 011, PSDMR[CL]=2 Figure 6 Peripheral-to-SDRAM Burst, Page Hit 9 IDMA Timing Diagram 1.2 GPCM-to-Peripheral, Peripheral-to-GPCM Fly-by Note: GPCM does not support burst mode. 1.2.1 IDMA Fly-by, GPCM-to-Peripheral, Single Beat CLKIN ADDR addr Data DATA TS ALE AACK ABB DBB DACK TA CS WE OE BCTL0 BADDR addr Figure 7 GPCM-to-Peripheral Single Beat Fly-by 10 IDMA Timing Diagram 1.2.2 IDMA Fly-by, Peripheral-to-GPCM, Single Beat CLKIN ADDR DATA addr Data TS ALE AACK ABB DBB DACK TA CS WE OE BCTL0 BADDR addr Figure 8 Peripheral-to-GPCM Single Beat Fly-by 11 IDMA Timing Diagram 1.3 UPM-to-Peripheral, Peripheral-to-UPM Fly-by 1.3.1 IDMA Fly-by, UPM-to-Peripheral/Peripheral-to-UPM, Single Beat CLKIN ADDR addr Data DATA TS ALE AACK ABB DBB DACK PSDVAL TA CS BS PGPLx Read/Write Pattern Figure 9 UPM-to-Peripheral/Peripheral-to-UPM Single Beat Fly-by Note: UPM-to-Peripheral corresponds to READ pattern. Peripheral-to-UPM corresponds to WRITE pattern. 12 IDMA Timing Diagram 1.3.2 IDMA Fly-by, UPM-to-Peripheral/Peripheral-to-UPM, Burst CLKIN ADDR addr DATA D0 D1 D2 D3 TS ALE AACK ABB DBB DACK PSDVAL TA CS BS PGPLx Burst Read/Write Pattern Figure 10 UPM-to-Peripheral/Peripheral-to-UPM Burst Fly-by Note: UPM-to-Peripheral corresponds to BURST READ pattern. Peripheral-to-UPM corresponds to BURST WRITE pattern. 13 IDMA Timing Diagram 1.4 Slave-to-Peripheral, Peripheral-to-Slave Fly-by 1.4.1 IDMA Fly-by, Slave-to-Peripheral CLKIN ADDR addr Data DATA TT 0A (read) TS ALE AACK ABB DBB DACK TA BADDR addr Figure 11 Slave-to-Peripheral Fly-by 14 IDMA Timing Diagram 1.4.2 IDMA Fly-by, Peripheral-to-slave CLKIN ADDR addr Data DATA TT 02 (write) TS ALE AACK ABB DBB DACK TA BADDR addr Figure 12 Peripheral-to-Slave Fly-by 15 IDMA Timing Diagram 1.5 Dual-Address Mode IDMA dual-address mode consists of read phase and write phase. The timing information of dual-address SDRAM transaction can be found in Burst Mode section of Application note: SDRAM Timing Diagram. GPCM does not support burst mode. The timing of dual-address GPCM is the regular GPCM read/write. Please refer to Application note: GPCM Timing Diagram. The timing information of dual-address UPM transaction can be found in Burst Mode section of Application note: UPM Timing Diagram if UPM burst mode is enabled( Clear ORx[BI] to 0). If burst mode is disabled, refer to the single beat section. The timing diagrams for dual-address peripheral-to/from-memory are shown in Figure 13 & 14. 16 IDMA Timing Diagram 1.5.1 Dual Address Peripheral-to-Memory CLKIN ADDR addr Data DATA TT 0A (read) TS ALE AACK ABB DBB DACK TA Figure 13 Peripheral-to-Memory Dual-Address Note: 1. Only read-from-peripheral phase is shown. The write-to-memory phase is the regular memory write. 2.The peripheral device can distinguish IDMA read from regular read by DACK which is asserted along with DBB during IDMA transaction. 3. After the peripheral determines that it is a IDMA transaction, it may use the information on the address bus and attribute signals to decide the action it needs to take. It needs to assert AACK to terminate the address tenure, output data and assert TA to terminate the data tenure. 17 IDMA Timing Diagram 1.5.2 Dual-address Memory-to-Peripheral CLKIN ADDR addr Data DATA TT 02 (write) TS ALE AACK ABB DBB DACK TA Figure 14 Memory-to-Peripheral Dual-Address Note: 1. Only write-to-peripheral phase is shown. The read-from-memory phase is the regular memory read. 2.The peripheral device can distinguish IDMA write from regular write by DACK which is asserted along with DBB during IDMA transaction. 3. After the peripheral determines that it is a IDMA transaction, it may use the information on the address bus and attribute signals to decide the action it needs to take. It needs to assert AACK to terminate the address tenure, latch the data and assert TA to terminate the data tenure. 18 IDMA Timing Diagram 1.6 DREQ Timing 1.6.1 DREQ Timing for Dual Address Peripheral-to-Memory CLKIN ADDR DATA addr Data DREQ TS ALE AACK ABB DBB DACK TA regular cycle Read of STS bytes from Peripheral Figure 15 Peripheral-to-Memory Dual Address Note: The first DREQ peripheral assertion triggers a read of STS bytes from the peripheral. Subsequent DREQ assertions trigger the same read from the peripheral. When the internal buffer reaches the steady-state level, it is automatically written to the memory destination in one transfer. 19 IDMA Timing Diagram 1.6.2 DREQ Timing for Dual Address Memory-to-Peripheral CLKIN ADDR DATA addr Data DREQ TS ALE AACK ABB DBB DACK TA regular cycle read SS_MAX bytes from memory write DTS to peripheral Figure 16 Memory-to-Peripheral Dual Address Note: The first DREQ peripheral assertion triggers a read of SS_MAX bytes from the memory into the internal transfer buffer, automatically followed by a write of DTS bytes to the peripheral. Subsequent DREQ assertions trigger writes to the pripheral. When the transfer buffer has fewer than DTS bytes left, the next DREQ assertion triggers a read of SS_MAX bytes from the memory, automatically followed by a write to the peripheral, and the sequence begins again. 20 IDMA Timing Diagram 1.6.3 DREQ Timing for Fly-by Mode CLKIN ADDR DATA addr Data DREQ TS ALE AACK ABB DBB DACK TA regular cycle One Fly-by Transfer of Port Size Figure 17 Fly-by Mode Note: Each DREQ peripheral assertion triggers a transfer of the port size between peripheral and memory directly. When the programmed transfer length is reached or DONE is asserted by the peripheral, the BD is closed. 21 IDMA Timing Diagram 1.7 DONE Internal Assertion of DONE: When IDMA has finished transferring the programmed number of data, at its last phase of read/write, MPC8260 MPC8260 asserts DONE. DONE can be enabled and disable by BD[SDN] and BD[DDN] bits. For dual-address memory-to-memory mode, DONE assertion is not supported, it should be disabled. For fly-by mode, SDN should be the same as DDN. If SDN=DDN=0, DONE is disabled. Otherwise enable. For dual-address peripheral-to/from-memory mode, in general, only the bit that is associated with peripheral may be enabled. For example, for peripheral-to-memory dual address mode, the peripheral is the source. SDN can be either 0 or 1, but DDN should be clear to 0. If DDN is set to 1, then during the last write to memory phase, DONE as well as DACK is asserted. The assertion of DACK during memory access cycles might cause problem to the peripheral. Whenever DONE is asserted, its waveform is the same as DACK. External Assertion of DONE: If the peripheral decides there is no more data to transfer, it can assert DONE externally to terminate the IDMA operation. For dual-address memory-to-memory mode, DONE assertion is not supported. Figure 18/19 illustrates two scenarios for the fly-by mode. When DONE is asserted, if prior to DONE assertion, there is DREQ assertion which has not been executed by IDMA, then IDMA will execute that pending DREQ, i.e., do one more transfer and stop. Otherwise, if there is no pending DREQ, IDMA will stop right after DONE assertion. For dual-address Memory-to-peripheral and Peripheral-to-memory modes, timing diagrams of three scenarios are given for each mode. 22 IDMA Timing Diagram 1.7.1 Fly-by mode Transfer Termination by External DONE 1.7.1.1 Fly-by mode Transfer Termination by External DONE without Pending DREQ DREQ DACK DONE STOP Figure 18 Fly-by Mode Extermination by DONE without Pending DREQ Note: When DONE is asserted, if all the previous DREQs have been serviced, there is no pending DREQ, the BD will be closed and IDMA stops right after DONE. All the signals are not scaled. DONE is one cycle. 1.7.1.2 Fly-by mode Transfer Termination by External DONE with Pending DREQ DREQ DACK DONE STOP Figure 19 Fly-by Mode Extermination by DONE with Pending DREQ Note: When DONE is asserted, there is one unserviced DREQ. The BD will be closed and IDMA stops after the pending DREQ is serviced. All the signals are not scaled. DONE is one cycle. 23 IDMA Timing Diagram 1.7.2 Dual-address Memory-to-Peripheral Termination by External DONE 1.7.2.1 Dual-address Memory-to-peripheral Mode Scenario 1 DREQ DACK DONE Memory READ 1st WRITE to Peripheral STOP Figure 20 Memory-to-Peripheral Mode Extermination by DONE Scenario 1 Note: This diagram shows the scenario that previous DREQ triggers a memory read. After the memory read, one write to the peripheral follows automatically without the need of DREQ assertion. This memory read plus one write is integral. Even if DONE is asserted after DREQ but before the peripheral write, IDMA will proceed with this Memory Read + Write to Peripheral combination and then stop. All the signals are not scaled. DONE is one cycle. 24 IDMA Timing Diagram 1.7.2.2 Dual-address Memory-to-peripheral Mode Scenario 2 DREQ DACK DONE STOP Figure 21 Memory-to-Peripheral Mode Extermination by DONE Scenario 2 Note: This diagram shows the scenario that the previous DREQ triggers a write to the peripheral. Then DONE assertion follows without pending DREQ. Under this situation, IDAM will stop right after DONE assertion. All the signals are not scaled. DONE is one cycle. 1.7.2.3 Dual-address Memory-to-peripheral Mode Scenario 3 DREQ DACK DONE STOP Figure 22 Memory-to-Peripheral Mode Extermination by DONE Scenario 3 Note: When DONE is asserted, there is one unserviced DREQ. IDMA will stop after this pending DREQ is serviced. All the signals are not scaled. DONE is one cycle. 25 IDMA Timing Diagram 1.7.3 Dual-address Peripheral-to-Memory Termination by External DONE 1.7.3.1 Dual-address Peripheral-to-memory Mode Scenario 1 DREQ DACK DONE Internal Buffer = SS_MAX Write to Memory STOP Figure 23 Peripheral-to-Memory Mode Extermination by DONE Scenario 1 Note: This diagram shows the scenario that when the internal buffer reaches SS_MAX bytes, it will automatically trigger write to memory without the need of DREQ assertion. Even the DONE is asserted prior to the memory write, IDMA will finish the memory write and stop. All the signals are not scaled. DONE is one cycle. 26 IDMA Timing Diagram 1.7.3.2 Dual-address Peripheral-to-memory Mode Scenario 2 DREQ DACK DONE Internal Buffer < SS_MAX Memory Write STOP Figure 24 Peripheral-to-Memory Mode Extermination by DONE Scenario 2 Note: This diagram shows the scenario that the previous DREQ does not fill the internal buffer. When DONE is asserted, there is no unserviced DREQ. Under this scenario, IDMA will transfer all the data in the buffer to memory and then stop. All the signals are not scaled. DONE is one cycle. 27 IDMA Timing Diagram 1.7.3.3 Dual-address Peripheral-to-memory Mode Scenario 3 DREQ DACK DONE Internal Buffer < SS_MAX Memory Write STOP Figure 25 Memory-to-Peripheral Mode Extermination by DONE Scenario 3 Note: This diagram shows the scenario that the previous DREQ does not fill the internal buffer. When DONE is asserted, there is one unserviced DREQ. IDMA will service this pending DREQ first, then transfer all the data in the buffer to memory and stop. All the signals are not scaled. DONE is one cycle. 28 DigitalDNA and Mfax are trademarks of Motorola, Inc. The PowerPC name, the PowerPC logotype, and PowerPC 603e are trademarks of International Business Machines Corporation used by Motorola under license from International Business Machines Corporation. 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