MPC7455 MPC7445 MPC7451 MPC7441 MPC7455/MPC7445 MPC7455FACT

MPC7455 MPC7445 HOST PROCESSORS MPC7455 and MPC7445 host processors are highperformance, low-power, 32-bit implementations of the

Fact Sheet MPC7455 MPC7455 MPC7445 MPC7445 HOST PROCESSORS MPC7455 MPC7455 and MPC7445 MPC7445 host processors are highperformance, low-power, 32-bit implementations of the PowerPC RISC architecture with a full 128-bit implementation of Motorola's AltiVecTM technology. These microprocessors are ideal for leading-edge computing, embedded network control, and signal processing applications. Designed as pin compatible replacements for Motorola's MPC7451 MPC7451 and MPC7441 MPC7441 products respectively, the newest processors have been shown to reach speeds of 1 GHz with 256 KB of on-chip L2 cache and to support of up to 2 MB of backside L3 cache. The MPC7445 MPC7445 has no backside L3 cache, allowing for a smaller package. Both devices benefit from Motorola's silicon-on-insulator process technology, engineered to help deliver tremendous power savings without sacrificing speed. Low-power versions of both are available. EMBEDDED ENHANCEMENTS MPC7455/MPC7445 MPC7455/MPC7445 CPU Speeds Internal 600, 733, 800, 867, 933 MHz and 1 GHz MPC7455/MPC7445 MPC7455/MPC7445 Low Power Version 600, 733 and 800 MHz Bus Frequency 133 MHz 133 MHz Bus Interface 64-bit 64-bit Bus Protocol MPX/60x MPX/60x 4 (3 + Branch) 4 (3 + Branch) Integrated L1 Cache 32 KB instruction 32 KB data 32 KB instruction 32 KB data Integrated L2 Cache 256 KB 256 KB 1 or 2 MB [MPC7455 MPC7455 only] 1 or 2 MB [MPC7455 MPC7455 only] 21.3W @ 1 GHz 10.3W @ 733 MHz Instructions per Clock L3 Cache support Typical Power Consumption Package 483/360 CBGA Process 0.18µ 6LM CMOS with SOI Voltage Performance (est.) Execution Units 483/360 CBGA 0.18µ 6LM CMOS with SOI 1.6V internal, 1.8/2.5V I/O 1.3V internal, 1.8/2.5V I/O 2310 Dhrystone 2.1 MIPS @ 1 GHz 1848 Dhrystone 2.1 MIPS @ 800 MHz Integer(4), Floating-Point, AltiVec(4), Branch, Load/Store Integer(4), Floating-Point, AltiVec(4), Branch, Load/Store The MPC7455 MPC7455 and MPC7445 MPC7445 have increased both the instruction BAT and data BAT registers from 4 to 8 to help support lightweight embedded operating systems, enabling more large tables of data. The processors have also added cache locking to the L1 caches so that key performance algorithms and code can be locked in the L1 cache. SUPERSCALAR MICROPROCESSOR MPC7455 MPC7455 Block Diagram Instruction Fetch Branch Unit Completion Unit Sequencer Unit Dispatch Unit AltiVecTM Issue BHT/ BTIC GPR Issue MPC7455 MPC7455 and MPC7445 MPC7445 microprocessors feature a highfrequency superscalar G4 core, capable of issuing four instructions per clock cycle (three instructions + branch) into eleven independent execution units: 32KB Instruction Cache FPR Issue CFX SFXO SFX1 SFX2 GPRs Rename Buffers FPRs Rename Buffers LSU SIMPLE PERMUTE COMPLEX FLOAT 32KB Data Cache VRs Rename Buffers · Four integer units (3 simple + 1 complex) · Double-precision floating-point unit · Four AltiVec units (simple, complex, floating, and permute) · Load/store unit · Branch processing unit FPU COMPATABILITY AND SUPPORT Interface to Memory Sub-System L3 Cache AltiVec Engine 256 KB Unified L2 and L3 Cache/Tag Control System Interface Unit 60x/MPX bus interface Instruction Fetch Branch Unit Completion Unit Sequencer Unit Dispatch Unit AltiVecTM Issue 32KB Instruction Cache BHT/ BTIC GPR Issue · Pin for pin compatible with MPC7451 MPC7451 and MPC7441 MPC7441 processors · As with all processors implanting the PowerPC instruction-set architecture, the MPC7455 MPC7455 and MPC7445 MPC7445 are software compatible with the MPC7xx family of processors from Motorola. · Processors implementing the PowerPC instruction-set architecture enjoy one of the broadest sets of operating systems, compilers, and development tools from third party vendors. FPR Issue CFX SFXO SFX1 SFX2 GPRs Rename Buffers FPRs Rename Buffers LSU SIMPLE PERMUTE FLOAT COMPLEX VRs Rename Buffers 32KB Data Cache FPU Interface to Memory Sub-System AltiVec Engine 256 KB Unified L2 Cache/Tag Control System Interface Unit 60x/MPX bus interface MPC7445 MPC7445 Block Diagram MOTOROLA and the Stylized M Logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners. © Motorola, Inc. 2002. MPC7455FACT MPC7455FACT Rev3