MPC7440 256KB 4/15W MPC7440FACT/D

High Performance, Low-Power 32-Bit PowerPC TM RISC Microprocessor The MPC7440 PowerPC microproces- MPC7440 is software-compatible

M P C 74 4 0 High Performance, Low-Power 32-Bit PowerPC TM RISC Microprocessor The MPC7440 MPC7440 PowerPC microproces- MPC7440 MPC7440 is software-compatible with sor is a high-performance, low-power, existing PowerPC 603e, 750, 7400, 7410 32-bit implementation of the PowerPC and 7450 processors and exploits the RISC architecture with a full 128-bit full potential of AltiVec technology. implementation of Motorola's AltiVec technology. This microprocessor is ideal for leading-edge computing, embedded network control, and signal processing Superscalar Microprocessor applications. The MPC7440 MPC7440 has a deep- MPC7440 MPC7440 microprocessors feature a er, seven-stage pipeline with eleven exe- high-frequency superscalar PowerPC cution units. The L2 cache has been core, capable of issuing four instruc- integrated onto the die for greater speed, tions per clock cycle (three instructions and a 256bit datapath to the L1 cache + branch) into eleven independent has been implemented. The MPC7440 MPC7440 execution units: offers increased address space and high- · Four integer units (3 simple + 1 complex) bandwidth MPX bus with minimized signal setup times and reduced idle cycles · Double-precision floating-point unit to increase bus bandwidth to a maxi- · Four AltiVec units (simple, complex, floating, and permute) mum speed of 133MHz. MPC7440 MPC7440 processors offer single-cycle throughput · Load/store unit double precision floating-point perfor- · Branch processing unit mance and full symmetric multi-process- Cache and MMU Support ing (SMP) capabilities. Finally, the The MPC7440 MPC7440 microprocessor has sepaInstruction Fetch Branch Unit Completion Unit Sequencer Unit Dispatch Unit AltiVec Issue BHT/ BTIC GPR Issue 32KB Instruction Cache FPR Issue rate 32KB, physically addressed instruction and data caches. Both L1 caches feature cache way locking and are eight-way set associative. This L2 is 256KB 256KB eight-way set associative. L2 cache access is fully CFX SFXO SFX1 SFX2 GPRs Rename Buffers FPRs Rename Buffers LSU PERMUTE SIMPLE FLOAT COMPLEX VRs Rename Buffers 32KB Data Cache FPU pipelined. Finally, in addition to supporting hardware table searching, the MPC7440 MPC7440 can be configured for software table Interface to Memory Sub-System searching. In this case, TLB entries are loaded by the system software. AltiVec Engine Unified L2 Cache System Interface Unit The MPC7440 MPC7440 microprocessor contains separate memory management units for instructions and data, supporting 4 60x/MPX bus interface MPC7440 MPC7440 Block Diagram Petabytes (252) of virtual memory and up to 64 Gigabytes (236) of physical memory. The MPC7440 MPC7440 also has four instruction block address translation and four data block address translation MPC7440 MPC7440 The AltiVec technology expands the capabilities of Motorola's fourth generation PowerPC microprocessors by providing leading-edge, general purpose processing performance while concur- 600 and 700MHz CPU Speeds Internal Bus Frequency 133MHz Bus Interface 64-bit Bus Protocol MPX/60x 4 (3 + Branch) Instructions per Clock Integrated L1 Cache 32 KB instruction 32 KB data Integrated L2 Cache 256 KB Typical/Maximum Power Dissipation 11.4/15W 4/15W @ 600MHz 13.4/17.5W @ 700MHz Package 360 CBGA Process 0.18µ 6LM CMOS Voltage 1.5V internal, 1.8/2.5V I/O Drystone 2.1: 1083 MIPS @ 600MHz 1264 @ 700MHz Other Performance Execution Units registers. AltiVec Technology Integer(4), Floating-Point, AltiVec(4), Branch, Load/Store MPX Bus Interface rently addressing high-bandwidth data processing and algorithmic-intensive MPC7440 MPC7440 microprocessors support the MPX bus protocol with a 64-bit data bus and a 32- or 36-bit address computations in a single-chip solution. AltiVec technology: · bus. Support is included for burst, split, of networking infrastructure such as pipelined and out-of-order transactions, echo cancellation equipment, and in addition to data streaming, and data intervention (in SMP systems). The basestation processing. · interface provides snooping for data SIMD processing model. · for multiprocessing support in hard- computers, desktop publishing, and ory for additional caching bus masters, Power Management Contact Information MPC7440 MPC7440 microprocessors feature a Motorola offers user's manuals, application notes, low-power 1.5-volt design with three sample code and full local support for the power-saving user-programmable PowerPC product line. For more information, visit: · Enables real-time processing of the most demanding data streams (MPEG-2 encode, continuous and sleep - which progressively http://motorola.com/AltiVec/ digital video processing. modes - nap, doze (with bus snoop) http://motorola.com/PowerPC/ and Provides compelling performance for multimedia-oriented desktop ware, allowing access to system mem- such as DMA devices. Enables faster, more secure encryption methods optimized for the cache coherency. The MPC7440 MPC7440 implements the cache coherency protocol Meets the computational demands reduce the power drawn by the speech recognition, real-time highresolution 3D memory for 3D graphics.) processor. The MPC7440 MPC7440 also provides For all other inquiries about Motorola products, a thermal assist unit and instruction please contact the Motorola Customer Response cache throttling for software-control- Center at: 1-800-521-6274 or lable thermal management. http://motorola.com/semiconductors TM © 2001 Motorola, Inc. All rights reserved. Motorola and the Motorola logo are registered trademarks of Motorola, Inc., and AltiVec, DigitalDNA and the DigitalDNA logo are trademarks of Motorola, Inc. PowerPC and the PowerPC logo are trademarks of International Business Machines Corporation and used under license therefrom. MPC7440FACT/D MPC7440FACT/D Rev. 0