MPC5604BC MPC5604B/C QFN12 MPC56 MPC560 OSC32K TDO10 CAN4TX11 CAN4RX11 CAN3RX11 - Datasheet Archive

 

Data Sheet: Advance Information Document Number: MPC5604BC Rev. 7, 07/2010 MPC5604B/C MAPBGA­225 QFN12 144 LQFP ##_mm_x_##mm

 

Freescale Semiconductor Data Sheet: Advance Information Document Number: MPC5604BC MPC5604BC Rev. 7, 07/2010 MPC5604B/C MPC5604B/C MAPBGA­225 QFN12 QFN12 144 LQFP ##_mm_x_##mm 208 15 mm x 15 mm MAPBGA (17 x 17 x 1.7 mm) MPC5604B/C MPC5604B/C Microcontroller Data Sheet 32-bit MCU family built on the Power Architecture® for automotive body electronics applications Features · · · · · · · · · · · · · Single issue, 32-bit CPU core complex (e200z0) - Compliant with the Power Architecture® embedded category - Includes an instruction set enhancement allowing variable length encoding (VLE) for code size footprint reduction. With the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. Up to 512 Kbytes on-chip data flash supported with the flash controller 64 (4 × 16) KB on-chip data flash memory with ECC Up to 48 Kbytes on-chip SRAM Memory protection unit (MPU) with 8 region descriptors and 32-byte region granularity Interrupt controller (INTC) with 148 interrupt vectors, including 16 external interrupt sources and 18 external interrupt/wakeup sources Frequency modulated phase-locked loop (FMPLL) Crossbar switch architecture for concurrent access to peripherals, flash, or RAM from multiple bus masters Boot assist module (BAM) supports internal flash programming via a serial link (CAN or SCI) Timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (eMIOS-lite) 10-bit analog-to-digital converter (ADC) 3 serial peripheral interface (DSPI) modules Up to 4 serial communication interface (LINFlex) modules SOT-343R ##_mm_x_##mm 100 LQFP (14 x 14 x 1.4 mm) 1 TBD PKG-TBD ## mm x ## mm 64 LQFP (10 x 10 x 1.4 mm) Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 Descrioption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . 8 3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 30 4.5 Recommended operating conditions . . . . . . . . . . . . . . 31 4.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 33 4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . 35 4.8 RESET electrical characteristics . . . . . . . . . . . . . . . . . 46 4.9 Power management electrical characteristics . . . . . . . 48 4.10 Low voltage domain power consumption . . . . . . . . . . . 51 4.11 Flash memory electrical characteristics . . . . . . . . . . . . 53 4.12 Electromagnetic compatibility (EMC) characteristics . . 57 4.13 Fast external crystal oscillator (4 to 16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 59 4.14 Slow external crystal oscillator (32 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 62 4.15 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 64 4.16 Fast internal RC oscillator (16 MHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 65 4.17 Slow internal RC oscillator (128 kHz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 65 4.18 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 66 4.19 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 5 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 5.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 84 6 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 7 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Appendix A Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009, 2010. All rights reserved. (20 x 20 x 1.4 mm) Introduction · · · · · · · · · Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers 1 inter IC communication interface (I2C) module Up to 123 configurable general purpose pins supporting input and output operations (package dependent) Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz internal RC oscillator supporting autonomous wakeup with 1 ms resolution with max timeout of 2 seconds Up to 6 periodic interrupt timers (PIT) with 32-bit counter resolution 1 System Module Timer (STM) Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1) On-chip voltage regulator (VREG) for regulation of input supply for all internal levels 1 Introduction 1.1 Document overview This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also to the device reference manual and errata sheet. 1.2 Descrioption The MPC5604B/C MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture® embedded category. The MPC5604B/C MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU, providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users implementations. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 2 Freescale Semiconductor Freescale Semiconductor Table 1. MPC5604B/C MPC5604B/C device comparison1 Device Feature MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC560 MPC560 02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL 4BxMG CPU e200z0h Execution speed2 Static ­ up to 64 MHz Code Flash 256 KB 384 KB MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Data Flash 64 KB (4 × 16 KB) RAM 24 KB 32 KB 28 KB 40 KB MPU ADC 512 KB 32 KB 48 KB 8-entry 12 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 8 ch, 10-bit 28 ch, 10-bit 12 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit CTU 8 ch, 10-bit 28 ch, 10-bit 12 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 8 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit Yes Total timer I/O3 12 ch, eMIOS 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 12 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit · PWM + MC + IC/OC4 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 2 ch 5 ch 10 ch 2 ch 5 ch 10 ch · PWM + IC/OC4 10 ch 20 ch 40 ch 10 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 10 ch 20 ch 40 ch 10 ch 20 ch 40 ch · IC/OC4 0 ch 3 ch 6 ch 0 ch 3 ch 0 ch 3 ch 6 ch 0 ch 3 ch 0 ch 3 ch 6 ch 0 ch 3 ch 6 ch 35 SCI (LINFlex) SPI (DSPI) 2 4 3 2 6 CAN (FlexCAN) 5 2 3 2 3 2 37 6 5 I2C 2 3 5 6 Yes 45 79 123 45 79 45 79 123 JTAG 45 79 123 45 79 123 Nexus2+ 3 Introduction Debug 79 3 37 6 45 2 1 32 kHz oscillator GPIO8 3 Device Feature Package 1 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC560 MPC560 02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL 4BxMG 64 LQFP9 100 LQFP 144 LQFP 64 LQFP9 100 LQFP 64 LQFP9 100 LQFP 144 LQFP 64 LQFP9 100 LQFP 64 LQFP9 Feature set dependent on selected peripheral multiplexing-table shows example implementation Based on 105 °C ambient operating temperature 3 Refer to eMIOS section of device reference manual for information on the channel configuration and functions 4 IC - Input Capture; OC - Output Compare; PWM - Pulse Width Modulation; MC - Modulus counter 5 SCI0, SCI1 and SCI2 are available. SCI3 is not available. 6 CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available. 7 CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available. 8 I/O count based on multiplexing with peripherals 9 All 64 LQFPinformation is indicative and must be confirmed during silicon validation. 10 208 MAPBGA available only as development package for Nexus2+ 2 100 LQFP 144 LQFP 64 LQFP9 100 LQFP 208 MAPBG A10 Introduction 4 Table 1. MPC5604B/C MPC5604B/C device comparison1 (continued) MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor Block diagram 2 Block diagram Figure 1 shows a top-level block diagram of the MPC5604B/C MPC5604B/C device series. Figure 1. MPC5604B/C MPC5604B/C series block diagram SRAM 48 KB Code Flash Data Flash 512 KB 64 KB SRAM controller Flash controller eDMA JTAG e200z0h Nexus (Master) Data NMI Nexus 2+ (Master) SIUL Voltage regulator Interrupt requests from peripheral blocks NMI INTC Clocks MPU Instructions Nexus port 64-bit 2 x 3 Crossbar Switch (Master) JTAG port (Slave) (Slave) (Slave) MPU registers CMU FMPLL RTC STM SWT ECSM MC_RGM MC_CGM MC_ME PIT MC_PCU SSCM BAM Peripheral bridge Interrupt request SIUL Reset control 36 Ch. ADC CTU 2x eMIOS 4x LINFlex 3x DSPI 6x FlexCAN I2C External interrupt request IMUX WKPU GPIO and pad control I/O . . . . . Interrupt request with wakeup functionality Legend: ADC BAM FlexCAN CMU CTU DSPI eDMA eMIOS FMPLL I2C IMUX INTC JTAG LINFlex ECSM Analog-to-Digital Converter Boot Assist Module Controller Area Network Clock Monitor Unit Cross Triggering Unit Deserial Serial Peripheral Interface Enhanced Direct Memory Access Enhanced Modular Input Output System Frequency-Modulated Phase-Locked Loop Inter-integrated Circuit Bus Internal Multiplexer Interrupt Controller JTAG controller Serial Communication Interface (LIN support) Error Correction Status Module MC_CGM MC_ME MC_PCU MC_RGM MPU Nexus NMI PIT RTC SIUL SRAM SSCM STM SWT WKPU Clock Generation Module Mode Entry Module Power Control Unit Reset Generation Module Memory Protection Unit Nexus Development Interface (NDI) Level Non-Maskable Interrupt Periodic Interrupt Timer Real-Time Clock System Integration Unit Lite Static Random-Access Memory System Status Configuration Module System Timer Module Software Watchdog Timer Wakeup Unit MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 5 Block diagram Table 2 summarizes the functions of all blocks present in the MPC5604B/C MPC5604B/C series of microcontrollers. Please note that the presence and number of blocks varies by device and package. Table 2. MPC5604B/C MPC5604B/C series block summary Block Function Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to digital-converter Boot assist module (BAM) A block of read-only memory containing VLE code which is executed according to the boot mode of the device Clock monitor unit (CMU) Monitors clock source (internal and external) integrity Cross triggering unit (CTU) Enables synchronization of ADC conversions with a timer event from the eMIOS or from the PIT Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices (DSPI) Error Correction Status Module (ECSM) Provides a myriad of miscellaneous control functions for the device including program-visible information about configuration and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors reported by error-correcting codes Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host processor (eDMA) via "n" programmable channels. Enhanced modular input output system (eMIOS) Provides the functionality to generate or measure events Flash memory Provides non-volatile storage for program code, constants and variables FlexCAN (controller area network) Supports the standard CAN communications protocol FMPLL (frequency-modulated phase-locked loop) Generates high-speed system clocks and supports programmable frequency modulation Internal multiplexer (IMUX) SIU subblock Allows flexible mapping of peripheral interface on the different pins of the device Inter-integrated circuit (I2CTM) bus A two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices Interrupt controller (INTC) Provides priority-based preemptive scheduling of interrupt requests JTAG controller Provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode LINflex controller Manages a high number of LIN (Local Interconnect Network protocol) messages efficiently with a minimum of CPU load Clock generation module (MC_CGM) Provides logic and control required for the generation of system and peripheral clocks Mode entry module (MC_ME) Provides a mechanism for controlling the device operational mode and mode transition sequences in all functional states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications Power control unit (MC_PCU) Reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called "power domains" which are controlled by the PCU Reset generation module (MC_RGM) Centralizes reset sources and manages the device reset sequence of the device MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 6 Freescale Semiconductor Block diagram Table 2. MPC5604B/C MPC5604B/C series block summary (continued) Block Function Memory protection unit (MPU) Provides hardware access control for all memory references generated in a device Nexus development interface (NDI) Provides real-time development support capabilities in compliance with the IEEE-ISTO 5001-2003 standard Periodic interrupt timer (PIT) Produces periodic interrupts and triggers Real-time counter (RTC) A free running counter used for time keeping applications, the RTC can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) System integration unit (SIU) Provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration Static random-access memory (SRAM) Provides storage for program code, constants, and variables System status configuration module (SSCM) Provides system configuration and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable System timer module (STM) Provides a set of output compare events to support AUTOSAR and operating system tasks System watchdog timer (SWT) Provides protection from runaway code Wakeup unit (WKPU) The wakeup unit supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. Crossbar (XBAR) switch Supports simultaneous connections between two master ports and three slave ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus width MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 7 Package pinouts and signal descriptions 3 Package pinouts and signal descriptions 3.1 Package pinouts The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions, please refer to the device reference manual. 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PB[2] PC[8] PC[4] PC[5] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] Figure 2. LQFP 64-pin configuration (top view)1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PA[11] PA[10] PA[9] PA[8] PA[7] PA[3] PB[15] PB[14] PB[13] PB[12] PB[11] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PB[4] 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB[3] PC[9] PA[2] PA[1] PA[0] VPP_TEST VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6] 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PB[2] PC[8] PC[4] PC[5] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] Figure 3. LQFP 64-pin configuration 5CAN 4LIN (top view)2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 LQFP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PA[11] PA[10] PA[9] PA[8] PA[7] PF[14] PF[15] PG[0] PG[1] PA[3] PB[15] PB[14] PB[11] PB[7] VDD_HV_ADC VSS_HV_ADC PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PB[4] 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PB[3] PC[9] PA[2] PA[1] PA[0] VPP_TEST VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[10] PB[0] PB[1] PC[6] 1. All 64 LQFPinformation is indicative and must be confirmed during silicon validation. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 8 Freescale Semiconductor Package pinouts and signal descriptions 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PE[12] Figure 4. LQFP 100-pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 LQFP 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PA[11] PA[10] PA[9] PA[8] PA[7] VDD_HV VSS_HV PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC PC[7] PA[15] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PB[3] PC[9] PC[14] PC[15] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PC[11] PC[10] PB[0] PB[1] PC[6] Note: Availability of port pin alternate functions depends on product selection. 2. All 64 LQFPinformation is indicative and must be confirmed during silicon validation. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 9 Package pinouts and signal descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 144 LQFP 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PA[11] PA[10] PA[9] PA[8] PA[7] PE[13] PF[14] PF[15] VDD_HV VSS_HV PG[0] PG[1] PH[3] PH[2] PH[1] PH[0] PG[12] PG[13] PA[3] PB[15] PD[15] PB[14] PD[14] PB[13] PD[13] PB[12] PD[12] PB[11] PD[11] PD[10] PD[9] PB[7] PB[6] PB[5] VDD_HV_ADC VSS_HV_ADC PC[7] PF[10] PF[11] PA[15] PF[13] PA[14] PA[4] PA[13] PA[12] VDD_LV VSS_LV XTAL VSS_HV EXTAL VDD_HV PB[9] PB[8] PB[10] PF[0] PF[1] PF[2] PF[3] PF[4] PF[5] PF[6] PF[7] PD[0] PD[1] PD[2] PD[3] PD[4] PD[5] PD[6] PD[7] PD[8] PB[4] 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PB[3] PC[9] PC[14] PC[15] PG[5] PG[4] PG[3] PG[2] PA[2] PE[0] PA[1] PE[1] PE[8] PE[9] PE[10] PA[0] PE[11] VSS_HV VDD_HV VSS_HV RESET VSS_LV VDD_LV VDD_BV PG[9] PG[8] PC[11] PC[10] PG[7] PG[6] PB[0] PB[1] PF[9] PF[8] PF[12] PC[6] 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 PB[2] PC[8] PC[13] PC[12] PE[7] PE[6] PH[8] PH[7] PH[6] PH[5] PH[4] PE[5] PE[4] PC[4] PC[5] PE[3] PE[2] PH[9] PC[0] VSS_LV VDD_LV VDD_HV VSS_HV PC[1] PH[10] PA[6] PA[5] PC[2] PC[3] PG[11] PG[10] PE[15] PE[14] PG[15] PG[14] PE[12] Figure 5. LQFP 144-pin configuration (top view) Note: Availability of port pin alternate functions depends on product selection. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 10 Freescale Semiconductor Package pinouts and signal descriptions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A PC[8] PC[13] NC NC PH[8] PH[4] PC[5] PC[0] NC NC PC[2] NC PE[15] NC NC NC A B PC[9] PB[2] NC PC[12] PE[6] PH[5] PC[4] PH[9] PH[10] NC PC[3] PG[11] PG[15] PG[14] PA[11] PA[10] B C PC[14] VDD_HV PB[3] PE[7] PH[7] PE[5] PE[3] VSS_LV PC[1] NC PA[5] NC PE[14] PE[12] PA[9] PA[8] C D NC NC PC[15] NC PH[6] PE[4] PE[2] VDD_LV VDD_HV NC PA[6] NC PG[10] PF[14] PE[13] PA[7] D E PG[4] PG[5] PG[3] PG[2] PG[1] PG[0] PF[15] VDD_HV E F PE[0] PA[2] PA[1] PE[1] PH[0] PH[1] PH[3] PH[2] F G PE[9] PE[8] PE[10] PA[0] VSS_HV VSS_HV VSS_HV VSS_HV VDD_HV NC NC MSEO G H VSS_HV PE[11] VDD_HV NC VSS_HV VSS_HV VSS_HV VSS_HV MDO3 MDO2 MDO0 MDO1 H J RESET VSS_LV NC NC VSS_HV VSS_HV VSS_HV VSS_HV NC NC NC NC J K EVTI NC VDD_BV VDD_LV VSS_HV VSS_HV VSS_HV VSS_HV NC PG[12] PA[3] PG[13] K L PG[9] PG[8] NC EVTO PB[15] PD[15] PD[14] PB[14] L M PG[7] PG[6] PC[10] PC[11] PB[13] PD[13] PD[12] PB[12] M N PB[1] PF[9] PB[0] NC NC PA[4] VSS_LV EXTAL VDD_HV PF[0] PF[4] NC PB[11] PD[10] PD[9] PD[11] N P PF[8] NC PC[7] NC NC PA[14] VDD_LV XTAL PB[10] PF[1] PF[5] PD[0] PD[3] VDD_HV _ADC PB[6] PB[7] P R PF[12] PC[6] PF[10] PF[11] VDD_HV PA[15] PA[13] NC OSC32K OSC32K _XTAL PF[3] PF[7] PD[2] PD[4] PD[7] VSS_HV _ADC PB[5] R T NC NC NC MCKO NC PF[13] PA[12] NC OSC32K OSC32K _EXTAL PF[2] PF[6] PD[1] PD[5] PD[6] PD[8] PB[4] T 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: 208 MAPBGA available only as development package for Nexus 2+. NC = Not connected Figure 6. 208 MAPBGA configuration MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 11 Package pinouts and signal descriptions 3.2 Pin muxing Table 1 defines the pin list and muxing for this device. Each entry of Table 1 shows all the possible configurations for each pin, via the alternate functions. The default function assigned to each pin after reset is indicated by AF0. Table 1. Functional port pin descriptions Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PA[0] PCR[0] AF0 AF1 AF2 AF3 - GPIO[0] E0UC[0] CLKOUT - WKUP[19]4 SIUL eMIOS0 CGL - WKPU I/O I/O O - I M Tristate 5 5 12 16 G4 PA[1] PCR[1] AF0 AF1 AF2 AF3 - - GPIO[1] E0UC[1] - - NMI5 WKUP[2]4 SIUL eMIOS0 - - WKPU WKPU I/O I/O - - I I S Tristate 4 4 7 11 F3 PA[2] PCR[2] AF0 AF1 AF2 AF3 - GPIO[2] E0UC[2] - - WKUP[3]4 SIUL eMIOS0 - - WKPU I/O I/O - - I S Tristate 3 3 5 9 F2 PA[3] PCR[3] AF0 AF1 AF2 AF3 - GPIO[3] E0UC[3] - - EIRQ[0] SIUL eMIOS0 - - SIUL I/O I/O - - I S Tristate 43 39 68 90 K15 PA[4] PCR[4] AF0 AF1 AF2 AF3 - GPIO[4] E0UC[4] - - WKUP[9]4 SIUL eMIOS0 - - WKPU I/O I/O - - I S Tristate 20 20 29 43 N6 PA[5] PCR[5] AF0 AF1 AF2 AF3 GPIO[5] E0UC[5] - - SIUL eMIOS0 - - I/O I/O - - M Tristate 51 51 79 118 C11 PA[6] PCR[6] AF0 AF1 AF2 AF3 - GPIO[6] E0UC[6] - - EIRQ[1] SIUL eMIOS0 - - SIUL I/O I/O - - I S Tristate 52 52 80 119 D11 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 12 Freescale Semiconductor Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PA[7] PCR[7] AF0 AF1 AF2 AF3 - GPIO[7] E0UC[7] LIN3TX - EIRQ[2] SIUL eMIOS0 LINFlex_3 - SIUL I/O I/O O - I S Tristate 44 44 71 104 D16 PA[8] PCR[8] AF0 AF1 AF2 AF3 - N/A6 - GPIO[8] E0UC[8] - - EIRQ[3] ABS[0] LIN3RX SIUL eMIOS0 - - SIUL BAM LINFlex_3 I/O I/O - - I I I S Input, weak pull-up 45 45 72 105 C16 PA[9] PCR[9] AF0 AF1 AF2 AF3 N/A6 GPIO[9] E0UC[9] - - FAB SIUL eMIOS_0 - - BAM I/O I/O - - I S Pulldown 46 46 73 106 C15 PA[10] PCR[10] AF0 AF1 AF2 AF3 GPIO[10] E0UC[10] SDA - SIUL eMIOS_0 I2C_0 - I/O I/O I/O - S Tristate 47 47 74 107 B16 PA[11] PCR[11] AF0 AF1 AF2 AF3 GPIO[11] E0UC[11] SCL - SIUL eMIOS0 I2C_0 - I/O I/O I/O - S Tristate 48 48 75 108 B15 PA[12] PCR[12] AF0 AF1 AF2 AF3 - GPIO[12] - - - SIN_0 SIUL - - - DSPI0 I/O - - - I S Tristate 22 22 31 45 T7 PA[13] PCR[13] AF0 AF1 AF2 AF3 GPIO[13] SOUT_0 - - SIUL DSPI_0 - - I/O O - - M Tristate 21 21 30 44 R7 PA[14] PCR[14] AF0 AF1 AF2 AF3 - GPIO[14] SCK_0 CS0_0 - EIRQ[4] SIUL DSPI_0 DSPI_0 - SIUL I/O I/O I/O - I M Tristate 19 19 28 42 P6 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 13 Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PA[15] PCR[15] AF0 AF1 AF2 AF3 - GPIO[15] CS0_0 SCK_0 - WKUP[10]4 SIUL DSPI_0 DSPI_0 - WKPU I/O I/O I/O - I M Tristate 18 18 27 40 R6 PB[0] PCR[16] AF0 AF1 AF2 AF3 GPIO[16] CAN0TX - - SIUL FlexCAN_0 - - I/O O - - M Tristate 14 14 23 31 N3 PB[1] PCR[17] AF0 AF1 AF2 AF3 - - GPIO[17] - - - WKUP[4]4 CAN0RX SIUL - - - WKPU FlexCAN_0 I/O - - - I I S Tristate 15 15 24 32 N1 PB[2] PCR[18] AF0 AF1 AF2 AF3 GPIO[18] LIN0TX SDA - SIUL LINFlex_0 I2C_0 - I/O O I/O - M Tristate 64 64 100 144 B2 PB[3] PCR[19] AF0 AF1 AF2 AF3 - - GPIO[19] - SCL - WKUP[11]4 LIN0RX SIUL - I2C_0 - WKPU LINFlex_0 I/O - I/O - I I S Tristate 1 1 1 1 C3 PB[4] PCR[20] AF0 AF1 AF2 AF3 - GPIO[20] - - - ANP[0] SIUL - - - ADC I - - - I I Tristate 32 32 50 72 T16 PB[5] PCR[21] AF0 AF1 AF2 AF3 - GPIO[21] - - - ANP[1] SIUL - - - ADC I - - - I I Tristate 35 - 53 75 R16 PB[6] PCR[22] AF0 AF1 AF2 AF3 - GPIO[22] - - - ANP[2] SIUL - - - ADC I - - - I I Tristate 36 - 54 76 P15 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 14 Freescale Semiconductor Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PB[7] PCR[23] AF0 AF1 AF2 AF3 - GPIO[23] - - - ANP[3] SIUL - - - ADC I - - - I I Tristate 37 35 55 77 P16 PB[8] PCR[24] AF0 AF1 AF2 AF3 - - GPIO[24] - - - ANS[0] OSC32K OSC32K_XTAL7 SIUL - - - ADC SXOSC I - - - I I/O I Tristate 30 30 39 53 R9 PB[9] PCR[25] AF0 AF1 AF2 AF3 - - GPIO[25] - - - ANS[1] OSC32K OSC32K_EXTAL7 SIUL - - - ADC SXOSC I - - - I I/O I Tristate 29 29 38 52 T9 PB[10] PCR[26] AF0 AF1 AF2 AF3 - - GPIO[26] - - - ANS[2] WKUP[8]4 SIUL - - - ADC WKPU I/O - - - I I J Tristate 31 31 40 54 P9 PB[11]8 PCR[27] AF0 AF1 AF2 AF3 - GPIO[27] E0UC[3] - CS0_0 ANS[3] SIUL eMIOS_0 - DSPI_0 ADC I/O I/O - I/O I J Tristate 38 36 59 81 N13 PB[12] PCR[28] AF0 AF1 AF2 AF3 - GPIO[28] E0UC[4] - CS1_0 ANX[0] SIUL eMIOS - DSPI_0 ADC I/O I/O - O I J Tristate 39 - 61 83 M16 PB[13] PCR[29] AF0 AF1 AF2 AF3 - GPIO[29] E0UC[5] - CS2_0 ANX[1] SIUL eMIOS_0 - DSPI_0 ADC I/O I/O - O I J Tristate 40 - 63 85 M13 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 15 Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PB[14] PCR[30] AF0 AF1 AF2 AF3 - GPIO[30] E0UC[6] - CS3_0 ANX[2] SIUL eMIOS0 - DSPI_0 ADC I/O I/O - O I J Tristate 41 37 65 87 L16 PB[15] PCR[31] AF0 AF1 AF2 AF3 - GPIO[31] E0UC[7] - CS4_0 ANX[3] SIUL eMIOS_0 - DSPI_0 ADC I/O I/O - O I J Tristate 42 38 67 89 L13 PC[0]9 PCR[32] AF0 AF1 AF2 AF3 GPIO[32] - TDI - SIUL - JTAGC - I/O - I - M Input, weak pull-up 59 59 87 126 A8 PC[1]9 PCR[33] AF0 AF1 AF2 AF3 GPIO[33] - TDO10 TDO10 - SIUL - JTAGC - I/O - O - M Tristate 54 54 82 121 C9 PC[2] PCR[34] AF0 AF1 AF2 AF3 - GPIO[34] SCK_1 CAN4TX11 CAN4TX11 - EIRQ[5] SIUL DSPI_1 LINFlex_4 - SIUL I/O I/O O - I M Tristate 50 50 78 117 A11 PC[3] PCR[35] AF0 AF1 AF2 AF3 - - - GPIO[35] CS0_1 MA[0] - CAN1RX CAN4RX11 CAN4RX11 EIRQ[6] SIUL DSPI_1 ADC - FlexCAN_1 FlexCAN_4 SIUL I/O I/O O - I I I S Tristate 49 49 77 116 B11 PC[4] PCR[36] AF0 AF1 AF2 AF3 - - GPIO[36] - - - SIN_1 CAN3RX11 CAN3RX11 SIUL - - - DSPI_1 FlexCAN_3 I/O - - - I I M Tristate 62 62 92 131 B7 PC[5] PCR[37] AF0 AF1 AF2 AF3 - GPIO[37] SOUT_1 CAN3TX11 CAN3TX11 - EIRQ[7] SIUL DSPI1 FlexCAN_3 - SIUL I/O O O - I M Tristate 61 61 91 130 A7 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 16 Freescale Semiconductor Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PC[6] PCR[38] AF0 AF1 AF2 AF3 GPIO[38] LIN1TX - - SIUL LINFlex_1 - - I/O O - - S Tristate 16 16 25 36 R2 PC[7] PCR[39] AF0 AF1 AF2 AF3 - - GPIO[39] - - - LIN1RX WKUP[12]4 SIUL - - - LINFlex_1 WKPU I/O - - - I I S Tristate 17 17 26 37 P3 PC[8] PCR[40] AF0 AF1 AF2 AF3 GPIO[40] LIN2TX - - SIUL LINFlex_2 - - I/O O - - S Tristate 63 63 99 143 A1 PC[9] PCR[41] AF0 AF1 AF2 AF3 - - GPIO[41] - - - LIN2RX WKUP[13]4 SIUL - - - LINFlex_2 WKPU I/O - - - I I S Tristate 2 2 2 2 B1 PC[10] PCR[42] AF0 AF1 AF2 AF3 GPIO[42] CAN1TX CAN4TX11 CAN4TX11 MA[1] SIUL FlexCAN_1 FlexCAN_4 ADC I/O O O O M Tristate 13 13 22 28 M3 PC[11] PCR[43] AF0 AF1 AF2 AF3 - - - GPIO[43] - - - CAN1RX CAN4RX11 CAN4RX11 WKUP[5]4 SIUL - - - FlexCAN_1 FlexCAN_4 WKPU I/O - - - I I I S Tristate - - 21 27 M4 PC[12] PCR[44] AF0 AF1 AF2 AF3 - GPIO[44] E0UC[12] - - SIN_2 SIUL eMIOS_0 - - DSPI_2 I/O I/O - - I M Tristate - - 97 141 B4 PC[13] PCR[45] AF0 AF1 AF2 AF3 GPIO[45] E0UC[13] SOUT_2 - SIUL eMIOS_0 DSPI_2 - I/O I/O O - S Tristate - - 98 142 A2 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 17 Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PC[14] PCR[46] AF0 AF1 AF2 AF3 - GPIO[46] E0UC[14] SCK_2 - EIRQ[8] SIUL eMIOS_0 DSPI_2 - SIUL I/O I/O I/O - I S Tristate - - 3 3 C1 PC[15] PCR[47] AF0 AF1 AF2 AF3 GPIO[47] E0UC[15] CS0_2 - SIUL eMIOS_0 DSPI_2 - I/O I/O I/O - M Tristate - - 4 4 D3 PD[0] PCR[48] AF0 AF1 AF2 AF3 - GPIO[48] - - - ANP[4] SIUL - - - ADC I - - - I I Tristate - - 41 63 P12 PD[1] PCR[49] AF0 AF1 AF2 AF3 - GPIO[49] - - - ANP[5] SIUL - - - ADC I - - - I I Tristate - - 42 64 T12 PD[2] PCR[50] AF0 AF1 AF2 AF3 - GPIO[50] - - - ANP[6] SIUL - - - ADC I - - - I I Tristate - - 43 65 R12 PD[3] PCR[51] AF0 AF1 AF2 AF3 - GPIO[51] - - - ANP[7] SIUL - - - ADC I - - - I I Tristate - - 44 66 P13 PD[4] PCR[52] AF0 AF1 AF2 AF3 - GPIO[52] - - - ANP[8] SIUL - - - ADC I - - - I I Tristate - - 45 67 R13 PD[5] PCR[53] AF0 AF1 AF2 AF3 - GPIO[53] - - - ANP[9] SIUL - - - ADC I - - - I I Tristate - - 46 68 T13 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 18 Freescale Semiconductor Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PD[6] PCR[54] AF0 AF1 AF2 AF3 - GPIO[54] - - - ANP[10] SIUL - - - ADC I - - - I I Tristate - - 47 69 T14 PD[7] PCR[55] AF0 AF1 AF2 AF3 - GPIO[55] - - - ANP[11] SIUL - - - ADC I - - - I I Tristate - - 48 70 R14 PD[8] PCR[56] AF0 AF1 AF2 AF3 - GPIO[56] - - - ANP[12] SIUL - - - ADC I - - - I I Tristate - - 49 71 T15 PD[9] PCR[57] AF0 AF1 AF2 AF3 - GPIO[57] - - - ANP[13] SIUL - - - ADC I - - - I I Tristate - - 56 78 N15 PD[10] PCR[58] AF0 AF1 AF2 AF3 - GPIO[58] - - - ANP[14] SIUL - - - ADC I - - - I I Tristate - - 57 79 N14 PD[11] PCR[59] AF0 AF1 AF2 AF3 - GPIO[59] - - - ANP[15] SIUL - - - ADC I - - - I I Tristate - - 58 80 N16 PD[12]8 PCR[60] AF0 AF1 AF2 AF3 - GPIO[60] CS5_0 E0UC[24] - ANS[4] SIUL DSPI_0 eMIOS_0 - ADC I/O O I/O - I J Tristate - - 60 82 M15 PD[13] AF0 AF1 AF2 AF3 - GPIO[61] CS0_1 E0UC[25] - ANS[5] SIUL DSPI_1 eMIOS_0 - ADC I/O I/O I/O - I J Tristate - - 62 84 M14 PCR[61] Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 19 Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PD[14] PCR[62] AF0 AF1 AF2 AF3 - GPIO[62] CS1_1 E0UC[26] - ANS[6] SIUL DSPI_1 eMIOS_0 - ADC I/O O I/O - I J Tristate - - 64 86 L15 PD[15] PCR[63] AF0 AF1 AF2 AF3 - GPIO[63] CS2_1 E0UC[27] - ANS[7] SIUL DSPI_1 eMIOS_0 - ADC I/O O I/O - I J Tristate - - 66 88 L14 PE[0] PCR[64] AF0 AF1 AF2 AF3 - - GPIO[64] E0UC[16] - - CAN5RX11 CAN5RX11 WKUP[6]4 SIUL eMIOS_0 - - FlexCAN_5 WKPU I/O I/O - - I I S Tristate - - 6 10 F1 PE[1] PCR[65] AF0 AF1 AF2 AF3 GPIO[65] E0UC[17] CAN5TX11 CAN5TX11 - SIUL eMIOS_0 FlexCAN_5 - I/O I/O O - M Tristate - - 8 12 F4 PE[2] PCR[66] AF0 AF1 AF2 AF3 - GPIO[66] E0UC[18] - - SIN_1 SIUL eMIOS0 - - DSPI_1 I/O I/O - - I M Tristate - - 89 128 D7 PE[3] PCR[67] AF0 AF1 AF2 AF3 GPIO[67] E0UC[19] SOUT_1 - SIUL eMIOS0 DSPI_1 - I/O I/O O - M Tristate - - 90 129 C7 PE[4] PCR[68] AF0 AF1 AF2 AF3 - GPIO[68] E0UC[20] SCK_1 - EIRQ[9] SIUL eMIOS0 DSPI_1 - SIUL I/O I/O I/O - I M Tristate - - 93 132 D6 PE[5] PCR[69] AF0 AF1 AF2 AF3 GPIO[69] E0UC[21] CS0_1 MA[2] SIUL eMIOS_0 DSPI_1 ADC I/O I/O I/O O M Tristate - - 94 133 C6 PE[6] PCR[70] AF0 AF1 AF2 AF3 GPIO[70] E0UC[22] CS3_0 MA[1] SIUL eMIOS_0 DSPI_0 ADC I/O I/O O O M Tristate - - 95 139 B5 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 20 Freescale Semiconductor Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. M Tristate - - 96 140 C4 SIUL I/O FlexCAN_2 O I/O eMIOS0 FlexCAN_3 O M Tristate - - 9 13 G2 GPIO[73] - E0UC[23] - WKUP[7]4 CAN2RX12 CAN2RX12 CAN3RX11 CAN3RX11 SIUL - eMIOS_0 - WKPU FlexCAN_2 FlexCAN_3 I/O - I/O - I I I S Tristate - - 10 14 G1 AF0 AF1 AF2 AF3 - GPIO[74] LIN3TX CS3_1 - EIRQ[10] SIUL LINFlex_3 DSPI_1 - SIUL I/O O O - I S Tristate - - 11 15 G3 PCR[75] AF0 AF1 AF2 AF3 - - GPIO[75] - CS4_1 - LIN3RX WKUP[14]4 SIUL - DSPI_1 - LINFlex_3 WKPU I/O - O - I I S Tristate - - 13 17 H2 PE[12] PCR[76] AF0 AF1 AF2 AF3 - - GPIO[76] - E1UC[19]13 - SIN_2 EIRQ[11] SIUL - eMIOS_1 - DSPI_2 SIUL I/O - I/O - I I S Tristate - - 76 109 C14 PE[13] PCR[77] AF0 AF1 AF2 AF3 GPIO[77] SOUT2 E1UC[20] - SIUL DSPI_2 eMIOS_1 - I/O O I/O - S Tristate - - - 103 D15 PE[14] PCR[78] AF0 AF1 AF2 AF3 - GPIO[78] SCK_2 E1UC[21] - EIRQ[12] SIUL DSPI_2 eMIOS_1 - SIUL I/O I/O I/O - I S Tristate - - - 112 C13 Port pin PCR register Alternate function1 Function Peripheral PE[7] PCR[71] AF0 AF1 AF2 AF3 GPIO[71] E0UC[23] CS2_0 MA[0] SIUL eMIOS_0 DSPI_0 ADC PE[8] PCR[72] AF0 AF1 AF2 AF3 GPIO[72] CAN2TX12 CAN2TX12 E0UC[22] CAN3TX11 CAN3TX11 PE[9] PCR[73] AF0 AF1 AF2 AF3 - - - PE[10] PCR[74] PE[11] Pad RESET I/O direction2 type config. I/O I/O O O MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 21 Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PE[15] PCR[79] AF0 AF1 AF2 AF3 GPIO[79] CS0_2 E1UC[22] - SIUL DSPI_2 eMIOS_1 - I/O I/O I/O - M Tristate - - - 113 A13 PF[0] PCR[80] AF0 AF1 AF2 AF3 - GPIO[80] E0UC[10] CS3_1 - ANS[8] SIUL eMIOS_0 DSPI_1 - ADC I/O I/O O - I J Tristate - - - 55 N10 PF[1] PCR[81] AF0 AF1 AF2 AF3 - GPIO[81] E0UC[11] CS4_1 - ANS[9] SIUL eMIOS_0 DSPI_1 - I I/O I/O O - I J Tristate - - - 56 P10 PF[2] PCR[82] AF0 AF1 AF2 AF3 - GPIO[82] E0UC[12] CS0_2 - ANS[10] SIUL eMIOS_0 DSPI_2 - ADC I/O I/O I/O - I J Tristate - - - 57 T10 PF[3] PCR[83] AF0 AF1 AF2 AF3 - GPIO[83] E0UC[13] CS1_2 - ANS[11] SIUL eMIOS_0 DSPI_2 - ADC I/O I/O O - I J Tristate - - - 58 R10 PF[4] PCR[84] AF0 AF1 AF2 AF3 - GPIO[84] E0UC[14] CS2_2 - ANS[12] SIUL eMIOS_0 DSPI_2 - ADC I/O I/O O - I J Tristate - - - 59 N11 PF[5] PCR[85] AF0 AF1 AF2 AF3 - GPIO[85] E0UC[22] CS3_2 - ANS[13] SIUL eMIOS_0 DSPI_2 - ADC I/O I/O O - I J Tristate - - - 60 P11 PF[6] PCR[86] AF0 AF1 AF2 AF3 - GPIO[86] E0UC[23] - - ANS[14] SIUL eMIOS_0 - - ADC I/O I/O - - I J Tristate - - - 61 T11 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 22 Freescale Semiconductor Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PF[7] PCR[87] AF0 AF1 AF2 AF3 - GPIO[87] - - - ANS[15] SIUL - - - ADC I/O - - - I J Tristate - - - 62 R11 PF[8] PCR[88] AF0 AF1 AF2 AF3 GPIO[88] CAN3TX14 CAN3TX14 CS4_0 CAN2TX15 CAN2TX15 SIUL FlexCAN_3 DSPI_0 FlexCAN_2 I/O O O O M Tristate - - - 34 P1 PF[9] PCR[89] AF0 AF1 AF2 AF3 - - GPIO[89] - CS5_0 - CAN2RX15 CAN2RX15 CAN3RX14 CAN3RX14 SIUL - DSPI_0 - FlexCAN_2 FlexCAN_3 I/O - O - I I S Tristate - - - 33 N2 PF[10] PCR[90] AF0 AF1 AF2 AF3 GPIO[90] - - - SIUL - - - I/O - - - M Tristate - - - 38 R3 PF[11] PCR[91] AF0 AF1 AF2 AF3 - GPIO[91] - - - WKUP[15]4 SIUL - - - WKPU I/O - - - I S Tristate - - - 39 R4 PF[12] PCR[92] AF0 AF1 AF2 AF3 GPIO[92] E1UC[25] - - SIUL eMIOS_1 - - I/O I/O - - M Tristate - - - 35 R1 PF[13] PCR[93] AF0 AF1 AF2 AF3 - GPIO[93] E1UC[26] - - WKUP[16]4 SIUL eMIOS_1 - - WKPU I/O I/O - - I S Tristate - - - 41 T6 PF[14] PCR[94] AF0 AF1 AF2 AF3 GPIO[94] CAN4TX11 CAN4TX11 E1UC[27] CAN1TX SIUL FlexCAN_4 eMIOS_1 FlexCAN_4 I/O O I/O O M Tristate - 43 - 102 D14 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 23 Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PF[15] PCR[95] AF0 AF1 AF2 AF3 - - - GPIO[95] - - - CAN1RX CAN4RX11 CAN4RX11 EIRQ[13] SIUL - - - FlexCAN_1 FlexCAN_4 SIUL I/O - - - I I I S Tristate - 42 - 101 E15 PG[0] PCR[96] AF0 AF1 AF2 AF3 GPIO[96] CAN5TX11 CAN5TX11 E1UC[23] - SIUL FlexCAN_5 eMIOS_1 - I/O O I/O - M Tristate - 41 - 98 E14 PG[1] PCR[97] AF0 AF1 AF2 AF3 - - GPIO[97] - E1UC[24] - CAN5RX11 CAN5RX11 EIRQ[14] SIUL - eMIOS_1 - FlexCAN_5 SIUL I/O - I/O - I I S Tristate - 40 - 97 E13 PG[2] PCR[98] AF0 AF1 AF2 AF3 GPIO[98] E1UC[11] - - SIUL eMIOS_1 - - I/O I/O - - M Tristate - - - 8 E4 PG[3] PCR[99] AF0 AF1 AF2 AF3 - GPIO[99] E1UC[12] - - WKUP[17]4 SIUL eMIOS_1 - - WKPU I/O I/O - - I S Tristate - - - 7 E3 PG[4] PCR[100] AF0 AF1 AF2 AF3 GPIO[100] E1UC[13] - - SIUL eMIOS_1 - - I/O I/O - - M Tristate - - - 6 E1 PG[5] PCR[101] AF0 AF1 AF2 AF3 - GPIO[101] E1UC[14] - - WKUP[18]4 SIUL eMIOS_1 - - WKPU I/O I/O - - I S Tristate - - - 5 E2 PG[6] PCR[102] AF0 AF1 AF2 AF3 GPIO[102] E1UC[15] - - SIUL eMIOS_1 - - I/O I/O - - M Tristate - - - 30 M2 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 24 Freescale Semiconductor Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PG[7] PCR[103] AF0 AF1 AF2 AF3 GPIO[103] E1UC[16] - - SIUL eMIOS_1 - - I/O I/O - - M Tristate - - - 29 M1 PG[8] PCR[104] AF0 AF1 AF2 AF3 - GPIO[104] E1UC[17] - CS0_2 EIRQ[15] SIUL eMIOS_1 - DSPI_2 SIUL I/O I/O - I/O I S Tristate - - - 26 L2 PG[9] PCR[105] AF0 AF1 AF2 AF3 GPIO[105] E1UC[18] - SCK_2 SIUL eMIOS1 - DSPI_2 I/O I/O - I/O S Tristate - - - 25 L1 PG[10] PCR[106] AF0 AF1 AF2 AF3 GPIO[106] E0UC[24] - - SIUL eMIOS_0 - - I/O I/O - - S Tristate - - - 114 D13 PG[11] PCR[107] AF0 AF1 AF2 AF3 GPIO[107] E0UC[25] - - SIUL eMIOS_0 - - I/O I/O - - M Tristate - - - 115 B12 PG[12] PCR[108] AF0 AF1 AF2 AF3 GPIO[108] E0UC[26] - - SIUL eMIOS_0 - - I/O I/O - - M Tristate - - - 92 K14 PG[13] PCR[109] AF0 AF1 AF2 AF3 GPIO[109] E0UC[27] - - SIUL eMIOS_0 - - I/O I/O - - M Tristate - - - 91 K16 PG[14] PCR[110] AF0 AF1 AF2 AF3 GPIO[110] E1UC[0] - - SIUL eMIOS_1 - - I/O I/O - - S Tristate - - - 110 B14 PG[15] PCR[111] AF0 AF1 AF2 AF3 GPIO[111] E1UC[1] - - SIUL eMIOS_1 - - I/O I/O - - M Tristate - - - 111 B13 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 25 Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Port pin PCR register Alternate function1 Function Peripheral 64 LQFP 64 LQFP 5CAN 4 LIN 100 LQFP 144 LQFP 208 MAPBGA3 Pin No. PH[0] PCR[112] AF0 AF1 AF2 AF3 - GPIO[112] E1UC[2] - - SIN1 SIUL eMIOS_1 - - DSPI_1 I/O I/O - - I M Tristate - - - 93 F13 PH[1] PCR[113] AF0 AF1 AF2 AF3 GPIO[113] E1UC[3] SOUT1 - SIUL eMIOS_1 DSPI_1 - I/O I/O O - M Tristate - - - 94 F14 PH[2] PCR[114] AF0 AF1 AF2 AF3 GPIO[114] E1UC[4] SCK_1 - SIUL eMIOS_1 DSPI_1 - I/O I/O I/O - M Tristate - - - 95 F16 PH[3] PCR[115] AF0 AF1 AF2 AF3 GPIO[115] E1UC[5] CS0_1 - SIUL eMIOS_1 DSPI_1 - I/O I/O I/O - M Tristate - - - 96 F15 PH[4] PCR[116] AF0 AF1 AF2 AF3 GPIO[116] E1UC[6] - - SIUL eMIOS_1 - - I/O I/O - - M Tristate - - - 134 A6 PH[5] PCR[117] AF0 AF1 AF2 AF3 GPIO[117] E1UC[7] - - SIUL eMIOS_1 - - I/O I/O - - S Tristate - - - 135 B6 PH[6] PCR[118] AF0 AF1 AF2 AF3 GPIO[118] E1UC[8] - MA[2] SIUL eMIOS_1 - ADC I/O I/O - O M Tristate - - - 136 D5 PH[7] PCR[119] AF0 AF1 AF2 AF3 GPIO[119] E1UC[9] CS3_2 MA[1] SIUL eMIOS_1 DSPI_2 ADC I/O I/O O O M Tristate - - - 137 C5 PH[8] PCR[120] AF0 AF1 AF2 AF3 GPIO[120] E1UC[10] CS2_2 MA[0] SIUL eMIOS_1 DSPI_2 ADC I/O I/O O O M Tristate - - - 138 A5 PH[9]9 PCR[121] AF0 AF1 AF2 AF3 GPIO[121] - TCK - SIUL - JTAGC - I/O - I - S Input, weak pull-up - - 88 127 B8 Pad RESET I/O direction2 type config. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 26 Freescale Semiconductor Package pinouts and signal descriptions Table 1. Functional port pin descriptions (continued) Peripheral AF0 AF1 AF2 AF3 GPIO[122] - TMS - SIUL - JTAGC - Pad RESET I/O direction2 type config. I/O - I - S Input, weak pull-up 208 MAPBGA3 Function 144 LQFP PH[10]9 PCR[122] Alternate function1 100 LQFP PCR register 64 LQFP 5CAN 4 LIN Port pin 64 LQFP Pin No. - - 81 120 B9 1 Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00 -> AF0; PCR.PA = 01 -> AF1; PCR.PA = 10 -> AF2; PCR.PA = 11 -> AF3. This is intended to select the output functions; to use one of the input functions, the PCR.IBE bit must be written to `1', regardless of the values selected in the PCR.PA bitfields. For this reason, the value corresponding to an input only function is reported as "-". 2 Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of the PSMIO.PADSELx bitfields inside the SIUL module. 3 208 MAPBGA available only as development package for Nexus2+ 4 All WKUP pins also support external interrupt capability. See wakeup unit chapter for further details. 5 NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored. 6 "Not applicable" because these functions are available only while the device is booting. Refer to BAM chapter of the reference manual for details. 7 Value of PCR.IBE bit must be 0 8 This pad is used on MPC5607B MPC5607B 100-pin and 144-pinto provide supply for the second ADC. Therefore it is recommended not using it to keep the compatibility with the family devices. 9 Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO. PC[0:1] are available as JTAG pins (TDI and TDO respectively). PH[9:10] are available as JTAG pins (TCK and TMS respectively). It is up to the user to configure these pins as GPIO when needed, in this case MPC5604B/C MPC5604B/C get incompliance with IEEE 1149.1-2001. 10 The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY mode. However, no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an input. When no debugger is connected the TDO pad is floating causing additional current consumption. To avoid the extra consumption TDO must be connected. An external pull-up resistor in the range of 47­100 kOhms should be added between the TDO pin and VDD. Only in case the TDO pin is used as application pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between TDO pin and GND instead. 11 Available only on MPC560xC versions and MPC5604B MPC5604B 208 MAPBGA devices 12 Not available on MPC5602B MPC5602B devices 13 Not available in 100 LQFP package 14 Available only on MPC5604B MPC5604B 208 MAPBGA devices 15 Not available on MPC5603B MPC5603B 144-pin devices MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 27 Electrical characteristics 4 Electrical characteristics 4.1 Introduction This section contains electrical characteristics of the device as well as temperature and power considerations. This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application of any voltage higher than the specified maximum rated voltages. To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (VDD or VSS). This could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. The parameters listed in the following tables represent the characteristics of the device and its demands on the system. In the tables where the device logic provides signals with their respective timing characteristics, the symbol "CC" for Controller Characteristics is included in the Symbol column. In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol "SR" for System Requirement is included in the Symbol column. CAUTION All 64 LQFPinformation is indicative and must be confirmed during silicon validation. 4.2 Parameter classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding, the classifications listed in Table 2 are used and the parameters are tagged accordingly in the tables where appropriate. Table 2. Parameter classifications Classification tag Tag description P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled "C" in the parameter tables where appropriate. 4.3 NVUSRO register Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 28 Freescale Semiconductor Electrical characteristics 4.3.1 NVUSRO[PAD3V5V] field description Table 3 shows how NVUSRO[PAD3V5V] controls the device configuration. Table 3. PAD3V5V field description1 Value2 Description 0 1 1 2 High voltage supply is 5.0 V High voltage supply is 3.3 V See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The DC electrical characteristics are dependent on the PAD3V5V bit value. 4.3.2 NVUSRO[OSCILLATOR_MARGIN] field description Table 4 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration. Table 4. OSCILLATOR_MARGIN field description1 Value2 Description 0 1 1 2 Low consumption configuration (4 MHz/8 MHz) High margin configuration (4 MHz/16 MHz) See the device reference manual for more information on the NVUSRO register. '1' is delivery value. It is part of shadow Flash, thus programmable by customer. The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value. For a detailed description of the NVUSRO register, please refer to the MPC5604B/C MPC5604B/C Reference Manual. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 29 Electrical characteristics 4.4 Absolute maximum ratings Table 5. Absolute maximum ratings Value Symbol Parameter Conditions Unit Min Max VSS SR Digital ground on VSS_HV pins - 0 0 V VDD SR Voltage on VDD_HV pins with respect to ground (VSS) - -0.3 6.0 V VSS_LV SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) - VDD_BV SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) - - VDD_ADC SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) - SR Voltage on any GPIO pin with respect to ground (VSS) -0.3 6.0 -0.3 Relative to VDD VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) VIN VSS-0.1 VSS+0.1 V VDD+0.3 VSS-0.1 VSS+0.1 -0.3 6.0 V V V VDD -0.3 VDD+0.3 Relative to VDD Relative to VDD -0.3 6.0 - - VDD+0.3 V IINJPAD SR Injected input current on any pin during overload condition - -10 10 IINJSUM SR Absolute sum of all injected input currents during overload condition - -50 50 - 70 - 64 - - 150 mA - -55 150 °C IAVGSEG SR Sum of all the static I/O current within a VDD = 5.0 V ± 10%, PAD3V5V = 0 supply segment VDD = 3.3 V ± 10%, PAD3V5V = 1 ICORELV SR Low voltage static current sink through VDD_BV TSTORAGE SR Storage temperature mA mA NOTE Stresses exceeding the recommended absolute maximum ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN > VDD or VIN < VSS), the voltage on pins with respect to ground (VSS) must not exceed the recommended values. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 30 Freescale Semiconductor Electrical characteristics 4.5 Recommended operating conditions Table 6. Recommended operating conditions (3.3 V) Value Symbol Parameter Conditions Unit Min VSS Max SR Digital ground on VSS_HV pins - 0 0 V SR Voltage on VDD_HV pins with respect to ground (VSS) - 3.0 3.6 V VSS_LV2 SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) - VDD_BV3 SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) - VDD 1 Relative to VDD VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS) - VDD_ADC4 SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) - VIN SR Voltage on any GPIO pin with respect to ground (VSS) Relative to VDD - Relative to VDD VSS-0.1 VSS+0.1 3.0 3.6 V V VDD-0.1 VDD+0.1 VSS-0.1 VSS+0.1 3.05 3.6 V V VDD-0.1 VDD+0.1 VSS-0.1 - - VDD+0.1 V IINJPAD SR Injected input current on any pin during overload condition - -5 5 IINJSUM SR Absolute sum of all injected input currents during overload condition - -50 50 SR VDD slope to ensure correct power up6 - - 0.25 V/µs TA C-Grade Part SR Ambient temperature under bias - -40 85 °C TJ C-Grade Part SR Junction temperature under bias - -40 110 TA V-Grade Part SR Ambient temperature under bias - -40 105 TJ V-Grade Part SR Junction temperature under bias - -40 130 TA M-Grade Part SR Ambient temperature under bias - -40 125 TJ M-Grade Part SR Junction temperature under bias - -40 150 TVDD 1 2 3 4 5 6 mA 100 nF capacitance needs to be provided between each VDD/VSS pair 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 400 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below VLVDHVL, device is reset. Guaranteed by device validation MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 31 Electrical characteristics Table 7. Recommended operating conditions (5.0 V) Value Symbol Parameter Conditions Unit Min VSS VDD 1 SR Digital ground on VSS_HV pins - 0 0 V SR Voltage on VDD_HV pins with respect to ground (VSS) - 4.5 5.5 V 3.0 5.5 VSS_LV3 VDD_BV4 SR Voltage on VDD_BV pin (regulator supply) with respect to ground (VSS) Voltage drop2 SR Voltage on VSS_LV (low voltage digital supply) pins with respect to ground (VSS) - - Voltage VSS_ADC SR Voltage on VSS_HV_ADC (ADC reference) pin with respect to ground (VSS - VDD_ADC5 SR Voltage on VDD_HV_ADC pin (ADC reference) with respect to ground (VSS) - 4.5 - Relative to VDD V 5.5 5.5 V VDD-0.1 VDD+0.1 VSS-0.1 VSS+0.1 4.5 V 5.5 3.0 Voltage drop2 Relative to VDD SR Voltage on any GPIO pin with respect to ground (VSS) VSS-0.1 VSS+0.1 3.0 drop2 Relative to VDD VIN Max V 5.5 VDD-0.1 VDD+0.1 VSS-0.1 - - VDD+0.1 V IINJPAD SR Injected input current on any pin during overload condition - -5 5 IINJSUM SR Absolute sum of all injected input currents during overload condition - -50 50 SR VDD slope to ensure correct power up6 - - 0.25 V/µs TA C-Grade Part SR Ambient temperature under bias - -40 85 °C TJ C-Grade Part SR Junction temperature under bias - -40 110 TA V-Grade Part SR Ambient temperature under bias - -40 105 TJ V-Grade Part SR Junction temperature under bias - -40 130 TA M-Grade Part SR Ambient temperature under bias - -40 125 TJ M-Grade Part SR Junction temperature under bias - -40 150 TVDD 1 2 3 4 5 6 mA 100 nF capacitance needs to be provided between each VDD/VSS pair. Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain analog electrical characteristics will not be guaranteed to stay within the stated limits. 330 nF capacitance needs to be provided between each VDD_LV/VSS_LV supply pair. 100 nF capacitance needs to be provided between VDD_BV and the nearest VSS_LV (higher value may be needed depending on external regulator characteristics). 100 nF capacitance needs to be provided between VDD_ADC/VSS_ADC pair. Guaranteed by device validation MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 32 Freescale Semiconductor Electrical characteristics NOTE RAM data retention is guaranteed with VDD_LV not below 1.08 V. 4.6 4.6.1 Thermal characteristics Package thermal characteristics Table 8. LQFP thermal characteristics1 Symbol C RJA CC D Parameter Conditions2 Single-layer board - 1s Four-layer board - 2s2p 64 TBD 34 35 64 TBD 22 22 64 TBD 22 22 64 TBD 33 34 64 TBD 34 144 Junction-to-board thermal characterization parameter, natural convection 37 100 D 36 144 JB CC TBD 100 Four-layer board - 2s2p 64 100 Single-layer board - 1s 49 144 Thermal resistance, junction-to-case5 51 100 D TBD 144 RJC CC 64 144 Four-layer board - 2s2p 64 100 Single-layer board - 1s 64 100 Thermal resistance, junction-to-board4 °C/W 144 D TBD 144 RJB CC 64 100 Four-layer board - 2s2p Unit 100 Single-layer board - 1s Value 144 Thermal resistance, junction-to-ambient natural convection3 Pin count 35 °C/W °C/W °C/W MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 33 Electrical characteristics Table 8. LQFP thermal characteristics1 (continued) Symbol C JC CC D Parameter Conditions2 64 TBD °C/W 9 10 64 TBD 100 9 144 Four-layer board - 2s2p Unit 100 Single-layer board - 1s Value 144 Junction-to-case thermal characterization parameter, natural convection Pin count 10 1 Thermal characteristics are based on simulation. VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C 3 Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 JESD51-3 and JESD51-6 JESD51-6. Thermal test board meets JEDEC specification for this package. When Greek letters are not available, the symbols are typed as RthJA and RthJMA. 4 Junction-to-board thermal resistance determined per JEDEC JESD51-8 JESD51-8. Thermal test board meets JEDEC specification for the specified package. When Greek letters are not available, the symbols are typed as RthJB. 5 Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate temperature is used for the case temperature. Reported value includes the thermal resistance of the interface layer. When Greek letters are not available, the symbols are typed as RthJC. 2 MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 34 Freescale Semiconductor Electrical characteristics 4.6.2 Power considerations The average chip-junction temperature, TJ, in degrees Celsius, may be calculated using Equation 1: TJ = TA + (PD x RJA) Eqn. 1 Where: TA is the ambient temperature in °C. RJA is the package junction-to-ambient thermal resistance, in °C/W. PD is the sum of PINT and PI/O (PD = PINT + PI/O). PINT is the product of IDD and VDD, expressed in watts. This is the chip internal power. PI/O represents the power dissipation on input and output pins; user determined. Most of the time for the applications, PI/O < PINT and may be neglected. On the other hand, PI/O may be significant, if the device is configured to continuously drive external modules and/or memories. An approximate relationship between PD and TJ (if PI/O is neglected) is given by: PD = K / (TJ + 273 °C) Eqn. 2 K = PD x (TA + 273 °C) + RJA x PD2 Eqn. 3 Therefore, solving equations 1 and 2: Where: K is a constant for the particular part, which may be determined from Equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ may be obtained by solving equations 1 and 2 iteratively for any value of TA. 4.7 4.7.1 I/O pad electrical characteristics I/O pad types The device provides four main I/O pad types depending on the associated alternate functions: · · · · Slow pads-These pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. Medium pads-These pads provide transition fast enough for the serial communication channels with controlled current to reduce electromagnetic emission. Fast pads-These pads provide maximum speed. There are used for improved Nexus debugging capability. Input only pads-These pads are associated to ADC channels and the external 32 kHz crystal oscillator (SXOSC) providing low input leakage. Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 35 Electrical characteristics 4.7.2 I/O input DC characteristics Table 9 provides input DC electrical characteristics as described in Figure 7. Figure 7. I/O input DC electrical characteristics definition VIN VDD VIH VHYS VIL PDIx = `1' (GPDI register of SIUL) PDIx = `0' Table 9. I/O input DC electrical characteristics Symbol C Parameter Value Conditions1 Unit Min Typ Max VIH SR P Input high level CMOS (Schmitt Trigger) - 0.65VDD 65VDD - VDD+0.4 VIL SR P Input low level CMOS (Schmitt Trigger) - -0.4 - 0.35VDD 35VDD - 0.1VDD - - TA = -40 °C - 2 - TA = 25 °C - 2 - D TA = 105 °C - 12 500 P TA = 125 °C - 70 1000 - - - 40 ns - 1000 - - ns VHYS CC C Input hysteresis CMOS (Schmitt Trigger) ILKG CC P Digital input leakage P WFI 2 SR P Wakeup input filtered pulse WNFI2 SR P Wakeup input not filtered pulse 1 2 No injection on adjacent pin V nA VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and voltage. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 36 Freescale Semiconductor Electrical characteristics 4.7.3 I/O output DC characteristics The following tables provide DC characteristics for bidirectional pads: · · · · Table 10 provides weak pull figures. Both pull-up and pull-down resistances are supported. Table 11 provides output driver characteristics for I/O pads when in SLOW configuration. Table 12 provides output driver characteristics for I/O pads when in MEDIUM configuration. Table 13 provides output driver characteristics for I/O pads when in FAST configuration. Table 10. I/O pull-up/pull-down DC electrical characteristics Symbol C Value Conditions1 Parameter Unit Min 1 - 150 10 - 250 VIN = VIL, VDD = 3.3 V ± 10% PAD3V5V = 1 10 - 150 VIN = VIH, VDD = 5.0 V ± 10% PAD3V5V = 0 10 - 150 PAD3V5V = 1 10 - 250 VIN = VIH, VDD = 3.3 V ± 10% PAD3V5V = 1 10 - 150 2 |IWPD| CC P Weak pull-down current absolute value C 2 10 VIN = VIL, VDD = 5.0 V ± 10% PAD3V5V = 0 P P Max PAD3V5V = 1 |IWPU| CC P Weak pull-up current absolute value C Typ µA µA VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified. The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 11. SLOW configuration output buffer electrical characteristics Symbol C Parameter Value Conditions1 Unit Min Typ Max Push Pull IOH = -2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) 0.8VDD - - C IOH = -2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 0.8VDD - - C IOH = -1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) VDD-0.8 - - - - 0.1VDD VOH CC P Output high level SLOW configuration VOL CC P Output low level SLOW configuration Push Pull IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) C 1 - - IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) - - V 0.1VDD C 2 IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 V 0.5 VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 37 Electrical characteristics Table 12. MEDIUM configuration output buffer electrical characteristics Symbol C Value Conditions1 Parameter Unit Min Typ Max Push Pull IOH = -3.8 mA, VOH CC C Output high level MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD - - P IOH = -2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) 0.8VDD - - C IOH = -1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 0.8VDD - - C IOH = -1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) VDD-0.8 - - C IOH = -100 µA, VDD = 5.0 V ± 10%, PAD3V5V = 0 0.8VDD - - VOL CC C Output low level Push Pull IOL = 3.8 mA, MEDIUM configuration VDD = 5.0 V ± 10%, PAD3V5V = 0 - - 0.2VDD P IOL = 2 mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) - - 0.1VDD C IOL = 1 mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 - - 0.1VDD C IOL = 1 mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) - - 0.5 C IOH = 100 µA, VDD = 5.0 V ± 10%, PAD3V5V = 0 - - 0.1VDD 1 2 V V VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. Table 13. FAST configuration output buffer electrical characteristics Symbol C Value Conditions1 Parameter Unit Min Typ Max IOH = -14mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) 0.8VDD - - C IOH = -7mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 0.8VDD - - C IOH = -11mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) VDD-0.8 - - VOH CC P Output high level FAST configuration Push Pull V MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 38 Freescale Semiconductor Electrical characteristics Table 13. FAST configuration output buffer electrical characteristics (continued) Symbol C Value Conditions1 Parameter Unit Min Typ Max IOL = 14mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) - - 0.1VDD C IOL = 7mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 - - 0.1VDD C IOL = 11mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) - - 0.5 VOL CC P Output low level FAST configuration 1 2 Push Pull V VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified The configuration PAD3V5 = 1 when VDD = 5 V is only a transient configuration during power-up. All pads but RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state. 4.7.4 Output pin transition times Table 14. Output pin transition times Symbol C Value Conditions1 Parameter Unit Min Ttr CC D Output transition time output pin2 SLOW configuration T CL = 25 pF CL = 50 pF D D CL = 25 pF T CL = 50 pF D Ttr CC D Output transition time output pin2 MEDIUM configuration T CL = 25 pF CL = 50 pF D CL = 25 pF T CL = 50 pF CL = 100 pF D Ttr CC D Output transition time output pin FAST configuration 2 CL = 25 pF CL = 50 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 CL = 100 pF CL = 25 pF CL = 50 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF 1 - - 100 - 125 - - 50 - - 100 - 125 - - 10 - - 20 - 40 - - 12 - - 25 - 40 - - 4 - - 6 - VDD = 3.3 V ± 10%, PAD3V5V = 1 SIUL.PCRx.SRC = 1 50 - CL = 100 pF D VDD = 5.0 V ± 10%, PAD3V5V = 0 SIUL.PCRx.SRC = 1 - - CL = 100 pF VDD = 3.3 V ± 10%, PAD3V5V = 1 - - CL = 100 pF Max - VDD = 5.0 V ± 10%, PAD3V5V = 0 Typ - 12 - - 4 - - 7 - - 12 ns ns ns VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 39 Electrical characteristics 2 CL includes device and package capacitances (CPKG < 5 pF). 4.7.5 I/O pad current specification The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair as described in Table 15. Table 16 provides I/O consumption figures. In order to ensure device reliability, the average current of the I/O on a single segment should remain below the IAVGSEG maximum value. In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain below the IDYNSEG maximum value. Table 15. I/O supply segment Supply segment Package 1 208 MAPBGA1 2 3 4 Equivalent to 144 LQFP segment pad distribution 6 MCKO MDOn/MSEO - - 144 LQFP pin20­pin49 pin51­pin99 100 LQFP pin16­pin35 pin37­pin69 pin70­pin83 pin 84­pin15 - - pin8­pin26 pin28­pin55 pin56­pin7 - - - 64 LQFP 1 2 2 pin100­pin122 pin 123­pin19 5 208 MAPBGA available only as development package for Nexus2+ All 64 LQFPinformation is indicative and must be confirmed during silicon validation. Table 16. I/O consumption Symbol C Value Conditions1 Parameter Unit Min ISWTSLW,2 ISWTMED2 ISWTFST2 CC D Dynamic I/O current for MEDIUM configuration CL = 25 pF CC D Dynamic I/O current for FAST configuration CL = 25 pF VDD = 5.0 V ± 10%, PAD3V5V = 0 - - 20 - - 16 VDD = 5.0 V ± 10%, PAD3V5V = 0 - - 29 VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 25 pF Max VDD = 3.3 V ± 10%, PAD3V5V = 1 CC D Dynamic I/O current for SLOW configuration Typ - - 17 VDD = 5.0 V ± 10%, PAD3V5V = 0 - - 110 VDD = 3.3 V ± 10%, PAD3V5V = 1 - - 50 mA mA mA MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 40 Freescale Semiconductor Electrical characteristics Table 16. I/O consumption (continued) Symbol C Value Conditions1 Parameter Unit Min Max - - 2.3 - - 3.2 - - 6.6 - - 1.6 - - 2.3 - - 4.7 - - 6.6 - - 13.4 - - 18.3 - - 5 - - 8.5 - - 11 - - 22 - - 33 - - 56 - - 14 - - 20 CL = 100 pF, 40 MHz IRMSSLW Typ - - 35 VDD = 5.0 V ± 10%, PAD3V5V = 0 - - 70 VDD = 3.3 V ± 10%, PAD3V5V = 1 - - 65 CC D Root medium square CL = 25 pF, 2 MHz I/O current for SLOW CL = 25 pF, 4 MHz configuration CL = 100 pF, 2 MHz CL = 25 pF, 2 MHz CL = 25 pF, 4 MHz VDD = 5.0 V ± 10%, PAD3V5V = 0 VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF, 2 MHz IRMSMED CC D Root medium square CL = 25 pF, 13 MHz VDD = 5.0 V ± 10%, I/O current for PAD3V5V = 0 CL = 25 pF, 40 MHz MEDIUM configuration CL = 100 pF, 13 MHz CL = 25 pF, 13 MHz CL = 25 pF, 40 MHz VDD = 3.3 V ± 10%, PAD3V5V = 1 CL = 100 pF, 13 MHz IRMSFST CC D Root medium square CL = 25 pF, 40 MHz VDD = 5.0 V ± 10%, I/O current for FAST PAD3V5V = 0 CL = 25 pF, 64 MHz configuration CL = 100 pF, 40 MHz CL = 25 pF, 40 MHz CL = 25 pF, 64 MHz IAVGSEG 1 2 SR D Sum of all the static I/O current within a supply segment VDD = 3.3 V ± 10%, PAD3V5V = 1 mA mA mA mA VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to125 °C, unless otherwise specified Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. Table 17 provides the weight of concurrent switching I/Os. In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain below the 100%. Table 17. I/O weight1 64 LQFP2 144/100 LQFP PAD Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 PB[3] 10% - 12% - 10% - 12% - PC[9] 10% - 12% - 10% - 12% - PC[14] 9% - 11% - 9% - 11% - PC[15] 9% 13% 11% 12% 9% 13% 11% 12% MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 41 Electrical characteristics Table 17. I/O weight1 64 LQFP2 144/100 LQFP PAD Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 PG[5] 9% - 11% - 9% - 11% - PG[4] 9% 12% 10% 11% 9% 12% 10% 11% PG[3] 9% - 10% - 9% - 10% - PG[2] 8% 12% 10% 10% 8% 12% 10% 10% PA[2] 8% - 9% - 8% - 9% - PE[0] 8% - 9% - 8% - 9% - PA[1] 7% - 9% - 7% - 9% - PE[1] 7% 10% 8% 9% 7% 10% 8% 9% PE[8] 7% 9% 8% 8% 7% 9% 8% 8% PE[9] 6% - 7% - 6% - 7% - PE[10] 6% - 7% - 6% - 7% - PA[0] 5% 8% 6% 7% 5% 8% 6% 7% PE[11] 5% - 6% - 5% - 6% - PG[9] 9% - 10% - 9% - 10% - PG[8] 9% - 11% - 9% - 11% - PC[11] 9% - 11% - 9% - 11% - PC[10] 9% 13% 11% 12% 9% 13% 11% 12% PG[7] 10% 14% 11% 12% 10% 14% 11% 12% PG[6] 10% 14% 12% 12% 10% 14% 12% 12% PB[0] 10% 14% 12% 12% 10% 14% 12% 12% PB[1] 10% - 12% - 10% - 12% - PF[9] 10% - 12% - 10% - 12% - PF[8] 10% 15% 12% 13% 10% 15% 12% 13% PF[12] 10% 15% 12% 13% 10% 15% 12% 13% PC[6] 10% - 12% - 10% - 12% - PC[7] 10% - 12% - 10% - 12% - PF[10] 10% 14% 12% 12% 10% 14% 12% 12% PF[11] 10% - 11% - 10% - 11% - PA[15] 9% 12% 10% 11% 9% 12% 10% 11% PF[13] 8% - 10% - 8% - 10% - PA[14] 8% 11% 9% 10% 8% 11% 9% 10% PA[4] 8% - 9% - 8% - 9% - PA[13] 7% 10% 9% 9% 7% 10% 9% 9% MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 42 Freescale Semiconductor Electrical characteristics Table 17. I/O weight1 64 LQFP2 144/100 LQFP PAD Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 PA[12] 7% - 8% - 7% - 8% - PB[9] 1% - 1% - 1% - 1% - PB[8] 1% - 1% - 1% - 1% - PB[10] 6% - 7% - 6% - 7% - PF[0] 6% - 7% - 6% - 7% - PF[1] 7% - 8% - 7% - 8% - PF[2] 7% - 8% - 7% - 8% - PF[3] 7% - 9% - 8% - 9% - PF[4] 8% - 9% - 8% - 9% - PF[5] 8% - 10% - 8% - 10% - PF[6] 8% - 10% - 9% - 10% - PF[7] 9% - 10% - 9% - 11% - PD[0] 1% - 1% - 1% - 1% - PD[1] 1% - 1% - 1% - 1% - PD[2] 1% - 1% - 1% - 1% - PD[3] 1% - 1% - 1% - 1% - PD[4] 1% - 1% - 1% - 1% - PD[5] 1% - 1% - 1% - 1% - PD[6] 1% - 1% - 1% - 1% - PD[7] 1% - 1% - 1% - 1% - PD[8] 1% - 1% - 1% - 1% - PB[4] 1% - 1% - 1% - 1% - PB[5] 1% - 1% - 1% - 2% - PB[6] 1% - 1% - 1% - 2% - PB[7] 1% - 1% - 1% - 2% - PD[9] 1% - 1% - 1% - 2% - PD[10] 1% - 1% - 1% - 2% - PD[11] 1% - 1% - 1% - 2% - PB[11] 11% - 13% - 17% - 21% - PD[12] 11% - 13% - 18% - 21% - PB[12] 11% - 13% - 18% - 21% - PD[13] 10% - 12% - 18% - 21% - PB[13] 10% - 12% - 18% - 21% - MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 43 Electrical characteristics Table 17. I/O weight1 64 LQFP2 144/100 LQFP PAD Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 PD[14] 10% - 12% - 18% - 21% - PB[14] 10% - 12% - 18% - 21% - PD[15] 10% - 11% - 18% - 21% - PB[15] 9% - 11% - 18% - 21% - PA[3] 9% - 11% - 18% - 21% - PG[13] 9% 13% 10% 11% 18% 26% 21% 23% PG[12] 9% 12% 10% 11% 18% 26% 21% 23% PH[0] 5% 8% 6% 7% 18% 26% 21% 23% PH[1] 5% 7% 6% 6% 18% 26% 21% 23% PH[2] 5% 6% 5% 6% 18% 25% 21% 22% PH[3] 4% 6% 5% 5% 18% 25% 21% 22% PG[1] 4% - 4% - 18% - 21% - PG[0] 3% 4% 4% 4% 17% 25% 21% 22% PF[15] 3% - 4% - 17% - 20% - PF[14] 4% 5% 5% 5% 16% 23% 20% 21% PE[13] 4% - 5% - 16% - 19% - PA[7] 5% - 6% - 16% - 19% - PA[8] 5% - 6% - 16% - 19% - PA[9] 5% - 6% - 15% - 18% - PA[10] 6% - 7% - 15% - 18% - PA[11] 6% - 8% - 14% - 17% - PE[12] 7% - 8% - 11% - 14% - PG[14] 7% - 8% - 10% - 12% - PG[15] 7% 10% 8% 9% 10% 14% 12% 12% PE[14] 7% - 8% - 9% - 11% - PE[15] 7% 9% 8% 8% 9% 12% 10% 11% PG[10] 6% - 8% - 8% - 10% - PG[11] 6% 9% 7% 8% 8% 11% 9% 10% PC[3] 6% - 7% - 7% - 9% - PC[2] 6% 8% 7% 7% 6% 9% 8% 8% PA[5] 5% 7% 6% 6% 6% 8% 7% 7% PA[6] 5% - 6% - 5% - 6% - PC[1] 5% - 5% - 5% - 5% - MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 44 Freescale Semiconductor Electrical characteristics Table 17. I/O weight1 64 LQFP2 144/100 LQFP PAD Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 SRE=0 SRE=1 PC[0] 7% 8% 6% 9% 7% 8% 7% 10% 9% 9% 7% 10% 9% 9% PE[3] 8% 11% 9% 9% 8% 11% 9% 9% PC[5] 8% 11% 9% 10% 8% 11% 9% 10% PC[4] 8% 12% 10% 10% 8% 12% 10% 10% PE[4] 8% 12% 10% 11% 8% 12% 10% 11% PE[5] 9% 12% 10% 11% 9% 12% 10% 11% PH[4] 9% 13% 11% 11% 9% 13% 11% 11% PH[5] 9% - 11% - 9% - 11% - PH[6] 9% 13% 11% 12% 9% 13% 11% 12% PH[7] 9% 13% 11% 12% 9% 13% 11% 12% PH[8] 10% 14% 11% 12% 10% 14% 11% 12% PE[6] 10% 14% 12% 12% 10% 14% 12% 12% PE[7] 10% 14% 12% 12% 10% 14% 12% 12% PC[12] 10% 14% 12% 13% 10% 14% 12% 13% PC[13] 10% - 12% - 10% - 12% - PC[8] 10% - 12% - 10% - 12% - PB[2] 2 9% PE[2] 1 6% 10% 15% 12% 13% 10% 15% 12% 13% VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to125 °C, unless otherwise specified All 64 LQFPinformation is indicative and must be confirmed during silicon validation. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 45 Electrical characteristics 4.8 RESET electrical characteristics The device implements a dedicated bidirectional RESET pin. Figure 8. Start-up reset requirements VDD VDDMIN RESET VIH VIL device reset forced by RESET device start-up phase Figure 9. Noise filtering on reset signal VRESET hw_rst VDD `1' VIH VIL `0' filtered by hysteresis filtered by lowpass filter WFRST filtered by lowpass filter unknown reset state device under hardware reset WFRST WNFRST MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 46 Freescale Semiconductor Electrical characteristics Table 18. Reset electrical characteristics Symbol C Parameter Value Conditions1 Unit Min Typ Max VIH SR P Input High Level CMOS (Schmitt Trigger) - 0.65VDD 65VDD - VDD+0.4 V VIL SR P Input low Level CMOS (Schmitt Trigger) - -0.4 - 0.35VDD 35VDD V VHYS CC C Input hysteresis CMOS (Schmitt Trigger) - 0.1VDD - - V VOL CC P Output low level Push Pull, IOL = 2mA, VDD = 5.0 V ± 10%, PAD3V5V = 0 (recommended) - - 0.1VDD V Push Pull, IOL = 1mA, VDD = 5.0 V ± 10%, PAD3V5V = 12 - - 0.1VDD Push Pull, IOL = 1mA, VDD = 3.3 V ± 10%, PAD3V5V = 1 (recommended) - - 0.5 CL = 25pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 - - 10 CL = 50pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 - - 20 CL = 100pF, VDD = 5.0 V ± 10%, PAD3V5V = 0 - - 40 CL = 25pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 - - 12 CL = 50pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 - - 25 CL = 100pF, VDD = 3.3 V ± 10%, PAD3V5V = 1 - - 40 WFRST SR P RESET input filtered pulse - - - 40 ns WNFRST SR P RESET input not filtered pulse - 1000 - - ns VDD = 3.3 V ± 10%, PAD3V5V = 1 10 - 150 µA VDD = 5.0 V ± 10%, PAD3V5V = 0 10 - 150 VDD = 5.0 V ± 10%, PAD3V5V = 12 10 - 250 Ttr CC D Output transition time output pin3 |IWPU| CC P Weak pull-up current absolute value ns VDD = 3.3 V ± 10% / 5.0 V ± 10%, TA = -40 to 125 °C, unless otherwise specified This transient configuration does not occurs when device is used in the VDD = 3.3 V ± 10% range. 3 C includes device and package capacitance (C L PKG < 5 pF). 1 2 MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 Freescale Semiconductor 47 Electrical characteristics 4.9 Power management electrical characteristics 4.9.1 Voltage regulator electrical characteristics The device implements an internal voltage regulator to generate the low voltage core supply VDD_LV from the high voltage ballast supply VDD_BV. The regulator itself is supplied by the common I/O supply VDD. The following supplies are involved: · · · HV-High voltage external power supply for voltage regulator module. This must be provided externally through VDD power pin. BV-High voltage external power supply for internal ballast module. This must be provided externally through VDD_BV power pin. Voltage values should be aligned with VDD. LV-Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure noise isolation between critical LV modules within the device: - LV_COR-Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding. - LV_CFLA-Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. - LV_DFLA-Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to LV_COR through double bonding. - LV_PLL-Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding. Figure 10. Voltage regulator capacitance connection CREG2 (LV_COR/LV_CFLA) GND VDD VSS_LV VDD_BV Voltage Regulator I VSS_LVn VDD_BV CREG1 (LV_COR/LV_DFLA) VDD_LVn CDEC1 (Ballast decoupling) VREF VDD_LV VDD_LV DEVICE VSS_LV GND VSS_LV DEVICE GND VSS VDD_LV VDD GND CREG3 (LV_COR/LV_PLL) CDEC2 (supply/IO decoupling) The internal voltage regulator requires external capacitance (CREGn) to be connected to the device in order to provide a stable low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins. Care should also be taken to limit the serial inductance of the board to less than 5 nH. MPC5604B/C MPC5604B/C Microcontroller Data Sheet, Rev. 7 48 Freescale Semiconductor Electrical characteristics Each decoupling capacitor must be placed between each of the three VDD_LV/VSS_LV supply pairs to ensure stable voltage (see Section 4.5, "Recommended operating conditions). Table 19. Voltage regulator electrical characteristics Symbol C Parameter Value Conditions1 Unit Min Typ Max CREGn SR - Internal voltage regulator external capacitance - 200 - 500 nF RREG SR - Stability capacitor equivalent serial resistance - - - 0.2 CDEC1 SR - Decoupling capacitance2 ballast VDD_BV/VSS_LV pair: VDD_BV = 4.5 V to 5.5 V 1003 4704 - nF VDD_BV/VSS_LV pair: VDD_BV = 3 V to 3.6 V 400 - CDEC2 SR - Decoupling capacitance regulator supply VDD/VSS pair 10 100 - nF VMREG CC T Main regulator output voltage Before exting from reset - 1.32 - V 1.15 1.28 1.32 - - 150 mA IMREG = 200 mA - - 2 mA IMREG = 0 mA - - 1 1.15 1.23 1.32 V - - 15 mA - - 600 µA ILPREG = 0 mA; TA = 55 °C