GT-32090 MON960 256KB RS232 EPM7032 JS127JS128 JS66-JS67 JS31-JS32 J38-J43 - Datasheet Archive

 

Galileo-5 Evaluation & Development Preliminary May 96, Rev. 1.0 System NOTE: Always contact Galileo Technology for possible

 

32-bit i960Jx Galileo-5 Evaluation & Development Preliminary May 96, Rev. 1.0 System NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES · Flexible evaluation, benchmark, software, and hardware development system for the GT-32090 GT-32090 System Controller - Master CPU and optional "secondary" CPU - Debug monitor software (MON960 MON960) · Flexible uses - As standalone system - As slave card in a standard ISA slot · Several CPU options - Intel i960Jx 32-bit CPUs (shipped with 33MHz i960) - 16MHz to 66MHz internal CPU frequency - 16 to 33MHz CPU bus frequency · DRAM - 2 SIMM slots (4 banks) - 1MB to 64MB (shipped with 1MB) - 32-bit width · Flash memory - 4 32-pin PLCC sockets - 256KB 256KB to 2MB (shipped with 0MB) - 120ns access time, 5V or 12V - 8-, 16-, or 32-bit width · EPROM - 32-pin DIP socket - 32KB to 1MB (shipped with 512 KB) - 8-bit width · ISA Interface - Message passing protocol between the i960Jx and the Host CPU - May be used for software downloading · DMA - Three independent channels - Chaining via linked lists of records Secondary CPU · · · · · - Byte alignment on source and destination - Transfers through 16-byte internal FIFO - Moves data between SIO, memory, and devices - Packing and unpacking of 8- and 16-bit data into 32-bit data - Packing and unpacking from/to SIO bus concurrent with AD bus activity - Fixed and round robin programmable priorities Simple I/O (SIO) Bus - 80186 style bus for glueless interface to low cost peripherals - 8/16-bit wide bus accessible via expansion connector - Four chip selects - Programmable timing - External wait support PCMCIA - Supports two 8/16-bit PCMCIA devices DUART - Two serial channels - Max speed of 115,200 baud I/O bus expansion - Two 96-pin AMP connectors - SIO bus and controls - Device controls - 32-bit address bus - 32-bit buffered data bus - DMA request and acknowledge signals - External interrupt signals to CPU Debug environment - Shipped with ported Intel Monitor software on EPROM (MON960 MON960) - Test points and configuration jumpers Expansion AD Bus i960Jx CPU P2 AD Bus DRAM Control & Addr OSC DRAM SIMMs Flash 373 ROM Expansion SIO Bus GT-32090 GT-32090 System Controller Address Bus PCMCIA Interface PCMCIA x2 P1 UART SIO Bus COM1 ISA Interface RS232 RS232 Driver COM2 ISA Bus 1735 N. First St. #308, San Jose, CA 95112, Tel (408)451-1400, Fax (408)451-1404 1 Galileo-5 32-bit i960Jx Evaluation & Development Syste m Table of Contents 1.0 Overview 2.0 Start-Up Instructions 3.0 Address Map 3.1 960 Address Map 3.2 Host PC Address Map 4.0 Expansion Connectors Pin List 5.0 Customer Configurable Options 5.1 Removable Jumpers 5.2 Power On Configuration Jumpers 5.3 Zero-Ohm Resistors 6.0 Hardware Information 6.1 Schematics 6.2 Orcad Files Description 6.3 Physical Board Layout 6.4 Bill Of Materials 7.0 PAL Equations 7.1 ISA Interface 7.2 PCMCIA Control/Decoding 8.0 Software Information 8.1 Intel MON960 MON960 Software 9.0 Data Sheets/Manuals 10.0 1 OVERVIEW The Galileo-5 32-bit i960Jx Evaluation and Development System greatly facilitates the development of embedded control systems based on the i960JA, i960JD, and i960JF Intel processors. The centerpiece of the system is Galileo's GT-32090 GT-32090 System Controller, which integrates most of the core logic necessary in embedded applications. The Galileo-5 board serves two main objectives: 1) It allows customers to easily evaluate the performance of a GT-32090 GT-32090 based system, using their own software, as opposed to generic benchmarks. 2) It greatly facilitates and expedites the development of the final product, since hardware designers can use its design as a reference and software designers can use it to start porting software ahead of their own hardware platform. The shipping configuration of the Galileo-5 includes a 33MHz i960JD CPU, 1MByte of DRAM, sockets for Flash, a 512KByte EPROM, a DUART, Intel MON960 MON960 software, and 2 PCMCIA sockets. Jumpers allow customers to evaluate a large variety of system configurations, and expansion connectors allow customerdesigned options to be easily interfaced to. More details on the board will be found in subsequent sections. The Galileo-5 Main Controller can either be used in stand-alone fashion, or it can be plugged directly into an ISA slot of standard personal computers. Appendices 10.1 Appendix 1 Test Points 10.2 Appendix 2 Schematics WARNING #1: extra caution should be taken not to short signals when modifying jumper settings. Please only change jumpers when the board is powered down. WARNING #2: the PCMCIA slots do NOT support Hot Swapping. Please make sure to only insert and remove PCMCIA cards when the board is powered down. 2 Galileo-5 32-bit i960JX Evaluation & Development System 1.1 GT-32090 GT-32090 System Controller The GT-32090 GT-32090 is a highly integrated system controller for embedded control applications. It gives high system performance, while reducing cost, complexity, device count, and board space. The GT-32090 GT-32090 controls two separate and independent buses, the CPU's 32-bit wide address/data bus, and a 16-bit I/O bus (named Simple I/O bus or SIO bus). The two buses can work concurrently at different frequencies. The GT-32090 GT-32090 has a direct interface to the Intel family of i960Jx processors. It has the capability to support various device types through programmable address decoding and timing. It controls devices like ROM, Flash, SRAM, and slave peripherals with different size and time requirements. each bank separately from 256K to 4M, and the width of all banks is 32-bits. With these options, each DRAM bank size can vary from 1 MByte to 16MBytes. The DRAM timing is optimized for the different frequencies and device types supported. There is optional support for an external bi-directional latch on the DRAM's data bus for improved DRAM performance. Refresh can be programmed to different periodicities by a 16-bit refresh counter. Staggered and non-staggered refresh modes are supported. For systems requiring more than 64MBytes of DRAM, it is possible to add 4 more DRAM banks with a simple external multiplexer, to get to a total of 128MBytes of DRAM with 8 RAS control signals, using Address[26] to multiplex between two banks. The GT-32090 GT-32090 includes a DRAM controller supporting both Page Mode and EDO DRAM. The GT-32090 GT-32090 has a powerful three channel DMA controller with data alignment capabilities and sophisticated chaining support via linked lists. The DMA can move data between devices and DRAM on the CPU bus or between the CPU bus and devices on the SIO bus. The SIO is an 80186-like bus that interfaces to a large variety of support components like UARTs, SCSI controllers, network controllers, and other low cost devices. It supports 8-bit or 16-bit peripherals, including slave DMA devices. Device Interfac e The GT-32090 GT-32090 supports directly four devices on the AD bus. The GT-32090 GT-32090 device controller has the control signals and the timing programmability to control 8-, 16-, or 32-bit general purpose devices like Flash, SRAM, ROM, FIFO, and slave peripherals. Each device chip select has a programmable address space of 2 to 32MBytes. The GT-32090 GT-32090 includes a direct interface to two 16-bit PCMCIA slots. The Ready* pin enables an extension of a device cycle beyond the programmed values. CPU Interface The controller has control signals for optional Bidirectional buffers, which buffers slow devices from the AD bus. The GT-32090 GT-32090 has a glueless interface to the Intel i960JX family of processors, with bus frequencies between 16MHz and 33MHz. External agents can take control of the AD bus and access all the GT-32090 GT-32090 resources. The GT-32090 GT-32090 handles the priorities between internal DMA resources, the CPU, and the external agent. For systems that need extension of the capabilities offered by the GT-32090 GT-32090, up to four GT-32090 GT-32090 devices can support one CPU. For example, with four GT-32090s, the system can have up to 512MBytes of DRAM and 12 DMA channels. SIO Interface The SIO interface is similar to that of the popular 80186 bus interface and supports directly four devices on the SIO bus. The GT-32090 GT-32090 SIO controller has the control signals and the timing programmability to control 8- or 16-bit general purpose devices like UARTs, SCSI controllers, network controllers, and others. Each device chip select refers to an address space of 16MBytes. DRAM Interfac e The DRAM controller supports 4 banks of Page Mode or EDO DRAMs. DRAM types supported are those with 0.5K, 1K, and 2K refresh, as well asymmetric RAS/CAS addressing. The depth of the DRAM devices can vary for The SWait* pin enables the extension of a device cycle beyond the programmed values. The data bus is shared with the PCMCIA devices, and the address bus is common to the AD bus devices. 3 Galileo-5 32-bit i960Jx Evaluation & Development Syste m records in memory. PCMCIA Interfac e The GT-32090 GT-32090 PCMCIA controller supports two PCMCIA cards, which may be used for Flash card firmware upgrades in the field, interfacing to low cost modems, etc. Each card has a 128MByte address space dedicated to it, 64MBytes of I/O space and 64MBytes of memory space. The GT-32090 GT-32090 PCMCIA controller supports 8- or 16- bit big or little endian accesses. In non-chained mode, the DMA will assert an interrupt every time the programmed DMA transaction finishes. In chained mode, the DMA can be programmed to assert an interrupt every time a DMA transaction finishes, or when the Next Pointer register is NULL. 1.2 CPU The static control signals reset and reg need external latches and an external buffer is needed to read the PCMCIA status signals. Either one or two CPUs can be used on the Galileo-5 board, the Master CPU and the Secondary CPU. The design includes the latter mostly for Galileo internal testing of the External Agent interface, but customers might occasionally want to use it too. DMA Engines When using one CPU, the Master CPU resides in the socket U17 (this is the default shipping configuration). The DMA controller can move data between devices on the AD bus, or between devices on the AD bus and devices on the SIO bus. There are two DMA subsystems on the GT-32090 GT-32090, one handles the DMA activity on the SIO bus, and the other handles the activity on the AD bus. Each DMA subsystem has its own data resources and arbiters. The two DMA subsystems can work simultaneously or independently, except when data is transferred between the SIO bus and the AD bus. Both DMA subsystems can have at one time, three DMA channels that can be allocated to service the SIO bus or the AD bus. DMA accesses can be initiated by an external request by asserting one of the three DMAReq pins (Demand mode), or by setting an internal bit in a register (Block mode). Access can be non-aligned both at the source and at the destination, and up to 64KBytes of data can be transferred in each transaction. The AD bus DMA subsystem can transfer data in two ways, through an internal 16 byte FIFO, or directly between DRAM and an AD bus device ("fly-by"). The SIO bus DMA subsystem can transfer data between an 8/16-bit device on the SIO bus, or between 8/16-bit devices on the SIO bus and 32-bit devices on the AD bus. The DMA controller supports chained and non-chained modes of operation. In non-chained mode, the CPU programs the DMA channel for each transaction, and in chained mode the DMA controller fetches the information from linked lists of 4 When using two CPUs, the user needs to install socket U8 and the Secondary CPU in it. An EPM7032 EPM7032 PAL (U31- not included) needs then to be installed to control the two CPUs (see PAL overview section for code and explanation). The Secondary CPU acts as the external agent. The CPU sockets are 144-pin 14x14 matrix PGA sockets with 3 rows of pins. Two 12 x 2 Headers (J12 & J48) enable the selection of interrupt sources to the Master and Secondary CPUs. Surface mounted jumpers (zero-ohm resistors JS127JS128 JS127JS128) enable or disable the Master CPU self-test. Surface mounted jumpers (JS66-JS67 JS66-JS67) enable or disable the Secondary CPU self-test. The Galileo-5 is shipped with a 33MHz i960Jx. 1.3 CPU Clocking The clock for the board can be derived from an external source via a connector that the user would need to solder to footprint P7, or from the on-board oscillator (OSC1), as defined by the position of the surface mounted jumpers JS31-JS32 JS31-JS32. The external oscillator option has mainly been installed for internal Galileo testing, and is not recommended for users. The on-board oscillator is socketed and thus can be easily changed to use various frequency versions of the CPUs. The CPU bus frequency can be set to anywhere between 16-33MHz. The shipping configuration includes a 33MHz oscillator. Since the clock signal is used by many components, buffers are used (U7). The name of the buffered clock signal Galileo-5 32-bit i960JX Evaluation & Development System is "clkin", and four copies of it are generated (clkin[1:4]). 1.4 GT-32090 GT-32090 Configuration The configuration of the GT-32090 GT-32090 is defined by combinations of pull-up/pull-down resistors that are sampled at reset by the DMAReq[2:0] and DMAAck[2:0]* pins, and determine a common address for all devices, and a base address for the internal registers of the GT-32090 GT-32090. The values at reset are selected via jumpers J38-J43 J38-J43. The default configuration shipped is: - Starting address of devices: 0xfe000000 - Internal registers base address: 0xcc000000 When using a 28-pin EPROM, make sure pin 1 of the EPROM is inserted into pin 3 of the 32-pin socket U9. The EPROM can be either the Boot Device or Device 0, depending on the J13, J14, J68, J69 configuration (alternatively allowing the Flash memory to become the Boot Device). The jumpers J15 through J20 select the EPROM device size, as indicated below by identifying the jumpers that must be installed: 27C256 27C256 (32K x 8) - jumpers J16, J18, J20 27C512 27C512 (64K x 8) - jumpers J16, J18, J20 27C010 27C010 (128K x 8) - jumpers J15, J18, J20 27C020 27C020 (256K x 8) - jumpers J15, J18, J20 1.5 Device Control 27C040 27C040 (512K x 8) - jumpers J15, J17, J20 The address in the multiplexed AD bus is latched externally by U25 and U26. 27C080 27C080 (1M x 8) - jumpers J15, J17, J19 The GT-32090 GT-32090 (U12) controls the boot EPROM, the Flash Memory, and the SRAM (Flash and SRAM are not included in the shipping configuration). Flash Since some devices' output enable-to-high impedance time is relatively slow, transceivers can be used to accelerate the AD bus operation. Examples of this are some ROMs and A/D converters. Transceivers U10 and U16 are transceivers which act as buffers between slow devices and the AD bus. The Galileo-5 is shipped without Flash, so it is up to the user to insert the appropriate devices in the sockets U2, U3, U11, U15, and to select the jumpers accordingly. Flash width is configurable to 8-, 16-, or 32-bits, and any 5 volt or 12 volt 32-pin PLCC Flash compatible with Intel's. AMD-compatible Flash may also be used, but is not supported by the MON960 MON960 monitor program. In order to work with an 8-bit wide Flash, insert an 8-bit device into the U3 socket, and connect the following jumpers according to device type: If transceivers are needed, JS126 JS126 should be installed, thus enabling U10 & U16's OE* by connecting the GT32090 GT32090 BufOE* to them. If transceivers are not needed, J125 should be installed instead. 28256 - J21, J24, J27, J30 If transceivers are not needed, JS68-JS75 JS68-JS75, JS109JS124 JS109JS124, and JS129-JS136 JS129-JS136 should be installed (thus bypassing the transceivers). 28020 - J21, J24, J27, J30, J35, J44, J49 SRAM Footprints U27, U28, U29, & U32 are used for SRAMs that Galileo uses for internal testing. Several surfacemounted jumpers are associated with this testing. 28512 - J21, J24, J27, J30, J35 28010 - J21, J24, J27, J30, J35, J44 28040 - J21, J24, J27, J30, J35, J44, J49, J53 In order to work with 16-bit wide Flash, insert 8-bit devices into the U3 and U11 sockets, install jumper J61 (U11 WE# signal connected to GT-32090 GT-32090's WrEn[3]* signal), as well as the following jumpers according to device type: 28256 - J22, J24, J29, J30 28512 - J22, J24, J29, J30, J36 Boot EPROM 28010 - J22, J24, J29, J30, J36, J45 The boot EPROM sizes may range from 32K x 8 to 1M x 8. Any AT27C256-AT27C080 AT27C256-AT27C080 (or compatible) 28-pin or 32-pin EPROM can be used. The board is shipped with 512K x 8 (27C040 27C040). 28020 - J22, J24, J29, J30, J36, J45, J50 28040 - J22, J24, J29, J30, J36, J45, J50, J54 In order to work with 32-bit wide Flash, insert 8-bit 5 Galileo-5 32-bit i960Jx Evaluation & Development Syste m devices into the U3, U11, U15, and U20 sockets. Install jumper J62 (U11 WE# signal connected to GT-32090 GT-32090's WrEn[1]* signal), as well as the following jumpers according to device type: ational details. 28256 - J23, J26, J29, J32 1.8 ISA Bus 28512 - J23, J26, J29, J32, J37 28010 - J23, J26, J29, J32, J37, J46 28020 - J23, J26, J29, J32, J37,J46, J51 28040 - J23, J26, J29, J32, J37, J46, J51, J55 NOTE: Only the 32-bit Flash is contiguous. The jumpers J64, J65, and J66 enable the selection of the 28256 to 28020 devices' VPP voltage as either 12V, 5V, or GND. Devices like the 28040 may only have VPP at 5 volts. 1.6 DRAM Control The Galileo-5 board contains two 72-pin SIMM sockets (U1 and U2). Both sockets can handle single or double sided SIMMS, EDO or Standard Page Mode DRAM. U1 supports DRAM banks 0 and 2. U2 supports DRAM banks 1 and 3. Each DRAM bank can hold from 1 to 16MBytes, so a maximum of 64MBytes can be installed on-board. In order to increase performance at some CPU frequencies, bi-directional DRAM latches (U4 & U5) can be used (improved performance at 16, 20 & 25MHz is gained when using a latch with Standard Page Mode DRAM, for more details consult the GT-32090 GT-32090 data sheet). When using DRAM latches U4 and U5, JS42 should be installed (thus enabling the latches CE# signal). When disabling the latch, JS43 should be installed, as well as the bypass surface-mounted jumpers JS9-JS16 JS9-JS16, JS33-JS41 JS33-JS41, JS44-JS51 JS44-JS51, & JS76-JS82 JS76-JS82. 1.7 Serial Controller The Galileo-5 contains a DUART (two serial channels), that can be used to interface to a terminal or a PC. Customer software can be downloaded to the Galileo-5 via these UARTs, or alternatively, through the ISA bus. The devices used for serial communications are the 16552 DUART controller (U19), which supports two channels via serial connectors P10 & P11, and the Maxim MAX238 MAX238 5V transceiver (U14). Please refer to the data sheets of the 16552 and the MAX238 MAX238 for their oper- 6 The 16552 uses a 3.6864 MHz oscillator (OSC2). The Galileo-5 board can be inserted into a standard ISA bus (P3 & P4). This option can greatly accelerate downloading of programs and data transfer between the host computer and the board. Two 373 type octal latches (U22 & U23) form a bidirectional latch to buffer the host computer's ISA data bus from the Galileo-5's SIO data bus. An EPM7032 EPM7032 PAL (U21) is responsible for the latches' OC* and G signals, decoding of ISA bus address using isaSA[2.9] and jumpers J58-J59 J58-J59, and handshaking between the board and the host computer. Both sides can read status words from the PAL (through isaSD[1.0] and SData[1.0]), to find out whether data is pending for read or whether the latch was read by the other side and can be rewritten. The PAL can also be programmed by the Galileo-5 to cause an interrupt or DMAReq signal whenever data is read or written by the host computer (board program execution can be stopped this way). 1.9 PCMCIA Bus The Galileo-5 board has two PCMCIA slots, A and B (P8 and P9). Each slot's VPP1 and VPP2 voltages can be selected to be either 5 volts, 12 volts, or floating, using surface mounted jumpers JS1-JS8. The irq*, cd1*, cd2*, bvd1, and wait* signals are pulled up according to the PCMCIA standard. The status signals irq*, wp, bvd1, bvd2, cd1*, and cd2* can be read through a 244 buffer (U13) connected to the SIO bus. A PAL (U31 or U18) controls the U13 buffer's OE# signal and the static signals reg* and reset of the PCMCIA cards (see PALS section). 1.10 Boundary Scan (JTAG) Jumpers J1-J3 and J5-J10 J5-J10 are used for internal Galileo testing of JTAG chaining between the GT-32090 GT-32090, the i960Jx master CPU, and the i960Jx secondary CPU. . Galileo-5 32-bit i960JX Evaluation & Development System 1.11 Reset 1.13 Buffers-Drivers A MAX708 MAX708 (U24) is used for reset and reset* signal generation. Two buffers (U6 and U7) are used to drive the DRAM control signals RAS*, CAS*, DWr* and DAdr[10.0], and the loaded W/R* and Clock signals. The reset source can be either the push-button S1 (when the board is not plugged into an ISA slot), or the host computer's reset signal when the board is plugged into an ISA slot. The J67 three-position jumper enables the selection of the reset source: - Set jumper J67 to 1,2 for push-button reset. - Set jumper J67 to 2,3 for ISA slot reset. These buffers can be individually bypassed or used according to the existence or absence of surface mounted jumpers. Surface mounted jumpers for bypassing the buffers are the following: JS17-JS30 JS17-JS30, JS84, JS86, JS88, JS90, JS92, JS94, JS96-JS102 JS96-JS102. Surface mounted jumpers for using the buffers are the following: JS52-JS65 JS52-JS65, JS83, JS85, JS87, JS89, JS91, JS93, JS95, JS103-JS108 JS103-JS108. 1.12 Power-On Configuration The GT-32090 GT-32090 DMAReq[2:0] and DMAAck[2:0]* pins define the internal base address and device address at reset. Three-position jumpers J38-J43 J38-J43 enable pull-up or pulldown of those pins. In order to pull up a pin, jumper pins 1 and 2; in order to pull down a pin, jumper pins 2 and 3. - J38 pulls up or down DMAReq[0] signal, - J39 pulls up or down DMAReq[1] signal, - J40 pulls up or down DMAReq[2] signal, - J41 pulls up or down DMAAck[0]* signal, - J42 pulls up or down DMAAck[1]* signal, - J43 pulls up or down DMAAck[2]* signal. The CPU's STEST and ONCE* signals are also sampled at reset. The ONCE* signal is pulled up internally (and might be pulled up externally as well), thus ensuring that the CPU will not wake up in HIGH-Z state. The STEST signal is sampled at reset and determines whether the CPU will start self-test after reset. In order to enable self-test for the master CPU, JS127 JS127 should be installed. In order to disable self-test for the master CPU, JS128 JS128 should be installed. In order to enable self-test for the secondary CPU, JS66 should be installed. In order to disable self-test for the secondary CPU, JS67 should be installed. 1.14 PALs There are two PALs in the design: The first is an EPM7032 EPM7032 PAL (U21) controlling the handshaking between the ISA bus and the Galileo-5 board (refer to the ISA bus overview section for more details). The second PAL is a small 22V10 22V10 PAL (U18) used for PCMCIA decoding. U18 controls the PCMCIA and different Chip Selects. It generates the static PCMCIA signals reset and reg*, and enables reading the PCMCIA status using the reg_rd* signal. The pc_cs* signal decodes access to the ISA bus PAL. Footprints for three more PALs that customers do not need to use are included on the underside: U30 is a test PAL, U33 is a spare PAL, and U31's main purpose is internal testing for dual CPUs functionality. 1.15 Expansion Connectors There are two 96-pin expansion connectors (P1 & P2). The P1 connector includes: - SIO bus data, address, and control lines, allowing the addition of SIO bus devices in daughter cards. - DMAReq[2.0] and DMAAck[2.0]*, allowing the use of DMA engines. - ex_int[2.0]*, allowing the interrupt of the CPUs by external sources. The P2 connector includes: - AD bus latched address ladd[31.0], AD bus transceiver, buffered data rdata[31.0], and control lines 7 Galileo-5 32-bit i960Jx Evaluation & Development Syste m enabling the addition of AD bus devices. Clock & Rst* lines are also included in the P1 & P2 connectors. 1.16 Test Points Several test headers (TP1-TP11 TP1-TP11) are provided to facilitate system debugging. A list of these test points appears in section 10 of this manual. 1.17 Power The Galileo-5 may be powered by the motherboard if inserted into an ISA slot, or by applying power directly to connector P5 for standalone operation. The power supply needed by P5 is a standard PC supply, via a connector with both +12V and +5V. 8 Galileo-5 32-bit i960JX Evaluation & Development System 2 START-UP INSTRUCTION S 2.1 Standalone Mode 1) There are two serial connectors, use the P11 connector. 2) Using a terminal or a PC as terminal, use the following communications settings: Baud Rate - Up to 115200 (9600 default) Data Bits - 8 Stop Bits - 1 Parity - None Flow Control - None 3) Use a crossed 9-pin cable (pins 2, 3, 5 at one end connected respectively to pins 3, 2, 5 at the other end) to connect P11 to the terminal. 4) Insert the enclosed 1MB SIMM into the U1 slot. 5) Connect a standard PC power supply to P5 via a connector with +12V and +5V. P5 VCC GND 12V 6) Power up 7) If you are not using 9600 as your standard Baud Rate, press the ENTER key a few times until the Baud Rate is detected and a greeting message from the monitor program should appear. Proceed according to Intel MON960 MON960 manual. 2.2 ISA Adapter Card Mode 1) Same 2) Same 3) Same 4) Same 5) If you want the Galileo-5 to be reset by the PC, move J67 to positions 2,3. 6) Plug the board into a free ISA slot in the PC. 7) Power up 8) Same as 7 in 2.1 9 Galileo-5 32-bit i960Jx Evaluation & Development Syste m 3 ADDRESS MAP 3.1 i960 Address Map The following is the default memory map. The application can change the GT-32090 GT-32090 default values, by writing to the GT-32090 GT-32090 Address Space decode registers. Physical Addres s Size Description 0x00000000 1 to 16Mbyte DRAM Bank0 0x01000000 1 to 16Mbyte DRAM Bank1 0x02000000 1 to 16Mbyte DRAM Bank2 0x03000000 1 to 16Mbyte DRAM Bank3 0x20000000 Up to 32Mbyte Device 0 0x40000000 Up to 32Mbyte Device 1 0x60000000 Up to 32Mbyte Device 2 0x80000000 Up to 16Mbyte SIO 0 0x81000000 Up to 16Mbyte SIO 1 0x82000000 Up to 16Mbyte SIO 2 0x83000000 Up to 16Mbyte SIO 3 0xa0000000 128 Mbyte PCMCIA A 0xa8000000 128 Mbyte PCMCIA B 0xcc000000 64 Mbyte GT-32090 GT-32090 Internal Address Space 0xe0000000 Up to 32Mbyte Boot Device 0x83000000 16-bit Read PCMCIA A & B Status P/SData[0]- irq#A P/SData[1]- wpA P/SData[2]- bvdA1 P/SData[3]- bvdA2 P/SData[4]- cdA#1 P/SData[5]- cda#2 P/SData[6]- P.D. P/SData[7]- P.D. P/SData[8]- irq#B P/SData[9]- wpB P/SData[10]- bvdB1 P/SData[11]- bvdB2 P/SData[12]- cdB#1 P/SData[13]- cdB#2 P/SData[14]- P.D. P/SData[15]- P.D. 10 Galileo-5 32-bit i960JX Evaluation & Development System 0x83000000 1-bit Reset PCMCIA A Card. The value written to P/SData[0] is latched to resetA signal. 0x83000004 1-bit Reset PCMCIA B Card. The value written to P/SData[0] is latched to resetB signal. 0x83000008 1-bit Set PCMCIA A Card Reg Signal The value written to P/SData[0] is latched to to regA# signal. 0x8300000C 1-bit Set PCMCIA B Card Reg Signal The value written to P/SData[0] is latched to to regB# signal. 0x83400000 8-bit Write Byte to Host PC or Read Byte from Host PC. The value written to P/SData[0.7] is latched at U22 and can be read by the HOST PC. The value written by the Host PC can be read by the i960 from U23 on P/SData[0:7]. 11 Galileo-5 32-bit i960Jx Evaluation & Development Syste m 0x83400004 2-bit Read Latch Status or Program DMAReq[0] Behavior. Read Latch Status The Galileo-5 and the PC communicate with each other using status word which can be read. When the PC writes a byte of data to the Galileo-5, the board will know it by polling the status word. P/SData[0] is high whenever data has been written by the PC, and should be read by the Galileo-5 board. If the Galileo-5 writes a byte of data to the PC, only after the PC reads that data can the Galileo-5 write the next byte of data. P/SData[1] is high whenever data has been written by the Galileo-5, but has not yet been read by the PC. The Galileo-5 should not write the next byte of data until P/SData[1] is low. DMAReq Control The Galileo-5 Board supports DMA operation between the board and the PC, but only on the board's side. One channel of DMA is available for the Galileo-5, so the user controls the DMA direction to be either board to PC or PC to board. To transfer data from the board to the PC using DMA, write P/SData[1:0]=1. When the last data sent by the Galileo-5 is read by the PC, the DMAReq[0] signal will become active, and a new word of data will be sent to the PC. To transfer data from the PC to the board using DMA, write P/SData[1:0]=2. When data is sent by the PC to the board, the DMAReq[0] signal will be active, and the data word will be sent to the Galileo-5 memory. Note: a. The GT-32090 GT-32090 must be programmed for DMA operation with the right direction before enabling the Galileo-5's DMA option. b. The Status word can be read, when using the DMA option. 12 Galileo-5 32-bit i960JX Evaluation & Development System 3.2 Host PC Address Map The physical address accessed is composed of the following bits {1100, isa_sel[5.4], isaSA[3.2], xx}; isa_sel[5.4] are configured by the user, using jumpers J58-J59 J58-J59. The default address that the board is configured to when shipped is 0x330. isaSA[3.2] valu e Size Description isaSA[3.2] = 00 8-bit Write Byte to i960 or Read Byte from i960. The value written to isaSD[0.7] is latched at U23 and can be read by the i960. The value written by the i960 can be read by the Host PC from U22. isaSA[3.2] = 01 2-bit Read Latches' Status. isaSD0 is HIGH when the data written by the Host PC has not been read yet (new data can't be written until this bit is LOW). isaSD1 is HIGH when data has been written to the latch by the i960 (the data should be read by the Host PC). isaSA[3.2] = 10 Send interrupt to the i960. Writing to this address activates pc_int# 13 Galileo-5 32-bit i960Jx Evaluation & Development Syste m 4 EXPANSION CONNECTORS PIN LIS T P1 A1 VCC B1 VCC C1 VCC A2 Rst* B2 clkin[4] C2 N.C. A3 GND B3 GND C3 GND A4 SBE[0]* B4 SBE[1]* C4 SCS[0]* A5 SCS[1]* B5 SCS[2]* C5 SCS[3]* A6 SWr* B6 SRd* C6 SWait* A7 P/SAddr[0] B7 P/SAddr[1] C7 P/SData[0] A8 P/SData[1] B8 P/SData[2] C8 P/SData[3] A9 P/SData[4] B9 P/SData[5] C9 P/SData[6] A10 P/SData[7] B10 P/SData[8] C10 P/SData[9] A11 P/SData[10] B11 P/SData[11] C11 P/SData[12] A12 P/SData[13] B12 P/SData[14] C12 P/SData[15] A13 VCC B13 VCC C13 VCC A14 ex_int[0]* B14 ex_int[1]* C14 EX_INT[2]* A15 N.C. B15 N.C. C15 N.C. A16 GND B16 GND C16 GND A17 DMAAck[0]* B17 DMAAck[1]* C17 DMAAck[2]* A18 DMAReq[0] B18 DMAReq[1] C18 DMAReq[2] A19 N.C. B19 Rst* C19 clkin[4] A20 VCC B20 VCC C20 VCC A21 N.C. B21 N.C. C21 N.C. A22 N.C. B22 N.C. C22 N.C. A23 N.C. B23 N.C. C23 N.C. A24 N.C. B24 N.C. C24 N.C. A25 N.C. B25 N.C. C25 N.C. A26 N.C. B26 N.C. C26 N.C. A27 N.C. B27 N.C. C27 N.C. A28 N.C. B28 N.C. C28 N.C. A29 N.C. B29 N.C. C29 N.C. A30 N.C. B30 N.C. C30 N.C. A31 N.C. B31 N.C. C31 N.C. A32 GND B32 GND C32 GND 14 Galileo-5 32-bit i960JX Evaluation & Development System P2 A1 VCC B1 VCC C1 VCC A2 Rst* B2 clkin[4] C2 Ready* A3 GND B3 GND C3 GND A4 ladd[0] B4 ladd[1] C4 ladd[2] A5 ladd[3] B5 ladd[4] C5 ladd[5] A6 ladd[6] B6 ladd[7] C6 ladd[8] A7 ladd[9] B7 ladd[10] C7 ladd[11] A8 ladd[12] B8 ladd[13] C8 ladd[14] A9 ladd[15] B9 ladd[16] C9 ladd[17] A10 ladd[18] B10 ladd[19] C10 ladd[20] A11 ladd[21] B11 ladd[22] C11 ladd[23] A12 ladd[24] B12 ladd[25] C12 ladd[26] A13 ladd[27] B13 ladd[28] C13 ladd[29] A14 ladd[30] B14 ladd[31] C14 A2 A15 A3 B15 BE[0]* C15 BE[1]* A16 BE[2]* B16 BE[3]* C16 BootCS* A17 VCC B17 VCC C17 VCC A18 DevCS[0]* B18 DevCS[1]* C18 DevCS[2]* A19 WrEn[0]* B19 WrEn[1]* C19 WrEn[2]* A20 WrEn[3]* B20 BW/R2* C20 GND A21 GND B21 GND C21 rdata[0] A22 rdata[1] B22 rdata[2] C22 rdata[3] A23 rdata[4] B23 rdata[5] C23 rdata[6] A24 rdata[7] B24 rdata[8] C24 rdata[9] A25 rdata[10] B25 rdata[11] C25 rdata[12] A26 rdata[13] B26 rdata[14] C26 rdata[15] A27 rdata[16] B27 rdata[17] C27 rdata[18] A28 rdata[19] B28 rdata[20] C28 rdata[21] A29 rdata[22] B29 rdata[23] C29 rdata[24] A30 rdata[25] B30 rdata[26] C30 rdata[27] A31 rdata[28] B31 rdata[29] C31 rdata[30] A32 rdata[31] B32 DAdr[0] C32 DAdr[1] 15 Galileo-5 32-bit i960Jx Evaluation & Development Syste m 5 CUSTOMER CONFIGURABLE OPTION S 5.1 Removable Jumpers The following table describes the various optional settings of the Galileo-5 board, as a function of the presence or absence of its removable jumpers. The default setting found in the shipping configuration is shown. Removable Jumpers Settings Default Function J1 OFF * Do not chain ON J2 OFF Chains GT-32090 GT-32090 JTDO to P6 connector TDO (internal testing) * ON J3 OFF Chains Master CPU TDO to P6 connector TDO (internal testing) * ON J5 OFF OFF * OFF * OFF * OFF * OFF * Do not chain Chains GT-32090 GT-32090 JTDO to Secondary CPU TDI (internal testing) * ON J12 Do not chain Chains GT-32090 GT-32090 JTDO to Master CPU TDI (internal testing) ON J10 Do not chain Chains P6 connector TDI to Secondary CPU TDI (internal testing) ON J9 Do not chain Chains P6 connector TDI to Master CPU TDI (internal testing) ON J8 Do not chain Chains P6 connector TDI to GT-32090 GT-32090 JTDI (internal testing) ON J7 Do not chain Chains Secondary CPU TDO to P6 connector TDO (internal testing) ON J6 Do not chain Do not chain Chains Master CPU TDO to Secondary CPU TDI (internal testing) All OFF A 12 x 2 header enabling the selection of interrupt sources entering each of the Secondary CPU's interrupt inputs (use jumpers or wirewraps to make your selection). Odd pins are connected to interrupt sources, while even pins are connected to the Secondary CPU. pin 1 ex_int[2]]# interrupt from expansion port pin 2 N.C. pin 3 irqA# interrupt from PCMCIA A card pin 4 N.C. pin 5 irqB# interrupt from PCMCIA B card pin 6 N.C. pin 7 serint1 interrupt from the DUART pin 8 Secondary CPU NMI# input pin 9 serint2 interrupt from the DUART pin 10 Secondary CPU XINT[0]# input 16 Galileo-5 32-bit i960JX Evaluation & Development System Removable Jumpers Settings Default Function pin 11 DMAInt[0]* interrupt from GT-32090 GT-32090 pin 12 Secondary CPU XINT[1]# input pin 13 DMAInt[1]* interrupt from GT-32090 GT-32090 pin 14 Secondary CPU XINT[2]# input pin 15 DMAInt[2]* interrupt from GT-32090 GT-32090 pin 16 Secondary CPU XINT[3]# input pin 17 ex_int#0 interrupt from expansion port pin 18 Secondary CPU XINT[4]# input pin 19 ex_int#1 interrupt from expansion port pin 20 Secondary CPU XINT[5]# input pin 21 pc_int# interrupt from ISA PAL pin 22 Secondary CPU XINT[6]# input pin 23 M2Sint# interrupt from Master to Secondary CPU pin 24 Secondary CPU XINT[7]# input J13, J14, J68, J69 OFF, ON, ON, OFF ON, OFF, OFF, ON J15, J16, J17, J18, J19, J20 EPROM connected as Device 0, Flash connected as Boot Device * EPROM connected as Boot Device, Flash connected as Device 0 OFF, ON, OFF, ON, OFF, ON EPROM type is 27C256 27C256 or 27C512 27C512 ON, OFF, OFF, ON, OFF, ON EPROM type is 27C010 27C010 or 27C020 27C020 ON, OFF, ON, OFF, OFF, ON * ON, OFF, ON, OFF, ON, OFF J21, J24, J27, J30, J35, J44, J49, J531 OFF, OFF, OFF, OFF, OFF, OFF, OFF, OFF EPROM type is 27C040 27C040 EPROM type is 27C080 27C080 * 16-bit or 32-bit wide Flash ON, ON, ON, ON, OFF, OFF, OFF, OFF 8-bit wide Flash with 28F256 28F256 type ON, ON, ON, ON, ON, OFF, OFF, OFF 8-bit wide Flash with 28F512 28F512 type ON, ON, ON, ON, ON, ON, OFF, OFF 8-bit wide Flash with 28F010 28F010 type ON, ON, ON, ON, ON, ON, ON, OFF 8-bit wide Flash with 28F020 28F020 type ON, ON, ON, ON, ON, ON, ON, ON 8-bit wide Flash with 28F040 28F040 type 17 Galileo-5 32-bit i960Jx Evaluation & Development Syste m Removable Jumpers Settings Default Function J22, J24, J29, J30, J36, J45, J50, J541 OFF, OFF, OFF, OFF, OFF, OFF, OFF, OFF * 8-bit or 32-bit wide Flash ON, ON, ON, ON, OFF, OFF, OFF, OFF ON, ON, ON, ON, ON, OFF, OFF, OFF 16-bit wide Flash with 28F512 28F512 type ON, ON, ON, ON, ON, ON, OFF, OFF 16-bit wide Flash with 28F010 28F010 type ON, ON, ON, ON, ON, ON, ON, OFF 16-bit wide Flash with 28F020 28F020 type ON, ON, ON, ON, ON, ON, ON, ON 16-bit wide Flash with 28F040 28F040 type OFF, OFF, OFF, OFF, OFF, OFF, OFF, OFF 8-bit or 16-bit wide Flash ON, ON, ON, ON, OFF, OFF, OFF, OFF 32-bit wide Flash with 28F256 28F256 type ON, ON, ON, ON, ON, OFF, OFF, OFF J23, J26, J29, J32, J37, J46, J51, J551 16-bit wide Flash with 28F256 28F256 type 32-bit wide Flash with 28F512 28F512 type ON, ON, ON, ON, ON, ON, OFF, OFF * 32-bit wide Flash with 28F010 28F010 type ON, ON, ON, ON, ON, ON, ON, OFF ON, ON, ON, ON, ON, ON, ON, ON J48 32-bit wide Flash with 28F020 28F020 type 32-bit wide Flash with 28F040 28F040 type All OFF A 12 x 2 header enabling the selection of interrupt sources entering each of the Master CPU's interrupt inputs (use jumpers or wirewraps to make your selection). Odd pins are connected to interrupt sources, while even pins are connected to the Master CPU. pin 1 ex_int[2]# interrupt from expansion port pin 2 N.C. pin 3 irqA# interrupt from PCMCIA A card pin 4 N.C. pin 5 irqB# interrupt from PCMCIA B card 18 Galileo-5 32-bit i960JX Evaluation & Development System Removable Jumpers Settings Default Function pin 6 N.C. pin 7 serint[1] interrupt from the DUART pin 8 Master CPU NMI# input pin 9 serint2 interrupt from the DUART pin 10 Master CPU XINT[0]# input pin 11 DMAInt[0]* interrupt from GT-32090 GT-32090 pin 12 Master CPU XINT[1]# input pin 13 DMAInt[1]* interrupt from GT-32090 GT-32090 pin 14 Master CPU XINT[2]# input pin 15 DMAInt[2]* interrupt from GT-32090 GT-32090 pin 16 Master CPU XINT[3]# input pin 17 ex_int[0]# interrupt from expansion port pin 18 Master CPU XINT[4]# input pin 19 ex_int[1]# interrupt from expansion port pin 20 Master CPU XINT[5]# input pin 21 pc_int# interrupt from ISA PAL pin 22 Master CPU XINT[6]# input pin 23 S2Mint# interrupt from Secondary to Master CPU pin 24 Master CPU XINT[7]# input J58,J59 OFF,OFF * Standard Mode OFF, ON ON, OFF Selects different address for the ISA PAL. ON, ON Selects different address for the ISA PAL. OFF, OFF J61, J62 Selects different address for the ISA PAL. 8-bit Flash configuration OFF, ON * 16-bit Flash configuration ON, OFF 2 J64, J65, J66 ON, OFF, OFF 32-bit Flash configuration * Connects 28F256/512/010/020 28F256/512/010/020 VPP voltage to 12V OFF, ON, OFF OFF, OFF, ON 3 J67 Connects 28F256/512/010/020 28F256/512/010/020 VPP voltage to 5V Connects 28F256/512/010/020 28F256/512/010/020 VPP voltage to 0V 1, 2 ON 2, 3 ON * On-board switch is the reset source Host PC (via ISA bus) is the reset source Notes: 1. J25, J28, and J31, although present on the board, are dummy jumpers. They are not needed, so their absence or presence does n ot affect the Flash configuration. 2. 28F040 28F040 devices cannot use a 12V option. 3. If you hold the board with the two serial ports facing down, pin 3 on J67 will be on the left and pin 1 on the right. 19 Galileo-5 32-bit i960Jx Evaluation & Development Syste m 5.2 Power On Configuration Jumpers The following table describes the possible configurations attainable at power on depending on the presence or absence of removable jumpers. These configurations determine the MSB's of the Internal Space Decode and the four Devices (please consult the GT-32090 GT-32090 data sheet). The default setting found in the shipping configuration is shown. Removable Jumpers 1 J38 Settings Default Function 1,2 ON * Pull up DMAReq[0] at power up 2,3 ON J391 1,2 ON Pull down DMAReq[0] at power up * 2,3 ON 1 J40 1,2 ON Pull up DMAReq[1] at power up Pull down DMAReq[1] at power up * Pull up DMAReq[2] at power up 2,3 ON 1 J41 Pull down DMAReq[2] at power up 1,2 ON Pull up DMAAck[0]* at power up 2,3 ON J421 * Pull down DMAAck[0]* at power up 1,2 ON * Pull up DMAAck[1]* at power up 2,3 ON 1 J43 1,2 ON 2,3 ON Pull down DMAAck[1]* at power up * Pull up DMAAck[2]* at power up Pull down DMAAck[0]* at power up Notes: 1. If you hold the board with the two serial ports facing down, pin 3 on J38-J43 J38-J43 will be on the left and pin 1 on the right. 20 Galileo-5 32-bit i960JX Evaluation & Development System 5.3 Zero-ohm Resistors The following table describes the settings associated with the presence or absence of zero-ohm resistors (surface mounted jumpers) that help configure several signal paths on the Galileo-5 module. The default setting found in the shipping configuration is shown. Zero-ohm Resistors Settings Default Function JS1, JS2 ON, OFF * Selects VPP2 of PCMCIA card A to be 5V OFF, ON JS3, JS4 ON, OFF Selects VPP2 of PCMCIA card A to be 12V * OFF, ON JS5, JS6 ON, OFF Selects VPP1 of PCMCIA card A to be 12V * OFF, ON JS7, JS8 ON, OFF ON, OFF Selects VPP1 of PCMCIA card B to be 5V Selects VPP1 of PCMCIA card B to be 12V * OFF, ON JS42, JS43 Selects VPP1 of PCMCIA card A to be 5V Selects VPP2 of PCMCIA card B to be 5V Selects VPP2 of PCMCIA card B to be 12V * OFF, ON Enable DRAM latches Disable DRAM latches JS9-JS16 JS9-JS16, All OFF * Use DRAM latches (used in conjunction with JS42) JS33-JS41 JS33-JS41, All ON Bypass DRAM latches (used in conjunction with JS43) ON, OFF Bypass CAS[0]* signal driving JS44-JS51 JS44-JS51, JS76-JS82 JS76-JS82 JS17, JS52 OFF, ON JS18, JS53 ON, OFF OFF, ON JS19, JS54 JS21, JS56 JS23, JS58 JS84, JS83 * Enable DAdr[0] signal driving Bypass DAdr[1] signal driving * Enable DAdr[1] signal driving Bypass DAdr[2] signal driving * Enable DAdr[2] signal driving Bypass DAdr[3] signal driving * Enable DAdr[3] signal driving Bypass DAdr[4] signal driving * ON, OFF OFF, ON Enable CAS[3]* signal driving Bypass DAdr[0] signal driving ON, OFF OFF, ON JS86, JS85 * ON, OFF OFF, ON Enable CAS[2]* signal driving Bypass CAS[3]* signal driving ON, OFF OFF, ON JS24, JS59 * ON, OFF OFF, ON Enable CAS[1]* signal driving Bypass CAS[2]* signal driving ON, OFF OFF, ON JS22, JS57 * ON, OFF OFF, ON Enable CAS[0]* signal driving Bypass CAS[1]* signal driving ON, OFF OFF, ON JS20, JS55 * Enable DAdr[4] signal driving Bypass DAdr[5] signal driving * Enable DAdr[5] signal driving 21 Galileo-5 32-bit i960Jx Evaluation & Development Syste m Zero-ohm Resistors Settings JS88, JS87 ON, OFF OFF, ON JS90, JS89 JS94, JS93 JS25, JS60 JS27, JS62 JS29, JS64 JS97, JS103 JS103 JS99, JS105 JS105 JS101 JS101, JS107 JS107 Enable RAS[1]* signal driving Bypass RAS[2]* signal driving * Enable RAS[2]* signal driving Bypass RAS[3]* signal driving * Enable RAS[3]* signal driving Bypass DWr* signal driving (copy #1) * Enable DWr* signal driving (copy #1) Bypass DWr* signal driving (copy #2) * Enable DWr* signal driving (copy #2) Bypass Clock signal driving (copy #1) * Enable Clock signal driving (copy #1) Bypass Clock signal driving (copy #2) * Enable Clock signal driving (copy #2) Bypass Clock signal driving (copy #3) * Enable Clock signal driving (copy #3) Bypass Clock signal driving (copy #4) * ON, OFF OFF, ON JS102 JS102, JS108 JS108 * ON, OFF OFF, ON Enable RAS[0]* signal driving Bypass RAS[1]* signal driving ON, OFF OFF, ON JS100 JS100, JS106 JS106 * ON, OFF OFF, ON Enable DAdr[10] signal driving Bypass RAS[0]* signal driving ON, OFF OFF, ON JS98, JS104 JS104 * ON, OFF OFF, ON Enable DAdr[9] signal driving Bypass DAdr[10] signal driving ON, OFF OFF, ON JS30, JS65 * ON, OFF OFF, ON Enable DAdr[8] signal driving Bypass DAdr[9] signal driving ON, OFF OFF, ON JS28, JS63 * ON, OFF OFF, ON Enable DAdr[7] signal driving Bypass DAdr[8] signal driving ON, OFF OFF, ON JS26, JS61 * ON, OFF OFF, ON Enable DAdr[6] signal driving Bypass DAdr[7] signal driving ON, OFF OFF, ON JS96, JS95 * ON, OFF OFF, ON Function Bypass DAdr[6] signal driving ON, OFF OFF, ON JS92, JS91 Default Enable Clock signal driving (copy #4) Bypass W/R* signal driving (copy #1) * ON, OFF Enable W/R* signal driving (copy #1) Bypass W/R* signal driving (copy #1) OFF, ON JS66, JS67 * Enable W/R* signal driving (copy #2) ON, OFF * Do Secondary CPU self-test after reset OFF, ON JS127 JS127, JS128 JS128 ON, OFF OFF, ON 22 Skip Secondary CPU self-test after reset * Do Master CPU self-test after reset Skip Master CPU self-test after reset Galileo-5 32-bit i960JX Evaluation & Development System Zero-ohm Resistors Settings JS31, JS32 ON, OFF OFF, ON Default Function Use external oscillator as clock source * Use on-board oscillator as clock source JS137 JS137, JS140 JS140, JS142 JS142, JS144 JS144 All OFF 16-bit or 32-bit wide SRAM (internal testing) All ON Selects 8-bit wide SRAM JS138 JS138, JS140 JS140, JS143 JS143, JS144 JS144, JS146 JS146 All OFF 8-bit or 32-bit wide SRAM (internal testing) All ON Selects 16-bit wide SRAM JS139 JS139, JS141 JS141, JS143 JS143, JS145 JS145, JS147 JS147 All OFF 8-bit or 16-bit wide SRAM (internal testing) JS125 JS125, JS126 JS126 ON, OFF All ON * Selects 32-bit wide SRAM Disable buffers for slow devices on AD bus OFF, ON JS68-JS75 JS68-JS75, * Enable buffers for slow devices on AD bus All OFF * Use buffers for slow devices on AD bus (used in conjunction with JS126 JS126). JS109-JS124 JS109-JS124, JS129-JS136 JS129-JS136 All ON Bypass buffers for slow devices on the AD bus (used in conjunction with JS125 JS125). 23 Galileo-5 32-bit i960Jx Evaluation & Development Syste m 6 HARDWARE INFORMATIO N 6.1 Schematics The schematics of the Galileo-5 can be found in Appendix 2. 6.2 ORCAD Files Description For customers using ORCAD, diskettes are provided with all the schematic information. The files included and their descriptions follow: Galileo-5 board sbc32090.sch - Root schematic for the Galileo-5 board master.sch - Intel 960JX 960JX master processor (under sbc32090.sch) slave.sch - Intel 960JX 960JX secondary processor (under sbc32090.sch) gt32090.sch - GT-32090 GT-32090 module (under sbc32090.sch) misc.sch - Reset, clock, power, & JTAG (under sbc32090.sch) buffers.sch - DRAM control signal drivers (under sbc32090.sch) dram.sch - Buffers, DRAM, & latches (under sbc32090.sch) simm72.sch - 72 pin SIMMS (under dram.sch) fla.sch - Address latch, memories, & transceivers (under dev.sch) latch.sch - DRAM latches (under dram.sch) sram.sch - SRAM memories (under dev.sch) dev.sch - Root schematic for all device schematics (under sbc32090.sch) boot.sch - 8-bit boot ROM or flash (under dev.sch) trans.sch - Transceiver (under dev.sch) adlatch.sch - Address latches (under dev.sch) pcmcia.sch - PCMCIA slots (under sbc32090.sch) stab.sch - Logic for 2 CPUs and address decoding (under sbc32090.sch) serial.sch - 16552 UART (under sbc32090.sch) isa.sch - Connection to PC ISA port test_p.sch - Test points (under sbc32090.sch) exp.sch - expansion connectors (under sbc32090.sch) testing.sch - Logic for GT196 GT196 testing (under sbc32090.sch) 24 Galileo-5 32-bit i960JX Evaluation & Development System Galileo-5 Board 6.3 Physical Board Layout 25 Galileo-5 32-bit i960Jx Evaluation & Development Syste m 6.4 Bill Of Materials Jumpers, resistors and capacitors have been omitted. Qty Reference Part Descriptio n 1 D1 LED 2 J12, J48 12 x 2 header 1 OSC1 33.33MHz oscillator 1 OSC2 3.6864 MHz oscillator 2 P1, P2 DIN96 DIN96 connector 1 P5 CON4 2 P8, P9 PCMCIA 68-pin connector 2 P10, P11 DB-9 connector 1 S1 SPDT switch 11 TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10, TP11 HP Header connector for test points 2 U1, U2 DRAM SIMM 72-pin 4 U3, U11, U15, U20 32PLCC 32PLCC sockets for Flash 2 U4, U5 IDT74FCT16543 IDT74FCT16543 3 U6, U7, U13 IDT74FCT162244CTPA IDT74FCT162244CTPA 2 U17 i960Jx Master i960Jx 33MHz CPU (socketed) 1 U9 27C040 27C040 EPROM (socketed) 2 U10, U16 IDT74FCT16245 IDT74FCT16245 1 U12 GT-32090 GT-32090 1 U14 MAX238CWG MAX238CWG 1 U18 22V10 22V10 PCMCIA Decoding PAL 1 U19 PC16552DV PC16552DV 1 U21 EPM7032 EPM7032 ISA EPLD 2 U22, U23 74LS373SC 74LS373SC 1 U24 MAX708CSA MAX708CSA 2 U25, U26 IDT74FCT162373CTPA IDT74FCT162373CTPA The following footprints are provided, with no parts in them, since they are mainly for internal testing: 1 U8 Footprint for optional socket for Secondary i960Jx CPU 4 U27, U28, U29, U32 Footprints for IDT71256 IDT71256 SRAMs 1 U30 Footprint for test PAL 1 U31 Footprint for dual CPUs PAL 1 U33 Footprint for spare bug PAL 26 Galileo-5 32-bit i960JX Evaluation & Development System 7 PAL EQUATIONS isaWE 7.1 ISA Interface PAL (U21) /gtOE :OUTPUT; gtWE :OUTPUT; % PLD Function: ISA interface /dmareq0 Altera part number: 7032-10 Circuit board: :OUTPUT; :OUTPUT; /pc_int Galileo-5 :OUTPUT; /pc_reset % :OUTPUT; /swait TITLE "ISA interface"; :OUTPUT; ) CONSTANT DMA_ISA2GT = 1; % DMA transfer from ISA bus to GT % VARIABLE CONSTANT DMA_GT2ISA = 2; % DMA transfer from GT to ISA BUS % isaEn : NODE; DESIGN IS "isa" isaRead[1.0] : DFF; BEGIN gtWrote[1.0] : DFF; isaWrote[1.0] : DFF; DEVICE "" IS "EPM7032LC44-10 EPM7032LC44-10"; gtRead[1.0] : DFF; END; isaFull : DFF; SUBDESIGN isa gtFull : DFF; ( DMAmode[1.0] : DFFE; isaRST :INPUT; clk ISArstCmd :INPUT; /isaIORD :INPUT; TRIsdata[1.0] : TRI; :INPUT; /isaIOWR /isaAEN : NODE; TRIsd[1.0] : TRI; BEGIN :INPUT; % Disable Hold option % isaSA[9.2] :INPUT; /swait = vcc; isaSel0 :INPUT; % isa decode % isaSel1 :INPUT; /ioe1 :INPUT; isaEn = (isaSA[5.4] = isaSel[1.0]) & (isaSA[9.6] = H"c") & !/isaAEN /ioe2 :INPUT; ; /swr :INPUT; % isa latch control % /srd :INPUT; !/isaOE = isaEn & (isaSA[3.2] = 0) & !/isaIORD; ladd2 :INPUT; isaWE = isaEn & (isaSA[3.2] = 0) & !/isaIOWR; /pc_cs :INPUT; % gt latch control % /dmaack0 :INPUT; !/gtOE = !/pc_cs & !ladd2 & !/srd; isaSD[1.0] :BIDIR; gtWE = !/pc_cs & !ladd2 & !/swr; sdata[1.0] % Latch flags % :BIDIR; /ooe1 :OUTPUT; isaWrote[0] = isaWE; /ooe2 :OUTPUT; isaWrote[1] = isaWrote[0]; /isaOE :OUTPUT; isaWrote[].clk = GLOBAL(clk); 27 Galileo-5 32-bit i960Jx Evaluation & Development Syste m isaWrote[].clrn = !isaRST; !/ooe2 = isaEn & (isaSA[3.2] = 1) & !/isaIORD; isaRead[0] = !/isaOE; TRIsd[].oe = !/ioe2; isaRead[1] = isaRead[0]; TRIsd[0] = isaFull; isaRead[].clk = GLOBAL(clk); TRIsd[1] = gtFull; isaRead[].clrn = !isaRST; isaSD[] = TRIsd[]; gtWrote[0] = gtWE; % Control - PAL configuration % gtWrote[1] = gtWrote[0]; DMAmode[] = sdata[]; gtWrote[].clk = GLOBAL(clk); DMAmode[].clk = GLOBAL(clk); gtWrote[].clrn = !isaRST; DMAmode[].clrn = isaRST; gtRead[0] = !/gtOE; DMAmode[].ena = !/pc_cs & ladd2 & !/swr; gtRead[1] = gtRead[0]; % ISA control % gtRead[].clk = GLOBAL(clk); gtRead[].clrn = !isaRST; isaFull = !isaWrote[0] & isaWrote[1] # isaFull & !(!gtRead[0] & gtRead[1]); % ISArstCmd = isaEn & (isaSA[3.2] = 1) & !/ isaIOWR; !/pc_int = isaEn & (isaSA[3.2] = 2) & !/isaIOWR; END; isaFull = isaWE # isaFull & /gtOE; % isaFull.clk = GLOBAL(clk); isaFull.clrn = !isaRST; gtFull = !gtWrote[0] & gtWrote[1] # gtFull & !(!isaRead[0] & isaRead[1]); % gtFull = gtWE # gtFull & /isaOE; % gtFull.clk = GLOBAL(clk); gtFull.clrn = !isaRST; % gt dma request % !/dmareq0 = isaFull & (DMAmode[] = DMA_ISA2GT) # !gtFull & (DMAmode[] = DMA_GT2ISA); % Reset from isa board % !/pc_reset = isaRST # ISArstCmd; % gt statuses % !/ooe1 = !/pc_cs & ladd2 & !/srd; TRIsdata[].oe = !/ioe1; TRIsdata[0] = isaFull; TRIsdata[1] = gtFull; sdata[] = TRIsdata[]; % isa statuses % 28 7.2 PCMCIA Control/Decoding PAL (U18) module gtpcmcia flag '-r3' title 'Control signals for the PCMCIA and general decoding' pcmcia device 'P22V10 P22V10'; " Ref: U? " Type: SMD " Speed: 10 nsec. "Inputs _reset pin 2; _scs3 pin 3; _swr pin 4; _srd pin 5; ladd23 pin 6; ladd22 pin 7; ladd21 pin 8; ladd3 pin 9; ladd2 pin 10; _iordA pin 11; _iordB pin 13; wpA pin 18; wpB pin 17; "Ootputs _regrd pin 23; resetA pin 22; resetB pin 21; regA pin 20; regB pin 19; _pc_cs pin 15; Galileo-5 32-bit i960JX Evaluation & Development System "Bidirectional sdata0 pin 16; "Variables pcmcia_en pin 14; reset node 25; chip = [ladd23,ladd22,ladd21]; regadd = [ladd3,ladd2]; Ck,X,Z = .C. , .X., .Z.; ^L equations " Address mapping: " ladd 23 22 21 3 2 op " PCMCIA regrd 0 0 0 0 0 rd " PCMCIA A width 0 0 0 0 1 rd " PCMICA B width 0 0 0 1 0 rd " PCMCIA resetA 0 0 0 0 0 wr value at sdata0 " PCMCIA resetB 0 0 0 0 1 wr value at sdata0 " PCMCIA regA 0 0 0 1 0 wr value at sdata0 " PCMCIA regB 0 0 0 1 1 wr value at sdata0 " PC CS 0 1 0 x x rd/wr " %-% " % PCMCIA control and general decoding % " %-% reset = !_reset; pcmcia_en = !_scs3 & (chip = 0); _regrd = !(pcmcia_en & !_srd & (regadd = 0); " % ResetA % resetA := sdata0 & pcmcia_en & (regadd = 0) & !_swr # resetA & !(pcmcia_en & (regadd = 0) & !_swr); " % ResetB % resetB := sdata0 & pcmcia_en & (regadd = 1) & !_swr # resetB & !(pcmcia_en & (regadd = 1) & !_swr); " % RegA % regA := sdata0 & pcmcia_en & (regadd = 2) & !_swr # regA & !(pcmcia_en & (regadd = 2) & !_swr); " % RegB % regB := sdata0 & pcmcia_en & (regadd = 3) & !_swr # regB & !(pcmcia_en & (regadd = 3) & !_swr); " % accesss isa pal % _pc_cs = !(!_scs3 & (chip = 2); end gtpcmcia 29 Galileo-5 32-bit i960Jx Evaluation & Development Syste m 8 SOFTWARE INFORMATIO N 8.1 Intel MON960 MON960 Software The software provided in the on-board EPROM is a customized version of the Intel Monitor program. Please refer to the corresponding documentation provided by Intel. Galileo may supply source for this code provided certain conditions are met. Please contact Galileo directly for more information. 30 Galileo-5 32-bit i960JX Evaluation & Development System 9 DATA SHEETS/MANUAL S This manual is designed to be used in conjunction with other documentation. We recommend the following: a) Galileo's GT-32090 GT-32090 Data Sheet b) Intel i960JX Data Sheet c) Intel's MON960 MON960 Manual 31 Galileo-5 32-bit i960Jx Evaluation & Development Syste m 10 APPENDICES Pin Number Signal 10.1 Appendix 1. Test Points 13 S2Mint# 14 M2Sint# 15 DMAInt[2]* 16 DMAInt[1]* 17 DMAInt[0]* 18 serint[2] 19 serint[1] 20 GND TP1 - SIO data Pin Number Signal 1 N.C. 2 clkin[4] 3 clkin[4] 4 P/SData[15] 5 P/SData[14] 6 P/SData[13] 7 P/SData[12] Pin Number Signal 8 P/SData[11] 1 N.C. 9 P/SData[10] 2 clkin[4] 10 P/SData[9] 3 clkin[4] 11 P/SData[8] 4 clkin[4] 12 P/SData[7] 5 WaitB* 13 P/SData[6] 6 CardEnB[2]* 14 P/SData[5] 7 CardEnB[1]* 15 P/SData[4] 8 OEB* 16 P/SData[3] 9 WrEnB* 17 P/SData[2] 10 IORdB* 18 P/SData[1] 11 IOWrB* 19 P/SData[0] 12 reg_rd# 20 GND 13 WaitA* 14 CardEnA[2]* 15 CardEnA[1]* 16 OEA* 17 WrEnA* 18 IORdA* 19 IOWrA* 20 GND TP2 - CPU interrupts TP3 - PCMCIA control Pin Number Signal 1 N.C. 2 clkin[4] 3 clkin[4] 4 clkin[4] 5 N.C. 6 N.C. 7 reset# Pin Number Signal 8 irqB# 1 N.C. 9 irqA# 2 clkin[4] 10 ex_int#[2]# 3 clkin[4] 11 ex_int[1]# 4 AD[15] 12 ex_int[0]# 5 AD[14] 32 TP4 - CPU bus Galileo-5 32-bit i960JX Evaluation & Development System Pin Number Signal 6 AD[13] 7 AD[12] TP6 - CPU bus 8 AD[11] Pin Number Signal 9 AD[10] 1 N.C. 10 AD[9] 2 clkin[4] 11 AD[8] 3 clkin[4] 12 AD[7] 4 AD[31] 13 AD[6] 5 AD[30] 14 AD[5] 6 AD[29] 15 AD[4] 7 AD[28] 16 AD[3] 8 AD[27] 17 AD[2] 9 AD[26] 18 AD[1] 10 AD[25] 19 AD[0] 11 AD[24] 20 GND 12 AD[23] 13 AD[22] 14 AD[21] 15 AD[20] 16 AD[19] 17 AD[18] 18 AD[17] 19 AD[16] 20 GND TP5 - SIO control & external bus signals Pin Number Signal 1 N.C. 2 clkin[4] 3 clkin[4] 4 clkin[4] 5 N.C. 6 N.C. 7 pc_cs# 8 test_cs# 9 SWait* 10 SAddr[1] 11 SAddr[0] 12 SBE[1]* 13 SBE[0]* 14 SRd* 15 SWr* 16 SCS[3]* 17 SCS[2]* 18 SCS[1]* 19 SCS[0]* 20 GND TP7 - Device control Pin Number Signal 1 N.C. 2 clkin[4] 3 clkin[4] 4 clkin[4] 5 N.C. 6 N.C. 7 DAdr[1] 8 DAdr[0]* 9 Ready* 10 BufOE* 11 W/R* 12 WrEn[3]* 13 WrEn[2]* 33 Galileo-5 32-bit i960Jx Evaluation & Development Syste m Pin Number Signal Pin Number Signal 14 WrEn[1]* 7 resetB 15 WrEn[0]* 8 resetA 16 DevCS[2]* 9 DAdr[10] 17 DevCS[1]* 10 DAdr[9] 18 DevCS[0]* 11 DAdr[8] 19 BootCS* 12 DAdr[7] 20 GND 13 DAdr[6] 14 DAdr[5] 15 DAdr[4] 16 DAdr[3] 17 DAdr[2] 18 DAdr[1] 19 DAdr[0] 20 GND TP8 - CPU control Pin Number Signal 1 N.C. 2 clkin[4] 3 clkin[4] 4 d/c# 5 blast# 6 width[0] 7 den# 8 width[1] Pin Number Signal 9 dt/r# 1 N.C. 10 a3 2 clkin[4] 11 a2 3 clkin[4] 12 BE[3]* 4 clkin[4] 13 BE[2]* 5 Sfail# 14 BE[1]* 6 N.C. 15 BE[0]* 7 Mfail# 16 RdyRcv* 8 LWrOE* 17 W/R* 9 LRdOE* 18 ADS* 10 LE* 19 ALE 11 DWr* 20 GND 12 CAS[3]* 13 CAS[2]* 14 CAS[1]* 15 CAS[0]* TP9 - DRAM & PCMCIA control TP10 - DRAM control Pin Number Signal 16 RAS[3]* 1 N.C. 17 RAS[2]* 2 clkin[4] 18 RAS[1]* 3 clkin[4] 19 RAS[0]* 4 clkin[4] 20 GND 5 regB# 6 regA# 34 Galileo-5 32-bit i960JX Evaluation & Development System TP11 - Bus arbitration signals & GT-32090 GT-32090 Req & Ack Pin Number Signal 1 N.C. 2 clkin[4] 3 clkin[4] 4 clkin[4] 5 Mbstat 6 Sbstat 7 DMAAck[2]* 8 DMAReq[2] 9 DMAAck[1]* 10 DMAReq[1] 11 DMAAck[0]* 12 DMAReq[0] 13 sdmareq# 14 Sholda 15 Shold 16 Mholda 17 Mhold 18 ADBusGnt 19 ADBusReq 20 GND Grounded Test Points Name Signal J4 GND J11 GND J33 GND J34 GND J47 GND J52 GND J56 GND J57 GND J60 GND J63 GND J70 GND 35 Galileo-5 32-bit i960Jx Evaluation & Development Syste m 10.2 Appendix 2. Schematics Schematics for the Galileo-5 Board follow. 36 1 2 3 4 clock,reset & JTAG tck tms trst# Gtdi Gtdo Mtdi Mtdo Stdi Stdo tck tms trst# Gtdi Gtdo Mtdi Mtdo Stdi Stdo reset# reset clock swr# srd# swr# srd# dmareq#0 dmaack#0 cas#[0.3] ras#[0.3] dadr[0.10] dwr# clock w/r# bcas#[0.3] bras#[0.3] bdadr[0.10] bdwr#[1.2] clkin[1.4] bw/r#[1.2] bcas#[0.3] bras#[0.3] bdadr[0.10] bdwr#[1.2] clkin[1.4] bw/r#[1.2] bdadr[0.10] bras#[0.3] bcas#[0.3] bdwr#[1.2] B irqA# irqB# pc_int# ale ads# be#[0.3] rdyrcv# Mholda Mhold Mbstat w/r# a[2.3] blast# den# dt/r# Mfail# ad[0.31] irqA# irqB# pc_int# ale ads# be#[0.3] rdyrcv# Mholda Mhold Mbstat w/r# a[2.3] blast# den# dt/r# Mfail# lwroe# lrdoe# le# clkin3 ad[0.31] DRAM.SCH Devices ale bdadr[0.1] ad[0.31] bootcs# we#[0.3] bw/r#[1.2] bufoe# a2 be#[0.1] devcs#[0.1] MASTER.SCH testing logic clkin2 reset# sdata0 swr# srd# dmaack#[0.2] test_cs# ladd[2.4] clkin2 reset# sdata0 swr# srd# dmaack#[0.2] test_cs# ladd[2.4] swait# ready# sdmareq# sdata0 ladd[2.4] ladd[21.23] scs#3 srd# swr# C sdata0 ladd[2.4] ladd[21.23] scs#3 srd# swr# iordA# iordB# ladd[2.5] D ladd[0.31] rdata[0.31] wpA wpB wpA wpB irqA# irqB# pc_int# ale ads# be#[0.3] rdyrcv# Sholda Shold Sbstat w/r# a[2.3] blast# den# dt/r# Sfail# irqA# irqB# pc_int# ale ads# be#[0.3] rdyrcv# Sholda Shold Sbstat w/r# a[2.3] blast# den# dt/r# Sfail# dadr[0.10] ras#[0.3] cas#[0.3] dwr# le# lrdoe# lwroe# clkin4 reset# sdmareq# reg_rd# test_cs# pc_cs# irqA# irqB# d/c# width0 width1 reset# clkin4 sbe#[0.1] scs#[0.3] swr# srd# swait# sdata[0.15] saddr[0.1] gt32090 adbusreq adbusgnt dmareq#[0.2] dmaack#[0.2] dmaint#[0.2] ale w/r# ads# Mholda Mhold rdyrcv# be#[0.3] ad[0.31] ale w/r# ads# Mholda Mhold rdyrcv# be#[0.3] ad[0.31] dadr[0.10] ras#[0.3] cas#[0.3] dwr# le# lrdoe# lwroe# dadr[0.10] ras#[0.3] cas#[0.3] dwr# le# lrdoe# lwroe# Gtdi tck tms trst# Gtdo Gtdi tck tms trst# Gtdo clkin1 reset# A bootcs# devcs#[0.2] we#[0.3] ready# bufoe# bootcs# devcs#[0.2] we#[0.3] ready# bufoe# Mfail# Sfail# Mfail# Sfail# resetA resetB regA# regB# Mbstat Sbstat blast# den# dt/r# resetA resetB regA# regB# Mbstat Sbstat blast# den# dt/r# sbe#[0.1] scs#[0.3] swr# srd# swait# sdata[0.15] saddr[0.1] ex_int#[0.2] serint[1.2] reset adbusreq adbusgnt dmareq#[0.2] dmaack#[0.2] dmaint#[0.2] iowrA# iordA# weA# oeA# waitA# ceA#[1.2] iowrB# iordB# weB# oeB# waitB# ceB#[1.2] iowrA# iordA# weA# oeA# waitA# ceA#[1.2] iowrB# iordB# weB# oeB# waitB# ceB#[1.2] reset# clkin4 ex_int#[0.2] serint[1.2] SERIAL.SCH Shold adbusreq reg_rd# M2Sint# S2Mint# resetA resetB regA# regB# test_cs# pc_cs# ale w/r# ads# rdyrcv# be#[0.3] a[2.3] ad[0.31] sbe#[0.1] scs#[0.3] swr# srd# swait# sdata[0.15] saddr[0.1] sbe#[0.1] scs#[0.3] swr# srd# swait# sdata[0.15] saddr[0.1] B TEST_P.SCH Expantion ladd[2.5] reset Shold adbusreq reg_rd# M2Sint# S2Mint# resetA resetB regA# regB# test_cs# pc_cs# iordA# iordB# serint[1.2] dmaint#[0.2] M2Sint# ex_int#[0.2] clkin1 reset# ad[0.31] tck Stdi Stdo tms trst# d/c# width0 width1 rdata[0.31] sdata[0.7] scs#0 swr# srd# dmareq#[0.2] STAB.SCH cpu2 serint[1.2] dmaint#[0.2] M2Sint# ex_int#[0.2] clkin1 reset# ad[0.31] tck Stdi Stdo tms trst# d/c# width0 width1 ladd[0.31] Mholda Mhold Sholda Shold Serial sdata[0.7] scs#0 swr# srd# TESTING.SCH stab logic clkin2 reset# Mbstat Sbstat Sholda adbusgnt ads# sdmareq# ale bdadr[0.1] ad[0.31] bootcs# we#[0.3] bw/r#[1.2] bufoe# a2 be#[0.1] devcs#[0.1] DEV.SCH swait# ready# sdmareq# dmareq#[0.2] clkin2 reset# Mbstat Sbstat Sholda adbusgnt ads# sdmareq# pc_int# bdadr[0.10] bras#[0.3] bcas#[0.3] bdwr#[1.2] lwroe# lrdoe# le# clkin3 8 adbusreq adbusgnt dmareq#[0.2] dmaack#[0.2] serint[1.2] dmaint#[0.2] M2Sint# S2Mint# ex_int#[0.2] dadr[0.10] ras#[0.3] cas#[0.3] dwr# le# lrdoe# lwroe# clkin4 reset# sdmareq# reg_rd# test_cs# pc_cs# irqA# irqB# d/c# width0 width1 dmareq#0 dmaack#0 Dram BUFFERS.SCH master_cpu serint[1.2] dmaint#[0.2] S2Mint# ex_int#[0.2] clkin1 reset# ad[0.31] tck Mtdi Mtdo tms trst# d/c# width0 width1 pc_int# swait# ISA.SCH cas#[0.3] ras#[0.3] dadr[0.10] dwr# clock w/r# serint[1.2] dmaint#[0.2] S2Mint# ex_int#[0.2] clkin1 reset# ad[0.31] tck Mtdi Mtdo tms trst# d/c# width0 width1 pc_reset# swait# pc_cs# adbusreq adbusgnt dmareq#[0.2] dmaack#[0.2] serint[1.2] dmaint#[0.2] M2Sint# S2Mint# ex_int#[0.2] ale w/r# ads# rdyrcv# be#[0.3] a[2.3] ad[0.31] pc_reset# pc_cs# 7 Mholda Mhold Sholda Shold clkin2 ladd2 sdata[0.15] MISC.SCH buffers 6 test points clkin2 ladd2 sdata[0.15] pc_reset# pc_reset# A reset# reset clock dmareq#[0.2] dmaack#[0.2] dmareq#[0.2] dmaack#[0.2] 5 Isa_bus clkin1 reset# sbe#[0.1] scs#[0.3] swr# srd# swait# sdata[0.15] saddr[0.1] iowrA# iordA# weA# oeA# waitA# ceA#[1.2] iowrB# iordB# weB# oeB# waitB# ceB#[1.2] bootcs# devcs#[0.2] we#[0.3] ready# bufoe# sbe#[0.1] scs#[0.3] swr# srd# swait# sdata[0.15] saddr[0.1] iowrA# iordA# weA# oeA# waitA# ceA#[1.2] iowrB# iordB# weB# oeB# waitB# ceB#[1.2] bootcs# devcs#[0.2] we#[0.3] ready# bufoe# bootcs# devcs#[0.2] dadr[0.1] a[2.3] be#[0.3] ladd[0.31] we#[0.3] bw/r#2 rdata[0.31] ready# bootcs# devcs#[0.2] dadr[0.1] a[2.3] be#[0.3] ladd[0.31] we#[0.3] bw/r#2 rdata[0.31] ready# dmaack#[0.2] dmareq#[0.2] sdmareq# dmaack#[0.2] dmareq#[0.2] sdmareq# C EXP.SCH PCMCIA A & B MEMORIES sdata[0.15] ladd[2.25] saddr[0.1] sdata[0.15] ladd[2.25] saddr[0.1] regB# resetB ceB#[1.2] oeB# weB# iordB# iowrB# regB# resetB ceB#[1.2] oeB# weB# iordB# iowrB# regA# resetA ceA#[1.2] oeA# weA# iordA# iowrA# regA# resetA ceA#[1.2] oeA# weA# iordA# iowrA# wpA wpB reg_rd# wpA wpB reg_rd# irqB# waitB# irqB# waitB# irqA# waitA# irqA# waitA# D PCMCIA.SCH Galileo Technology Title GALILEO-5 BOARD Size B GT_CHIP.SCH Document Number Rev 1.2 cpu2.sch Date: 1 2 3 4 5 6 Thursday, November 23, 1995 7 Sheet 1 of 8 22 1 2 3 4 5 6 7 8 JS137 JS137 8bit be#0 16bit a2 32bit bdadr1 JS138 JS138 JS139 JS139 be#[0.1] 8+16bit IDT71256 IDT71256 32K*8bit memory size select a2 a2 A JS140 JS140 be#[0.1] bdadr[0.1] be#1 JS141 JS141 32bit A bdadr0 bdadr[0.1] JS142 JS142 8bit ladd2 JS143 JS143 ad[0.31] U25 ad[0.31] ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ale ale B 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 48 25 1 24 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 16+32bit ladd[0.31] 1O1 1O2 1O3 1O4 1O5 1O6 1O7 1O8 2O1 2O2 2O3 2O4 2O5 2O6 2O7 2O8 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 ladd0 ladd1 ladd2 ladd3 ladd4 ladd5 ladd6 ladd7 ladd8 ladd9 ladd10 ladd11 ladd12 ladd13 ladd14 ladd15 ladd15 jaddS[0.3] 8+16bit ladd3 JS145 JS145 32bit 8bit a2 32bit J21 1 J22 1 J23 1 be#0 16bit bdadr1 8+16bit 1LE 2LE 1OE 2OE J24 1 J25 1 J26 1 be#1 28256 32bit bdadr0 8bit ladd2 16+32bit U26 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 C ale 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 48 25 1 24 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 J27 1 J28 1 J29 1 ladd15 ladd[0.31] 1O1 1O2 1O3 1O4 1O5 1O6 1O7 1O8 2O1 2O2 2O3 2O4 2O5 2O6 2O7 2O8 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 ladd16 ladd17 ladd18 ladd19 ladd20 ladd21 ladd22 ladd23 ladd24 ladd25 ladd26 ladd27 ladd28 ladd29 ladd30 ladd31 8+16bit ladd16 8bit ladd15 16bit ladd16 32bit ladd17 28512 8bit J44 1 J45 1 J46 1 ladd17 32bit J35 1 J36 1 J37 1 ladd16 16bit 28010 J30 1 J31 1 J32 1 ladd3 32bit 1LE 2LE 1OE 2OE jaddS[0.3] ladd16 74FCT16373 74FCT16373 ad[0.31] jaddS0 jaddS1 jaddS2 jaddS3 JS144 JS144 ladd18 ladd[0.31] 2 ladd[0.31] 2 2 2 B 2 2 jaddF[0.7] 2 2 jaddF0 jaddF1 jaddF2 jaddF[0.7] 2 2 2 2 2 jaddF3 jaddF4 jaddF5 jaddF6 jaddF7 2 2 C 2 2 2 74FCT16373 74FCT16373 8bit ladd17 16bit ladd18 32bit J49 1 J50 1 J51 1 ladd19 28020 8bit ladd18 16bit ladd19 32bit J53 1 J54 1 J55 1 ladd20 28040 2 2 2 2 2 2 +12v D D Galileo Technology device pin 1 voltage select VCC 1 1 1 J64 2 J65 2 J66 2 Title ADDRESS LATCHES Size B Date: 1 2 3 4 5 6 Document Number Friday, May 31, 1996 7 Rev 1.2 Sheet 15 of 8 22 1 2 bootcs# bootcs# devcs#0 devcs#0 J13 1 J14 1 3 6 7 8 rcs# 2 U9 be#0 be#1 ladd2 ladd3 ladd4 ladd5 ladd6 ladd7 ladd8 ladd9 ladd10 ladd11 ladd12 ladd13 ladd14 ladd15 ladd16 ja0 ja1 ja2 ladd[2.19] ja[0.2] 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 31 1 rcs# A 5 2 be#[0.1] be#[0.1] ladd[2.19] 4 22 24 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17/VCC A17/VCC A18/PGM A18/PGM# A19/VPP A19/VPP rdata[0.7] O0 O1 O2 O3 O4 O5 O6 O7 13 14 15 17 18 19 20 21 rdata0 rdata1 rdata2 rdata3 rdata4 rdata5 rdata6 rdata7 rdata[0.7] A CE# OE#/VPP B B AT27CXXX AT27CXXX 27C256 27C256 to 27C080 27C080 27C010 27C010 to 27C080 27C080 27C256 27C256 to 27C512 27C512 27C040 27C040 to 27C080 27C080 27C256 27C256 to 27C020 27C020 ladd17 VCC ladd18 VCC J15 1 J16 1 J17 1 J18 1 2 2 2 2 ja[0.2] 27C080 27C080 ladd19 J19 1 J20 1 2 ja0 ja1 ja2 2 27C256 27C256 to 27C040 27C040 C C REMARK: any AT27CXXX AT27CXXX can be used (32 or 28 pin). when putting 28 bit rom in 32 bit socket, make sure rom pin1 faces socket pin3. D D Galileo Technology Title 8 BIT BOOT ROM Size B 1 2 3 4 5 6 Document Number Date: Friday, May 31, 1996 Rev 1.2 7 Sheet 13 of 8 22 1 2 3 4 5 6 7 8 U6 cas#[0.3] cas#[0.3] bcas#[0.3] cas#0 cas#1 cas#2 cas#3 dadr0 dadr1 dadr2 dadr3 dadr4 dadr5 dadr6 dadr7 dadr8 dadr9 dadr10 A dadr[0.10] dadr[0.10] 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 JS52 JS53 JS54 JS55 JS56 JS57 JS58 JS59 JS83 JS85 JS87 JS89 JS91 JS93 JS95 bcas#0 bcas#1 bcas#2 bcas#3 bdadr0 bdadr1 bdadr2 bdadr3 bdadr4 bdadr5 bdadr6 bdadr7 bdadr8 bdadr9 bdadr10 bcas#[0.3] bdadr[0.10] bdadr[0.10] A 4K7 JS21 JS22 JS23 JS24 JS84 JS86 JS88 JS90 JS92 JS94 JS96 bdadr0 bdadr1 bdadr2 bdadr3 bdadr4 bdadr5 bdadr6 bdadr7 bdadr8 bdadr9 bdadr10 JS25 JS26 JS27 JS28 bras#0 bras#1 bras#2 bras#3 dwr# JS29 JS30 bdwr#1 bdwr#2 clock JS97 JS98 JS99 JS100 JS100 clkin1 clkin2 clkin3 clkin4 w/r# 74FCT162244 74FCT162244 B bcas#0 bcas#1 bcas#2 bcas#3 dadr0 dadr1 dadr2 dadr3 dadr4 dadr5 dadr6 dadr7 dadr8 dadr9 dadr10 1OE~ 2OE~ 3OE~ 4OE~ JS17 JS18 JS19 JS20 ras#0 ras#1 ras#2 ras#3 1 48 25 24 R56 cas#0 cas#1 cas#2 cas#3 JS101 JS101 JS102 JS102 bw/r#1 bw/r#2 B U7 ras#[0.3] dwr# ras#[0.3] bras#[0.3] ras#0 ras#1 ras#2 ras#3 dwr# clock clock w/r# w/r# C R63 R62 R65 R64 R76 4K7 4K7 4K7 4K7 4K7 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1 48 25 24 1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4 JS60 JS61 JS62 JS63 JS64 JS65 JS103 JS103 JS104 JS104 JS105 JS105 JS106 JS106 JS107 JS107 JS108 JS108 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 bras#[0.3] bras#0 bras#1 bras#2 bras#3 bdwr#1 bdwr#2 clkin1 clkin2 clkin3 clkin4 bw/r#1 bw/r#2 bdwr#[1.2] bdwr#[1.2] clkin[1.4] clkin[1.4] bw/r#[1.2] bw/r#[1.2] C 1OE~ 2OE~ 3OE~ 4OE~ 74FCT162244 74FCT162244 Long pads on spare lines D D Galileo Technology Title DRAM CONTROL SIGNAL DRIVERS Size B 1 2 3 4 5 6 Document Number Date: Friday, May 31, 1996 Rev 1.2 7 Sheet 6 of 8 22 1 2 3 4 U3 ladd[4.14] ladd[4.14] 1 A jaddF[0.7] jaddF[0.7] we#[0.3] we#[0.3] bw/r#1 bw/r#1 jaddF1 jaddF0 ladd4 ladd5 ladd6 ladd7 ladd8 ladd9 ladd10 ladd11 ladd12 ladd13 ladd14 jaddF2 jaddF3 jaddF4 jaddF5 jaddF6 jaddF7 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VPP/N.C/A18 C/A18 5 6 U15 rdata[0.31] DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WE# OE# CE# 13 14 15 17 18 19 20 21 rdata0 rdata1 rdata2 rdata3 rdata4 rdata5 rdata6 rdata7 31 24 22 we#0 bw/r#1 cs# ladd[4.14] 1 J68 1 J69 1 2 bootcs# jaddF[0.7] 2 devcs#0 jaddF1 jaddF0 ladd4 ladd5 ladd6 ladd7 ladd8 ladd9 ladd10 ladd11 ladd12 ladd13 ladd14 jaddF2 jaddF3 jaddF4 jaddF5 jaddF6 jaddF7 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 1 FLASH32PLCC FLASH32PLCC 1 B jaddF[0.7] jaddF1 jaddF0 ladd4 ladd5 ladd6 ladd7 ladd8 ladd9 ladd10 ladd11 ladd12 ladd13 ladd14 jaddF2 jaddF3 jaddF4 jaddF5 jaddF6 jaddF7 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VPP/N.C/A18 C/A18 bootcs# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WE# OE# CE# 13 14 15 17 18 19 20 21 rdata16 rdata17 rdata18 rdata19 rdata20 rdata21 rdata22 rdata23 31 24 22 13 14 15 17 18 19 20 21 rdata24 rdata25 rdata26 rdata27 rdata28 rdata29 rdata30 rdata31 31 24 22 rdata[0.31] we#2 bw/r#1 cs# we#3 bw/r#1 cs# A U20 rdata[0.31] DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WE# OE# CE# 13 14 15 17 18 19 20 21 31 24 22 rdata8 rdata9 rdata10 rdata11 rdata12 rdata13 rdata14 rdata15 ladd[4.14] 1 J61 1 J62 1 2 we#3 16bit 2 we#1 32bit bw/r#1 cs# jaddF[0.7] FLASH32PLCC FLASH32PLCC jaddF1 jaddF0 ladd4 ladd5 ladd6 ladd7 ladd8 ladd9 ladd10 ladd11 ladd12 ladd13 ladd14 jaddF2 jaddF3 jaddF4 jaddF5 jaddF6 jaddF7 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 1 rdata[0.31] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VPP/N.C/A18 C/A18 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 WE# OE# CE# B FLASH32PLCC FLASH32PLCC bootcs# devcs#0 rdata[0.31] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 VPP/N.C/A18 C/A18 8 FLASH32PLCC FLASH32PLCC U11 ladd[4.14] 7 devcs#0 C C D D Galileo Technology Title 32 PIN FLASH SOCKETS Size B Date: 1 2 3 4 5 6 Document Number Rev 1.2 Friday, May 31, 1996 7 Sheet 12 of 8 22 1 2 3 4 5 6 7 8 A A B B 72 pin simm socket dram latches bcas#[0.3] bcas#[0.3] bcas#[0.3] bras#[0.3] bras#[0.3] bras#[0.3] lwroe# lwroe# bdwr#[1.2] bdwr#[1.2] bdwr#[1.2] lrdoe# lrdoe# bdadr[0.10] bdadr[0.10] le# le# bdadr[0.10] dd[0.31] dd[0.31] dd[0.31] clkin3 SIMM72 SIMM72.SCH ad[0.31] ad[0.31] ad[0.31] clkin3 LATCH.SCH lwroe# lrdoe# le# clkin3 lwroe# lrdoe# le# clkin3 C C D D Galileo Technology Title BUFFERS,DRAM'S & LATCHES Size B Date: 1 2 3 4 5 6 Document Number Friday, May 31, 1996 7 Rev 1.2 Sheet 7 of 8 22 1 2 3 4 5 6 7 8 A A P1 VCC reset# clkin4 reset# clkin4 B sbe#[0.1] scs#[0.3] swr# srd# sdata[0.15] saddr[0.1] bootcs# devcs#[0.2] dadr[0.1] a[2.3] be#[0.3] ladd[0.31] we#[0.3] bw/r#2 rdata[0.31] dmaack#[0.2] reset# clkin4 sbe#0 sbe#1 scs#0 scs#1 scs#2 scs#3 swr# srd# swait# saddr0 saddr1 sdata0 sdata1 sdata2 sdata3 sdata4 sdata5 sdata6 sdata7 sdata8 sdata9 sdata10 sdata11 sdata12 sdata13 sdata14 sdata15 sbe#[0.1] scs#[0.3] swr# srd# swait# sdata[0.15] saddr[0.1] ex_int#[0.2] bootcs# devcs#[0.2] dadr[0.1] a[2.3] be#[0.3] ladd[0.31] we#[0.3] bw/r#2 rdata[0.31] ready# dmaack#[0.2] dmareq#[0.2] sdmareq# C ex_int#0 ex_int#1 ex_int#2 VCC A1 B1 C1 A2 B2 C2 A3 B3 C3 A4 B4 C4 A5 B5 C5 A6 B6 C6 A7 B7 C7 A8 B8 C8 A9 B9 C9 A10 B10 C10 A11 B11 C11 A12 B12 C12 A13 B13 C13 A14 B14 C14 A15 B15 C15 A16 B16 C16 A1 B1 C1 A2 B2 C2 A3 B3 C3 A4 B4 C4 A5 B5 C5 A6 B6 C6 A7 B7 C7 A8 B8 C8 A9 B9 C9 A10 B10 C10 A11 B11 C11 A12 B12 C12 A13 B13 C13 A14 B14 C14 A15 B15 C15 A16 B16 C16 P2 A17 B17 C17 A18 B18 C18 A19 B19 C19 A20 B20 C20 A21 B21 C21 A22 B22 C22 A23 B23 C23 A24 B24 C24 A25 B25 C25 A26 B26 C26 A27 B27 C27 A28 B28 C28 A29 B29 C29 A30 B30 C30 A31 B31 C31 A32 B32 C32 A17 B17 C17 A18 B18 C18 A19 B19 C19 A20 B20 C20 A21 B21 C21 A22 B22 C22 A23 B23 C23 A24 B24 C24 A25 B25 C25 A26 B26 C26 A27 B27 C27 A28 B28 C28 A29 B29 C29 A30 B30 C30 A31 B31 C31 A32 B32 C32 VCC dmaack#0 dmaack#1 dmaack#2 dmareq#0 dmareq#1 dmareq#2 sdmareq# reset# clkin4 VCC reset# clkin4 ready# ladd0 ladd1 ladd2 ladd3 ladd4 ladd5 ladd6 ladd7 ladd8 ladd9 ladd10 ladd11 ladd12 ladd13 ladd14 ladd15 ladd16 ladd17 ladd18 ladd19 ladd20 ladd21 ladd22 ladd23 ladd24 ladd25 ladd26 ladd27 ladd28 ladd29 ladd30 ladd31 a2 a3 be#0 be#1 be#2 be#3 bootcs# A1 B1 C1 A2 B2 C2 A3 B3 C3 A4 B4 C4 A5 B5 C5 A6 B6 C6 A7 B7 C7 A8 B8 C8 A9 B9 C9 A10 B10 C10 A11 B11 C11 A12 B12 C12 A13 B13 C13 A14 B14 C14 A15 B15 C15 A16 B16 C16 DIN96 DIN96 A1 B1 C1 A2 B2 C2 A3 B3 C3 A4 B4 C4 A5 B5 C5 A6 B6 C6 A7 B7 C7 A8 B8 C8 A9 B9 C9 A10 B10 C10 A11 B11 C11 A12 B12 C12 A13 B13 C13 A14 B14 C14 A15 B15 C15 A16 B16 C16 A17 B17 C17 A18 B18 C18 A19 B19 C19 A20 B20 C20 A21 B21 C21 A22 B22 C22 A23 B23 C23 A24 B24 C24 A25 B25 C25 A26 B26 C26 A27 B27 C27 A28 B28 C28 A29 B29 C29 A30 B30 C30 A31 B31 C31 A32 B32 C32 A17 B17 C17 A18 B18 C18 A19 B19 C19 A20 B20 C20 A21 B21 C21 A22 B22 C22 A23 B23 C23 A24 B24 C24 A25 B25 C25 A26 B26 C26 A27 B27 C27 A28 B28 C28 A29 B29 C29 A30 B30 C30 A31 B31 C31 A32 B32 C32 VCC devcs#0 devcs#1 devcs#2 we#0 we#1 we#2 we#3 bw/r#2 swait# ex_int#[0.2] ready# ready# dmareq#[0.2] dmareq#[0.2] sdmareq# rdata0 rdata1 rdata2 rdata3 rdata4 rdata5 rdata6 rdata7 rdata8 rdata9 rdata10 rdata11 rdata12 rdata13 rdata14 rdata15 rdata16 rdata17 rdata18 rdata19 rdata20 rdata21 rdata22 rdata23 rdata24 rdata25 rdata26 rdata27 rdata28 rdata29 rdata30 rdata31 dadr0 dadr1 swait# ex_int#[0.2] sdmareq# B C DIN96 DIN96 D D Galileo Technology Title Expansion Connectors Size B Date: 1 2 3 4 5 6 Document Number Tuesday, May 28, 1996 7 Rev 1.2 Sheet 21 of 22 8 1 3 4 5 6 7 8 bufoe# bufoe# devcs#[0.1] devcs#[0.1] A 2 A bootcs# bootcs# ladd[0.31] rdata[0.31] bw/r#[1.2] we#[0.3] ladd[0.31] rdata[0.31] bw/r#[1.2] we#[0.3] Device latch 8/16/32 bit flash transceiver ale ale ad[0.31] ad[0.31] devcs#0 ale rdata[0.31] ad[0.31] bdadr[0.1] a2 a2 be#[0.1] be#[0.1] rdata[0.31] bootcs# bdadr[0.1] a2 bdadr[0.1] devcs#0 bw/r#1 rdata[0.31] bufoe# bw/r#1 bw/r#1 ad[0.31] ad[0.31] bufoe# bw/r#1 we#[0.3] be#[0.1] ladd[0.31] ladd[0.31] jaddF[0.7] jaddF[0.7] jaddS[0.3] B ladd[4.14] ladd[4.14] jaddS[0.3] jaddF[0.7] B TRANS.SCH FLA.SCH ADLATCH.SCH 8 bit boot rom bootcs# bootcs# devcs#0 ladd[2.19] rdata[0.7] devcs#0 ladd[2.19] be#[0.1] rdata[0.7] be#[0.1] BOOT.SCH 8/16/32 bit sram C C devcs#1 devcs#1 bw/r#2 bw/r#2 we#[0.3] we#[0.3] ladd[4.14] ladd[4.14] jaddS[0.3] rdata[0.31] rdata[0.31] jaddS[0.3] SRAM.SCH D D Galileo Technology Title ADDRESS LATCH, MEMORIES & TRANSCEIVER Size B Date: 1 2 3 4 5 6 Document Number Rev 1.2 Friday, May 31, 1996 7 Sheet 9 of 8 22 1 2 3 4 5 6 7 8 VCC R99 dadr[0.10] ras#[0.3] cas#[0.3] dwr# le# lrdoe# lwroe# 4K7 reset# clkin1 reset# clkin1 81 80 79 82 91 90 89 88 ADBusReq ADBusGnt DMAReq[0] DMAReq[1] DMAReq[2] w/r# ale w/r# 75 77 ads# ads# 78 Mholda Mholda Mhold 76 29 rdyrcv# 30 DMAInt[0]# DMAInt[1]# DMAInt[2]# SBE[0]# SBE[1]# P/SAddr[0] P/SAddr[1] ALE SRd# SWr# W/R# we#0 we#1 we#2 we#3 113 112 110 109 bufoe# devcs#[0.2] 114 117 116 115 108 C we#[0.3] ready# ready# 107 SWait# HoldA Hold IOWrA# IORdA# RdyRcv# BootCS# DevCS[0]# DevCS[1]# DevCS[2]# WaitA# CardEnA[1]# CardEnA[2]# WrEn[0]# WrEn[1]# WrEn[2]# WrEn[3]# IOWrB# IORdB# GT32090 GT32090 WrEnB# OEB# BufOE# WaitB# Ready# CardEnB[1]# CardEnB[2]# JTDO JTRst# JTMS JTClk JTDI Test# HiZAll# AD[0] AD[1] AD[2] AD[3] AD[4] AD[5] AD[6] AD[7] AD[8] AD[9] AD[10] AD[11] AD[12] AD[13] AD[14] AD[15] AD[16] AD[17] AD[18] AD[19] AD[20] AD[21] AD[22] AD[23] AD[24] AD[25] AD[26] AD[27] AD[28] AD[29] AD[30] AD[31] BE[0]# BE[1]# be[2]# BE[3]# R123 adbusreq adbusgnt 124 123 122 dmareq#0 dmareq#1 dmareq#2 129 128 127 dmaack#0 dmaack#1 dmaack#2 27 28 26 dmaint#0 dmaint#1 dmaint#2 131 130 sbe#0 sbe#1 adbusgnt dmareq#[0.2] dmaack#[0.2] dmaack#[0.2] dmaint#[0.2] dmaint#[0.2] sbe#[0.1] scs#[0.3] scs#[0.3] B 121 120 119 118 scs#0 scs#1 scs#2 scs#3 132 133 srd# swr# 134 swait# 138 139 iowrA# iordA# iowrA# iordA# 140 141 weA# oeA# weA# oeA# 144 waitA# 143 142 ceA#1 ceA#2 145 146 iowrB# iordB# iowrB# iordB# 147 150 weB# oeB# weB# oeB# 153 waitB# 152 151 ceB#1 ceB#2 saddr0 saddr1 saddr0 saddr1 srd# swr# ceA#[1.2] ceA#[1.2] C ceB#[1.2] ceB#[1.2] we#[0.3] bufoe# 160 157 158 156 159 20 19 31 32 35 36 37 38 39 40 41 42 43 44 46 47 48 49 50 51 52 53 54 55 58 59 60 61 64 65 66 67 68 69 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 be#0 be#1 be#2 be#3 bootcs# devcs#[0.2] be#[0.3] ad[0.31] rdyrcv# bootcs# devcs#[0.2] bufoe# 74 73 72 71 D Mhold we#[0.3] be#[0.3] Mhold rdyrcv# 4K7 waitA# waitB# waitA# waitB# ad[0.31] VCC R128 R127 Gtdo 4K7 4K7 Title GT32090 GT32090 Size B Date: 1 2 D Gtdo Galileo Technology Gtdi tck tms trst# Gtdi tck tms trst# A ADS# WrEnA# OEA# bootcs# devcs#0 devcs#1 devcs#2 23 22 sbe#[0.1] DMAAck[0]# DMAAck[1]# DMAAck[2]# SCS[0]# SCS[1]# SCS[2]# SCS[3]# ale dadr[0.10] ras#[0.3] cas#[0.3] dwr# le# lrdoe# lwroe# U12 LWrOE# LRdOE# LE# DWr# CAS[0]# CAS[1]# CAS[2]# CAS[3]# RAS[0]# RAS[1]# RAS[2]# RAS[3]# 154 155 87 86 85 83 saddr0 saddr1 B DAdr[0] DAdr[1] DAdr[2] DAdr[3] DAdr[4] DAdr[5] DAdr[6] DAdr[7] DAdr[8] DAdr[9] DAdr[10] sdata0 sdata1 sdata2 sdata3 sdata4 sdata5 sdata6 sdata7 sdata8 sdata9 sdata10 sdata11 sdata12 sdata13 sdata14 sdata15 P/SData[0] P/SData[1] P/SData[2] P/SData[3] P/SData[4] P/SData[5] P/SData[6] P/SData[7] P/SData[8] P/SData[9] P/SData[10] P/SData[11] P/SData[12] P/SData[13] P/SData[14] P/SData[15] 92 93 94 95 98 99 100 103 104 105 106 1 2 3 4 5 6 7 8 11 12 13 14 15 16 17 18 sdata0 sdata1 sdata2 sdata3 sdata4 sdata5 sdata6 sdata7 sdata8 sdata9 sdata10 sdata11 sdata12 sdata13 sdata14 sdata15 Rst# 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 CLK R98 R97 R96 R95 R94 R93 R118 R117 R122 R121 R120 R119 R116 R131 R130 R129 21 136 sdata[0.15] VCC cas#0 cas#1 cas#2 cas#3 ras#0 ras#1 ras#2 ras#3 adbusreq adbusreq A dadr0 dadr1 dadr2 dadr3 dadr4 dadr5 dadr6 dadr7 dadr8 dadr9 dadr10 swait# dmareq#[0.2] swait# dmareq#[0.2] 3 4 5 6 Document Number Rev 1.2 Thursday, November 23, 1995 7 Sheet 4 of 8 22 A B C D VCC +12v isaIOW# isaIORD# 3 VCC A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 isaSD7 isaSD6 isaSD5 isaSD4 isaSD3 isaSD2 isaSD1 isaSD0 2 5 6 9 12 15 16 19 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 3 4 7 8 13 14 17 18 1 11 isaOE# gtWE 3 Long pads on spare lines VCC 4K7 4K7 R149 R150 4 5 6 7 8 9 11 12 13 14 16 17 18 19 20 21 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN/OE2# IN/OE1# IN/GCLR# IN/GCLK isaSD0 isaSD1 isaAEN isaSA2 isaSA3 isaSA4 isaSA5 isaSA6 isaSA7 isaSA8 isaSA9 isaSA[2.9] 24 25 26 27 28 29 31 32 33 34 36 37 38 39 40 41 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O isaOE# isaWE gtOE# gtWE sdata0 sdata1 swait# dmareq#0 pc_int# dmaack#0 swr# srd# pc_cs# ladd2 swait# dmareq#0 pc_int# 2 2 J59 J58 U21 EPM7032 EPM7032 pc_reset# pc_reset# 1 1 CON AT36 dmaack#0 swr# srd# pc_cs# ladd2 clkin2 4 isaRESET clkin2 isaIORD# isaIOWR# C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 sdata[0.15] sdata0 sdata1 sdata2 sdata3 sdata4 sdata5 sdata6 sdata7 74LS373 74LS373 2 VCC 2 5 6 9 12 15 16 19 OC G OC G isaSA9 isaSA8 isaSA7 isaSA6 isaSA5 isaSA4 isaSA3 isaSA2 P4 2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 74LS373 74LS373 U22 isaAEN CON AT62 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 1 11 gtOE# isaWE D0 D1 D2 D3 D4 D5 D6 D7 2 44 1 43 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 3 4 7 8 13 14 17 18 isaSD0 isaSD1 isaSD2 isaSD3 isaSD4 isaSD5 isaSD6 isaSD7 P3 4 sdata[0.15] U23 isaSD[0.7] isaRESET E dmaack#0 swr# srd# pc_cs# ladd2 clkin2 1 1 Galileo Technology Title Connection To P.C. ISA Port Size Document Number Date: Friday, May 31, 1996 A B C D Rev 1.2 Sheet 19 of E 22 1 2 3 5 6 7 8 lwroe# lrdoe# le# clkin3 lwroe# lrdoe# le# clkin3 A U4 1 2 3 lrdoe# le# dd[0.31] dd[0.31] dd0 dd1 dd2 dd3 dd4 dd5 dd6 dd7 disable latch JS42 26 27 28 JS43 enable latch 15 16 17 19 20 21 23 24 ce# le# lrdoe# R39 2K2 5 6 8 9 10 12 13 14 dd8 dd9 dd10 dd11 dd12 dd13 dd14 dd15 VCC B 4 OEBA1# LEBA1# CEBA1# A11 A12 A13 A14 A15 A16 A17 A18 B11 B12 B13 B14 B15 B16 B17 B18 A21 A22 A23 A24 A25 A26 A27 A28 B21 B22 B23 B24 B25 B26 B27 B28 CEAB2# LEAB2# OEAB2# CEBA2# LEBA2# OEBA2# 56 55 54 lwroe# clkin3 1 2 3 52 51 49 48 47 45 44 43 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 dd16 dd17 dd18 dd19 dd20 dd21 dd22 dd23 5 6 8 9 10 12 13 14 42 41 40 38 37 36 34 33 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 dd24 dd25 dd26 dd27 dd28 dd29 dd30 dd31 15 16 17 19 20 21 23 24 31 30 29 ce# clkin3 lwroe# ce# le# lrdoe# 26 27 28 lrdoe# le# ad[0.31] dd[0.31] 74FCT16543 74FCT16543 ad[0.31] C OEAB1# LEAB1# CEAB1# 56 55 54 A11 A12 A13 A14 A15 A16 A17 A18 42 41 40 38 37 36 34 33 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 31 30 29 B21 B22 B23 B24 B25 B26 B27 B28 CEAB2# LEAB2# OEAB2# ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ce# clkin3 lwroe# ad[0.31] B11 B12 B13 B14 B15 B16 B17 B18 A21 A22 A23 A24 A25 A26 A27 A28 lwroe# clkin3 52 51 49 48 47 45 44 43 OEBA1# LEBA1# CEBA1# CEBA2# LEBA2# OEBA2# ad[0.31] B 74FCT16543 74FCT16543 dd[0.31] dd0 dd1 dd2 dd3 dd4 dd5 dd6 dd7 dd8 dd9 dd10 dd11 dd12 dd13 dd14 dd15 A U5 OEAB1# LEAB1# CEAB1# JS33 JS34 JS35 JS36 JS37 JS38 JS39 JS40 JS41 JS76 JS77 JS78 JS79 JS80 JS81 JS82 dd[0.31] ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad[0.31] dd16 dd17 dd18 dd19 dd20 dd21 dd22 dd23 dd24 dd25 dd26 dd27 dd28 dd29 dd30 dd31 JS9 JS10 JS11 JS12 JS13 JS14 JS15 JS16 JS44 JS45 JS46 JS47 JS48 JS49 JS50 JS51 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 C D D Galileo Technology Title DRAM LATCHES Size B Date: 1 2 3 4 5 6 Document Number Rev 1.2 Friday, May 31, 1996 7 Sheet 10 of 8 22 1 2 3 A 4 5 6 7 8 A J48 irqA# irqB# serint[1.2] irqA# irqB# serint[1.2] dmaint#[0.2] dmaint#[0.2] ex_int#[0.2] ex_int#2 irqA# irqB# serint1 serint2 dmaint#0 dmaint#1 dmaint#2 ex_int#0 ex_int#1 pc_int# S2Mint# ex_int#[0.2] pc_int# S2Mint# 1 3 5 7 9 11 13 15 17 19 21 23 VCC 2 4 6 8 10 12 14 16 18 20 22 24 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 4K7 MintN# Mint0# Mint1# Mint2# Mint3# Mint4# Mint5# Mint6# Mint7# Mtdo A10 C11 BSTAT RESET# HOLDA HOLD STEST LOCK#/ONCE# FAIL# RDYRCV# BLAST# R142 100 H12 C76 Mhold rdyrcv# C VCCPLL DEN# C75 4U7 .01U DT/R# W/R# Mhold D/C# WIDTH0 WIDTH1 rdyrcv# tck Mtdi tck Mtdi B13 D12 Mtdo tms tms trst# trst# B4 A14 C12 Mfail# R151 4K7 CLKIN VCC Mtdo Mfail# VCC U17 NMI# XINT0# XINT1# C6 XINT2# Mfail# C10 C13 XINT3# Mstest A13 4K7 XINT4# R141 B12 VCC JS127 JS127 JS128 JS128 XINT5# E12 B11 H14 reset# XINT6# clkin1 A12 XINT7# clkin1 reset# B B10 A11 HEADER 12X2 R140 R139 R143 R146 R144 R145 R153 R154 R152 BE0# BE1# BE2# BE3# TCK TDI A2 A3 TDO ADS# TMS ALE# ALE TRST# F3 Mbstat Mbstat C2 C9 Mholda Mhold Mholda B C1 F12 rdyrcv# C3 blast# blast# E3 den# den# D3 dt/r# dt/r# B1 w/r# w/r# B2 d/c# d/c# B3 A2 width0 width1 H3 J3 L1 L2 be#0 be#1 be#2 be#3 width0 width1 be#[0.3] C5 C4 a2 a3 A1 ads# ads# A3 G3 ale ale C a[2.3] AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 M14 L13 K12 N14 M13 L12 P14 N13 M12 M11 N12 P13 M10 P12 M9 M8 M7 M6 P4 P3 N4 M5 P2 M4 N3 P1 N2 N1 L3 M2 M1 K3 I960JX I960JX 132pin PGA ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 ad[0.31] D D Galileo Technology Title INTEL 960JX 960JX Master PROCESSOR Size B 1 2 3 4 5 6 Document Number Date: Friday, May 31, 1996 Rev 1.2 7 Sheet 2 of 8 22 1 2 3 4 5 6 7 8 Power On Configuration Reset Generator VCC VCC VCC U24 4 pb# J67 S1 A 1 1 PFI PFO PB RESET RESET R100 8 7 reset reset# reset reset# R101 R102 R103 R104 R105 4K7 5 4K7 4K7 4K7 4K7 4K7 dmareq#[0.2] 2 3 pc_reset# J38 J39 J40 J41 J42 dmareq#[0.2] dmaack#[0.2] dmareq#0 dmareq#1 dmareq#2 dmaack#0 dmaack#1 dmaack#2 R148 100K MAX708 MAX708 dmaack#[0.2] J43 1 VCC 1 1 1 1 For all jumpers: 2 2 2 2 2 Jumper on pins 1,2 means "1" Jumper on pins 3,2 means "0" 3 +12v 1 2 Power connector A 3 3 3 3 3 Device Base Address bits [31.25]: [J40.J38], 1, 1, 1, 1 Internal Registars Address bits [31.26]: [J43.J41], 0, 1, 1 R132 R133 R134 R135 R136 R137 4K7 4K7 4K7 4K7 4K7 4K7 +12v +5v R1 330 P5 4 3 2 1 B JTAG C6 + 47uf CON4 C5 + 47uf D1 B Stdo Mtdo Gtdo 1 1 Clock Source 1 P6 OSC1 OUT 5 4 3 2 1 8 OSC JS32 clock P7 C clock 1 tdo tdi tck tms trst# 1 1 J1 2 J2 2 J3 2 J5 2 J6 2 J7 2 tdoStdi Stdi R40 R125 R41 R26 R25 JS31 2 1 Gtdo->Mtdi 1 Gtdo->Stdi 1 Mtdo->Stdi 1 CON2 Clock JS32 On Off J8 2 J9 2 J10 2 4K7 4K7 4K7 4K7 4K7 C tck tms trst# JS31 Int Ext Stdi VCC CON5 Off On tck tms trst# R27 4K7 D D Galileo Technology Title Reset, Clock, Power & JTAG Size B 1 2 3 4 5 6 Document Number Date: Tuesday, May 28, 1996 7 Rev 1.2 Sheet 5 of 8 22 1 2 3 4 5 6 VCC VCC 7 +12v 8 VCC +12v VCC JS3 JS1 vppA1 ceA#[1.2] ceA#[1.2] ceA#1 ceA#2 A sdata[0.15] oeA# weA# vppA1 ladd16 ladd15 ladd12 ladd7 ladd6 ladd5 ladd4 ladd3 ladd2 saddr1 saddr0 sdata0 sdata1 sdata2 wpA B saddr[0.1] sdata3 sdata4 sdata5 sdata6 sdata7 ceA#1 ladd10 oeA# ladd11 ladd9 ladd8 ladd13 ladd14 weA# irqA# saddr[0.1] cdA#1 sdata11 sdata12 sdata13 sdata14 sdata15 ceA#2 iordA# iowrA# ladd17 ladd18 ladd19 ladd20 ladd21 iordA# iowrA# C vppA2 ladd22 ladd23 ladd24 ladd25 resetA waitA# resetA inpack# regA# bvdA2 bvdA1 sdata8 sdata9 sdata10 cdA#2 regA# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 +12v JS2 VCC +12v VCC A P9 sdata[0.15] sdata3 sdata4 sdata5 sdata6 sdata7 ceB#1 ladd10 oeB# ladd11 ladd9 ladd8 ladd13 ladd14 weB# irqB# oeB# weB# vppB1 ladd16 ladd15 ladd12 ladd7 ladd6 ladd5 ladd4 ladd3 ladd2 saddr1 saddr0 sdata0 sdata1 sdata2 wpB cdB#1 sdata11 sdata12 sdata13 sdata14 sdata15 ceB#2 iordB# iowrB# ladd17 ladd18 ladd19 ladd20 ladd21 iordB# iowrB# vppB2 ladd22 ladd