MN3610H WDIP022-G-0470 2048D - Datasheet Archive
MN3610H 2048-Bit High-Responsivity CCD Linear Image Sensor s Pin Assignments M Di ain sc te on na tin nc ue e/ d s Overview The
CCD Linear Image Sensor MN3610H MN3610H 2048-Bit High-Responsivity CCD Linear Image Sensor s Pin Assignments M Di ain sc te on na tin nc ue e/ d s Overview The MN3610H MN3610H is a 2048-pixel high sensitivity CCD linear image sensor combining photo-sites using low dark output floating photodiodes and CCD analog shift registers for read out. It provides large output at a high S/N ratio for visible light inputs over a wide range of wavelength. nt in ue Pl pl d in ea an c se ed lud pl vi an m m es si tf ed ain ai fo ol t n l ht low disc dis ena ten low tp in o co n an in :// g nt n ce c g pa U in tin t e fo na RL ue ue ype typ ur so a d t d e Pr od ty ni bo yp p c. u e e uc ne t l d tl ife t/s ate cy c/ st en in cl e fo st rm ag at e. io n. s Features 1 OS DS VDD øR ø1B ø1A NC NC NC NC NC · 2048 floating photodiodes and n-channel buried type CCD shift registers for read out are integrated in a single chip. · Use of photodiodes with a new structure has made the dark output voltage very low. · All the input pulses can be driven by CMOS 5V-type logics. · Has a smooth spectral characteristics that is close to the sensitivity of the human eye in the entire visible region. 1 2 3 4 5 6 7 8 9 10 11 · Large signal output of typically 2000mV at saturation can be obtained. · Since a compensation output pin (DS) is provided in addition to the signal output pin (OS), it is possible to obtain a signal with a high S/N ratio by carrying out differential amplification of the OS and DS outputs. · Operation with a single +12V positive power supply. 22 21 20 19 18 17 16 15 14 13 12 VSS ø SG ø 2B ø 2A NC NC NC NC NC NC NC 2048 (Top View) C20 WDIP022-G-0470 WDIP022-G-0470 s Application · Graphic and character read out in fax machines, image scanners, etc. · Measurement of position and dimensions of objects. s Block Diagram ø SG ø 2B ø 2A 22 21 20 19 1 21 2 1 21 2 1 21 2045 2046 2047 2048 D4 D5 D6 D7 D8 1 2 1 21 21 21 2 1 B 51 B 52 D1 D2 D3 1 2 3 4 5 M ai nt en an 2 1 21 21 2 B1 B2 B3 ce /D is co VSS 12121 1 21 21 21 21 2 21 21 21 21 21 2 2 B1 to B52 : Black reference pixels D 1 2 3 4 OS DS VDD ø R D1 to D8 : Dummy invalid pixels 5 6 ø 1B ø 1A CCD Linear Image Sensor MN3610H MN3610H s Absolute Maximum Ratings (Ta=25°C, VSS=0V) Symbol Rating Unit Power supply voltage Input pin voltage Output pin voltage VDD V VO 0.3 to +15 0.3 to +15 0.3 to +15 Operating temperature range Topr 2 5 to + 60 °C Storage temperature range Tstg 40 to +100 °C Parameter VI V V s Operating Conditions · Voltage conditions (Ta=25 to +60°C, VSS=0V) Parameter Power supply voltage Symbol VDD Condition min typ max Unit 11.4 12.0 13.0 V CCD shift register clock High level Vø H 4.5 5.0 5.5 V CCD shift register clock Low level Vø L 0 0.2 0.5 Shift gate clock High level Shift gate clock Low level VSH 4.5 5.0 5.5 V V VSL 0 0.2 0.5 Reset gate clock High level VRH 4.5 5.0 5.5 V V Reset gate clock Low level VRL 0 0.2 0.5 V · Timing conditions (Ta=20 to +60°C) min typ max Unit fC f C =1/2T - 0.5 2.5 MHz Reset clock frequency fR See drive timing diagram. f R =1/T - 1.0 5.0 MHz Shift register clock rise time Shift regisster clock fall time t Cr 0 0 50 50 100 100 ns ns Parameter Shift register clock frequency Symbol Condition t Cf t Sr Shift clock rise time Shift clock fall time t Sf 0 0 50 50 100 100 ns ns Shift clock set up time t Ss 0 100 - ns Shift clock pulse width t Sw 200 1000 - ns Shift clock hold time t Sh 0 100 - ns Reset clock rise time t Rr 0 15 30 ns Reset clock fall time 0 15 30 ns Reset clock pulse width t Rf t Rw t Rh 250 125 - Reset clock hold time 40 100 - ns ns min typ max Unit - 450 500 pF s Electrical Characteristics · Clock input capacitance (Ta=25 to +60°C) Parameter Symbol Shift register clock input capacitance C1A ,C 2A Shift register final stage clock input capacitance C1B ,C2B VIN =12V - 15 20 pF CR f =1MHz - - 10 130 20 150 pF pF min typ max Unit - 6 12 mA min typ max Unit - 50 - ns Reset clock input capacitance Shift clock input capacitance Condition CS · DC characteristics Parameter Power supply current Symbol I DD Condition VDD =+12V · AC characteristics Parameter Signal output delay time Symbol t OS Condition CCD Linear Image Sensor MN3610H MN3610H s Optical Characteristics · Ta=25°C, VDD=12V, VøH=VSH=VRH=5V (pulse), fC=0.5MHz, fR=1MHz, Tint (accumulation time)=10ms · Light source: Daylight type fluorescent lamp · Optical system: A slit with an aperture dimensions of 20mm × 20mm is used at a distance of 200mm from the sensor (equivalent to F=10). · Load resistance = 100k Ohms · These specifications apply to the 2048 valid pixels excluding the dummy pixels D1 to D6. Parameter Symbol Condition Photo response non-uniformity Odd/even bit non-uniformity Saturation output voltage Saturation exposure min typ max Unit 10.0 R Responsivity 12.0 14.0 V/lx·s PRNU Note 1 - - 10 % O/E - 1.5 - 2.0 3 VSAT Note 2 Note 3 % V SE Note 3 0.10 0.17 - lx·s VDRK Dark condition, see Note 4 - 0.4 - 1.0 Dark signal output non-uniformity DSNU Dark condition, see Note 4 0.2 2.0 mV Shift register total transfer efficiency STTE - 92 - - % Output impedance ZO - - 1 k Dynamic range Signal output pin DC level DR - 5000 - VOS 3.5 4.5 6.0 V Compensation output pin DC level V DS 3.5 4.5 20 6.0 100 mV Dark signal output voltage Signal and compensation output pin DC level difference VOS VDS Note 5 Note 6 Note 6 Note 6 - mV V Note 1) The photo response non-uniformity (PRNU) is defined by the following equation, where Xave is the average output voltage of the 2048 valid pixels and x is the absolute value of the difference between Xave and the voltage of the maximum (or minimum) output pixel, when the surface of the photo-sites is illuminated with light having a uniform distribution over the entire surface. x ×100 (%) PRNU= Xave The incident light intensity shall be 50% of the standard saturation light intensity. Note 2) The odd/even bit non-uniformity (O/E) is defined by the following equation, where Xave is the average output voltage of the 2048 valid pixels and Xn is the output voltage of the `n'th pixel, when the surface of the photo-sites is illuminated with light having a uniform distribution over the entire surface. 2047 | XnXn+1 | n=1 ×100 (%) 2047×X ave In other words, this is the value obtained by dividing the average of the output difference between the odd and even pixels by the average output voltage of all the valid pixels. The incident light intensity shall be 50% of the standard saturation light intensity. Note 3) The Saturation output voltage (VSAT) is defined as the output voltage at the point when the linearity of the photoelectric characteristics cannot be maintained as the incident light intensity is increased. (The light intensity of exposure at this point is called the saturation exposure.) Note 4) The dark signal output voltage (VDRK) is defined as the average output voltage of the 2048 pixels in the dark condition at Ta=25°C and Tint=10ms. Normally, the dark output voltage doubles for every 8 to 10°C rise in Ta, and is proportional to Tint. The dark signal output non-uniformity (DSNU) is defined as the difference between the maximum output voltage among all the valid pixels and VDRK in the dark condition at Ta=25°C and Tint=10ms. O/E= VDRK DSNU Note 5) The dynamic range is defined by the following equation. VSAT VDRK Since the dark signal voltage is proportional to the accumulation time, the dynamic range becomes wider when the accumulation time is shorter. DR= CCD Linear Image Sensor MN3610H MN3610H Note 6) The signal output pin DC level (VOS) and the compensation output pin DC level (VDS) are the voltage values shown in the following figure. Reset feed through level OS DS VDS V OS VSS VSS s Pin Descriptions Pin No. Symbol 1 OS Signal output Pin name Condition 2 DS Compensation output 3 VDD Power supply 4 øR Reset clock 5 6 7 ø1B ø1A NC CCD Final stage clock (Phase 1) CCD Clock (Phase 1) Non connection 8 NC Non connection 9 NC Non connection 10 NC Non connection 11 NC Non connection 12 13 NC NC Non connection Non connection 14 NC Non connection 15 NC Non connection 16 NC Non connection 17 NC Non connection 18 19 20 NC ø2A Non connection CCD Clock (Phase 2) CCD Final stage clock (Phase 2) 21 ø2B øSG Shift gate clock 22 VSS Ground Note) Connect all NC pins externally to VSS. s Construction of the Image Sensor The MN3610H MN3610H can be made up of the three sections of-a) photo detector region, b) CCD transfer region (shift register), and c) output region. a) Photo detector region · The photoelectric conversion device consists of an 11µm floating photodiode and a 3µm channel stopper for each pixel, and 2048 of these devices are linearly arranged side by side at a pitch of 14µm. · The photo detector's windows are 14µm × 14µm squares and light incident on areas other than these windows is optically shut out. · The photo detector is provided with 52 optically shielded pixels (black dummy pixels) which serve as the black reference. b) CCD Transfer region (shift register) · The light output that has been photoelectrically converted is transferred to the CCD transfer for each odd and even pixel at the timing of the shift clock (øSG). The optical signal electric charge transferred to this analog shift register is successively transferred out and guided to the output region. · A buried type CCD that can be driven by a two phase clock (ø1, ø2) is used for the analog shift register. c) Output region · The signal charge that is transferred to the output region is sent to the detector where impedance transformation is done using two source follower stages. · The DC level component and the clock noise component not containing optical signals are output from the DS pin. · By carrying out differential amplification of the two outputs OS and DS externally, it is possible to obtain an output signal with a high S/N ratio by reducing the clock noise, etc. CCD Linear Image Sensor MN3610H MN3610H s Timing Diagram (1) I/O timing Integration Time (Tint.) ø SG ø1 ø2 øR 1 2 3 4 6 7 8 9 10 11 58 59 60 61 62 63 64 65 66 2110 2112 2114 2116 2111 2113 2115 DS OS 1 2 3 4 6 7 8 B1 B2 Blank feed (for 8 pixels) B50 B52 B51 Black reference pixel signal (for 52 pixels) D1 D2 D3 1 2 3 2047 2048D 2048D 4 D6 D7 D8 Valid pixel signal (for 2048 pixels) Invalid pixel signal (for 3 pixels) (2)Drive timing D5 Note) Repeat the transfer pulses (cp) for more than 1060 periods. Invalid pixel signal (for 5 pixels) 90% 50% 10% ø1 t Cr t Cf 90% 50% 10% ø2 t Rh t Sr t Sf 90% øR 90% t Rf DS 10% ø SG 10% tRr t RW T t OS 90% Reference level OS ø1 t Ss t SW Signal output voltage t Sh 90% s Graphs and Characteristics Spectral Response Characteristics Relative responsivity (%) 100 Under standard operating condition 80 60 40 20 0 400 500 600 700 Wavelength (nm) 800 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. 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