MN15G00 MN15G0202/0402 20302-010E MN1500 MN15G MN15G0202 MN15G0402 MN15GXX02 - Datasheet Archive

 

MN15G00 MN15G0202/0402 LSI User's Manual Pub.No.20302-010E PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd.

 

MICROCOMPUTER MN15G00 MN15G00 MN15G0202/0402 MN15G0202/0402 LSI User's Manual Pub.No.20302-010E 20302-010E PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names, logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations. Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the "Foreign Exchange and Foreign Trade Control Law" is to be exported or taken out of Japan. (2) The contents of this book are subject to change without notice in matters of improved function. When finalizing your design, therefore, ask for the most up-to-date version in advance in order to check for any changes. (3) We are not liable for any damage arising out of the use of the contents of this book, or for any infringement of patents or any other rights owned by a third party. (4) No part of this book may be reprinted or reproduced by any means without written permission from our company. (5) This book deals with standard specifications. Ask for the latest individual Product Standards or Specifications in advance for more detailed information required for your design, purchasing and applications. If you have any inquiries or questions about this book or our semiconductors, please contact one of our sales offices listed at the back of this book or Matsushita Electronics Corporation's Sales Department. About This Manual nOrganization In this LSI manual, this LSI functions are presented in the following order : overview, basic CPU functions, interrupt functions, port functions, timer functions, serial functions, and other peripheral hardware functions. Each section contains overview of function, block diagram, control register, operation, and setting example. nManual Configuration Each section of this manual consists of a title, summary, main text, key information, precautions and warnings, and references. The layout and definition of each section are shown below. Subtitle Sub-subtitle Chapter 2 Basic CPU 2-8 Reset 2-8-1 Reset operation The smallest block in this manual. Main text Summary Introduction to the The CPU contents are reset and registers are initialized when the NRST pin (P.27) is pulled to low. section. n Initiating a Reset There are two methods to initiate a reset. (1) Drive the NRST pin low for at least four clock cycles. NRST pin should be holded "low" for more than 4 clock cycles (200 nS at a 20 MHz). NRST pin 4 clock cycles (200 nS at a 20 MHz) Figure 2-8-1 (2) Minimum Reset Pulse Width Setting the P2OUT7 flag of the P2OUT register to "0" outputs low level at P27 (NRST) pin. And transfering to reset by program (software reset) can be executed. If the internal LSI is reset and register is initiated, the P2OUT7 flag becomes "1" and reset is released. Key information [ References Chapter 4. 4-4-2 Registers ] References for the main text. Important information from the text. On this LSI, the starting mode is NORMAL mode that high oscillation is the base clock. Precautions and When the power voltage low circuit is connected to NRST pin, circuit that gives pulse for enough low level time at sudeen unconnected. And reset can be generated even if its pulse is low level as the oscillation clock is under 4 clocks, take notice of noise. warnings Precautions are listed in case. Be sure to read these of lost functionality or damage. II - 44 About This Manual 1 Reset nFinding Desired Information This manual provides three methods for finding desired information quickly and easily. (1) Consult the index at the front of the manual to locate the beginning of each section. (2) Consult the table of contents at the front of the manual to locate desired titles. (3) Chapter names are located at the top outer corner of each page, and section titles are located at the bottom outer corner of each page. nRelated Manuals Note that the following related documents are available. "MN1500 MN1500 Series Instruction Manual" "MN1500 MN1500 Series Cross-assembler User's Manual" "MN1500 MN1500 Series Source Code Debugger User's Manual" "MN1500 MN1500 Series PanaX Series Installation Manual" nWhere to Send Inquires We welcome your questions, comments, and suggestions. Please contact the semiconductor design center closest to you. See the last page of this manual for a list of addresses and telephone numbers. About This Manual 2 About This Manual 3 Chapter 1 Overview 1 Chapter 2 Basic CPU 2 Chapter 3 Ports 3 Chapter 4 Interrupts 4 Chapter 5 Timers 5 Chapter 6 A/D Converter 6 Chapter 7 AC Zero-Cross Detection 7 Chapter 8 Watchdog Timer 8 Chapter 9 Automatic Reset 9 Chapter 10 Appendices 10 Contents Chapter 1 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 Overview . I - 2 1-1-1 Product Summary . I - 2 Hardware Functions . I - 3 Block Diagram . I - 5 1-3-1 Overview . I - 5 1-3-2 Block Diagram . I - 6 Pin Description . I - 7 1-4-1 Pin Configuration . I - 7 1-4-3 Pin Functions . I - 8 Special Function Registers . I - 11 1-5-1 Register Map . I - 11 1-5-2 Special Function Registers . I - 12 Electrical Characteristics . I - 13 1-6-1 Absolute Maximum Ratings . I - 13 1-6-2 Operating Conditions . I - 14 1-6-3 DC Characteristics . I - 19 1-6-4 A/D Converter Characteristics . I - 23 External Dimension . I - 24 Option . I - 22 1-8-1 Mask Option . I - 25 1-8-2 Mask Option Form . I - 26 Chapter 2 2-1 2-2 2-3 2-4 ii contents Overview Basic CPU Clock Generator . II - 2 2-1-1 Clock Generator . II - 2 2-1-2 CPU Basic Timing . II - 3 Register Set . II - 4 Memory Space . II - 8 2-3-1 ROM Address Space (2 KB) . II - 8 2-3-2 ROM Address Space (4 KB) . II - 10 2-3-3 RAM Address Space . II - 12 2-3-4 Stacked Area . II - 13 Clock Switching . II - 14 2-4-1 Clock Switching . II - 14 2-4-2 CPU Mode Reigster . II - 15 2-5 2-6 Back Up Mode . 2-5-1 Cautions on Back Up Mode . Reset . 2-6-1 Reset Operation . Chapter 3 3-1 3-2 3-3 4-2 5-2 Interrupts Overview . IV - 2 4-1-1 Functions . IV - 2 4-1-2 Block Diagram . IV - 3 4-1-3 Operation . IV - 4 4-1-4 Interrupt Flag Setup . IV - 13 Control Registers . IV - 15 4-2-1 Registers List . IV - 15 4-2-2 Interrupt Control Registers . IV - 16 Chapter 5 5-1 Ports Overview . III - 2 3-1-1 Port Diagram . III - 2 3-1-2 Port Functions . III - 3 3-1-3 Port Status at Reset . III - 4 3-1-4 Port Disposal at Unused . III - 5 3-1-5 Setup Example . III - 6 3-1-6 Control Registers . III - 7 Port 0, Port 1 . III - 8 3-2-1 Description . III - 8 3-2-2 Registers . III - 9 3-2-3 Block Diagram . III - 10 Port 2, Port 3 . III - 11 3-3-1 Description . III - 11 3-3-2 Registers . III - 13 3-3-3 Block Diagram . III - 15 Chapter 4 4-1 II - 16 II - 18 II - 19 II - 19 Timers 8-bit Timer . 5-1-1 Functions . 5-1-2 Block Diagram . 8-bit Timer Control Registers . iii V-2 V-3 V-4 V-8 contents 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-2-1 Registers . V - 8 5-2-2 Compare Registers . V - 9 5-2-3 Binary Counters . V - 10 5-2-4 Timer Control Registers . V - 11 8-Bit Timer Operation . V - 15 5-3-1 Operation . V - 15 5-3-2 Setup Example . V - 17 8-Bit Timer Pulse Output . V - 18 5-4-1 Operation . V - 18 5-4-2 Setup Example . V - 19 8-Bit PWM Output . V - 21 5-5-1 Operation . V - 21 5-5-2 Setup Example . V - 23 8-Bit Timer Cascade Connection . V - 25 5-6-1 Operation . V - 25 5-6-2 Setup Example . Remote Control Career Output . 5-7-1 Operation . 5-7-2 Setup Example . High Precision PWM Output . 5-8-1 Operation . 5-8-2 Setup Example . Buzzer Output . 5-9-1 Operation . 5-9-2 Setup Example . Chapter 6 6-1 6-2 6-3 iv contents V - 26 V - 28 V - 28 V - 29 V - 31 V - 31 V - 32 V - 34 V - 34 V - 35 A/D Converter Overview . VI - 2 6-1-1 Functions . VI - 2 6-1-2 Block Diagram . VI - 3 Control Registers . VI - 4 6-2-1 Registers . VI - 4 6-2-2 Control Registers . VI - 5 6-2-3 Data Buffers . VI - 6 Operation . VI - 7 6-3-1 Setup . VI - 9 6-3-2 Setup Example . VI - 11 6-3-3 Cautions . VI - 12 Chapter 7 7-1 AC Zero-Cross Detection Overview . VII - 2 7-1-1 7-1-2 Block Diagram . VII - 3 7-1-3 7-2 Overview . VII - 2 Operation . VII - 4 Control Registers . VII - 5 Chapter 8 8-1 Overview . VIII - 2 8-1-1 Overview . VIII - 2 8-1-2 8-2 Block Diagram . VIII - 3 Control Registers . VIII - 4 Chapter 9 9-1 Watchdog Timer Automatic Reset Overview . IX - 2 9-1-1 Overview . IX - 2 9-1-2 Electrical Characteristics . IX - 3 Chapter 10 Appendices 10-1 EPROM Version . X - 2 10-1-1 Overview . X - 1 10-1-2 Cautions on Use . X - 3 10-1-3 Erasing Data in Windowed Package . X - 4 10-1-4 Differences between Mask ROM version and EPROM version . X - 5 10-1-5 Writing to Microcomputer with Internal EPROM. X - 6 10-1-6 Cautions on Operation of ROM Writer . X - 7 10-2 Instruction Set . X - 8 10-3 Instruction Map . X - 10 10-4 Differences between MN1500 MN1500 and MN15G MN15G . X - 11 10-5 Special Function Registers List . X - 12 10-6 Circuit Setup . X - 14 10-6-1 General Usage . X - 14 10-6-2 Unused Pins . X - 15 10-6-3 Power Supply . X - 17 10-6-4 Power Supply Circuit . X - 18 v contents Chapter 1 Overview 1 Chapter 1 Overview 1-1 Overview This LSI is 4-bit single-chip microcomputer. The MN15G0202 MN15G0202 has an internal 2 KB of ROM and 128 nibble of RAM and the MN15G0402 MN15G0402 has an internal 4 KB of ROM and 128 nibble of RAM. Peripheral functions include 2 sets of 8-bit timer counters (They can be used as 16-bit counter on cascade connection.), 10-bit A/D converter, AC zero-cross detection circuit, buzzer output circuit and LED driver pins. 1-1-1 Product Summary This manual describes the following models of the MN15GXX02 MN15GXX02 series. These products have identical functions. Table 1-1-1 Product Summary Model ROM Size RAM Size Classification MN15G0202 MN15G0202 2 KB 128 nibble Mask ROM version MN15G0402 MN15G0402 4 KB 128 nibble Mask ROM version MN15GP0402 MN15GP0402 4 KB 128 nibble EPROM version Table 1-1-2 Differences in Models Parameter MN15G0202 MN15G0202 MN15G0402 MN15G0402 MN15GP0402 MN15GP0402 Power supply voltage 2.0 V to 5.5 V 2.0 V to 5.5 V 2.3 V to 5.5 V Ambient operating temperature -40 °C to +85 °C -40 °C to +85 °C -20 °C to +70 °C Oscillation circuit 1 : High oscillation 2 : Low oscillation 3 : RC oscillation 1 : High oscillation 2 : Low oscillation 3 : RC oscillation 1 : High oscillation 1 : unused 2 : Automatic reset 1 3 : Automatic reset 2 1 : unused 2 : Automatic reset 1 3 : Automatic reset 2 1 : unused Mask option Automatic reset circuit For mask option, refer to 1-7 Option. I-2 Overview Chapter 1 Overview 1-2 Hardware Functions Table 1-2-1 Model Basic Specification MN15G0202 MN15G0202 ROM version MN15G0402 MN15G0402 Mask ROM version MN15GP0402 MN15GP0402 EPROM version ROM 2 KB 4KB 4KB RAM 128 nibble 128 nibble 128 nibble Package 20SOP 20SOP Machine cycle When automatic reset is not used : 0.50 µs / 8 MHz divided by 4 1.00 µs/ 4 MHz divided by 4 2.00 µs/ 4 MHz divided by 8 122 µs / 32.768 kHz divided by 4 When automatic reset circuit 1 is used : 0.50 µs / 8 MHz divided by 4 1.00 µs/ 4 MHz divided by 4 2.00 µs/ 4 MHz divided by 8 122 µs / 32.768 kHz divided by 4 When automatic reset circuit 2 is used : 2.00 µs / 4 MHz divided by 8 122 µs / 32.768 kHz divided by 4 Back up mode (3.0 V to 5.5 V) (2.4 V to 5.5 V) (2.0 V to 5.5 V) (2.0 V to 5.5 V) (VRSTL1 to 5.5 V) (VRSTL1 to 5.5 V) (VRSTL1 to 5.5 V) (VRSTL1 to 5.5 V) (VRSTL2 to 5.5 V) (VRSTL2 to 5.5 V) HALT mode STOP mode Ambient operating temperature -40 °C to +85 °C (-20 °C to +70 °C for MN15GP0402 MN15GP0402) Interrupts 3 levels - Interrupt 1 (IRQ1) - Interrupt 2 (IRQ2) - Interrupt 3 (IRQ3) Hardware Functions I-3 Chapter 1 Overview Timers / Counters 3 timers Timer 2 ( 8-Bit timer for general use ) - Timer pulse output, PWM output, Remote control carrier output - Clock source fsys/2, fsys/8, fsys/32, fsys/128, fosc, fosc/4, fosc/16, fosc/64 Timer 3 ( 8-Bit timer for general use ) - Timer pulse output, High precision PWM output, Remote control carrier output, 16-Bit cascade connection function (connected to timer 2) - Clock source fsys/2, fosc, fosc/26, fosc/214 Watchdog timer A/D converter 10 bits X 4 channels Buzzer output Output frequency can be selected from fosc/1024, fosc/2048, fosc/4096. PWM output Remote control output Duty cycle of 1/2, or 1/3. ACZ input 1 set Mask option Automatic reset is available. Oscillation is selected from high / low / RC. Port General I/O ports 15 ports (11 for dual function) - Buzzer output 1 ports (for timer output, too) - Timer output 1 ports (for buzzer output, too) - NSYNC output 1 ports - ACZ input 1 ports (for NIRQ input, too) - NIRQ input 1 ports (for ACZ input, too) - A/D converter input 4 ports - NRST input 1 ports EPROM version MN15GP0402SJ MN15GP0402SJ Emulator Process I-4 PX-ICE1500 PX-ICE1500+PX-PRB15G0402 PX-PRB15G0402 CMOS Hardware Functions Chapter 1 Overview 1-3 Block Diagram 1-3-1 Overview Table 1-3-1 Functions on Blocks Name Block Description CPU(MN150G MN150G) Instruction execution controller Controls CPU block operations in response to the result decoded by the instruction decoder and interrupt requests. Read Only Memory can be used as an area where instructions that CPU executes are stored. ROM Memory data RAM Timer 2, 3 Buzzer output Timer controller A/D converter A/D controller External interrupt Interrupt controller Port 0 Port 1 Port 2 Port 3 I/O controller Random Access Memory can be used as an data area where data that are needed on program execution are stored and as the stack area. Used as timer operation, timer pulse output, PWM output, cascade connection, remote control carrier output, buzzer output. Includes a set of A/D converter with 10-bits resolution. Analog input is switched channel 0 to 3(AD0 to AD3) by software. Controls interrupt by interrupt request flag (IF) and interrupt enable flag (IE). Port 0, port 1, port 2, port 3 are I/O port. Clock generator Clock generator Connect resonator to OSC1, OSC2 to generate systemclock. At RC oscillation in mask option, connect RC to external to generate system clock. Watchdog timer Error detector Counts watchdog timer. When counter is overflow, output "L" from NRST pin and reset. Automatic reset Low voltage detector When low voltage is detected, output "L" from NRST pin and reset. Block Diagram I-5 Chapter 1 Overview 1-3-2 Block Diagram OSC2 Oscillation stabilization wait time NRST OSC1 Clock generator A/D converter Watchdog timer Automatic reset Timer 2, 3 (8 bit x 2) VDD CPU MN150G MN150G VSS Buzzer output ROM RAM 2 KB / 4 KB 128 nibble Port 0 Port 1 Port 2 Port 3 P32/TCO/BZ/key2 P31/NIRQ/ACZ/key1 Block Function Diagram P30/NSYNC/key0 P23/AD3 P23/AD3 P22/AD2 P22/AD2 P21/AD1 P21/AD1 P20/AD0 P20/AD0 P13/PWMO3 P13/PWMO3 Block Diagram P12/PWMO2 P12/PWMO2 I-6 P11/PWMO1 P11/PWMO1 P10/PWMO0 P10/PWMO0 P03 P02 P01 P00 Figure 1-3-1 External interrupt Chapter 1 Overview 1-4 Pin Description 1-4-1 Pin Configuration VDD 1 20 P32/TCO/BZ/key2 OSC1 2 19 P31/NIRQ/ACZ/key1 OSC2 3 18 P30/NSYNC/key0 VSS 4 17 NRST P00 5 16 P23/AD3 P23/AD3 P01 6 15 P22/AD2 P22/AD2 P02 7 14 P21/AD1 P21/AD1 P03 8 13 P20/AD0 P20/AD0 P10/PWMO0 P10/PWMO0 9 12 P13/PWMO3 P13/PWMO3 P11/PWMO1 P11/PWMO1 10 11 P12/PWMO2 P12/PWMO2 Figure 1-4-1 Pin Configuration ( 20SOP 20SOP : Top view ) Pin Description I-7 Chapter 1 Overview 1-4-2 Pin Functions Table 1-4-1 Name Pin No. I/O VSS VDD 4 1 - Power supply pin Apply 2.0 V to 5.5 V to VDD and 0 V to VSS. OSC1 OSC2 2 3 Input Output Clock input pin Clock output pin Connect these oscillation pins to oscillators for clock operation. Feed back resistor is buit-in.(Not connected at RC oscillation) If the clock is an external input, connect it to OSC1 and leave OSC2 open. NRST 17 I/O Reset input pin [Schmitt] Reset by inputting "L" to NRST pin. After reset is cleared, internal reset is cleared after 214 counts of OSC input clock at high oscillation, and 27 counts of OSC input clock at low / RC oscillation. The output configuration is N-ch open-drain. Reset can be selected by watchdog timer or low voltage detector(*1) by automatic reset circuit. *1 Autoreset circuit is mask option. P00 P01 P02 P03 5 6 7 8 I/O I/O port 0 Parallel data I/O port. Each bit can be set individually as either an input or output by the P01DIR P01DIR register. The output configuration is N-ch open-drain. At reset, the input mode (high impedance output) is selected. P10 P11 P12 P13 9 10 11 12 I/O PWMO0 PWMO1 PWMO2 PWMO3 I/O port 1 Parallel data I/O port. Each bit can be set individually as either an input or output by the P01DIR P01DIR register. The output configuration is CMOS push-pull or N-ch open-drain. Each bit can be switched individually by the P01SC P01SC register. At reset, the input mode (high impedance output) is selected. They can be also used for PWM output (PWMO0 to 3). P20 P21 P22 P23 13 14 15 16 I/O AD0 AD1 AD2 AD3 I/O port 2 Parallel data I/O port. Each bit can be set individually as either an input or output by the P23DIR P23DIR register. A p ull-up re si sto r fo r e a ch b i t ca n b e se le cte d individually by the P23PLU P23PLU register. The output configuration is CMOS push-pull or N-ch open-drain. Each bit can be switched individually by the P23SC P23SC register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output). P20 / AD0, P21 / AD1, P22 / AD2 and P23 / AD3 are dual functions. I-8 Dual Function Pin Function Summary (1/3) Pin Description Function Description Chapter 1 Overview Table 1-4-2 Name Pin NO. I/O P30 18 I/O P31 19 P32 20 AD0 AD1 AD2 AD3 13 14 15 16 NSYNC 18 ACZ 18 BZ 20 NIRQ 19 TCO 20 Input Dual Function Description I/O port 3 [Schmitt] Parallel data I/O port. Each bit can be set individually as either an input or output by the P23DIR P23DIR register. A p ull-up re si sto r fo r e a ch b i t ca n b e se le cte d individually by the P23PLU P23PLU register. The output configuration is CMOS push-pull or N-ch open-drain. Each bit can be set individually by the P23SC P23SC register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output), but P30 outputs system clock during the internal reset. P30 / NSYNC, P31 / NIRQ/ACZ and P32 / TCO/BZ are dual functions. These can be used as key interrupt input. P20 P21 P22 P23 Analog input pin Analog input pins for 4 channels. Set pin's direction to input by the P23DIR P23DIR resister. When not used for analog input, these pins can be used as normal port. Systemclock synchronous output At internal reset, synchronous signal of system clock is output. At operation, the initial status is port, but NSYNC output / port data output can be selected by the ACZCNT register. These can be used as key interrupt input. AC zero-cross detection input AC zero-cross detection circuit input pin. AC zero-cross detection circuit is connected to ACZ interrupt input and P31 input circuit. P31 ACZ input / port input can be selected by the ACZCNT register. These can be used as key interrupt input. Buzzer output Buzzer output pin. Buzzer output / port data output can be selected by the BZCTR register. When not used for buzzer output, this can be used as normal port. This can be used as Key interrupt input. Interrupt input Interrupt 1 (IRQ1) input pin. When not used for interrupt input, this can be used as normal port. This can be used as key interrupt input. Timer output Timer output pins. Timer output / port data output can be selected by the TCOCNT register. When not used for timer output, this pin can be used as normal port. This can be used as key interrupt input. P31 NIRQ key1 Output P32 TCO key2 Input Function NSYNC key0 NIRQ ACZ key1 TCO BZ key2 Output P30 key0 Input Pin Function Summary (2/3) P31 ACZ key1 Output P32 BZ key2 Pin Description I-9 Chapter 1 Overview Table 1-4-3 Name Pin NO. I/O key0 18 Input key1 19 key2 20 PWMO0 PWMO1 PWMO2 PWMO3 9 10 11 12 I - 10 Dual Function P30 NSYNC P31 NIRQ ACZ P32 TCO BZ Output P10 P11 P12 P13 Pin Description Pin Function Summary (3/3) Function Description Key interrupt input Key interrupt input. Each bit can be set individually as either an enable or disable by the KEYCNT register. When not used for key interrupt input, these pins can be used as normal port. PWM output PWM output pins. Each bit can be set individually PWM output as either an enable or disable by the BZCTR register. When PWM output is enabled, the conjunction of the timer output selected by the MODCNT register and the port output latch data is output. Chapter 1 Overview 1-5 Special Function Registers 1-5-1 Register Map This special function registers of this LSI are located as shown below. Table 1-5-1 Register Map Page 0 0 0x 1x 2x 1 2 PORT0 PORT1 PORT2 P01DIR P01DIR 3x 4x 5x 6x CPUM 7x 8x 9x Ax Bx Cx Dx Ex Fx ADBUF0 3 4 5 6 7 8 9 A B C D E F PORT3 P23DIR P23DIR P23PLU P23PLU IRQM IRQC0 TM2BC TM2OC IRQC1 TM3BC TM3OC P01SC P01SC KEYCNT P23SC P23SC ACZCNT TM2MD TCOCNT ADBUF1 BZCTR TM3MD MODCNT WDCTR ADCTR0 Note : Access to x'000' to x'00F' is by 4-bit (I/O instruction on each port) and 8-bit. Access to x'010' to x'07F' is by only 8-bit. Special Function Registers I - 11 Chapter 1 Overview 1-5-2 Special Function Registers Address Register R/W Function Page x'000' PORT01 PORT01 R/W Port 0, port 1 data register III - 9 x'002' PORT23 PORT23 R/W Port 2, port 3 data register III - 13 x'010' P01DIR P01DIR R/W Port 0, port 1 direction control register III - 9 x'012' P23DIR P23DIR R/W Port 2, port 3 direction control register III - 13 x'022' P23PLU P23PLU R/W Port 2, port 3 pull-up resistor control register III - 13 x'028' P01SC P01SC R/W Port 1 output structure control register III - 9 x'02A' P23SC P23SC R/W Port 2, port 3 output structure control register III - 14 x'030' CPUM R/W CPU mode register II - 15 x'032' IRQM x'034' W IRQ mode register IV - 16 IRQC0 R/W Interrupt 0 control register IV - 16 x'036' IRQC1 R/W Interrupt 1 control register IV - 17 x'038' KEYCNT R/W Key interrupt 1 control register IV - 17 x'03A' ACZCNT R/W ACZ control register VII - 5 x'044' TM2BC R Timer 2 binary counter V - 10 x'046' TM3BC R Timer 3 binary counter V - 10 x'04C' TM2MD R/W Timer 2 mode register V - 11 x'04E' TM3MD R/W Timer 3 mode register V - 12 x'054' TM2OC R/W Timer 2 compare register V-9 x'056' TM3OC R/W Timer 3 compare register V-9 x'05E' MODCNT R/W Timer mode control register V - 12 x'06A' TCOCNT R/W Timer output control register V - 13 x'06C' BZCTR R/W Buzzer output control register V - 14 x'06E' WDCTR W Watchdog timer control register VIII - 4 x'070' ADBUF0 R A/D converter data storage buffer 0 VI - 6 x'072' ADBUF1 R A/D converter data storage buffer 1 VI - 6 x'074' ADCTR0 R/W A/D control register R/W : Readable / Writable R : Readable only W : Writable only I - 12 Special Function Registers VI - 5 Chapter 1 Overview 1-6 Electrical Characteristics This LSI user's manual describes the standard specification. Please ask our sales offices for its own product specifications. Contents Model MN15G0202 MN15G0202, MN15G0402 MN15G0402 Structure CMOS integrated circuit Application General purpose Function 1-6-1 CMOS, 4-bit, single-chip microcontroller Absolute Maximum Ratings *2 *3 VSS = 0 V Parameter Symbol Rating Unit 1 Power supply voltage VDD -0.3 to +7.0 V 2 Input clamp current (ACZ) IC -0.5 to +0.5 mA 3 I/O pin voltage VIO -0.3 to VDD+0.3 V P0 IOL(peak) 40 Other than P0 IOL(peak) 20 6 all IOH(peak) -10 7 P0 IOL(avg) 15 Other than P0 IOL(avg) 10 9 all IOH(avg) -2 10 P0 ITOL1 60-ITOL2 60-ITOL2 Other than P0 ITOL2 20 P0 ITOH1 60-ITOH2 60-ITOH2 Other than P0 ITOH2 20 4 5 8 11 12 13 Peak output current Average output current *1 Total output current *1 (except ACZ) mA 14 Power dissipation PD 180(Ta=85 °C) mW 15 Ambient operating temperature Topr -40 to +85 °C 16 Storage temperature Tstg -55 to +125 °C *1 *2 *3 Applied to any 100-ms period. Connect at least one bypass capacitor of 0.1µF or larger between the power supply pin and the ground for latch-up prevention. The absolute maximum ratings are the limit values beyond which the LSI may be damaged and proper operation is not assured. They do not assure operation. Electrical Characteristics I - 13 Chapter 1 Overview 1-6-2 Operating Conditions Ta = -40 °C to +85 °C VDD = 2.0 V to 5.5 V(VRSTL1,2 to 5.5 V) VSS = 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply voltage 1 VDD1 fosc8 MHz(divided by 4) High oscillation No automatic reset 3.0 - 5.5 2 VDD2 fosc4 MHz(divided by 4) High oscillation No automatic reset 2.4 - 5.5 3 VDD3 fosc4 MHz(divided by 8) High oscillation No automatic reset 2.0 - 5.5 4 VDD4 fosc100 kHz(divided by 4) Low oscillation No automatic reset 2.0 - 5.5 VDD5 fosc1 MHz(divided by 8) At RC oscillation No automatic reset 2.2 - 5.5 VDD6 *1 fosc8 MHz(divided by 4) fosc4 MHz(divided by 4) High oscillation Automatic reset VRSTL1 - 5.5 7 VDD7 fosc4 MHz(divided by 8) High oscillation fosc100 kHz(divided by 4) Low oscillation Automatic reset VRSTL1 VRSTL2 - 5.5 8 VDD8 *1 fosc1.2 MHz(divided by 4) At RC oscillation Automatic reset VRSTL1 - 5.5 - 3.90 4.40 3.20 3.70 - 0.05 0.20 - t/v 1.00 - - VRSTH2 - 2.20 2.40 1.80 2.05 - 0.05 0.15 - 1.00 - - 5 Power supply voltage 6 V *1 Automatic reset circuit 2 cannot be selected in mask option. Note : VRSTL1 and VRSTL2 is applied when automatic reset circuit is selected in mask option. They are voltage to activate reset by detecting power supply voltage. Automatic reset circuit 1 9 10 Power supply detection level 11 Hysteresis width 12 Power supply voltage change VRSTH1 VRSTL1 Vh figure 1-6-1. V ms/V Automatic reset circuit 2 13 14 Power supply detection level 15 Hysteresis width 16 I - 14 Power supply voltage change Electrical Characteristics VRSTL2 Vh t/v figure 1-6-1. V ms/V Chapter 1 Overview Ta = -40 °C to +85 °C VDD = 2.0 V to 5.5 V(VRSTL1,2 to 5.5 V) VSS = 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Operation speed 17 tc1 VDD=3.0 V to 5.5 V High oscillation (): At automatic reset 0.5 - 16 18 tc2 VDD=2.4 V(VRSTL1) to 5.5 V High oscillation (): At automatic reset 1.0 - 16 tc3 VDD=2.0 V(VRSTL1,2) to 5.5 V High oscillation (): At automatic reset 2.0 - 16 20 tc4 VDD=2.0 V(VRSTL1,2) to 5.5 V Low oscillation (): At automatic reset 40.0 - 250.0 21 tc5 VDD=2.2 V(VRSTL1) to 5.5 V At RC oscillation 3.3 - 20.0 19 Instruction execution time µs VDD VRSTH Vh VRSTL about 1.5 V t high status of generalport unstable impedance status of NRST pin unstable 'L' operation mode 'H' Figure 1-6-1 unstable high impedance 'L' unstable Automatic Reset Voltage Electrical Characteristics I - 15 Chapter 1 Overview Ta = -40 °C to +85 °C VDD = 2.0 V to 5.5 V(VRSTL1,2 to 5.5 V) VSS = 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX 0.5 - 8.0 - 30.0 - - 30.0 - Oscillation 1 (High oscillation) 22 Oscillation frequency fxtal1 23 C11 VDD=2.0 V to 5.5 V VDD=VRSTL to 5.5 V *1 figure 1-6-2. External capacitors MHz pF 24 C12 25 Internal feedback resistor RF1 - 500.0 - k 26 Oscillation frequency fxtal2 32.0 - 125.0 kHz 27 C21 - 30.0 - - 30.0 - - 4.0 - M 0.4 - 1.0 MHz Oscillation 2 (Low oscillation) VDD=2.0 V to 5.5 V VDD=VRSTL to 5.5 V *1 figure 1-6-3. External capacitors 28 C22 29 Internal feedback resistor RF2 pF Oscillation 3 (RC oscillation) 30 Oscillation frequency fRC 31 External capacitors C3 32 External resistor VDD=2.2 V to 5.5 V VDD=VRSTL to 5.5 V *1 figure 1-6-4. pF R3 k *1 when automatic reset is available Note : At RC oscillation, caution as follows. (1) Operation is not guaranteed over the recommended temperature of R and C, even if the operating ambient temperature is under the condition. ex.) When the operating ambient temperature is -40 °C, and the recommended temperature of C is -20 °C to +85 °C. (2) Frequency of RC oscillation is unfixed, so the following factors should be checked. - change of the power supply voltage - change of R and C (temperature feature, permitted level) - change of the LSI (temperature feature ±40 %, permitted level ±30 %) (3) R and C should be set near the LSI on board. The oscillation frequency may be changed by capacity of the board. OSC1 OSC1 fxtal2 RF2 fxtal1 RF1 OSC1 R3 OSC2 OSC2 C12 Figure 1-6-2 I - 16 C11 Oscillation 1 Electrical Characteristics OSC2 C22 Figure 1-6-2 C21 Oscillation 2 C3 Figure 1-6-2 Oscillation 3 Chapter 1 Overview Ta = -40 °C to +85 °C VDD = 2.0 V to 5.5 V(VRSTL1,2 to 5.5 V) VSS = 0 V Parameter Symbol Conditions Rating Unit External clock input 1 OSC1 (High oscillation. OSC2 is unconnected.) 0.5 - 8.0 56 - - twl1 56 - - 36 Rise time twr1 - - 20 37 Fall time twf1 - - 20 32 - 125 3.6 - - 3.6 - - - - 20 - - 20 33 Clock frequency fosc1 34 High level pulse width twh1 35 Low level pulse width MHz figure 1-6-5. *1 ns figure 1-6-5. External clock input 2 OSC1 (Low oscillation. OSC2 is unconnected.) 38 Clock frequency 39 High level pulse width twh2 40 Low level pulse width twl2 41 Rise time twr2 42 Fall time *1 fosc2 twf2 figure 1-6-6. *1 kHz µs figure 1-6-6. ns The clock duty cycle should be 45% to 55%. Electrical Characteristics I - 17 Chapter 1 Overview 0.9 VDD 0.1 VDD twh1 twl1 twr1 twf1 twc1 Figure 1-6-5 OSC1 Timing Chart (External clock input 1) 0.9 VDD 0.1 VDD twh2 twl2 twr2 twf2 twc2 Figure 1-6-6 I - 18 Electrical Characteristics OSC1 Timing Chart (External clock input 2) Chapter 1 Overview 1-6-3 DC Characteristics Ta = -40 °C to +85 °C VDD = 2.0 V to 5.5 V(VRSTL1,2 to 5.5 V) VSS = 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply current *1 IDD1 fosc=8.0 MHz (divided by 8) VDD=5.0 V - 1.5 3.0 IDD2 fosc=4.0 MHz (divided by 8) VDD=5.0 V - 1.2 2.5 IDD3 fosc=32.768 kHz (divided by 8) VDD=5.0 V - 30.0 60.0 µA IDD4 fosc=4.0 MHz (divided by 8) VDD=5.0 V - 0.3 0.6 mA IDD5 fosc=32.768 kHz (divided by 8) VDD=5.0 V - 1.5 8.0 IDD6 VDD=5 V ACZ=1/2VDD Ta=25 °C - 3.0 10.0 IDD7 VDD=5 V ACZ=1/2VDD Ta = -40 °C to +85 °C - - 20.0 8 IDD8 VDD=5 V Ta=25 °C - - 1.0 9 IDD9 VDD=5 V Ta=-40 °C to +85 °C - - 5.0 IDD10 IDD10 VDD=5 V - 4.0 8.0 1 Power supply current 2 3 4 Supply current during HALT mode 5 6 7 Supply current during STOP mode 10 *1 *2 Automatic reset current consumption *2 mA µA Measured under conditions of no load, Ta = 25 °C. The automatic reset current consumption I DD10 indicates the consumption, normally spent in automatic reset circuit, when automatic reset is used in mask option. So, if automatic reset circuit is selected, each rating is added. - The supply current during operation, IDD1, is measured under the following conditions : After reset is released and the oscillation is set to , the I/O pin is fixed at V DD, and a 8-MHz square wave of amplitude VDD, VSS is input to the OSC1 pin. - The supply current during operation, IDD2, is measured under the following conditions : After reset is released and the oscillation is set to , the I/O pin is fixed at V DD, and a 4-MHz square wave of amplitude VDD, VSS is input to the OSC1 pin. - The supply current during operation, IDD3, is measured under the following conditions : After reset is released and the oscillation is set to , the I/O pin is fixed at V DD, and a 32.768-kHz square wave of amplitude VDD, VSS is input to the OSC1 pin. - The supply current during HALT mode, IDD4, is measured under the following conditions : After reset is released and the oscillation is set to , the I/O pin is fixed at VDD, and a 4-MHz square wave of amplitude VDD, VSS is input to the OSC1 pin. - The supply current during HALT mode, IDD5, is measured under the following conditions : After reset is released and the oscillation is set to , the I/O pin is fixed at VDD, and a 32.768-kHz square wave of amplitude VDD, VSS is input to the OSC1 pin. - The supply current during STOP mode, IDD6, IDD7 are measured under the following conditions : After reset is released and the oscillation is set to , the I/O pin is fixed at V DD, the ACZ pin is fixed at 1/2 VDD and the OSC1 is unconnected. - The supply current during STOP mode, IDD8, IDD9 are measured under the following conditions : After reset is released and the oscillation is set to , the I/O pin is fixed at V DD and the OSC1 is unconnected. Electrical Characteristics I - 19 Chapter 1 Overview Ta=-40 °C to +85 °C VDD=2.0 V to 5.5 V(VRSTL1,2 to 5.5 V) VSS=0 V Rating Parameter Symbol Condition Unit MIN TYP MAX Input pin NRST (Schmitt input. Pull-up resistor built-in.) 11 Input high voltage VIH1 0.8VDD - VDD 12 Input low voltage VIL1 VSS - 0.15 VDD 13 Input current II1 -50 -140 -200 Pull-up resistor ON VI=1.5 V, VDD=5.0 V V µA I/O pin P00 to P03(N-ch open-drain output) 14 Input high voltage VIH2 0.8VDD - VDD 15 Input low voltage VIL2 VSS - 0.2VDD 16 Input leakage current ILI2 VI=0 V to VDD - ±0.01 ±1 µA 17 Output low voltage VOL2 IOL=15 mA,VDD=5.0 V VSS 0.4 1.0 V V I/O pin P10/PWMO0 P10/PWMO0 to P13/PWMO3 P13/PWMO3 18 Input high voltage VIH3 0.8VDD - VDD 19 Input low voltage VIL3 VSS - 0.2VDD 20 Input leakage current ILI3 VI=0 V to VDD - ±0.01 ±1 21 Output high voltage VOH3 IOH=-0.5 mA,VDD=5.0 V 4.5 4.9 VDD 22 Output low voltage VOL3 IOL=15 mA,VDD=5.0 V VSS 0.4 1.0 V µA V I/O pin P20/AD0 P20/AD0, P21/AD1 P21/AD1, P22/AD2 P22/AD2, P23/AD3 P23/AD3 (as port) 23 Input high voltage VIH4 0.8VDD - VDD 24 Input low voltage VIL4 VSS - 0.2VDD 25 Input current II4 Pull-up resistor ON VI=1.5 V, VDD=5.0 V -50 -140 -200 26 Input leakage current ILI4 Pull-up resistor OFF VI=0 V to VDD - ±0.01 ±1 27 Output high voltage VOH4 IOH=-0.5 mA,VDD=5.0 V 4.5 4.9 VDD 28 Output low voltage VOL4 IOL=3.5 mA,VDD=5.0 V VSS 0.1 0.5 V µA V I - 20 Electrical Characteristics Chapter 1 Overview Ta=-40 °C to +85 °C VDD=2.0 V to 5.5 V(VRSTL1,2 to 5.5 V) VSS=0 V Rating Parameter Symbol Condition Unit MIN TYP MAX I/O pin P30/NSYNC/key0, P31/NIRQ/ACZ/key1, P32/TCO/BZ/key2 (as P30/NSYNC/key0,P31/NIRQ/key1,P32/TCO/BZ/key2, schmitt input) 29 Input high voltage VIH5 0.8VDD - VDD 30 Input low voltage VIL5 VSS - 0.1VDD 31 Input current II5 Pull-up resistor ON VI=1.5 V, VDD=5.0 V -50 -140 -200 32 Input leakage current ILI5 Pull-up resistor OFF VI=0 V to VDD - ±0.01 ±1 33 Output high voltage VOH5 IOH=-0.5 mA,VDD=5.0 V 4.5 4.9 VDD 34 Output low voltage VOL5 IOL=3.5 mA,VDD=5.0 V VSS 0.1 0.5 - VDD V µA V Note : When P30/NSYNC/key0 pins are used, output voltage should be over 0.8 VDD at timing signal (NSYNC) output. Input pin P31/NIRQ/ACZ/key1 (as ACZ input) 35 Input high voltage 36 Input low voltage VDLH 37 Input high voltage VDHL 38 Input low voltage VDLL 39 Input leakage current ILI6 40 ICL6 VDD-0.5 VDHH Input clamp current 41 Rise time VSS - 1.5 - VDD VSS - 0.5 VI = 0 V to VDD - ±0.01 ±1 VI > VDD, VI < 0 V - - ±500 30 - - 30 - - VDD = 4.5 V to 5.5 V figure 1-6-7. trs figure 1-6-7. 42 Fall time tfs VDD-1.5 V µA Electrical Characteristics µs I - 21 Chapter 1 Overview trs tfs VDD VDHH input voltage level 1 VDLH (input) VDHL input voltage level 2 VDLL VSS (output) Figure 1-6-7 I - 22 Electrical Characteristics AC Zero-cross Detection Circuit Operation Chapter 1 Overview 1-6-4 A/D Converter Characteristics Ta = -40 °C to +85 °C VDD = 2.0 V to 5.5 V(VRSTL1,2 to 5.5 V) VSS = 0 V Rating Parameter Symbol Conditions Unit MIN 2 Non-linearity error 3 Differential non-linearity error 4 Zero transition voltage VDT 5 Full-scale transition voltage VFST 6 A/D conversion time 7 Sampling time TS 8 Analog input voltage VIA 9 Analog input leakage current ILIA 10 Ladder resistance VDD=5.0 V, VSS=0.0 V fosc=8 MHz (divided by 8) TAD=1.0 µs, TS=2.0 µs RIadd VDD=5.0 V VSS=0.0 V fosc=8 MHz (divided by 8) TAD=1.0 µs When channel OFF VI=0 V to VDD - 10 Bits - - ±3 LSB - - ±3 LSB - 10 30 mV 4950 4980 - mV 12.0 - 28.0 µs 2.0 - 18.0 µs VSS Resolution MAX - 1 TYP - VDD V - ±0.01 ±1 µs 10 30 100 k - Zero transition voltage It indicates how much difference between the nominal value and the analog input voltage, when digital output code is changed from "0" to "1" (x'000' x'001'). - Full-scale transition voltage It indicates how much difference between the nominal value and the analog input voltage, when digital output code reached the full-scale (x'3FE' x'3FF') . Electrical Characteristics I - 23 Chapter 1 Overview 1-7 External Dimensions * Package code : SOP020-P-0300 Unit : mm I - 24 External Dimension Chapter 1 Overview 1-8 Option 1-8-1 Mask Option This LSI has the following mask option. 1. Oscillation circuit setup The oscillation circuit of OSC is set with selection from high oscillation (0.5 MHz to 8 MHz), Low oscillation (32 kHz to 100 kHz) and RC oscillation. 2. Automatic reset circuit setup Automatic reset circuit (automatic reset circuit 1, automatic reset circuit 2) can be selected to "used" or "not used". Option I - 25 Chapter 1 Overview 1-8-2 Mask Option Form (VER 0.04) SE No. Model name MN15G MN15G 02 Date : Customer Approval 1. Power supply current and voltage voltage at operation V to V to V STOP mode V to not used V HALT mode used V 2. OSC oscillation circuit Mode Frequency High oscillation 0.5 MHz to 8.0 MHz Low oscillation 32 kHz to 125 kHz RC oscillation note 0.4 MHz to 1.2 MHz 3. Automatic reset circuit Used Unused When it is used, check the applicable item. VRSTL1 3.2 V to 4.4 V VRSTL2 1.6 V to 2.5 V Reset voltage VRSTL2 cannot be selected at RC oscillation, and at tc (the instruction execution time) < 2 µs. I - 26 Option 11 Chapter 2 Basic CPU 2 18 Chapter 2 Basic CPU 2-1 Clock Generator 2-1-1 Clock Generator This LSI has internal oscillator circuits for generating system clock (OSC1, OSC2). OSC oscillation can be selected from high speed / low speed / RC by mask option. When high speed oscillation or low speed oscillation is selected, these circuits require external oscillators and capacitors. Connect a crystal or ceramic oscillator (Figure 2-1-1(a). When RC oscillation is selected, the circuit require external capacitors and resistors. Oscillation frequency may be changed by capacitors, resistors, temperature and voltage or so (Figure 2-1-1(b). To minimize distortion, mount the oscillator and capacitor as close as possible to the pins. Also connect the VSS pin to a thick ground line with shortest possible distance to prevent noise and to stable oscillation. The best value of capacitor depends on oscillator, refer to the value specified by each manufacturer. nOscillator circuit connection Figure 2-1-1 provides oscillator circuit connections. VSS VSS OSC1 OSC1 OSC2 OSC2 Figure 2-1-1(a) II - 2 Oscillator circuit connection Clock Generator Figure 2-1-1(b) Oscillator circuit connection Chapter 2 Basic CPU 2-1-2 CPU Basic Timing Source oscillation generates 4 clocks (S0, S1, S2, S3) to form machine cycle (state). At 4.0 MHz, at high speed oscillation, 1 machine cycle is 1.0 µs at divided by 4, and 2.0 µs at divided by 8. At 32 kHz at low speed oscillation, 1 machine cycle is 122 µs at divided by 4, 250 µs at divided by 8. Machine cycle S3 S3 S2 S1 S0 S1 Fetch cycle n+1 Fetch cycle n Execution cycle n-1 ROM read out S0 Execution cycle n Execution cycle n+1 Instruction decode (JMP, CALL, RET, RETI interrupt) PC+1 RAM address SP-1 Figure 2-1-3 PC load RAM read out RAM write SP+1 Machine Cycle and CPU Basic Timing Clock Generator II - 3 Chapter 2 Basic CPU 2-2 Register Set This LSI has register for operation, for pointer and for store. 3 0 accumulator (A register) 3 0 accumulator expansion register (E register) 7 4 3 0 IRU IRL 3 0 IR (instruction register) IRU (IR upper) IRL (IR lower) X register 3 0 Y register 13 12 11 PCu 8 7 PCh 4 3 0 PCm PCl 3 0 PC (program counter) PCu (PC upper) PCh (PC high) PCm (PC middle) PCl (PC low) SX (stack register for X register) 3 0 SY (stack register for Y register) 3 0 SE (stack register for E register) 7 1 6 1 7 5 4 3 2 1 0 0 SP (stack pointer) 0 SB (special buffer) 7 0 TB (temporaly buffer) Figure 2-2-1 CPU Control Registers II - 4 Register Set Chapter 2 Basic CPU nAccumulator (A register) This register can be used generally for all operations. nAccumulator expansion register (E register) This register can be used generally for operation. At transfer instruction of 8-bit data, this register can be used for upper 4 bits or RAM odd address. 7 4 3 E 0 A ex. STBD (store byte direct) M (da + 1) E M (da) A Data in E register and accumulator are transferred to the address in RAM, specified directly (da). Data in E register is transferred to odd address (da + 1), data in accumulator is transferred to even address (da). nInstruction register (IR) This register reads out the instruction that CPU is going to execute, from ROM and latches. 7 4 IRU 3 0 IRL nProgram counter (PC) This register controls the execution order of instructions in program memory. PCu should be set to "0". Register Set II - 5 Chapter 2 Basic CPU nX register This register is 4-bit register, indirectly specifies RAM area. It specifies upper 4 bits of RAM address (X, Y). nY register This register is 4-bit register, indirectly specifies RAM area. It specifies lower 4 bits of RAM address (X, Y). nStack register for X register (SX) This is RAM for X register to stack. It can be used as normal RAM. RAM address X (0, 0) nStack register for Y register (SY) This is RAM for Y register to stack. It can be used as normal RAM. RAM address X (0, 0) nStack register for E register (SE) This is RAM for E register to stack. It can be used as normal RAM. RAM address X (0, 2) II - 6 Register Set Chapter 2 Basic CPU nFlag status Two flags (CF and ZF) reflect operation's results. LIFF reflects LI instruction execution status. CF (Carry Flag) The carry flag is set when ALU operation results is an overflow or an underflow. Otherwise, it is reset. ZF (Zero Flag) The zero flag is set when ALU operation results is zero. Otherwise, it is reset. LIFF (Load Immediate Flag) This memorizes that the last instruction is LI instruction. It is used to Instruction LIFF Description 0 NOP no execution LI 5 0 Set 5 to accumulator LI 8 1 no execution LI 9 1 no execution OUT 0, X'F' 0 Output 5 to port 0 nStack Pointer (SP) This is a 8-bit register that indicates address of stack area in data RAM. Stack area is used for PC to stack at subroutine call and at interrupt. 7 6 0 1 1 0 always "1" always "0" nSpecial Buffer (SB) This register can input / output data by 8-bits, by RDSB, WTSB instruction, between E register and A register. nTemporary Buffer (SB) This register can input / output data by 8-bits, by RDBC, WTTB instruction, between E register and A register. Register Set II - 7 Chapter 2 Basic CPU 2-3 Memory Space This LSI has independently, an instruction memory area (ROM) that stores instructions and a data memory area (RAM : include stack area) that stores data. ROM can be used as a memory for stable data such as table data. 2-3-1 ROM Address Space (2 KB) x'0000' RESET program starts. x'000A' IRQ1 interrupt service program starts. x'000C' IRQ2 interrupt service program starts. x'000E' IRQ3 interrupt service program starts. x'0010' User program area x'07FF' Figure 2-3-1 ROM Address Space ROM address can be specified by program counter, E register or accumulator. 1 page for 256 byte and ROM is divided by maximum 8 pages. nDirect address in page (ex. JZ, JNZ instruction) Address that is directly specified in instruction code indicates the branched address in the same page. x'000' x'020' as ZF=1 x'0FE' JZ X'20' as ZF=0 x'100' II - 8 Memory Space Chapter 2 Basic CPU nDirect address 1 (ex. JMP, CALL instruction) Address that is directly specified in instruction code indicates the branched address for no condition. or of subroutine. Directly specified address is 12-bit (PCh, PCm, PCI), an arbitrary address can be specified. nDirect address 2 (ex. JMPL, CALLL instruction) Address that is directly specified in instruction code indicates the branched address for no condition. or for subroutine. PCu should be set to "0". nSpecial address in zero page (x'0000' to x'00FF') (ex. CALS instruction) Address that is specified in instruction code indicates the branched address for subroutine by 16 byte in zero page. nAccumulator indirectly address (ex. JMPEA instruction) Address that is specified in 4 bit of E register (upper address) and in 4 bit of A register (lower address) indirectly indicates the branched address for no condition. That is branched in the same page. nCautions on the branch instruction with condition (JC, JNC, JZ, JNZ, JBZ, JBNZ, CYIJ) Conditional branch instruction is branched to the address that is indicated in 2 byte of instruction in the same page, if condition is set. At the border of page, jump address is to the next page. ex. JC Address 000 . . . 015 . . . 0FE 0FF 100 . . . 115 . . . 1FF Machine code 1 6F 15 jc xxx 2 PCh(PC8 to PC11) is changed here. 3 As shown the above example, if JC instruction is located from x'0FE' to x'0FF' it is branched to the address that is indicated in 2 when condition is set. And when condition is not set, it is executed the instruction of the address (x'115') that is indicated in 3. Memory Space II - 9 Chapter 2 Basic CPU 2-3-2 ROM Address Space (4KB) x'0000' RESET program starts. x'000A' IRQ1 interrupt service program starts. x'000C' IRQ2 interrupt service program starts. x'000E' IRQ3 interrupt service program starts. x'0010' User peogram area x'0FFF' Figure 2-3-2 ROM Address Space ROM address can be specified by program counter, E register or accumulator. 1 page for 256 byte. It is divided by maximum 16 pages. nDirect address in page (ex. JZ, JNZ instruction) Address that is directly specified in instruction code indicates the branched address in the same page. x'000' x'020' as ZF=1 x'0FE' JZ X'20' as ZF=0 x'100' II - 10 Memory Space Chapter 2 Basic CPU nDirect address 1 (ex. JMP, CALL instruction) Address that is directly specified in instruction code indicates the branched address for no condition. or of subroutine. Directly specified address is 12-bit (PCh, PCm, PCI), an arbitrary address can be specified. nDirect address 2 (ex. JMPL, CALLL instruction) Address that is directly specified in instruction code indicates the branched address for no condition. or for subroutine. PCu should be set to "0". nSpecial address in zero page (x'0000' to x'00FF') (ex. CALS instruction) Address that is specified in instruction code indicates the branched address for subroutine by 16 byte in zero page. nAccumulator indirectly address (ex. JMPEA instruction) Address that is specified in 4 bit of E register (upper address) and in 4 bit of A register (lower address) indirectly indicates the branched address for no condition. That is branched in the same page. nCautions on the branch instruction with condition (JC, JNC, JZ, JNZ, JBZ, JBNZ, CYIJ) Conditional branch instruction is branched to the address that is indicated in 2 byte of instruction in the same page, if condition is set. At the border of page, jump address is to the next page. ex. JC Address 000 . . . 015 . . . 0FE 0FF 100 . . . 115 . . . 1FF Machine code 1 6F 15 jc xxx 2 PCh(PC8 to PC11) is changed here. 3 As shown the above example, if JC instruction is located from x'0FE' to x'0FF', it is branched to the address that is indicated in 2 when condition is set. And when condition is not set, it is executed the instruction of the address (x'115') that is indicated in 3. Memory Space II - 11 Chapter 2 Basic CPU 2-3-3 RAM Address Space lower address (4-bit) Y X upper address (4-bit) 0 1 2 3 4 5 6 7 8 9 A B C D E F F E DCB A 9 8 7 6 5 4 3 2 1 0 SE SYSX Figure 2-3-3 II - 12 Memory Space Data area Stack area RAM Address Space Chapter 2 Basic CPU 2-3-4 Stack Area Stack area is allocated from x'C0' to x'FF' in RAM area. Stacked area is used for program counter, flag status (ZF,CF), accumulator, E, X, Y registers to stack at CALL instruction, PSH instruction and at interrupt. When the whole area is not used as stacked area, it can be used as a normal RAM. If only CALL instruction is used, the maximum 16 levels can be used. Figure 2-3-4 shows the status of stack area when CALL, PSH instructions and interrupt sequence are executed. (odd address) (even address) 3 3 2 1 0 2 1 0 x'F1' to x'F0' x'F3' to x'F2' x'F5' to x'F4' PCm PCl x'F7' to x'F6' CF ZF LIFF PCh x'F9' to x'F8' X Y x'FB' to x'FA' E A x'FD' to x'FC' PCm PCl x'FF' to x'FE' CF ZF LIFF PCh RAM area Figure 2-3-4 Status of Stacked Area nSP (Stack Pointer) shows x'C0' at reset. Also stacked data is used from x'FF' to x'C0' in order. nIn RET instruction, flags (CF, ZF, LIFF) are not recovered. Only RETI instruction is recovered. nLIFF memorizes that the last instruction is LI instruction. It is used to pile up instructions. Memory Space II - 13 Chapter 2 Basic CPU 2-4 Clock Switching 2-4-1 Clock Switching This LSI can be switched the system clock division factor by instruction. The CLKSEL1 flag of the CPU mode register (CPUM) switches the division factor of the system clock (Figure 2-4-1). At fosc=4.0 MHz, instruction cycle is 1.0 µs at divided by 4, and 2.0 µs at divided by 8. And at fosc=32 kHz, 125 µs at divided by 4. NORMAL mode means the mode that CPU is operated. As shown on figure 2-4-1, at reset, the CLKSEL1 is "0", NORMAL mode is selected and operation is started from the reset cycle. Reset reset release *1 WI HALT fosc : oscillation CPU stop interrupt NORMAL fosc : oscillation CPU operate EDI WI interrupt *1 STOP fosc : stop CPU stop *1 fosc oscillation stabilization waiting time is needed on hardware. Figure 2-4-1 II - 14 Clock Switching CPU Operation Mode and Setup Chapter 2 Basic CPU 2-4-2 CPU Mode Register This is readable / writable register that switches the division rate of the system clock. 7 CPUM 6 5 4 3 2 1 0 - - - - - - CLKSEL1 - ( at reset : XXXXXX0X ) CLKSEL1 Division for system clock 0 Figure 2-4-2 divided by 8 1 divided by 4 CPU Mode Register (CPUM : x'030', R/W) Table 2-4-1 Status of Operation Mode Operation clock Mode OSC1 / OSC2 (fosc) System clock (fsys) CPU NORMAL Oscillation fosc/8 or fosc/4 Operate HALT Oscillation fosc/8 or fosc/4 Stop STOP Stop Stop Stop Clock Switching II - 15 Chapter 2 Basic CPU 2-5 Back Up Mode There are two back up mode to save electric consumption. They can be controlled by program. HALT mode : The system clock is supplied. It is recovered by a reset or by an interrupt. STOP mode : The division circuit for the system clock is stopped, so that the electric consumption is more saved. It is recovered by a reset or by an interrupt. Table 2-5-1 STOP / HALT Functions Mode STOP Description Operation status 1) HALT System clock 1) oscillation circuit stop. 2) WI instruction is executed soon, after EDI instruction is done. (refer to ex.) Mode setup Recover - interrupt - reset System clock oscillation circuit operates (dividing circuit for system clock operates) Timer count operates WI instruction is executed soon, after instruction ( except EDI) is done. (refer to ex.) same as a normal interrupt same as a normal reset ex. STOP mode usage example When IRQ1 (interrupt 1) is generated, it is recovered from STOP mode. To stable the operation, more than 1 NOP should be inserted after EDI, WI instructions. EDI WI NOP II - 16 Back Up Mode 0, 4 ; ; ; Chapter 2 Basic CPU There are 2 interrupts that can be recovered from STOP mode. - Interrupt 1 (IRQ1) - Interrupt 3 (IRQ3) (except timer 3) ex. HALT mode usage example EDI 0, 7 (instructions except EDI) ; WI NOP ; Even any interrupt is generated, that can be recovered from HALT mode. ; ; There are 3 interrupts that can be recovered from HALT mode. - Interrupt 1 (IRQ1) - Interrupt 2 (IRQ2) - Interrupt 3 (IRQ3) More than 1 NOP should be inserted after WI instruction. In cross assembler we offer, NOP is automatically inserted. Back Up Mode II - 17 Chapter 2 Basic CPU 2-5-1 Cautions on Back Up Mode nI/O port Pull-up resistance for pins at high-impedance should be set by the software with corresponding the voltage level of external circuit at backup, to save the electric consumption at port . Set the voltage level of the input port to "H" level or "L" level. If the level is middle, micro controller spend much more the electric consumption. nRecover from STOP mode If the power supply voltage is less than 1.8 V at recover, RAM data after recover may be damaged. In this case, reset by the external circuit. II - 18 Back Up Mode Chapter 2 Basic CPU 2-6 Reset 2-6-1 Reset Operation The CPU contents are reset when the NRST pin is pulled to low from external, or outputs "L" level by overflow of watchdog timer, by low voltage detector of auto-reset circuit. When a reset is generated, registers and data memory is initialized. Auto-reset circuit is mask option. Table 2-6-1 Initial Value of Register / Memory Register / Memory Symbol Initial value 1 Program counter PC 0 2 accumulator A 0 3 E register E 0 4 X register X 0 5 Y register Y 0 6 Carrier flag CF 0 7 Zero flag ZF 0 8 Special buffer SB indefinite 9 Temporary buffer TB indefinite 10 RAM 11 Stack pointer SP 0 12 Interrupt flag IF 0 13 Interrupt enable / disable flag IE disable 14 Port data register 1 15 Port control register 0 16 Control register indefinite CR 0 Some registers can not be set to "0". For detail, refer to instructions of each register. Reset II - 19 Chapter 2 Basic CPU nInitiating a reset The CPU contents are reset when the NRST pin is pulled to low from external, or outputs "L" level by overflow of watchdog timer, low voltage detector of auto-reset circuit. For stable reset, the NRST pin should keep "L" for more than 1 machine cycle. nTiming of reset release After the NRST pin becomes "H", there is 214 pulse counts of OSC input clock (fosc) at high speed oscillation, 27 pulse counts at low speed oscillation, RC oscillation till the internal reset is released. The period from counting to overflow is called "oscillation stabilization wait time". This period is automatically inserted at reset release, at recover from STOP mode. This is happened because, if the internal reset is released when source oscillation of the system clock is unstable, micro controller may be wrongly operated. After oscillation stabilization wait time is finished, internal reset is released and program is started from the address x'0000'. This LSI starts form NORMAL mode. VDD NRST OSC2 Internal reset Figure 2-6-1 Oscillation stabilization wait time Reset Released Sequence At internal reset, P30 / NSYNC / key 0 pin outputs the system clock (S0). When the auto-reset circuit is selected in mask option, the circuit that has enough time of "L" level pulse should be used. II - 20 Reset Chapter 3 Portts 3 Chapter 3 Ports 3-1 Overview 3-1-1 Port Diagram There are four ports, port 0, port 1, port 2 and port 3. Each port is assigned to its corresponding special function register area in memory. P20/AD0 P20/AD0 P21/AD1 P21/AD1 P22/AD2 P22/AD2 P23/AD3 P23/AD3 Port 0 P00 P01 P02 P03 Port 1 P10/PWMO0 P10/PWMO0 P11/PWMO1 P11/PWMO1 P12/PWMO2 P12/PWMO2 P13/PWMO3 P13/PWMO3 Figure 3-1-1 III - 2 Overview Port 2 P30/NSYNC/key0 P31/NIRQ/ACZ/key1 P32/TCO/BZ/key2 Port 3 Port Functions Chapter 3 Ports 3-1-2 Port Functions Table 3-1-1 Dual function Port Port 0 P00 P01 P02 P03 - Port 1 P10 P11 P12 P13 Port 2 I/O Port Functions I/O control Function Pull-up resistor at reset Function at reset Function at reset Input - - - - I/O Each bit can be set individually as either an input or output. PWMO0 PWMO1 PWMO2 PWMO3 I/O Each bit can be set individually as either an input or output. Input P20 P21 P22 P23 AD0 AD1 AD2 AD3 I/O Each bit can be set individually as either an input or output. P30 NSYNC key0 NIRQ ACZ key1 TCO BZ key2 I/O Each bit can be set individually as either an input or output. P31 Port 3 P32 Output structure control Output structure can be selected individually on each bit. CMOS output Input Output structure can Pull-up resistor can be be selected set individually on No resistor individually on each each bit. bit. CMOS output Input Output structure can Pull-up resistor can be be selected set individually on No resistor individually on each each bit. bit. CMOS output - - Overview III - 3 4 Chapter 3 Ports 3-1-3 Port Status at Reset Table 3-1-2 Port Status at Reset Port I/O mode Pull-up resistor Port 0 Input mode - Port 1 Input mode - Port 2 Input mode No pull-up resistor Port 3 Input mode No pull-up resistor P30/NSYNC/key0 outputs the system clock (s0) at internal reset. III - 4 Overview Chapter 3 Ports 3-1-4 Port Disposal at Unused Disposal of unused pins should be considered the status at reset. Table 3-1-3 shows the disposal. Table 3-1-3 Pin's type Disposal of Unused Pins Unused pin Port 0 OPEN Port 1 OPEN Port 2 OPEN Port 3 I/O pin Port Pull-up or pull-down should be added. *1 *1 When the internal resistor is used, the through current is happened till the setup complete. Overview III - 5 Chapter 3 Ports 3-1-5 Setup Example nSetup example A setup example of input / output port by port 2, port 3. Port 3 is input port. Port 2 in output port. Pull-up resistor is added to port 3, not to port 2. An example setup procedure, with description of each step is shown below. Setup Procedure Description (1) Control the I/O direction of port. P23DIR P23DIR (x'012') bp6-4 :P3DIR2-0 = 000 bp3-0 :P2DIR3-0 = 1111 (1) Set the P3DIR2-0 flag of theP23DIR register to "000" to set port 3 to input port. Set the P2DIR3-0 flag to "1111" to set port 2 to output port. (2) Add pull-up resistor. P23PLU P23PLU (x'022') bp6-4 :P3PLU2-0 = 111 bp3-0 :P2PLU3-0 = 0000 (2) Set the P3PLU2-0 flag of theP23PLU register to "111" to add pull-up resistor to port 3. Set the P2PLU3-0 flag to "0000" not to add pull-up resistor to port 2. Port 2 outputs data when lower 4 bits of port 2, port 3 data register (PORT23 PORT23) are written, and OUT instruction is executed. The status of port 3 can be input when upper 4 bits of port 2, port 3 data register (PORT23 PORT23) are read, and IN instruction is executed. III - 6 Overview Chapter 3 Ports 3-1-6 Control Registers I/O port control register includes a data register (PORTn) that outputs data, a direction control register (PnDIR) that controls I/O direction, a pull-up resistor control register (PnPLU) that controls pull-up resistor and output structure control register (PnSC) that controls output structure. Table 3-1-4 Register Address Port Control Registers List R/W Function Page PORT01 PORT01 R/W Port 0, port 1 data register III - 9 P01DIR P01DIR x'010' R/W Port 0, port 1 direction control register III - 9 x'028' R/W Port 1 output structure control register III - 9 PORT23 PORT23 x'002' R/W Port 2, port 3 data register III - 13 P23DIR P23DIR x'012' R/W Port 2, port 3 direction control register III - 13 P23PLU P23PLU x'022' R/W Port 2, port 3 pull-up resistor control register III - 13 P23SC P23SC Port 2 Port 3 x'000' P01SC P01SC Port 0 Port 1 x'02A' R/W Port 2, port 3 output structure control register III - 14 R/W : Readable / Writable Access to x'010' to x'02A' can be available only by 8-bit Overview III - 7 Chapter 3 Ports 3-2 Port 0, 1 3-2-1 Description nGeneral Port Setup Each bit can be set individually as either an input or output by the port 0, port 1 I/O direction control register (P01DIR P01DIR). The control flag of the port 0, port 1 direction control register (P01DIR P01DIR) is set to "1" for output mode, and "0" for input mode. To read input data of pin, set the control flag of the direction control register (P01DIR P01DIR) to "0", or set the output configuration to "N-ch open drain" by the output structure control register (P01SC P01SC) and set the port 0, port 1 data register (PORT01 PORT01) to "1" to select "Hi-z output", then read the value of the port 0, port 1 data register (PORT01 PORT01). To read input data, the pin's status should be read, not the value of the PORT01 PORT01 register. To output data to pin, set the control flag of the direction control register (P01DIR P01DIR) to "1" and write the value of the port 0, port 1 data register (PORT01 PORT01). Each bit can be set individually the output configuration by the port 1 output structure control register (P01SC P01SC). Set the control flag of the port 1 output structure control register (P01SC P01SC) to "1" for N-ch opendrain, and to "0" for CMOS output. The output structure of port 0 is N-ch open-drain. When the port 0, 1 register is written to "1", it becomes high impedance output. nSpecial Function Pin Setup P10 to P13 are used as PWM output pin (General port : at reset). Each bit can be set individually if the PWM output is enabled or not, by the buzzer output control register (BZCTR). When it is enabled, the conjunction of the port 1 output data and the timer output that the timer control input control register (MODCNT) selects, is output to pin. III - 8 Port 0, 1 Chapter 3 Ports 3-2-2 Registers 7 PORT01 PORT01 6 5 4 3 2 1 0 P13DATA P13DATA P12DATA P12DATA P11DATA P11DATA P10DATA P10DATA P03DATA P03DATA P02DATA P02DATA P01DATA P01DATA P00DATA P00DATA ( at reset : 11111111) Port 0 output data P0DATA 0 Low (VSS level) is output. 1 Hiz is output. *1 *1 The output configuration is N-ch open-drain. Port 1 output data P1DATA Low (VSS level) is output. 0 High (VDD level) is output. 1 At reading, pin's status is read. Port 0, Port 1 Data Register (PORT01 PORT01 : x'000', R/W) 7 P01DIR P01DIR 6 5 4 3 2 1 0 P1DIR3 P1DIR2 P1DIR1 P1DIR0 P0DIR3 P0DIR2 P0DIR1 P0DIR0 ( at reset : 00000000) Port 0 direction control P0DIR 0 Input mode (output Hiz) 1 Output mode *1 Port 1 direction control P1DIR 0 Input mode (output Hiz) 1 Output mode *1 *1 It becomes special port output, when the pin function is switched. Port 0, Port 1 Direction Control Register (P01DIR P01DIR : x'010', R/W) 7 P01SC P01SC 6 5 4 3 2 1 0 P1SC3 P1SC2 P1SC1 P1SC0 - - - - ( at reset : 0000XXXX 0000XXXX) P1SC Port 1 output structure control 0 Figure 3-2-1 CMOS output 1 N-ch open-drain Port 0, Port 1 Registers Port 0, 1 III - 9 Chapter 3 Ports 3-2-3 Block Diagram P00 Port output data P0DIR0 (x'000') Port input data Input instruction Figure 3-2-2 Block Diagram (P00) P01-P03 P01-P03 Port output data P0DIR1-3 (x'000') Port input data Input instruction Figure 3-2-3 Block Diagram (P01, P02, P03) PWMEn PWM output Port output data P10-P13 P10-P13 Output structure control register (P01SC P01SC) Direction control register (P01DIR P01DIR) Port input data Input instruction Figure 3-2-4 III - 10 Port 0, 1 Block Diagram (P10, P11, P12, P13) Chapter 3 Ports 3-3 Port 2, 3 3-3-1 Description nGeneral Port Setup Each bit can be set individually as either an input or output by the port 2, port 3 I/O direction control register (P23DIR P23DIR). The control flag of the port 2, port 3 direction control register (P23DIR P23DIR) is set to "1" for output mode, and "0" for input mode. To read input data of pin, set the control flag of the direction control register (P23DIR P23DIR) to "0" or set the output configuration to "N-ch open drain" by the output structure control register (P23SC P23SC) and set the port 2, port 3 data register (PORT23 PORT23) to "1" to select "Hi-z output", then read the value of the port 2, port 3 data register (PORT23 PORT23). To read input data, the pin's status should be read, not the value of the PORT23 PORT23 register. To output data to pin, set the control flag of the direction control register (P23DIR P23DIR) to "1" and write the value of the port 2, port 3 data register (PORT23 PORT23). Each bit can be set individually if pull-up resistor is added or not, by the pull-up resistor control register (P23PLU P23PLU). Set the control flag of the pull-up resistor control register (P23PLU P23PLU) to "1" to add pull-up resistor. Each bit can be set individually the output configuration by the port 1 output structure control register (P23SC P23SC). Set the control flag of the port 1 output structure control register (P23SC P23SC) to "1" for N-ch opendrain, and to "0" for CMOS output. nSpecial Function Pin Setup P20 to P23 are used as analog input pin (AD0 to AD3) (General port : at reset). Set pin to input mode by the port 2, port 3 direction control register (P23DIR P23DIR) and set the port 2, port 3 output structure control register (P23PLU P23PLU) to "0" to select pull-up resistor "OFF". P30 is used as system clock synchronous output (NSYNC) (General port : at reset). NSYNC output outputs the synchronous signal of the system clock at internal reset. P31 is used as interrupt input (NIRQ), AC zero-cross detection input (ACZ) (General port : at reset). NIRQ is input pin of interrupt 1. Set P31 to input mode. At operation, the initial status is P31, but the ACZCNT register can switch NSYNC output / port data output. AC zero-cross detection input (ACZ) is input pin of AC zero-cross circuit. ACZCNT register can switch port input data / ACZ input. Port 2, 3 III - 11 Chapter 3 Ports P32 is used as timer output (TCO), and as buzzer output (BZ) (General port : at reset). TCO is timer output pin. TCOCNT register can switch timer output / port data output. BZ is buzzer output pin. BZCTR register can switch buzzer output / port data output. Also, P30, P31 and P32 are used as key interrupt. When key interrupt input is used, enable key interrupt by the key interrupt control register 1 (KEYCNT). Set pin to input mode by the port 2, 3 direction control register (P23DIR P23DIR), and add pull-up resistor if necessary. III - 12 Port 2, 3 Chapter 3 Ports 3-3-2 Registers 7 PORT23 PORT23 6 5 4 3 2 1 0 P32DATA P32DATA P31DATA P31DATA P30DATA P30DATA P23DATA P23DATA P22DATA P22DATA P21DATA P21DATA P20DATA P20DATA - ( at reset : X1111111 X1111111) Output data P2DATA 0 Low (VSS level) is output. 1 High (VDD level) is output. Output data P3DATA 0 Low (VSS level) is output. 1 High (VDD level) is output. At reading, pin's status is read. Port 2, Port 3 Data Register (PORT23 PORT23 : x'002', R/W) 7 P23DIR P23DIR 6 4 3 2 1 0 P3DIR2 - 5 P3DIR1 P3DIR0 P2DIR3 P2DIR2 P2DIR1 P2DIR0 ( at reset : X0000000 X0000000) P2DIR Port 2 direction control 0 Input mode (output Hiz) 1 Output mode *1 P3DIR Port 3 direction control 0 Input mode (output Hiz) 1 Output mode *1 *1 It becomes special port output, when the pin function is switched. Port 2, Port 3 Direction Control Register (P23DIR P23DIR : x'012', R/W) 7 P23PLU P23PLU - 6 5 4 3 2 1 P3PLU2 P3PLU1 P3PLU0 P2PLU3 P2PLU2 P2PLU1 0 P2LU0 ( at reset : X0000000 X0000000) P2PLU Port 2 pull-up control 0 Pull-up resistor OFF 1 Pull-up resistor ON *1 P3PLU Port 3 pull-up control 0 Pull-up resistor OFF 1 Pull-up resistor ON *1 *1 When 'L' outputs to pins, pull-up resistor is OFF on hardware. Port 2, Port 3 Pull-up Resistor Control Register (P23PLU P23PLU : x'022', R/W) Figure 3-3-1 Port 2, Port 3 Registers (1/2) Port 2, 3 III - 13 Chapter 3 Ports 7 P23SC P23SC 6 5 4 3 2 1 0 - P3SC2 P3SC1 P3SC0 P2SC3 P2SC2 P2SC1 P2SC0 ( at reset : X0000000 X0000000) Port 2 output structure control P2SC 0 CMOS output 1 N-ch open-drain Port 3 output structure control P3SC 0 CMOS output 1 N-ch open-drain Port 2, Port 3 Output Structure Control Register (P23SC P23SC : x'02A', R/W) Figure 3-3-2 III - 14 Port 2, 3 Port 2, Port 3 Registers (2/2) Chapter 3 Ports 3-3-3 Block Diagram Pull-up control (P2PLU0-3) Port output data P20-P23 P20-P23 Output structure control register (P2SC0-3) Direction control register (P2DIR0-3) Port input data Input instruction Analog input data Figure 3-3-3 NSYNC output MUX Port output data Block Diagram (P20, P21, P22, P23) Pull-up control (P3PLU0) NSYNCS RESET P30 Output structure control register (P3SC0) Direction control register (P3DIR0) RESET Port input data key0 input RESET At internal reset : L After reset release : H Figure 3-3-4 Block Diagram (P30) Port 2, 3 III - 15 Chapter 3 Ports Pull-up control (P3PLU1) Port output data P31 Output structure control register (P3SC1) Direction control register (P3DIR1) ACZ interrupt AC zero-cross detection circuit MUX Port input data RESET At internal reset : L After reset release : H NIRQ input ACZ1IN key1 input Figure 3-3-5 Block Diagram (P31) Pull-up control (P3PLU2) TCO/BZ output MUX Port output data P32 TCOE Output structure control register (P3SC2) Direction control register (P3DIR2) Port input data key2 input RESET At internal reset : L After reset release : H Figure 3-3-6 III - 16 Port 2, 3 Block Diagram (P32) 3 Chapter 4 Interrupts 4 Chapter 4 Interrupts 4-1 Overview 4-1-1 Functions This LSI has interrupt 1 (IRQ 1), interrupt 2 (IRQ 2) and interrupt 3 (IRQ 3). Interrupt controller stops the executing program flow by the interrupt request, and, at that time, push program counter (PC) and flag status (FS) to the stack, and controls the execution starting of the interrupt service routine depending on each interrupt factor. JMP instruction at the starting address can specify the head address of the interrupt service routine. Table 4-1-1 Interrupt Service Routine Starting Address Interrupt factor (CPU reset) Interrupt 1 Interrupt 2 Interrupt 3 Vector address (RESET) (IRQ1) (IRQ2) (IRQ3) x'000' x'00A' x'00C' x'00E' Priority High Low Interrupt is accepted by the interrupt controller, if only both of the interrupt request flag (IE) and the interrupt enable flag (IF) are set. Once an interrupt is accepted, the interrupt service routine is executed. But other interrupt enable flag is not masked. If multiple interrupts are accepted at the same time, the execution is done in order of priority decided in the hardware. The highest priority is interrupt 1 (IRQ1), then interrupt 2 (IRQ2), then interrupt 3 (IRQ3). Table 4-1-2 shows the program example of interrupt enable , disable. Table 4-1-2 Program Example for Interrupt Setup setup interrupt IRQ1 IRQ2 IRQ3 disable enable EDI EDI EDI 0,4 0,2 0,1 EDI EDI EDI 4,0 2,0 1,0 Interrupt request flag (IF) is set to "1" by an interrupt request, and cleared to "0" by the interrupt acceptance. This flag is managed by hardware, but can be reset by software. IRQ mode register (IRQM) can reset the request flag. Interrupt enable flag (IE) is the flag that enables interrupts in the group. This flag is valid when it is "1". IV - 2 Overview Chapter 4 Interrupts 4-1-2 Block Diagram EDI instruction (enable / disable) IRQ2 3 IRQ1SE0 edge switch NIRQ input timer 2 interrupt timer 3 interrupt MUX mask circuit 3 mask circuit IRQ3 mask circuit MUX interrupt enable / disable circuit interrupt IRQ1 MASKIR1 P30 P31 key interrupt P32 IRQ3S1 MASKIR3 IRQ3S0 KEY * EN IRQM register (IF clear flag) edge switch ACZ interrupt IRQ3SE Figure 4-1-1 Interrupt Block Diagram Overview IV - 3 Chapter 4 Interrupts 4-1-3 Operation nInterrupt Processing Sequence For interrupts other than reset input, the interrupt processing sequence consists of interrupt request, interrupt acceptance, and hardware processing. After acceptance, the program counter (PC) and the flag status (FS) are saved onto the stack, and execution branches to the starting address specified by the corresponding interrupt vector. After the interrupt service routine, the program counter and the flag status are restored the contents to the point at which execution was interrupted. (3) Interrupt serice routine Main program (2) Hardware processing Save up PC, FS Interrupt request flag and interrupt enable flag are cleared at head. (1) Interrupt 4 machine cycles 4 machine cycles (4) (5) Restart Hardware processing Restore PSW, FS up. Figure 4-1-2 IV - 4 Overview Interrupt Processing Sequence Chapter 4 Interrupts nInterrupt Acceptance Operation The interrupt service routine is started when the interrupt is accepted by branching the program to the head of the interrupt service routine, after an interrupt factor is generated. First of all, if an interrupt factor is generated, the interrupt request flag (IE) with the corresponding level is set. At that time, if the interrupt enable flag is set and it is corresponded to the IF flag, the generated interrupt factor can be accepted. Acceptance operation is similar to the operation on CALL instruction. On the acceptance cycle, the program counter (PC) and the flag status (FS) are written to the stack. (They are pushed onto the stack.) Then, the starting address of the interrupt service routine corresponded to the each factor is set to the program counter. And, reset the IE flag and IF flag, with the corresponded level to the interrupt acceptance. Each interrupt service routine should be used with JMP instruction at the starting address of the program, if necessary. main program 10 main program 11 main program 12 the start of the interrupt service routine *1) interrupt program 1 interrupt program 2 *2) RETI main program 13 the end of the routine main program 14 main program 15 *1) *2) Figure 4-1-3 The starting address of the interrupt service routine is set to PC, here. Also, PC and FS of main program is pushed to the stack. PC and FS of the stacked area are popped. Interrupt Operation Overview IV - 5 Chapter 4 Interrupts ex. IRQ2 absolute address x'000C' JMP Figure 4-1-4 LABEL LABEL: PSHXY PSHEA interrupt service routine POPEA POPXY EDI 0,2 RETI Interrupt Sequence Example nInterrupt return operation RETI instruction (Return from Interrupt) is used on return operation to the former program. This instruction is similar to the RET instruction (RET) that is used on return operation from subroutine. RETI instruction return the contents of the program counter (PC) and the flag status (FS), that are pushed onto the stack area (RAM). Then, the program is returned to the status before the interrupt is generated. For interrupt response speed, it takes 4 cycles after the interrupt factor is generated till the interrupt is accepted. If there is EDI instruction on the head address of the interrupt service routine, 3 to 4 machine cycles interrupt is disabled. IV - 6 Overview Chapter 4 Interrupts nStack at interrupt Stack level at acceptance and at recover are changed as much as the program counter (PC) and the flag status (FS) are pushed or popped. At normal interrupt, PC and FS are pushed so that 4 nibble of the stack area (RAM) is needed. Therefore, the value of SP is on the decrement for 4 at acceptance and on the increment for 4 at recover. Recover operation is done by RETI instruction. RETI instruction restore the contents of FS, PC that are pushed onto the stack area (RAM) and the exclusive stack area on the acceptance cycle. After the value of the stack area that SP indicates are read out, SP is on the increment. Address Address C1-C0 C1-C0 FB-FA FD-FC FF-FE FB-FA PCm FS PCl PCh FD-FC FF-FE RAM area RAM area : the address that SP indicates. Figure 4-1-5 Operation of Stack Pointer Overview IV - 7 Chapter 4 Interrupts nInterrupt Acceptance, Start and Finish The interrupt acceptance is not available at the following timing. (1) During interrupt is disabled. (2) At the 1st cycle of 2 cycles instruction. (3) At the 1st, 2nd cycle of 3 cycles instruction. (4) When the interrupt factor is generated in execution of EDI instruction, interrupt acceptance is disabled till the next instruction is completed. 1 cycle EDI instruction 1 instruction *1 interrupt request No acceptance (5) The interrupt acceptance is disabled after the interrupt is accepted till 4 cycles are completed. Also, if EDI instruction comes after that, the acceptance is disabled till EDI instruction and the next instruction are completed. 1 cycle 1 cycle acceptance JMP instruction, etc acceptance no acceptance the end of 4 cycles JMP instruction EDI instruction an instruction *1 no acceptance the end of 4 cycles 1 cycle acceptance 1 cycle instruction 2 cycles instruction no acceptance the end of 4 cycles *1 IV - 8 At 1 cycle instruction, the acceptance is disabled till 1 cycle instruction is completed. At 2 cycles instruction, the acceptance is disabled till 2 cycles instruction is completed. At 3 cycles instruction, the acceptance is disabled till 3 cycles instruction is completed. Overview Chapter 4 Interrupts Here is the example for acceptance operation. £When the interrupt factor is generated in execution of 2 cycles instruction, the interrupt acceptance is started after 2 cycles instruction is completed. 1 cycle 2 cycles instruction *2 JMP instruction, etc interrupt request acceptance service routine starts £When the interrupt factor is generated in execution of 3 cycles instruction, the interrupt acceptance is started after 3 cycles instruction is completed. 1 cycle 3 cycles instruction *2 JMP instruction, etc interrupt request acceptance service routine starts £When the interrupt factor is generated in execution of EDI instruction and the next instruction (1, 2, or 3 cycles instruction), the interrupt acceptance is started after the instruction (max. 5 cycles) is completed. 1 cycle EDI instruction 2 cycles instruction *2 JMP instruction, etc interrupt request *2 acceptance service routine starts 1. The contents of PC and FS in main program are pushed to the stack area. 2. The starting address of the interrupt service routine is set to PC. 3. IF and IE of the accepted interrupt are reset. Overview IV - 9 Chapter 4 Interrupts nInterrupt Acceptance, Start and Finish (at multiple interrupts) Here is the example of acceptance at multiple interrupts. £When the interrupt factor is generated in execution of instruction at the beginning of the interrupt service routine, the interrupt acceptance is started after the instruction is completed (except when the next instruction to JMP instruction is EDI instruction.). 1 cycle no acceptance no acceptance interrupt request 2 cycles instruction *2 JMP instruction *2 JMP instruction interrupt request acceptance service routine acceptance starts service routine starts £When the interrupt factor is generated in execution of instruction at the beginning of the interrupt service routine (Instructions is JMP + EDI), the interrupt acceptance is started after the next instruction to EDI is completed. 1 cycle no acceptance no acceptance interrupt request 2 cycles instruction *2 JMP instruction EDI instruction *3 2 cycles instruction *2 interrupt request acceptance service routine starts JMP instruction NOP acceptance service routine starts *2 1. The contents of PC and FS in main program are pushed to the stack area. 2. The starting address of the interrupt service routine is set to PC. 3. IF and IE of the accepted interrupt are reset. *3 EDI instruction that does not disable an interrupt. IV - 10 Overview Chapter 4 Interrupts £When two interrupt factors are generated at the same time, the interrupt with higher priority is accepted. 1 cycle no acceptance no acceptance 2 cycles instruction *2 JMP instruction disable EDI interrupt 2 enable EDI interrupt 2 *2 interrupt request JMP instruction acceptance (interrupt 1) (interrupt 1) service routine starts acceptance (interrupt 2) service routine starts (interrupt 1) interrupt request (interrupt 2) (interrupt 2) £When two interrupt factors are generated at the same time, the interrupt with higher priority is accepted. If the second interrupt is not disabled in the program, the operation is switched to accept the second one. 1 cycle no accpetance no accpetance 2 cycles instruction *2 except dsiable EDI interrupt 2 JMP instruction 2 cycles instruction *2 interrupt request (interrupt 1) JMP instruction acceptance (interrupt 1) service routine start (interrupt 1) interrupt request (interrupt 2) *2 acceptance (interrupt 2) service routine start Acceptance of interrupt 2 is started here, if the instruction after JMP instruction is any instruction except for EDI instruction. (interrupt 2) 1. The contents of PC and FS in main program are pushed to the stack area. 2. The starting address of the interrupt service routine is set to PC. 3. IF and IE of the accepted interrupt are reset. This example shows the case when the interrupt 2 is not disabled after the interrupt with higher priority (the interrupt 1) is accepted first. Therefore, during the service routine of the interrupt 1, only 3 instructions (JMP, EDI, 2 cycles instruction) are executed, then the operation is switched to the acceptance of the interrupt 2. Overview IV - 11 Chapter 4 Interrupts £When an interrupt factor with high priority is generated at the acceptance operation (at 1st cycle), it is regarded as a multiple interrupt, and the interrupt with higher priority is accepted. 1