FEDL9475-01 ML9475 QFP56-P-910-0 65-2K SEG40 SEG34 SEG33 SEG10 SEG32 SEG11

Issue Date: Mar. 1, 2010 ML9475 1/3 or 1/4 Duty, 40-Output LCD Driver GENERAL DESCRIPTION The ML9475 is an LCD driver for dynamic

FEDL9475-01 FEDL9475-01 Issue Date: Mar. 1, 2010 ML9475 ML9475 1/3 or 1/4 Duty, 40-Output LCD Driver GENERAL DESCRIPTION The ML9475 ML9475 is an LCD driver for dynamic display. It has a function to switch between 1/3 and 1/4 duty. When 1/4 duty is selected, an LCD of up to 160 segments can be driven directly; when 1/3 duty is selected, an LCD of up to 120 segments can be driven directly. FEATURES · · · · · · · · Logic power supply voltage : 2.7 to 3.6 V, 4.5 to 5.5 V Driver power supply voltage : 3.5 to 5.5 V Operating temperature : -40 to +105°C 40 segment outputs 1/4 duty : Up to 160 segments can be displayed. 1/3 duty : Up to 120 segments can be displayed. Serially interfaces with the CPU using the three signal lines of LOAD, DATA_IN, and CLOCK Built-in RC oscillator circuit for LCD AC drive (the CLKSEL pin allows selecting an external clock input) Built-in voltage-dividing resistor for bias voltage generation Package : 56-pin plastic QFP (QFP56-P-910-0 QFP56-P-910-0.65-2K 65-2K) 1/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 BLOCK DIAGRAM SEG1 SEG40 SEG40 DVDD 40-Dot Segment Driver Bias Res. 40-Ch Data Selector 40 TEST 40-Bit Latch4 LOAD 40 40-Bit Latch3 40 40-Bit Latch2 40 40-Bit Latch1 LATCH SELECTOR 40 DATA_IN 46(40 + 6)-bit Shift Register CLOCK OSC OSC TIMING GENERATOR COM1 CLKSEL 3/4SEL COMMON Driver COM2 COM3 COM4 RESET LVDD VSS 2/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 COM1 COM2 COM3 COM4 CLKSEL VSS OSC LVDD 3/4SEL TEST RESET NC DATA_IN CLOCK 56 55 54 53 52 51 50 49 48 47 46 45 44 43 PIN CONFIGURATION (TOP VIEW) SEG8 8 35 SEG34 SEG34 SEG9 9 34 SEG33 SEG33 SEG10 SEG10 10 33 SEG32 SEG32 SEG11 SEG11 11 32 SEG31 SEG31 SEG12 SEG12 12 31 SEG30 SEG30 SEG13 SEG13 13 30 SEG29 SEG29 SEG14 SEG14 14 29 SEG28 SEG28 28 SEG35 SEG35 SEG27 SEG27 36 27 7 SEG26 SEG26 SEG7 26 SEG36 SEG36 SEG25 SEG25 37 25 6 SEG24 SEG24 SEG6 24 SEG37 SEG37 SEG23 SEG23 38 23 5 SEG22 SEG22 SEG5 22 SEG38 SEG38 SEG21 SEG21 39 21 4 DVDD SEG4 20 SEG39 SEG39 SEG20 SEG20 40 19 3 SEG19 SEG19 SEG3 18 SEG40 SEG40 SEG18 SEG18 41 17 2 SEG17 SEG17 SEG2 16 LOAD SEG16 SEG16 42 15 1 SEG15 SEG15 SEG1 56-Pin Plastic QFP 3/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 PIN DESCRIPTION Symbol I/O OSC I/O DATA_IN I CLOCK I LOAD I TEST I CLKSEL I 3/4SEL I RESET I COM1 COM2 COM3 COM4 O SEG1 to SEG40 SEG40 O LVDD DVDD VSS - - - Description Pin for oscillation. Has a Schmitt circuit built in. An oscillator circuit can be configured by connecting one external resistor and one external capacitor. Since an oscillator circuit is susceptible to external noise, make the wiring between this pin and external components as short as possible. An external clock input can be selected by CLKSEL. The relationship between oscillation frequency fOSC and frame frequency fFRM is: fFRM = fOSC/24(*1) Serial data input pin. Has a Schmitt circuit built in. The LCD display is turned on when the input data signal is at a "H" level and turned off when the input data signal is at a "L" level. Shift clock input pin. Has a Schmitt circuit built in. Data to the DATA_IN pin is shifted in sync with the rising edges of the shift clock pulses. Load pulse input pin. Has a Schmitt circuit built in. Used to transfer serially input data to the display latch or write commands. IC test pin. Has a pull-down resistor built in. Leave this pin open or connect it to VSS when not used. OSC pin input switching pin. When using the built-in oscillator circuit, set this pin to a "L" level; when inputting an external clock, set this pin to a "H" level. While this pin is at a "H" level, the oscillator circuit connected is disabled. 1/3- or 1/4-duty switching input pin. When "H" level is input, 1/3 duty is selected and when "L" level is input, 1/4 duty is selected. Reset signal input pin for initializing the IC. Has a Schmitt circuit built in. This pin is enabled by setting it to "L" level. This pin has a built-in pull-up resistor. Normally, this pin, when connected with an external capacitor, performs power-on reset.(*2) Output pins for LCD display. Connect to the common pins of the LCD panel. - When 1/3 duty is selected: Common signals are outputted through the COM1, COM2, and COM3 pins. Leave the COM4 pin open. - When 1/4 duty is selected: Common signals are outputted through the COM1, COM2, COM3, and COM4 pins. Output pins for LCD display. Connect to the segment pins of the LCD panel. For the relationship between each output of these pins and data, see the section on "Data Structure." Logic power supply pin. LCD driver power supply pin. Ground pin. 4/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 *1: Oscillator circuit configuration LVDD RO OSC CO *2: Reset circuit configuration LVDD CRST RESET 5/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 ABSOLUTE MAXIMUM RATINGS Parameter Power supply voltage Symbol Condition Rating Unit LVDD, DVDD Ta = 25°C 0.3 to +6.5 V Input voltage VI Ta = 25°C 0.3 to LVDD+0.3 V Power dissipation Output current PD Ta 105°C 350 mW IO Ta = 25°C 2.0 to +2.0 mA TSTG 55 to +150 °C Storage temperature RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Range Unit Logic power supply voltage LVDD VSS= 0 V 2.7 to 3.6, 4.5 to 5.5 V LCD drive voltage DVDD VSS= 0 V 3.5 to 5.5 V CLOCK frequency fcp 0.01 to 2 MHz Operating temperature Ta 40 to +105 °C Recommended setting range for external parts (for oscillator circuit) Parameter (LVDD = 4.5 to 5.5 V) Unit Symbol Condition Min. Max. RO 20 82 Oscillator capacitor CO 0.01 0.047 F Frame frequency fFRM 14.6 451.0 Hz Oscillator resistor k The relationship between external oscillator resistor value, external oscillator capacitor value, and frame frequency is as follows: fFRM = fOSC / 24 fOSC = 1 / (device coefficient × external oscillator resistor value RO × external oscillator capacitor value CO) Device coefficient = 0.6±23% Parameter (LVDD = 2.7 to 3.6 V) Unit Symbol Condition Min. Max. RO 20 82 Oscillator capacitor CO 0.01 0.047 F Frame frequency fFRM 14.6 451.0 Hz Oscillator resistor k The relationship between external oscillator resistor value, external oscillator capacitor value, and frame frequency is as follows: fFRM = fOSC / 24 fOSC = 1 / (device coefficient × external oscillator resistor value RO × external oscillator capacitor value CO) Device coefficient = 0.6±23% 6/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 ELECTRICAL CHARACTERISTICS DC Characteristics Parameter Symbol VIH "H" input voltage VIHOSC VIL "L" input voltage VILOSC IIH1 "H" input current IIHOSC IIL1 "L" input current IIL2 IILOSC VOS0 Segment output voltage VOS1 VOS2 VOS3 VOC0 Common output voltage VOC1 VOC2 VOC3 Dynamic supply current *1 *2 *3 IDVDD+IL VDD (LVDD = 2.7 to 3.6 V, 4.5 to 5.5 V, DVDD = 3.5 to 5.5, Ta = 40 to +105°C) Applicable Condition Min. Max. Unit pin LVDD = 4.5 to 5.5V 0.8LVDD *1 LVDD = 2.7 to 3.6V 0.85LVDD 85LVDD LVDD = 4.5 to 5.5V LVDD V 0.8LVDD CLKSEL = "H" OSC LVDD = 2.7 to 3.6V 0.85LVDD 85LVDD CLKSEL = "H" LVDD = 4.5 to 5.5V 0.2LVDD *1 LVDD = 2.7 to 3.6V 0.15LVDD 15LVDD LVDD = 4.5 to 5.5V 0 V 0.2LVDD CLKSEL = "H" OSC LVDD = 2.7 to 3.6V 0.15LVDD 15LVDD CLKSEL = "H" VI = LVDD 1 A *2 VI = LVDD 1 A OSC CLKSEL = "H" VI = 0V 1 A *2 LVDD = 5V 0.009 0.045 mA VI = 0V RESET LVDD = 3V 0.004 0.030 mA VI = 0V VI = 0V 1 A OSC CLKSEL = "H" DVDD = 4.5V DVDD 0.8 V IO = 10A DVDD = 4.5V 2/3DVDD 0.8 2/3DVDD + 0.8 V SEG1 to IO = ±10A SEG40 SEG40 DVDD = 4.5V 1/3DVDD 0.8 1/3DVDD + 0.8 V IO = ±10A DVDD = 4.5V 0.8 V IO = 10A DVDD = 4.5V DVDD 0.77 V IO = 10A DVDD = 4.5V 2/3DVDD 2/3DVDD+0.77 V IO = ±10A COM1 to 0.77 COM4 DVDD = 4.5V 1/3DVDD 1/3DVDD+0.77 V IO = ±10A 0.77 DVDD = 4.5V 0.77 V IO = 10A LVDD, *3 0.5 mA DVDD CLOCK, LOAD, DATA_IN, RESET, 3/4SEL, and CLKSEL CLOCK, LOAD, DATA_IN, 3/4SEL, and CLKSEL CO = 0.022 F, RO = 33 k, no load 7/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 Switching Characteristics (Serial Interface) (LVDD = 2.7 to 3.6 V, 4.5 to 5.5 V, DVDD = 3.5 to 5.5 V, Ta = -40 to +105°C) Symbol Condition Min. Max. Unit fCP - 0.01 2.0 MHz Parameter Clock frequency Clock pulse width tWCP - 70 - ns Rise time, Fall time *4 tr, tf - - 3 s Data setup time tDSU - 50 - ns Data hold time tDHD - 50 - ns Load pulse width tWLD - 100 - ns Clock to load time tCL - 100 - ns Load to clock time tLC - 100 - ns *4 Applied to CLOCK pin tWCP tr VIH CLOCK tWCP tf VIH VIL VIL 1/fCP tDSU tDHD DATA_IN VIH VIL tWLD tCL LOAD VIH tLC VIL 8/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 Switching Characteristics (External Clock Input to OSC) Parameter OSC input frequency (LVDD = 2.7 to 3.6 V, 4.5 to 5.5 V, DVDD = 3.5 to 5.5 V, Ta = -40 to +105°C) Symbol Condition Min. Max. Unit fosc CLKSEL = "H" 0.5 10 kHz OSC rise time, fall time *5 trosc, tfOSC CLKSEL = "H" - 1 OSC "H" period tWHOSC CLKSEL = "H" 4 - s OSC "L" period tWLOSC CLKSEL = "H" 4 - s *5 s Applied to OSC pin 1/fOSC trosc OSC VIHOSC VILOSC tfosc tWHOSC VILOSC VIHOSC VILOSC tWLOSC 9/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 POWER-ON/OFF TIMING Voltage DVDD LVDD t t Time If LVDD is in the range of 0 V to LVDDmin, make sure that LVDD DVDD and t 0[ns] are satisfied. When performing power-on reset with a capacitor connected to the RESET pin, be careful about the relationship between the capacitance value and the rise time of the power supply. INITIALIZATION TIMING LVDD LVDDmin RESET VIL t1 Drive the RESET pin Low and hold it Low under the condition "t1 0[ns]" until LVDD reaches LVDDmin. The value of the current of the pull-up resistor is specified for RESET pin. The customer needs to select an external capacitor that meets the timing requirements shown above. 10/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 FUNCTIONAL DESCRIPTION Description of Operation · Display data input As described in the section on "Data Structure," display data consists of a data field, which corresponds to the LCD segments ON and OFF, and a command field, which indicates the input of display data. Set a value in each of bits C0 and C1 in the command field according to the common output that corresponds to the display data, and set a display data input command in the remaining four bits. Data that has been input to the DATA_IN pin is loaded into the shift register on the rising edges of the CLOCK pulses, transferred to the display data latch during the "H" level period of the LOAD pulse, and then output via the segment driver. CLOCK DATA_IN D1 D2 D3 D4 D38 D39 D40 C0 C1 C2 C3 C4 C5 LOAD Display output Old data New data 11/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 · Display ON, display OFF Display goes off when power-on reset is executed; therefore, to turn display on, write the display ON command (F5). The display OFF command (F4) is a command that makes all segments go off. By writing the display OFF command, the segments go off irrespective of display data. The display ON command (F5) is a command that clears a display off state. By writing the display ON command, display goes back to the previous state. CLOCK DATA_IN D1 D2 C4 C5 C2 C3 C4 C5 C2 C3 C4 C5 LOAD Display ON/OFF RESET Input of display data Write display ON command Write display OFF command 12/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 List of Commands Command name F0 F0' F1 C5 0 0 0 C4 0 0 0 C3 0 0 1 C2 0 1 0 C1 × × 0 1 F2 F3 0 0 1 1 0 1 × 0 × 0 1 F3' F4 F5 F6 F7 F8 0 1 1 1 1 1 1 0 0 1 0 1 1 1 1 0 0 1 1 0 1 × × × × × × × × × C0 × × 0 1 0 1 × 0 1 0 1 × × × × × × Description Disabled Disabled Display data input (corresponds to COM1) Display data input (corresponds to COM2) Display data input (corresponds to COM3) Display data input (corresponds to COM4) Disabled Disabled Disabled Disabled Disabled Disabled Display OFF Display ON Disabled Disabled Disabled ×: Don't care If a "Disabled" command is executed, no transfer is carried out from the shift register to the latch; however, data within the shift register will be rewritten. To transfer correct data to the latch, it is necessary to transfer data again using the F1 command. 13/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 Data Structure [Input data] First bit Corresponds to SEG40 SEG40 Corresponds to SEG1 C5 C4 C3 C2 Command C1 C0 D40 D39 D38 D3 D2 D1 LCD display data Note 1: The setting of command F4 or F5 becomes enabled by inputting only the four bits of C2 to C5. (No need to input D1 to D40, C0, or C1.) Note 2: If any dummy bits are required because of the transfer bit count, add them before the first bit. Note 3: Command execution depends on the value of bits C5 to C0 stored immediately before LOAD goes to a "H" level. 14/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 Common and Segment Output Waveforms 1/3 duty COM1 DVDD V1 V2 VSS COM2 DVDD V1 V2 VSS COM3 DVDD V1 V2 VSS SEG1 S E G 1 S E G 2 COM1 COM2 COM3 DVDD V1 V2 VSS SEG2 Display DVDD V1 V2 VSS 15/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 1/4 duty COM1 DVDD V1 V2 VSS COM2 COM3 COM4 DVDD V1 V2 VSS SEG2 S E G 2 DVDD V1 V2 VSS SEG1 S E G 1 DVDD V1 V2 VSS DVDD V1 V2 VSS Display DVDD V1 V2 VSS COM1 COM2 COM3 COM4 16/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 APPLICATION CIRCUIT COM1 1/4 duty LCD COM2 COM3 COM4 SEG1 SEG40 SEG40 SEG1 SEG40 SEG40 COM1 COM2 COM3 LOAD DATA_IN CPU CLOCK CLKSEL ML9475 ML9475 COM4 DVDD +5 V LVDD +5 V OSC 3/4SEL VSS RESET TEST 17/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 PACKAGE DIMENSIONS (Unit: mm) Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact OKI SEMICONDUCTOR's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 18/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 REVISION HISTORY Document No. Date Previous Edition FEDL9475-01 FEDL9475-01 Mar. 1, 2010 Page Current Edition Description Final edition 1 19/20 FEDL9475-01 FEDL9475-01 ML9475 ML9475 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. OKI SEMICONDUCTOR CO., LTD. assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by OKI SEMICONDUCTOR CO., LTD., authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2010 OKI SEMICONDUCTOR CO., LTD. 20/20