ML9051G PEDL9051G-01 COM47 SEG131 ML9050E COM10 COM11 COM12 COM13 COM14 COM15 - Datasheet Archive

 

ML9051G PEDL9051G-01 Issue Date: Jul. 23, 2002 Preliminary 132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays

 

OKI Semiconductor ML9051G ML9051G PEDL9051G-01 PEDL9051G-01 Issue Date: Jul. 23, 2002 Preliminary 132-Channel LCD Driver with Built-in RAM for LCD Dot Matrix Displays GENERAL DESCRIPTION The ML9051G ML9051G is an LSI for dot matrix graphic LCD devices carrying out bit map display. This LSI can drive a dot matrix graphic LCD display panel under the control of an 8-bit microcomputer (hereinafter described MPU). Since all the functions necessary for driving a bit map type LCD device are incorporated in a single chip, using the ML9051G ML9051G makes it possible to realize a bit map type dot matrix graphic LCD display system with only a few chips. Since the bit map method in which one bit of display RAM data turns ON or OFF one dot in the display panel, it is possible to carry out displays with a high degree of freedom such as Chinese character displays, etc. With one chip, it is possible to construct a graphic display system with a maximum of 49 × 132 dots. The display can be expanded further using two chips. However, the ML9051G ML9051G is not used in a multiple chip configuration when a line reversal drive is set. The ML9051G ML9051G is made using a CMOS process. Because it has a built-in RAM, low power consumption is one of its features, and is therefore suitable for displays in battery-operated portable equipment. The ML9051G ML9051G has 49 common signal outputs and 132 segment signal outputs and one chip can drive a display of up to 49 × 132 dots. FEATURES · Direct display of the RAM data using the bit map method Display RAM data "1" . Dot is displayed Display RAM data "0" . Dot is not displayed (during forward display) · Display RAM capacity 65 × 132 = 8580 bits · LCD Drive circuits 49 common outputs, 132 segment outputs · MPU interface: Can select an 8-bit parallel or serial interface · Built-in voltage multiplier circuit for the LCD drive power supply · Built-in LCD drive voltage adjustment circuit · Built-in LCD drive bias generator circuit · Can select frame reversal drive or line reversal drive by command · Built-in oscillator circuit (Internal RC oscillator/external clock input) · A variety of commands Read/write of display data, display ON/OFF, forward/reverse display, all dots ON/all dots OFF, set page address, set display start address, etc. · Power supply voltage Logic power supply: VDD-VSS = 3.7 V to 5.5 V Voltage multiplier reference voltage: VIN-VSS = 3.7 V to 5.5 V (2- to 4-time multiplier available) LCD Drive voltage: VBI-VSS = 6.0 to 18 V · Package: Gold bump chip (Bump hardness: Low, DV) · This device is not resistant to radiation and light. 1/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G COMS1 COMS0 COM47 COM47 COM0 SEG0 SEG131 SEG131 BLOCK DIAGRAM VDD V1 V3 COMMON Drivers SEGMENT Drivers V4 COMS V2 V5 VSS Display timing generator circuit Common Output state selection circuit Display data latch circuit VS1­ VC5+ VC6+ VOUT VIN VR I/O Buffer Power supply circuit VC4+ Page address circuit VC3+ Line address circuit VS2­ Display data RAM 65 × 132 Oscillator circuit Column address circuit VRS IRS HPM FRS FR CL DOF M/S CLS TEST0 TEST1 Bus holder Command decoder Status DB0 DB1 DB2 DB3 DB4 DB5 DB6(SCL) DB7(SI) RES P/ S WR(R/W) RD(E) A0 CS2 CS1 C86 MPU lnterface 2/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G ABSOLUTE MAXIMUM RATINGS VSS = 0 V Parameter Symbol Condition Rated value Unit Applicable pins Power supply voltage VDD Tj = 25°C ­0.3 to +7 V VDD Bias voltage VBI Tj = 25°C ­0.3 to +20 V V1 to V5 VOUT Tj = 25°C ­0.3 to +20 V VOUT 2-time multiplication ­0.3 to +5.5 3-time multiplication ­0.3 to +5.5 V VIN 4-time multiplication ­0.3 to +5.0 VI Tj = 25°C ­0.3 to VDD+0.3 V All inputs TSTG Chip ­55 to +125 °C - Applicable pins Voltage multiplier output voltage Voltage multiplier reference voltage Input voltage Storage temperature range VIN Tj:Chip surface temperature RECOMMENDED OPERATING CONDITIONS VSS = 0 V Parameter Symbol Condition Rated value Unit Power supply voltage VDD - 3.7 to 5.5 V VDD Bias voltage VBI - 6 to 18 V V1 to V5 2-time multiplication 3.7 to 5.5 3-time multiplication 3.7 to 5.5 V VIN 4-time multiplication 3.7 to 4.5 VOUT External input 6.0 to 18 V VOUT TJOP - ­40 to +85 °C - Voltage multiplier reference voltage Voltage multiplier output voltage Operating temperature range Note 1: VIN The electrical characteristics are influenced by COG trace resistance. This LSI always has to be evaluated before using. VOUT V1 to V5 VIN VCC VDD GND VSS System (MPU) Note 2: Note 3: Note 4: ML9051G ML9051G The voltages VDD, V1 to V5, and VOUT are values taking VSS = 0 V as the reference. The highest bias potential is V1 and the lowest is VSS. Always maintain the relationship V1 V2 V3 V4 V5 VSS among these voltages. 3/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G Note 5: When using an external power supply, follow the procedure for power application. When applying external power to the VOUT pin only, apply VOUT after VDD. When applying external power to the V1 pin only, apply V1 after VDD. When applying external power to the V1 pin to V5 pin, apply V1 to V5 after VDD. Note that the above (Note 4) must be satisfied including transient state at power application. Note 6: When using an external power supply, follow the procedure for power removal described below. When external power is in use for the VOUT pin only, remove VOUT after VDD. When external power is in use for the V1 pin only, remove V1 after VDD. When external power is in use for the V1 pin to V5 pin, remove V1 to V5 after VDD. Note that the above (Note 4) must be satisfied including transient state at power removal. 4/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G ELECTRICAL CHARACTERISTICS DC Characteristics [VSS = 0 V, VDD = 3.7 to 5.5 V, Tj =­40 to +85°C] Parameter Symbol Condition Min Typ Max Unit Applicable pins V *1 V *2 V *3 µA *4 *5 "H" Input voltage VIH 0.8 × VDD - VDD "L" Input voltage VIL 0 - 0.2 × VDD "H" Input voltage VIH 0.8 × VDD - VDD "L" Input voltage VIL 0 - 0.2 × VDD Hysteresis width V VDD = 5.0 V - 1.0 - "H" output voltage VOH IOH = ­0.5 mA 0.8 × VDD - - "L" output voltage VOL IOL = 0.5 mA - - 0.2 × VDD "H" Input current IIH VI = VDD ­1.0 - +1.0 "L" Input current IIL VI = 0 V ­3.0 - +3.0 - ­0.05 - %/°C V1 *6 10.63 10.85 11.07 V V1 3-time multiplication *7 13.0 - - V VOUT 4-time multiplication *8 15.9 - - V VOUT *9 0.6 - - V VOUT, V1 V1 output voltage temperature gradient V1 output voltage V1TC V1 Voltage multiplier output voltage VOUT VOUT - V1 voltage Vot1 LCD driver ON *1: *2: *3: *4: *5: *6: *7: *8: V1 = 12 V RON IO = ±50 µA Internal oscillation fOSC Tj = 25°C External input fEXT resistance Oscillator frequency Tj = 25°C - - 10 k SEG1 to 131, COMS0, COMS1, COM0 to 47 27 33 39 kHz *10 21 - 47 kHz 14 17 20 kHz CL*10 A0, DB0 to DB5, DB7 (SI), CS1, CS2, CLS, FR, M/S, C86, P/S, DOF, IRS, HPM Pins RD (E), WR (R/W), RES, CL, DB6 (SCL) Pins DB0 to DB7, FR, FRS, DOF, CL Pins A0, RD (E), WR (R/W), CS1, CS2, CLS, M/S, C86, P/S, RES, IRS, HPM Pins Applicable to the pins DB0 to DB5, DB6 (SCL), DB7 (SI), CL, FR, DOF in the high impedance state. Tj = 25°C, = 31, (1+Rb/Ra) = 4, VOUT = 13.5 V (External input), LCD drive output = no-load During high-power mode, VIN = 4.8 V, voltage multiplier capacitor C1 = 3.7 to 5.7 µF, voltage multiplier output load current I = 500 µA. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and V/F circuit, by command "2C". During high-power mode, VIN = 4.5 V, voltage multiplier capacitor C1 = 3.7 to 5.7 µF, voltage multiplier output load current I = 500 µA. Only a voltage multiplier circuit operates, not activating the voltage adjustment circuit and V/F circuit, by command "2C". 5/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor *9: *10: ML9051G ML9051G During high-power mode, V1 load current I = 400 µA. 8 V is externally input to VOUT. The voltage adjustment circuit and V/F circuit operate by command "2B". LCD output = no load See Table 1 for the relationship between the oscillator frequency and the frame frequency. Table 1. Relationship among the oscillator frequency (fOSC), display clock frequency (fLCDCK), and LCD frame frequency (fFR) Parameter ML9051G ML9051G When the internal oscillator is used When the internal oscillator is not used Display clock frequency LCD frame frequency (fLCDCK) (fFR) fOSC/8 fOSC/(8 × 49) External input (fLCDCK) fLCDCK/196 6/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G · Operating current consumption value (1) During display operation, internal power supply OFF (The current flowing through VDD with V1 to V5 externally applied when an external power supply is used, not including the current for the LCD drive) [VSS = 0 V, Tj = 25°C] Display mode Symbol All-white IDD Checker pattern IDD Condition Rated value Min Typ Max VDD = 5 V, V1- VSS = 11 V, no load - 25 50 VDD = 3.7 V, V1- VSS = 8 V, no load - 15 35 VDD = 5 V, V1- VSS = 11 V, no load - 25 50 VDD = 3.7 V, V1- VSS = 8 V, no load - 15 35 Unit µA µA (2) During display operation, internal power supply ON (Total of currents flowing through VDD and VIN) [VSS = 0 V, Tj = 25°C] Display mode Symbol Rated value Condition Min Typ Max Checker pattern IDDIN IDDIN Normal mode - 225 330 High-power mode - 515 790 Normal mode - 255 360 High-power mode - 605 890 High-power mode - 525 810 Frame reversal, VDD, VIN = 5 V, 3-time voltage multiplication V1 - VSS= 11 V, no load All-white Frame reversal, VDD, VIN = 5 V, 3-time voltage multiplication V1 - VSS= 11 V, no load Frame reversal, VDD, VIN = 3.7 V, 4-time voltage multiplication V1 - VSS= 8 V, no load 16-line reversal, VDD, VIN = 5 V, 3-time voltage multiplication V1 - VSS= 11 V, no load Normal mode - 295 430 High-power mode - 585 860 Frame reversal, VDD, VIN = 3.7 V, 4-time voltage multiplication V1 - VSS= 8 V, no load Normal mode - 325 515 High-power mode - 675 1030 High-power mode - 595 Unit 875 16-line reversal, VDD, VIN = 5 V, 3-time voltage multiplication V1 - VSS= 11 V, no load µA µA · Power save mode current consumption [VSS = 0 V, Tj = 25°C] Parameter Symbol Condition Sleep mode IDDS1 Standby mode IDDS2 Rated value Min Typ Max VDD = 3.7 V - 0.3 5 VDD = 3.7 V - 7 15 Unit µA 7/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G Parallel Interface Timing Characteristics · System bus Write characteristics 1 (80-series MPU) A0 VIH VIL VIH VIL tAW8 tAH8 CS1 (CS2 = "H") tCYC8 WR tCCLW VIH VIH VIH VIL VIL tCCHW tDS8 DB0 to DB7 (Write) · System bus tDH8 VIH VIL VIH VIL Read characteristics 1 (80-series MPU) A0 VIH VIL VIH VIL tAH8 tAW8 CS1 (CS2 = "H") tCYC8 RD tCCLR VIH VIL VIL VIH VIH tCCHR tOH8 tACC8 DB0 to DB7 (Read) VOH VOL VOH VOL 8/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G [VDD = 4.5 to 5.5 V, Tj = ­40 to +85°C] Parameter Symbol Condition Rated value Min Max Address hold time tAH8 5 - Address setup time tAW8 5 - System cycle time tCYC8 166 - Control L pulse width (WR) tCCLW 30 - Control L pulse width (RD) tCCLR 70 - Control H pulse width (WR) tCCHW 55 - Control H pulse width (RD) tCCHR 55 - tDS8 30 - Data hold time tDH8 10 - RD Access time tACC8 - 70 Output disable time tOH8 5 Unit 50 Data setup time CL = 100 pF ns [VDD = 3.7 to 4.5 V, Tj = ­40 to +85°C] Parameter Symbol Condition Rated value Min Max Address hold time tAH8 5 - Address setup time tAW8 5 - System cycle time tCYC8 300 - Control L pulse width (WR) tCCLW 60 - Control L pulse width (RD) tCCLR 120 - Control H pulse width (WR) tCCHW 60 - Control H pulse width (RD) Unit tCCHR 60 - Data setup time tDS8 40 - Data hold time tDH8 15 - RD Access time tACC8 - 140 Output disable time tOH8 10 ns 100 Note 1: Note 2: Note 3: CL = 100 pF The input signal rise and fall times are specified as 15ns or less. When using the system cycle time for fast speed, the specified values are (tr + tf) (tCYC8 ­ tCCLW ­ tCCHW) or (tr + tf) (tCYC8 ­ tCCLR ­ tCCHR). All timings are specified taking the levels of 20% and 80% of VDD as the reference. The values of tCCLW and tCCLR are specified during the overlapping period of CS1 at "L" (CS2 = "H") and the "L" levels of WR and RD, respectively. 9/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor · System bus ML9051G ML9051G Write characteristics 2 (68-series MPU) VIH VIL A0 VIL R/W VIH VIL tAW6 tAH6 VIL CS1 (CS2 = "H") tCYC6 tEWHW E VIL VIH VIH VIL VIL tEWLW tDS6 DB0 to DB7 (Write) · System bus tDH6 VIH VIL VIH VIL Read characteristics 2 (68-series MPU) A0 VIH VIL VIH VIL R/W VIH tAW6 tAH6 VIH CS1 (CS2 = "H") tCYC6 tEWHR E VIL VIH VIH VIL VIL tEWLR tOH6 tACC6 DB0 to DB7 (Read) VOH VOL VOH VOL 10/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G [VDD = 4.5 to 5.5 V, Tj = ­40 to +85°C] Parameter Symbol Condition Rated value Min Max Address hold time tAH6 5 - Address setup time tAW6 5 - System cycle time tCYC6 166 - Data setup time tDS6 30 - Data hold time tDH6 10 - Access time tACC6 - 70 Output disable time tOH6 10 50 Read tEWHR 70 Unit - Enable H pulse width Enable L pulse width CL = 100 pF Write tEWHW 30 - Read tEWLR 60 - Write tEWLW 60 ns - [VDD = 3.7 to 4.5 V, Tj = ­40 to +85°C] Parameter Symbol Address hold time Condition Rated value Max 5 tAH6 Min Unit - Address setup time tAW6 5 - System cycle time tCYC6 300 - Data setup time tDS6 40 - Data hold time tDH6 15 - Access time tACC6 - 140 Output disable time Enable H pulse width Enable L pulse width Note 1: Note 2: Note 3: tOH6 CL = 100 pF 10 100 Read tEWHR 120 - Write tEWHW 60 - Read tEWLR 60 - Write tEWLW 60 ns - The input signal rise and fall times are specified as 15ns or less. When using the system cycle time for fast speed, the specified values are (tr + tf) (tCYC6 ­ tEWLW ­ tEWHW) or (tr + tf) (tCYC6 ­ tEWLR ­ tEWHR). All timings are specified taking the levels of 20% and 80% of VDD as the reference. The values of tEWLW and tEWLR are specified during the overlapping period of CS1 at "L" (CS2 = "H") and the "H" level of E. 11/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G Serial Interface Timing Characteristics · Serial interface tCSS CS1 (CS2 = "1") tCSH VIL VIL tSAH tSAS VIH VIL A0 VIH VIL tSCYC SCL tSLW VIH tf VIL tSHW tr tSDS SI VIH VIH VIL VIL VIH VIL tSDH VIH VIL [VDD = 4.5 to 5.5 V, Tj = ­40 to +85°C] Parameter Symbol Condition Rated value Min Max 200 Unit - Serial clock period tSCYC SCL "H" Pulse width tSHW 75 - SCL "L" Pulse width tSLW 75 - Adress setup time tSAS 50 - Address hold time tSAH 100 - Data setup time tSDS 50 - Data hold time tSDH 50 - CS setup time tCSS 100 - CS hold time tCSH 100 - Note 1: Note 2: ns The input signal rise and fall times are specified as 15ns or less. All timings are specified taking the levels of 20% and 80% of VDD as the reference. 12/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G [VDD = 3.7 to 4.5 V, Tj = ­40 to +85°C] Parameter Symbol Rated value Condition Min Max Serial clock period tSCYC 250 - SCL "H" Pulse width tSHW 100 - SCL "L" Pulse width tSLW 100 - Address setup time tSAS 150 - Address hold time tSAH 150 - Data setup time tSDS 100 - Data hold time tSDH 100 - CS setup time tCSS 150 - CS hold time tCSH 150 Unit - Note 1: Note 2: ns The input signal rise and fall times are specified as 15ns or less. All timings are specified taking the levels of 20% and 80% of VDD as the reference. · Display control output timing VOH CL(OUT) tDFR VIH VIL FR [VDD = 4.5 to 5.5 V, Tj = ­40 to +85°C] Parameter FR Delay time Symbol Condition tDFR CL = 50 pF Rated value Min Typ Max - 10 40 Unit ns [VDD = 3.7 to 4.5 V, Tj = ­40 to +85°C] Parameter FR Delay time Note 1: Note 2: Symbol Condition tDFR CL = 50 pF Rated value Min Typ Max - 20 80 Unit ns All timings are specified taking the levels of 20% and 80% of VDD as the reference. Valid only when the device operates in master mode. 13/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G · Reset input timing tf tr tRW VIH VIH RES VIL VIL Internal state tR Being reset Reset complete [VDD = 4.5 to 5.5 V, Tj = ­40 to +85°C] Parameter Symbol Condition Rated value Reset "L" pulse width Typ Max tR Reset time Min - - 0.5 tRW 0.5 - - Unit µs [VDD = 3.7 to 4.5 V, Tj = ­40 to +85°C] Parameter Reset time Reset "L" pulse width Note 1: Note 2: Symbol Condition Rated value Min Typ Max tR - - 1 tRW 1 - - Unit µs The input signal rise and fall times (tr, tf) are specified as 15 ns or less. All timings are specified taking the levels of 20% and 80% of VDD as the reference. 14/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G PIN DESCRIPTION Function Pin name Number of pins I/O Description These are 8-bit bi-directional data bus pins that can be connected to 8-bit standard MPU data bus pins. When a serial interface is selected (P/S = "L"): DB0 to DB7 DB7: Serial data input pin (SI) 8 I/O DB6: Serial clock input pin (SCL) In this case, DB0 to DB5 will be in the high impedance state. DB0 to DB7 will all be in the high impedance state when the chip select is in the inactive state. Fix the DB0 to DB5 pins at "H" or "L" level. A0 1 I Normally, the lowest bit of the MPU address bus is connected and used for distinguishing between data and commands. A0 = "H": Indicates that DB0 to DB7 is display data. A1 = "L": Indicates that DB0 to DB7 is control data. RES CS1 CS2 1 I Initial setting is made by making RES = "L". The reset operation is made during the active level of the RES signal. 2 I These are the chip select signals. The Chip Select of the LSI becomes active when CS1 is "L" and also CS2 is "H" and allows the input/output of data or commands. The active level of this signal is "L" when connected to an 80-series MPU. This pin is connected to the RD signal of the 80-series MPU, and the data bus of the ML9051G ML9051G goes into the output state when this signal is "L". MPU Interface RD (E) 1 I The active level of this signal is "H" when connected to a 68-series MPU. This pin will be the Enable and clock input pin when connected to a 68-series MPU. When a serial interface is selected (P/S = "L"), fix this pin at "H" or "L" level. WR (R/W) The active level of this signal is "L" when connected to an 80-series MPU. This pin is connected to the WR signal of the 80-series MPU. The data on the data bus is latched into the ML9051G ML9051G at the rising edge of the WR signal. 1 I When connected to a 68-series MPU, this pin becomes the input pin for the Read/Write control signal. R/W = "H": Read, R/W = "L": Write When a serial interface is selected (P/S = "L"), fix this pin at "H" or "L" level. This is the pin for selecting the MPU interface type. C86 1 I C86 = "H": 68-Series MPU interface. C86 = "L": 80-Series MPU interface. 15/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor Function Pin name ML9051G ML9051G Number of pins I/O Description This is the pin for selecting parallel data input or serial data input. P/S = "H": Parallel data input. P/S = "L": Serial data input. MPU Interface The pins of the LSI have the following functions depending on the state of P/S input. P/S 1 I P/S Data/command Data Read/Write Serial clock "H" A0 DB0 to DB7 RD, WR - "L" A0 SI (D7) - SCL(DB6) During serial data input, it is not possible to read the display data in the RAM This is the pin for selecting whether to enable or disable the internal oscillator circuit for the display clock. Oscillator circuit CLS 1 I CLS = "H": The internal oscillator circuit is enabled. CLS = "L": The internal oscillator circuit is disabled (External input). When CLS = "L", the display clock is input at the pin CL. This is the pin for selecting whether master operation or slave operation is made towards the ML9051G ML9051G. During master operation, the synchronization with the LCD display system is achieved by inputting the timing signals necessary for LCD display. M/S = "H": Master operation Display timing generator circuit M/S = "L": Slave operation M/S 1 I The functions of the different circuits and pins will be as follows depending on the states of M/S and CLS signals. M/S "H" "L" Oscillator Power circuit supply circuit "H" Enabled "L" Disabled "H" "L" CLS CL FR FRS DOF Enabled Output Output Output Output Enabled Input Output Output Output Disabled Disabled Input Input Output Input Disabled Disabled Input Input Output Input 16/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor Function Pin name ML9051G ML9051G Number of pins I/O Description This is the display clock input/output pin. The function of this pin will be as follows depending on the states of M/S and CLS signals. M/S CL 1 I/O "H" "L" CLS CL "H" Output "L" Input "H" Input "L" Input When the ML9051G ML9051G is used in the master/slave mode, the corresponding CL pin has to be connected. Display timing generator circuit This is the input/output pin for LCD display frame reversal signal. M/S = "H": Output FR 1 I/O M/S = "L": Input When the ML9051G ML9051G is used in the master/slave mode, the corresponding FR pin has to be connected. This is the blanking control pin for the LCD display. M/S = "H": Output DOF 1 I/O M/S = "L": Input When the ML9051G ML9051G is used in the master/slave mode, the corresponding DOF pin has to be connected. FRS 1 O This is the output pin for static drive. This pin is used in combination with the FR pin. This is the pin for selecting the resistor for adjusting the voltage V1. IRS = "H": The internal resistor is used. IRS Power supply circuit 1 I IRS = "L": The internal resistor is not used. The voltage V1 is adjusted using the external potential divider resistors connected to the pins VR. This pin is effective only in the master operation. This pin is tied to the "H" or the "L" level during slave operation. This is the power control pin for the LCD drive power supply circuit. HPM = "H": Normal mode HPM 1 I HPM = "L": High power mode This pin is effective only during master operation mode. This pin is tied to the "H" or the "L" level during slave operation. VDD 13 - These pins are tied to the MPU power supply pin VCC. VSS 9 - These are the 0 V pins connected to the system ground (GND). VIN 4 - These are the reference power supply pins of the voltage multiplier circuit for driving the LCD. 17/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G Pin name Number of pins I/O VRS 2 - These are the test pins for the LCD power supply voltage adjustment circuit. Leave these pins open. VOUT Function 2 I/O These are the output pins during voltage multiplication. Connect a capacitor between these pins and VSS. Description These are the multiple level power supply pins for the LCD power supply. The voltages specified for the LCD cells are applied to these pins after resistor network voltage division or after impedance transformation using operational amplifiers. The voltages are specified taking VSS as the reference, and the following relationship should be maintained among them. V1 V2 V3 V4 V5 VSS V1 V2 V3 10 I/O V4 V5 Master operation: When the power supply is ON, the following voltages are applied to V2 to V5 from the built-in power supply circuit. The selection of voltages is determined by the LCD bias set command. ML9050E ML9050E V2 5/6 × V1 V3 6/8 × V1 4/6 × V1 V4 2/8 × V1 2/6 × V1 V5 Power supply circuit 7/8 × V1 1/8 × V1 1/6 × V1 Voltage adjustment pins. Voltages between V1 and VSS are applied using a resistance voltage divider. VR 2 I These pins are effective only when the internal resistors for voltage V1 adjustment are not used (IRS = "L"). Do not use these pins when the internal resistors for voltage V1 adjustment are used (IRS = "H"). VS1­ 2 O These are the pins for connecting the negative side of the capacitors for voltage multiplication. Connect capacitors between these pins and VC3+, VC5+. VS2­ 2 O These are the pins for connecting the negative side of the capacitors for voltage multiplication. Connect capacitors between these pins and VC4+, VC6+. VC3+ 2 O These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS1­ and these pins. VC4+ 2 O These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS2­ and these pins. 18/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor Function Power supply circuit ML9051G ML9051G Pin name Number of pins I/O VC5+ 2 O Description These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS1­ and these pins. VC6+ 2 O These are the pins for connecting the positive side of the capacitors for voltage multiplication. Connect capacitors between VS2­ and these pins. These are the LCD segment drive outputs. One of the levels among V1, V3, V4, and VSS is selected depending on the combination of the display RAM content and the FR signal Output voltage RAM Data LCD Drive output V1 H L VSS V4 H V3 V1 L O H L V4 Power save 132 H L SEG0 to SEG131 SEG131 FR - Forward display Reverse display V3 VSS VSS The output voltage is VSS when the Display OFF command is executed. These are the LCD common drive outputs. One of the levels among V1, V2, V5, and VSS is selected depending on the combination of the scan data and the FR signal. Scan data Output voltage H COM0 to COM47 COM47 FR H VSS L V1 H V2 L L V5 Power save O H L 48 - VSS The output voltage is VSS when the Display OFF command is executed. These are the common output pins only for indicators. Both pins output the same signal. Leave these pins open when they are not used. The same signal is output in both master and slave operation modes. COMS0 COMS1 Test pin - 2 TEST0 1 I TEST1 1 O These are the pins for testing the IC chip. Leave these pins open during normal use. DUMMY 72 - Leave this pin open. O 19/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G FUNCTIONAL DESCRIPTION MPU Interface MPU Read mode Write mode Pin RD = "L" Pin R/W = "L" Pin E = "H" 68-Series Pin WR = "L" Pin R/W = "H" 80-Series Pin E = "H" In the case of the 80-series MPU interface, a command is started by applying a low pulse to the RD pin or the WR pin. In the case of the 68-series MPU interface, a command is started by applying a high pulse to the E pin. · Selection of interface type The ML9051G ML9051G carries out data transfer using either the 8-bit bi-directional data bus (DB0 to DB7) or the serial data input line (SI). Either the 8-bit parallel data input or serial data input can be selected as shown in Table 2 by setting the P/S pin to the "H" or the "L" level. Table 2 Selection of interface type (parallel/serial) P/S CS1 CS2 A0 RD WR C86 D7 D6 DB0 to DB5 H: Parallel input CS1 CS2 A0 RD WR C86 D7 D6 L: Serial input CS1 CS2 A0 - - - SI SCL DB0 to DB5 - A hyphen (-) indicates that the pin can be tied to the "H" or the "L" level. · Parallel interface When the parallel interface is selected, (P/S = "H"), it is possible to connect this LSI directly to the MPU bus of either an 80-series MPU or a 68-series MPU as shown in Table 3. depending on whether the pin C86 is set to "H" or "L". Table 3 Selection of MPU during parallel interface (80­/68­series) CS1 CS2 A0 H: 68-Series MPU bus CS1 CS2 L: 80-Series MPU bus CS1 CS2 C86 RD WR DB0 to DB7 A0 E R/W DB0 to DB7 A0 RD WR DB0 to DB7 The data bus signals are identified as shown in Table 4 below depending on the combination of the signals A0, RD (E), and WR (R/W) of Table 3. Table 4 Identification of data bus signals during parallel interface Common 68-Series A0 R/W RD 80-Series WR Display data read 1 1 0 1 Display data write 1 0 1 0 Status read 0 1 0 1 Control data write (command) 0 0 1 0 20/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G Serial Interface When the serial interface is selected (P/S = "L"), the serial data input (SI) and the serial clock input (SCL) can be accepted if the chip is in the active state (CS1 = "L" and CS2 = "H"). The serial interface consists of an 8-bit shift register and a 3-bit counter. The serial data is read in from the serial data input pin in the sequence DB7, DB6, . , DB0 at the rising edge of the serial clock input, and is converted into parallel data at the rising edge of the 8th serial clock pulse and processed further. The identification of whether the serial data is display data or command is judged based on the A0 input, and the data is treated as display data when A0 is "H" and as command when A0 is "L". The A0 input is read in and identified at the rising edge of the (8 × n) th serial clock pulse after the chip has become active. Fig. 1 shows the signal chart of the serial interface. (When the chip is not active, the shift register and the counter are reset to their initial states. No data read out is possible in the case of the serial interface. It is necessary to take sufficient care about wiring termination reflection and external noise in the case of the SCL signal. We recommend verification of operation in an actual unit.) CS1 CS2 SI SCL DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 DB5 DB4 DB3 DB2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A0 Fig. 1 Signal chart during serial interface · Chip select The ML9051G ML9051G has the two chip select pins CS1 and CS2, and the MPU interface or the serial interface is enabled only when CS1 = "L" and CS2 = "H". When the chip select signals are in the inactive state, the DB0 to DB7 lines will be in the high impedance state and the inputs A0, RD, and WR will not be effective. When the serial interface has been selected, the shift register and the counter are reset when the chip select signals are in the inactive state. · Accessing the display data RAM and the internal registers Accessing the ML9051G ML9051G from the MPU side requires merely that the cycle time (tCYC) be satisfied, and high speed data transfer without requiring any wait time is possible. Also, during the data transfer with the MPU, the ML9051G ML9051G carries out a type of pipeline processing between LSIs via a bus holder associated with the internal data bus. For example, when the MPU writes data in the display data RAM, the data is temporarily stored in the bus holder, and is then written into the display data RAM before the next data read cycle. Further, when the MPU reads out data in the display data RAM, first a dummy data read cycle is carried out to temporarily store the data in the bus holder which is then placed on the system bus and is read out during the next read cycle. There is a restriction on the read sequence of the display data RAM, which is that the read instruction immediately after setting the address does not read out the data of that address, but that data is output as the data of the address specified during the second data read sequence, and hence care should be taken about this during reading. Therefore, always one dummy read is necessary immediately after setting the address or after a write cycle: (The status read cannot use dummy read cycles.) This relationship is shown in Figs 2(a) and 2(b). 21/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G · Data write MPU WR DATA Dn Dn + 1 Dn + 2 Dn + 3 Internal timing Latch Dn BUS Holder Dn + 1 Dn + 2 Dn + 3 Write Signal Fig. 2(a) Write sequence of display data RAM · Data read MPU WR RD DATA N unknown Dn Dn + 1 Internal timing Address Preset Read Signal Column Address Preset N Dn unknown BUS Holder Address Set N Increment N + 1 Data Read (Dummy) N+2 Dn + 1 Data Read Dn Dn + 2 Data Read Dn + 1 Fig. 2(b) Read sequence of display data RAM Dn = Data N = Address data · Busy flag The busy flag being "1" indicates that the ML9051G ML9051G is carrying out reset operations, and hence no instruction other than a status read instruction is accepted during this period. The busy flag is output at pin DB7 when a status read instruction is executed. 22/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G Display Data RAM · Display data RAM This is the RAM storing the dot data for display and has an organization of 65 (8 pages × 8 bits +1) × 132 bits. It is possible to access any required bit by specifying the page address and the column address. Since the display data DB7 to DB0 from the MPU corresponds to the LCD display in the direction of the common lines as shown in Fig. 3, there are fewer restrictions during display data transfer when the ML9051G ML9051G is used in a multiple chip configuration, thereby making it easily possible to realize a display with a high degree of freedom. Also, since the display data RAM read/write from the MPU side is carried out via an I/O buffer, it is done independent of the signal read operation for the LCD drive. Consequently, the display is not affected by flickering, etc., even when the display data RAM is accessed asynchronously during the LCD display operation. DB0 0 1 1 1 . 0 COM0 . DB1 1 0 0 0 . 0 COM1 . DB2 0 0 0 0 . 0 COM2 . DB3 0 1 1 1 . 0 COM3 . DB4 1 0 0 0 . 0 COM4 . Display data RAM LCD Display Fig. 3 Relationship between display data RAM and LCD display · Page address circuit The page address of the display data RAM is specified using the page address set command as shown in Fig. 4. Specify the page address again when accessing after changing the page. The page address 8 (DB3, DB2, DB1, DB0 1, 0, 0, 0) is the RAM area dedicated to the indicator, and only the display data DB0 is valid in this page. · Column address circuit The column address of the display data RAM is specified using the column address set command as shown in Fig. 4. Since the specified column address is incremented (by +1) every time a display data read/write command is issued, the MPU can access the display data continuously. Further, the incrementing of the column address is stopped at the column address of 83(H). Since the column address and the page address are independent of each other, it is necessary, for example, to specify separately the new page address and the new column address when changing from column 83(H) of page 0 to column 00(H) of page 1. Also, as is shown in Table 5, it is possible to reverse the correspondence relationship between the display data RAM column address and the segment output using the ADC command (the segment driver direction select command). This reduces the IC placement restrictions at the time of assembling LCD modules. Table 5 Correspondence relationship between the display data RAM column address and the segment output ADC SEGMENT Output SEG0 SEG131 SEG131 DB0 = "0" 0(H) Column Address 83(H) DB0 = "1" 83(H) Column Address 0(H) 23/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G · Line address circuit The line address circuit is used for specifying the line address corresponding to the common output when displaying the contents of the display data RAM as is shown in Fig. 4. Normally, the topmost line in the display is specified using the display start line address set command (COM0 output in the forward display state of the common output, and COM47 COM47 output in the reverse display state). The display area is 48 lines in the direction of increasing line address from the specified display start line address. When the indicator­dedicated common output pin (COMS) is selected, data in Line Address 40 H = page 8 and bit 0 is displayed irrespective of the display start line address. COMS selection is 49th in order. It is possible to carry out screen scrolling by dynamically changing the line address using the display start line address set command. · Display data latch circuit The display data latch circuit is a latch for temporarily storing the data from the display data RAM before being output to the LCD drive circuits. Since the commands for selecting forward/reverse display and turning the display ON/OFF control the data in this latch, the data in the display data RAM will not be changed. Oscillator Circuit This is an RC oscillator that generates the display clock. The oscillator circuit is effective only when M/S = "H" and also CLS = "H". The oscillations will be stopped when CLS = "L", and the display clock has to be input to the CL pin. 24/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor 0 1 1 0 0 1 1 1 1 0 0 0 48 Lines Page4 Page5 Page6 Page7 Page8 1 0 DB0 DB0 ADC Column Address 0 1 0 1 Page3 COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM10 COM11 COM11 COM12 COM12 COM13 COM13 COM14 COM14 COM15 COM15 COM16 COM16 COM17 COM17 COM18 COM18 COM19 COM19 COM20 COM20 COM21 COM21 COM22 COM22 COM23 COM23 COM24 COM24 COM25 COM25 COM26 COM26 COM27 COM27 COM28 COM28 COM29 COM29 COM30 COM30 COM31 COM31 COM32 COM32 COM33 COM33 COM34 COM34 COM35 COM35 COM36 COM36 COM37 COM37 COM38 COM38 COM39 COM39 COM40 COM40 COM41 COM41 COM42 COM42 COM43 COM43 COM44 COM44 COM45 COM45 COM46 COM46 COM47 COM47 COMS The 40(H) is displayed irrespective of the display start line address. LCD Output 0 1 0 0 Page2 7F(H) 80(H) 81(H) 82(H) 83(H) 0 0 1 1 Page1 SEG127 SEG127 04(H) SEG128 SEG128 03(H) SEG129 SEG129 02(H) SEG130 SEG130 01(H) SEG131 SEG131 00(H) 0 0 1 0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH (Start) 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H Page0 83(H) 00(H) 82(H) 01(H) 81(H) 02(H) 80(H) 03(H) 7F(H) 04(H) 7E(H) 05(H) 7D(H) 06(H) 7C(H) 07(H) 0 0 0 1 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 0 0 0 0 When the common output state is normal display Line Address Data SEG0 Page Address ML9051G ML9051G Fig. 4 Display data RAM address map 25/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G Display Timing Generator Circuit This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. This circuit generates the timing signals for the line address circuit and the display data latch circuit from the display clock. The display data is latched in the display data latch circuit and is output to the segment drive output pins in synchronization with the display clock. The read out of the display data to the LCD drive circuits is completely independent of the display data RAM access from the MPU. As a result, there is no bad influence such as flickering on the display even when the display data RAM is accessed asynchronously during the LCD display. Also, the internal common timing and LCD frame reversal (FR) signals are generated by this circuit from the display clock. The drive waveforms of the frame reversal drive method shown in Fig. 5(a) for the LCD drive circuits are generated by this circuit. The drive waveforms of the line reversal drive method shown in Fig. 5(b) are also generated by the command. 48 49 1 2 3 4 5 6 44 45 46 47 48 49 1 2 3 4 5 6 LCDCK (display clock) FR V1 V2 COM0 V5 VSS V1 V2 COM1 V5 VSS RAM DATA V1 V3 SEGn V4 VSS Fig. 5(a) Waveforms in the frame reversal drive method 26/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G 48 49 1 2 3 4 5 6 44 45 46 47 48 49 1 2 3 4 5 6 LCDCK (display clock) FR V1 V2 COM0 V5 VSS V1 V2 COM1 V5 VSS RAM DATA V1 V3 V4 VSS SEGn Fig. 5(b) Waveforms in the line reversal drive method When the ML9051G ML9051G is used in a multiple chip configuration, it is necessary to supply the slave side display timing signals (FR, CL, and DOF) from the master side. However, when the line reversal drive is set, the ML9051G ML9051G is not used in a multiple chip configuration. The statuses of the signals FR, CL, and DOF are shown in Table 6. Table 6 Display timing signals in master mode and slave mode FR CL DOF Internal oscillator circuit enabled (CLS = H) Output Output Output Internal oscillator circuit disabled (CLS = L) Output Input Output Internal oscillator circuit disabled (CLS = H) Input Input Input Internal oscillator circuit disabled (CLS = L) Input Input Input Operating mode Master mode (M/S = "H") Slave mode (M/S = "L") Note: During master mode, the oscillator circuit operates from the time the power is applied. The oscillator circuit can be stopped only in the sleep state. 27/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G Common Output State Selection Circuit (see Table 7) Since the common output scanning directions can be set using the common output state selection command in the ML9051G ML9051G, it is possible to reduce the IC placement restrictions at the time of assembling LCD modules. Table 7 Common output state settings State Common Scanning direction Forward Display COM0 COM47 COM47 Reverse Display COM47 COM47 COM0 LCD Drive Circuit This LSI incorporates 181 sets of multiplexers for the ML9051G ML9051G, that generate 4-level outputs for driving the LCD. These output the LCD drive voltage in accordance with the combination of the display data, common scanning signals, and the FR signal. Fig. 6 shows examples of the segment and common output waveforms in the frame reversal drive method. Static Indicator Circuit The FR pin is connected to one side of the LCD drive electrode of the static indicator and the FRS pin is connected to the other side. The static indicator display is controlled by a command only independently of other display control commands. The electrode of the static indicator should has a wiring pattern that is distant from the dynamic drive electrode. If the wiring pattern is placed too near to the dynamic drive electrode, the LCD and electrode may be degraded. 28/74 PEDL9051G-01 PEDL9051G-01 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 CO M10 CO M11 CO M12 CO M13 CO M14 CO M15 ML9051G ML9051G SEG4 SEG3 SEG2 SEG1 SEG0 OKI Semiconductor FR COM0 COM1 COM2 SEG0 SEG1 SEG2 C O M 0 -S E G 0 C O M 0 -S E G 1 V DD V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 V SS V1 V2 V3 V4 V5 0V -V 5 -V 4 -V 3 -V 2 -V 1 V1 V2 V3 V4 V5 0V -V 5 -V 4 -V 3 -V 2 -V 1 Fig. 6 Output waveforms in the frame reversal drive method (FR waveform/common waveform/segment waveform/voltage difference between common and segment) 29/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G Power Supply Circuit This is the low power consumption type power supply circuit for generating the voltages necessary for driving LCD devices, and consists of voltage multiplier circuits, voltage adjustment circuits, and voltage follower circuits. In the power supply circuit, it is possible to control the ON/OFF of each of the circuits of the voltage multiplier, voltage adjustment circuits, and voltage follower circuits using the power control set command. As a result, it is also possible to use parts of the functions of both the external power supply and the internal power supply. Table 8 shows the functions controlled by the 3-bit data of the power control set command and Table 9 shows a sample combination. Table 8 Details of functions controlled by the bits of the power control set command Control bit Function controlled by the bit DB2 Voltage multiplier circuit control bit DB1 Voltage adjustment circuit (V1 voltage adjustment circuit) control bit DB0 Voltage follower circuit (V/F circuit) control bit Table 9 Sample combination for reference Circuit State used DB2 DB1 DB0 Adjustment Only the internal power supply is used 1 1 0 1 1 × Only V/F circuits are used 0 0 1 × × Only the external power supply is used 0 0 0 × × *1: × Used OPEN V1 1 Only V adjustment and V/F circuits are used V/F Voltage multiplier pins *1 VOUT V External voltage input VIN Voltage multiplier OPEN V1 to V5 OPEN The voltage multiplier pins are the pins VS1­, VS2­, VC3+, VC4+, VC5+, and VC6+. If combinations other than the above are used, normal operation is not guaranteed. 30/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G · Voltage multiplier circuits The connections for 2- to 4-time voltage multiplier circuits are shown below. VIN VIN VSS + VOUT + OPEN VC6+ VSS + VOUT + VC4+ OPEN VC3+ VS1­ 2-time voltage multiplier circuit VC6+ VC4+ VS2­ VC5+ VIN VSS + VOUT + + VS2­ + VC5+ VC6+ VC4+ VS2­ + VC5+ VC3+ VC3+ VS1­ OPEN VS1­ 3-time voltage multiplier circuit 4-time voltage multiplier circuit Fig. 7 Connection examples for voltage multiplier circuits 31/74 PEDL9051G-01 PEDL9051G-01 OKI Semiconductor ML9051G ML9051G The voltage relationships in voltage multiplication are shown in Fig. 8. VOUT = 3 × VIN = 15.0 V *1 VIN VSS VOUT = 4 × VIN = 18 V = 5.0 V =0V *1 VIN = 4.5 V VSS = 0 V Voltage relationship in 3-time multiplication Voltage relationship in 4-time multiplication Fig. 8 Voltage relationships in voltage multiplication *1: The voltage range of VIN should be set so that the voltage at the pin VOUT does not exceed the voltage multiplier output voltage operating range. · Voltage adjustment circuit The voltage multiplier output VOUT produces the LCD drive voltage V1 via the voltage adjustment circuit. Since the ML9051G ML9051G incorporates a high accuracy constant voltage generator, a 64-level electronic potentiometer function, and also resistors for voltage V1 adjustment, it is possible to build a high accuracy voltage adjustment circuit with very few components. In addition, the ML9051G ML9051G is available with the temperature gradients of a VREG - about ­0.05%/°C. (a) When the internal resistors for voltage V1 adjustment are used It is possible to control the LCD power supply voltage V1 and adjust the intensity of LCD display using commands and without needing any external resistors, if the internal voltage V1 adjustment resistors and the electronic potentiometer function are used. The voltage V1 can be obtained by the following equation A-1 in the range of V1