PEUL70511-01 ML70511 ML7050LA ARM7TDMI/32 MA0-19 MD0-15 GPIO0-15 CIO14 CIO11 - Datasheet Archive

 

Preliminary ML70511 Family User's Manual Bluetooth LSI Issue Date: September 2, 2002 Notation Classification Notation ·

 

PEUL70511-01 PEUL70511-01 Preliminary ML70511 ML70511 Family User's Manual Bluetooth LSI Issue Date: September 2, 2002 Notation Classification Notation · Numeric value Description xxH xxb Represents a hexadecimal number Represents a binary number · Unit Word, W byte, B nibble, N mega­, M kilo­, K kilo­, k mil­, m micro­, µ nano­, n second, s KB MB 1 word = 16 bits 1 byte = 2 nibbles = 8 bits 1 nibble = 4 bits 106 210 = 1024 103 = 1000 10­3 10­6 10­9 second 1KB = 1 kilobyte = 1024 bytes 1MB = 1 megabyte = 220 bytes = 1,048,576 bytes · Terminology "H" level The signal level of the high side of the voltage; indicates the voltage level of VIH and VOH described in the electrical characteristics. The signal level of the low side of the voltage; indicates voltage level of VIL and VOL described in the electrical characteristics. "L" level Opcode trap Operation code trap. Occurs when an empty area that has not been assigned an instruction is fetched, or when an instruction code combination that does not contain an instruction is addressed. · Register description Register name Invalid bit ADCON0L At reset 7 SCNC0 6 1 0 Fixed bit 5 4 SNEX0 ADRUN0 0 0 3 Bit name Bit number 2 1 0 0 0 0 "0" 0 Address : 009C [H] R/W : R/W Initial value when reset Invalid bit Fixed bit Read/Write attribute : Indicates that the bit does not exist. Writing into this bit is invalid. : When writing, always write the specified value. If read, the specified value will be read. Values of fixed bits are specified as "0" or "1". Read/write attribute : R indicates that reading is possible and W indicates that writing is possible. ML70511 ML70511 Family User's Manual Contents Table of Contents Chapter 1 General Description 1.1 General Description.1-1 1.2 Features .1-1 1.3 Block Diagram .1-4 1.4 Pin Layout .1-5 1.5 Pin Descriptions .1-6 1.5.1 Description of Each Pin .1-6 1.5.2 Pin Configuration.1-10 1.5.3 Connection of Unused Pins.1-11 Chapter 2 CPU 2.1 General Description.2-1 2.2 CPU Operating States.2-1 2.3 States Transition.2-1 2.4 Memory Format .2-1 2.5 Instruction Length .2-2 2.6 Data Type .2-2 2.7 Operating Modes .2-2 2.8 Registers.2-2 2.8.1 Registers Set in ARM State .2-2 2.8.2 Register Sets in THUMB State .2-4 2.8.3 Register Relationship in ARM and THUMB States .2-5 2.8.4 Access to Upper Registers in THUMB State .2-5 2.9 Program Status Register .2-6 2.9.1 Condition Code Flags .2-6 2.9.2 Control Bits.2-7 2.10 Exceptions .2-8 2.10.1 Operation at the Start of Exception.2-8 2.10.2 End of Exception Operation.2-8 2.10.3 Exception Start/End Operations.2-9 2.10.4 FIQ(*) .2-9 2.10.5 IRQ .2-9 2.10.6 Abort .2-10 2.10.7 Software Interrupt .2-10 2.10.8 Undefined Instructions.2-10 2.10.9 Exception Vectors.2-11 2.10.10 Exception Priority Sequence.2-11 2.11 Reset.2-11 Chapter 3 Memory Control Function 3.1 General Description.3-1 3.2 Memory Map.3-1 3.2.1 Registers.3-2 3.2.2 Memory.3-2 3.3 Description of Signals .3-3 3.4 List of Registers .3-3 3.5 Description of Registers .3-3 3.5.1 Remap Control Register (RMPCON) .3-3 3.6 Remap Function .3-4 3.7 Bus Width at Boot.3-5 Contents ­ 1 ML70511 ML70511 Family User's Manual Contents Chapter 4 LSI Control Function 4.1 General Description.4-1 4.2 Description of Signals .4-1 4.3 List of Registers .4-1 4.4 Description of the Registers .4-2 4.4.1 Clock Control Register (CLKCNTL).4-2 4.4.2 Reset Control Register (RSTCNTL).4-5 4.4.3 Regulator Control Register (REGCNTL) .4-6 4.4.4 Clock Stop Register (CKSTP) .4-6 4.4.5 SCLKFSEL Monitor Register (PINSTAT).4-8 4.5 Clock Control Function.4-9 4.5.1 Configuration of Clock Control Circuit .4-9 4.5.2 Clock Switching Function.4-10 4.5.3 Examples of Modes by Clock Selection .4-13 4.6 Power Down Function.4-15 4.6.1 Clock Stop.4-15 4.6.2 Block Stop.4-16 4.7 Reset Function.4-17 4.7.1 Power On Reset .4-17 4.7.2 Reset Input .4-18 4.7.3 Block Reset .4-18 4.7.4 Reset by Watch Dog Timer.4-18 Chapter 5 Interrupt Function 5.1 General Description.5-1 5.2 Features .5-1 5.3 Configuration .5-1 5.4 Description of Interrupt Signals .5-2 5.5 List of Registers .5-2 5.6 Description of the Registers .5-3 5.6.1 IRQ Status Register (IRQ) .5-3 5.6.2 IRQ Software Register (IRQS) .5-4 5.6.3 IRQ Number Register (IRN).5-5 5.6.4 Current IRQ Level Register (CIL) .5-6 5.6.5 IRQ Level Register (IRL) .5-7 5.6.6 IRQ Level Control Register 0 (ILC0) .5-8 5.6.7 IRQ Level Control Register 1 (ILC1) .5-9 5.7 Interrupt Processing Sequence .5-10 Chapter 6 Cache Function 6.1 General Description.6-1 6.2 Features .6-1 6.3 Configuration .6-1 6.4 List of Registers .6-2 6.5 Description of the Registers .6-2 6.5.1 Cache Control Register (CON) .6-2 6.5.2 Cache Valid/Invalid Register (CACHE).6-3 6.5.3 Flush Register (FLUSH) .6-4 6.6 Valid/Invalid Bank of Cache.6-4 Chapter 7 7.1 7.2 7.3 7.4 CIO Switching Function General Description.7-1 Feature.7-1 Configuration .7-1 Description of Signals .7-2 Contents ­ 2 ML70511 ML70511 Family User's Manual Contents 7.5 List of Registers .7-2 7.6 Description of the Registers .7-3 7.6.1 CIO Switching Control Register (CIOCNTL) .7-3 Chapter 8 Port Function (GPIO) 8.1 General Description.8-1 8.2 Features .8-1 8.3 Configuration .8-1 8.4 Description of Signal.8-2 8.5 List of Registers .8-2 8.6 Description of the Registers .8-2 8.6.1 Port Output Register (PO).8-2 8.6.2 Port Input Register (PI).8-3 8.6.3 Port Mode Register (PM).8-3 8.6.4 Interrupt Enable Register (IE).8-4 8.6.5 Interrupt Attribute Register (IP).8-5 8.6.6 Interrupt Status Register (IS) .8-6 8.7 Description of the Interrupt Operation .8-7 Chapter 9 Bluetooth Baseband Processing Function 9.1 General Description.9-1 9.2 Features .9-1 9.3 Configuration .9-1 9.4 Description of Signals .9-2 9.5 Interface Specifications .9-3 9.5.1 RF Chip Control Signals.9-3 9.5.2 Serial Interface Function.9-5 9.5.3 PCM Input/Output .9-6 9.6 Speech Data Sampling Conversion Outline .9-8 Chapter 10 USB Function 10.1 General Description.10-1 10.2 Features .10-1 10.3 Configuration .10-1 10.4 Description of Signals .10-2 10.5 List of Registers .10-3 10.6 Description of the Registers .10-5 10.6.1 EP0 Send FIFO Register (EP0TXFIFO).10-5 10.6.2 EP0 Receive FIFO Register (EP0RXFIFO).10-6 10.6.3 EP1 Send/Receive FIFO Register (EP1FIFO) .10-7 10.6.4 EP2 Send/Receive FIFO Register (EP2FIFO) .10-8 10.6.5 EP3 Send/Receive FIFO Register (EP3FIFO) .10-9 10.6.6 EP4 Send/Receive FIFO Register (EP4FIFO) .10-10 10.6.7 EP5 Send/Receive FIFO Register (EP5FIFO) .10-11 10.6.8 bmRequestType Setup Register (BmRequestType).10-12 10.6.9 bRequest Setup Register (bRequest).10-12 10.6.10 wValueLSB Setup Register (wValueLSB) .10-13 10.6.11 wValueMSB Setup Register (wValueMSB) .10-13 10.6.12 windexLSB Setup Register (wIndexLSB) .10-13 10.6.13 windexMSB Setup Register (WIndexMSB) .10-14 10.6.14 wLengthLSB Setup Register (WLengthLSB).10-14 10.6.15 wLengthMSB Setup Register (wLengthMSB) .10-14 10.6.16 Device Address Register (DVCADR) .10-15 10.6.17 Interrupt Status Register 1 (INTSTAT1) .10-16 10.6.18 Interrupt Status Register 2 (INTSTAT2) .10-17 10.6.19 Interrupt Enable Register 1 (INTENBL1).10-18 Contents ­ 3 ML70511 ML70511 Family User's Manual Contents 10.6.20 Interrupt Enable Register 2 (INTENBL2).10-19 10.6.21 Frame Number Register LSB (FRAMELSB) .10-20 10.6.22 Frame Number Register MSB (FRAMEMSB).10-20 10.6.23 System Control Register (SYSCON) .10-21 10.6.24 Polarity Select Register (POLSEL).10-22 10.6.25 EP0 Configuration Register (EP0CONF) .10-22 10.6.26 EP1to EP5 Configuration Register (EP1-5CONF) .10-23 10.6.27 EP0 Control Register (EP0CONT) .10-24 10.6.28 EP1 to EP5 Control Register (EP1-5CONT) .10-25 10.6.29 EP0 Payload Register (EP0PLD).10-26 10.6.30 EP1, 2 Payload Register (EP1,2PLD) .10-26 10.6.31 EP3 Payload Register (EP3PLD).10-27 10.6.32 EP4, 5 Payload Register (EP4,5PLD) .10-27 10.6.33 EP0 Receive Byte Count Counter Register (EP0RXCNT) .10-28 10.6.34 EP1, 2 Receive Byte Count Counter Register (EP1, 2RXCNT) .10-28 10.6.35 EP3 Receive Byte Count Counter Register (EP3RXCNT) .10-29 10.6.36 EP4, 5 Receive Byte Count Counter Register (EP4, 5RXCNT) .10-29 10.6.37 EP0 Status Register (EP0STAT).10-30 10.6.38 P1, 2, 4, 5 Status Register (EP1, 2, 4, 5STAT) .10-32 10.6.39 P3 Status Register (EP3STAT) .10-33 10.6.40 Packet Error Register (PKTERR) .10-34 10.7 Description of the Functions .10-35 Chapter 11 UART Function 11.1 General Description.11-1 11.2 Features .11-1 11.3 Configuration .11-1 11.4 Description of Signals .11-2 11.5 Registers.11-2 11.6 Description of the Registers .11-3 11.6.1 Send Buffer Register (THR) .11-3 11.6.2 Receive Buffer Register (RBR) .11-3 11.6.3 Line Control Register (LCR) .11-4 11.6.4 Line Status Register (LSR) .11-6 11.6.5 FIFO Control Register (FCR) .11-8 11.6.6 Modem Control Register (MCR) .11-9 11.6.7 Modem Status Register (MSR) .11-10 11.6.8 Interrupt Identification Register (IIR).11-12 11.6.9 Interrupt Enable Register (IER) .11-14 11.6.10 Divisor Latch (DIV).11-15 11.6.11 Scratch Pad Register (SCR) .11-16 11.7 Programming.11-16 11.8 Operation in FIFO Interrupt Mode.11-17 11.9 Operation in FIFO Poll Mode .11-18 Chapter 12 Serial Port Functions (SIO1) 12.1 General Description.12-1 12.2 Features .12-1 12.3 Configuration .12-1 12.4 Description of Signals .12-2 12.5 List of Registers .12-2 12.6 Description of the Registers .12-3 12.6.1 SIO1 Send Control Register (STCON) .12-3 12.6.2 SIO1 Receive Control Register (SRCON).12-5 12.6.3 SIO1 Status Register (S1ST).12-6 12.6.4 Send/Receive Buffer Register (S1BUF) .12-7 12.6.5 SIO1 Send/Receive Registers .12-7 Contents ­ 4 ML70511 ML70511 Family User's Manual Contents 12.6.6 SIO1 Timer Control Register (STMCON).12-8 12.6.7 SIO1 Timer Counter (STMC) .12-9 12.6.8 SIO1 Timer Register (STMR).12-9 12.7 Transmit Operation .12-10 12.7.1 UART Mode .12-10 12.7.2 Sync Master Mode .12-10 12.7.3 Sync Slave Mode .12-10 12.8 Receive Operation .12-11 12.8.1 UART Mode .12-11 12.8.2 Sync Master Mode .12-12 12.8.3 Sync Slave Mode .12-12 Chapter 13 Serial Port Functions (SIO2) 13.1 General Description.13-1 13.2 Features .13-1 13.3 Configuration .13-1 13.4 Description of Signals .13-2 13.5 List of Registers .13-2 13.6 Description of the Registers .13-2 13.6.1 Send/Receive Buffer Register (SIOBUF) .13-2 13.6.2 SIO2 Status Register (SIOSTA) .13-3 12.6.3 SIO2 Control Register (SIOCON) .13-4 13.6.4 Baud Rate Control Register (SIOBCN) .13-5 13.6.5 Baud Rate Timer Counter Register (SIOBTC) .13-5 13.6.6 Baud Rate Timer Reload Register (SIOBTR).13-6 13.7 Send/Receive Data Setting .13-6 13.8 Sending Data .13-7 13.9 Receiving Data .13-7 13.10 Interrupt Signals .13-7 Chapter 14 Timer (TIMER1) 14.1 General Description.14-1 14.2 Features .14-1 14.3 Configuration .14-1 14.4 Registers.14-2 14.5 Description of the Registers .14-3 14.5.1 Timer Control Registers (TIMECNTL0, TIMECNTL1, TIMECNTL2) .14-3 14.5.2 Timer Base Registers (TIMEBASE0, TIMEBASE1, TIMEBASE2) .14-4 14.5.3 Timer Counters (TIMECNT0, TIMECNT1, TIMECNT2).14-4 14.5.4 Timer Comparison Registers (TIMECMP0, TIMECMP1, TIMECMP2).14-5 14.5.5 Timer Status Registers (TIMESTAT0, TIMESTAT1, TIMESTAT2).14-5 14.6 Operation.14-6 14.6.1 General Description .14-6 14.6.2 Free-run Mode .14-6 14.6.3 Interval Mode.14-7 14.6.4 One-shot Mode .14-8 Chapter 15 Timer (TIMER2) 15.1 General Description.15-1 15.2 Features .15-1 15.3 Configuration .15-1 15.4 Registers.15-1 15.5 Description of the Registers .15-2 15.5.1 Timer Control Register (TMCON) .15-2 15.5.2 Timer Enable Register (TMEN) .15-2 15.5.3 Timer Reload Register (TMRLR).15-3 Contents ­ 5 ML70511 ML70511 Family User's Manual Contents 15.5.4 15.5.5 Timer Counter Register (TMC) .15-3 Overflow Register (TMOVFR).15-4 Chapter 16 WDT 16.1 General Description.16-1 16.2 Features .16-1 16.3 Configuration .16-1 16.4 List of Registers .16-2 16.5 Description of Register.16-3 16.5.1 Watchdog Timer Control Register (WDTCON).16-3 16.5.2 Timebase Counter Control Register (TBGCON).16-3 16.5.3 Status Register (INTST) .16-4 16.6 Operating Sequence.16-5 Chapter 17 Bus Port Functions 17.1 General Description.17-1 17.2 Features .17-1 17.3 Configuration .17-1 17.4 Description of Signals .17-2 17.5 List of Registers .17-2 17.6 Description of Registers .17-3 17.6.1 Bus Width Control Register (BWC) .17-4 17.6.2 Bus Access Control Register (BAC).17-5 17.6.3 ROM Access Control Register (ROMAC) .17-6 17.6.4 ROM Page Mode Control Register (ROMPC) .17-7 17.6.5 SRAM Access Control Register (SRMAC).17-8 17.6.6 SRAM Page Mode Control Register (SRMIPC).17-9 17.6.7 Access Control Register 1 (IOAC1) .17-10 17.6.8 Access Control Register 2 (IOAC 2) .17-11 17.7 Description of Operation.17-12 17.7.1 Basic Access .17-12 17.7.2 Page Mode Access .17-13 17.7.3 External IO Access .17-14 Chapter 18 JTAG 18.1 18.2 18.3 18.4 General Description.18-1 Features .18-1 Description of Signals .18-1 Example of System Connection .18-1 Chapter 19 Flash Memory 19.1 General Description.19-1 19.2 Features .19-1 19.3 Description of Operation.19-2 19.3.1 Standby .19-2 19.3.2 Command Entry .19-3 19.3.3 Read/Reset (Software Reset) .19-3 19.3.4 Erase .19-3 19.3.5 Word Programming .19-3 19.3.6 Protect .19-3 19.3.7 Protect Release.19-4 19.3.8 Verify Protect.19-4 19.3.9 Protecting Data From Miswriting .19-4 19.3.10 End of Write Operation Detection .19-4 19.3.11 Note on System Design.19-5 Contents ­ 6 ML70511 ML70511 Family User's Manual Contents 19.4 Overwrite Modes.19-7 19.4.1 Serial Mode.19-7 19.4.2 User Mode.19-7 19.5 Serial Mode .19-8 19.5.1 Serial Mode Outline.19-8 19.5.2 Serial Mode Setting.19-8 19.6 User Mode.19-10 19.6.1 User Mode Outline.19-10 Chapter 20 List of Registers 20.1 General Description.20-1 20.2 List of Registers .20-1 Chapter 21 Electrical Characteristics 21.1 Absolute Maximum Ratings.21-1 21.2 Recommended Operating Conditions.21-1 21.3 Internal Flash ROM Operating Conditions .21-1 21.4 DC Characteristics.21-2 21.4.1 DC characteristics (1) (Excluding USB Port) .21-2 21.4.2 DC characteristics (2) USB Port (D+, D­).21-2 21.5 AC Characteristics.21-3 21.5.1 Clock.21-3 21.5.2 Memory Interface.21-4 21.5.3 PCM Interface.21-5 21.5.4 SIO Interface.21-6 21.5.5 USB Port .21-7 21.5.6 Reset .21-7 Chapter 22 Package Dimensions Chapter 23 Application Notes 23.1 Operation at Boot .23-1 23.2 Clock Selection .23-1 23.3 HCI Transport Selection.23-1 23.4 USB Peripheral Circuits .23-2 23.5 UART Baud Rate Setting.23-2 23.6 PCM-CVSD Transcoder Setting .23-2 23.7 External Memory .23-3 23.8 Processing of Unused Interface Pins .23-6 23.9 Software Products .23-9 23.10 Vender Specific Command .23-9 23.11 Power Supply Wiring .23-10 23.12 System Configuration.23-11 Revision History Revision History . R-1 Contents ­ 7 Chapter 1 General Description ML70511 ML70511 Family User's Manual Chapter 1 General Description Chapter 1 General Description 1.1 General Description The ML70511 ML70511 family comprises 2.4 GHz band Bluetooth baseband CMOS digital ICs. It allows data and voice communications having mutual connectivity with other Bluetooth systems by using together with the ML7050LA ML7050LA (Bluetooth RF transceiver IC) and OKI's Bluetooth protocol stack software. It incorporates an ARM7TDMI as a core CPU and supports interface for applications having superb expandability such as UART allowing transfer of up to USB1.1, 921.6 kbps complying with various transfer modes, synchronous/start-stop synchronous SIO, 16-bit GPIO, etc. Incorporates regulator/power on reset functions to operate power management function complying with low power consumption applications as well. 1.2 Features The ML70511 ML70511 family has the following features. · Bluetooth · Complies with Bluetooth standard (Ver. 1.1) · Supports OKI RF-LSI (ML7050LA ML7050LA) interface · RF control signal system timing adjusting function · Clock regeneration (1MHz) function at the time of receiving data · Incorporates CODEC I/F complying with A-law/µ-law/CVSD/PCM · Low power operation in park mode at 3.2 kHz clock · CPU · ARM7TDMI/32 ARM7TDMI/32 MHz operating frequency · 8KB 4 Way Unified Cache - Interrupt: 16 factors · Bus Interface · Flash ROM (256/512 KB) in package · Flash ROM (1024 KB max.) outside of package · SRAM (1024 KB max.) · Built-in Memory · 32K byte RAM · Clock · Supports 3 types of input clocks, 12/13/16 MHz · Supports 2 types of external clocks · Timer · 3ch, 18-bit timer - Auto reload (interval), one-shot, and free run functions · Auto reload Watch Dog Timer - Interrupt and reset functions · 1ch, 16-bit auto reload 1­1 ML70511 ML70511 Family User's Manual Chapter 1 General Description · USB · Complies with USB1.1 · Supports 12 Mbps · Complies with 4 data transfer types - Control transfer, bulk transfer, interrupt transfer, and isochronous transfer · Built-in USB transceiver circuit · 5 or 6 end points can be selected · Built-in FIFO for storing data · 8-, 16-, and 32-bit readable/writable for FIFO of EP0 to EP5 (With byte control) · UART · Full duplex buffer system · All status inform function · Built-in 64 byte transmit/receive FIFO · Modem control: CTS, DCD, DSR · Programmable serial interface · 5-, 6-, 7-, and 8-bit character · Odd parity, even parity, or no parity generation and verification · 1, 1.5, and 2 stop bits · Programmable baud rate generator (1200 bps to 921.6 kbps) · Error service relating to parity, overrun, and framing · SIO · 2 SIO systems are incorporated · UART serial port interface (SIO2) · UART/synchronous type serial port interface (SIO1) · UART modes (SIO1, 2): - Data length: 7 or 8 bits selectable - Supports odd parity, even parity, or no parity - Error service relating to parity, overrun, and framing - Supports stop bit of 1 or 2 bits - Allows full duplex communication · Clock sync mode (SIO1): - Data length: 7 or 8 bits selectable - Error service relating to overrun - Allows full duplex communication · PCM-CVSD Transcoder · Input/output on application side - PCM CODEC - APB-bus (USB) · Format on application side - PCM linear (8, 16 bits/sample, 64 kHz sampling frequency)/A-law/µ-law · Format on Bluetooth side - CVSD/A-law/µ-law · Supports all above-mentioned conversion combinations. · PCMSYNC/PCMCLK input/output can be selected (default direction: input) · GPIO · 16 parallel ports · Input/output selection possible for each bit · Interrupt can be used for all 16 bits · Interrupt mask and interrupt mode can be set for all bits 1­2 ML70511 ML70511 Family User's Manual Chapter 1 General Description · Power Management · STOP mode: Entire chip stops · HALT mode: Internal blocks stop individually · JTAG Interface · Complies with ARM-JTAG debugger · Allows Flash ROM writer connection · Power Supply Voltage Change, Power On Reset · 3.0 to 3.6 V single power supply · Outputs power on reset signal to outside · Package · 144-pin BGA (P-LFBGA 144-1111-0.80) (Refer to Chapter 22 for detailed dimensions.) 1­3 ML70511 ML70511 Family User's Manual Chapter 1 General Description 1.3 Block Diagram WDT TDI TDO TRST TMS TCK ARM7 TDMI Control 1 JTAG Cache/ Bus Interface MA0-19 MA0-19 MD0-15 MD0-15 MWE MRE MCS0, 1 MBS0, 1 MOE0, 1 UART SOUT SIN DCD RTS CTS DSR DTR RI SIO1 GPIO XMC STXD SRXD STDXCLK SRDXCLK GPIO0-15 GPIO0-15 APB Ctl USB D+ D­ Control 2 Timer 2 (1ch) RESET RESET_out BBWSEL REMAP0, 1 PCM/ CVSD SIO2 UTXD URXD SCLK XCLK SCLKSEL SCLKFSEL0, 1 IRC µPLATcore-7C CLK GEN LSI Control AHB RAM Baseband Controller TIMER 1 (3ch) APB Ctl Figure 1-1 ML70511 ML70511 Family Block Diagram 1­4 Bluetooth Baseband Controller PCMOUT PCMIN PCMSYNC PCMCLK TXD RXD PLL_DATA PLL_CLK PLL_LE PLL_OFF PLL_POW TX_POW RX_POW RSSI RSSI_CLK PLL_PS PLLLOCK RXC TXC_IN TXCSEL ML70511 ML70511 Family User's Manual Chapter 1 General Description 1.4 Pin Layout REG GND NC TCK TRST SCLK MOE0 GND MD2 MD5 MD8 MD10 NC TEST_L TMS GND VDD REGVDD REGOUT GND MD0 VDD MD3 MD6 MD11 GND AGND1 GND AVDD1 AGND0 REMAP1 MOE1 VDD MD4 MD7 MD9 MD14 MD12 TXCSEL SCLK SEL TEST_L REMAP0 REGVBG GND MBS1 MD1 MD13 VDD MA2 MD15 SCLK FSEL0 RESET OUT MA3 MA0 MA5 MA1 MA6 MA7 GND MA4 AVDD0 13 12 XCLK 11 MBS0 10 VTM SCLK FSEL1 9 TEST_L BBWEL TEST_L TEST_L 8 D­ TEST_L GND TEST_L VDD MA9 MA10 MA8 GND TEST_L VDD D+ MA11 GND MA12 MA13 RESET MA15 MA17 MA14 GND CIO14 CIO14* CIO7* CIO0* MA16 MA18 CIO11 CIO11* CIO10 CIO10* CIO2* MA19 CIO*1 GND CIO13 CIO13* CIO8* CIO5* CIO*3 CIO9* CIO6* CIO4* NC 7 6 MRE TEST_PU MCS1 5 MCS0 TEST_H LVDD RSSI TEST_L PLL_ POW TX_ POW RSSI_ CLK PCM GND PCMCLK SYNC PLL_PS RXC TXD PLL_ DATA GND TXC_IN PCM OUT NC PLL_LE RX_ POW PLL_ OFF PLL_ CLK RXD VDD C D GND MWE PLL LOCK PCMIN TDI 4 3 TDO 2 CIO15 CIO15* CIO12 CIO12* 1 A B E F H G J K L M N Figure 1-2 ML70511 ML70511 Family Pin Layout For outer dimensions refer to Chapter 22 "Package Dimensions Diagram". For method of dealing with unused pins refer to section 1.5.3. * The CIO0 to CIO15 CIO15 pins correspond as follows. CIO0 = GPIO0 CIO1 = GPIO1 CIO2 = GPIO2 or URXD CIO3 = GPIO3 or UTXD CIO4 = GPIO4 or SRDXCLK CIO5 = GPIO5 or STDXCLK CIO6 = GPIO6 or SRXD CIO7 = GPIO7 or STXD CIO8 = GPIO8 or RI CIO9 = GPIO9 or DTR CIO10 CIO10 = GPIO10 GPIO10 or DSR CIO11 CIO11 = GPIO11 GPIO11 or CTS CIO12 CIO12 = GPIO12 GPIO12 or RTS CIO13 CIO13 = GPIO13 GPIO13 or DCD CIO14 CIO14 = GPIO14 GPIO14 or SIN CIO15 CIO15 = GPIO15 GPIO15 or SOUT 1­5 ML70511 ML70511 Family User's Manual Chapter 1 General Description 1.5 Pin Descriptions 1.5.1 Description of Each Pin The pin functions of the ML70511 ML70511 family are shown in Table1-1. In input/output column, "I" represents input pin, "O" represents output pin, "Oc" represents open collector pin, and "I/O" represents input/output pin. Table 1-1 (1/4) Pin Description Pin description Classification Symbol I/O Primary function I/O Initial value Secondary function GPIO0 I/O I - - GPIO1 I/O I - - I/O I - Serial data input I/O O H Serial data output I/O I/O - Serial data input clock I/O I/O - Serial data output clock I/O I - Serial data input I/O O H Serial data output I - Ring indicator I/O O H Receive ready I/O I - Receive data ready I/O I - ACE transmit ready I/O O H ACE transmit data ready I/O I - Data carrier detection I/O I - ACE receive serial data I/O O H ACE transmit serial data GPIO2/ URXD GPIO3/ UTXD GPIO4/ SRDXCLK GPIO5/ STDXCLK GPIO6/ SRXD GPIO7/ STXD Port GPIO8/ RI GPIO9/ DTR GPIO10/ GPIO10/ DSR GPIO11/ GPIO11/ CTS GPIO12/ GPIO12/ RTS GPIO13/ GPIO13/ DCD GPIO14/ GPIO14/ SIN GPIO15/ GPIO15/ SOUT I/O Parallel input/output data (input in the beginning) 1­6 ML70511 ML70511 Family User's Manual Chapter 1 General Description Table 1-1 (2/4) Pin Description Classification Port Symbol Internal pull up/down I/O Initial value D+ - I/O Z D­ - I/O Z Description USB data TDI I - JATG data input - O L JTAG data output TRST Pull down I - JTAG reset pin TMS Pull down I - JTAG mode setting pin TCK Pull down I - JTAG clock MA0 to 19 - O L External address bus MD0 to 15 Pull up I/O - External data bus MWE JTAG Pull down TDO - O H External write enable signal output MRE H External read enable signal output O H External RAM space chip select MCS1 - O H External I/O space chip select MBS0 - O H External lower byte select - O H External upper byte select MOE0 - O H External MCS0 device output enable (OR output of MCS0 and MRE) MOE1 - O H External MCS1 device output enable (OR output of MCS1 and MRE) TXD - O L Transmit data output (To ML7050LA ML7050LA pin A8) RXD - I - Receive data input (To ML7050LA ML7050LA pin H5) PLL_DATA RF O - MBS1 External memory - MCS0 - O L Data output for PLL setting (To ML7050LA ML7050LA pin H3) PLL_CLK - O L Clock output for PLL setting (To ML7050LA ML7050LA pin G3) PLL_LE - O L Load enable output for PLL setting (To ML7050LA ML7050LA pin H4) PLL_OFF - O L PLL open-loop/close-loop control signal output (To ML7050LA ML7050LA pin G8) PLL_POW - O H Power supply control signal output for local oscillator circuit (To ML7050LA ML7050LA pin A7) 1­7 ML70511 ML70511 Family User's Manual Chapter 1 General Description Table 1-1 (3/4) Pin Description Internal pull up/down I/O Initial value - O H RX_POW - O H RSSI RSSI_CLK Pull down - I O - H Receive electric field strength data input RSSI transmit clock PLL_PS PLLLOCK RF Symbol TX_POW Classification - Pull down O I L - PLL power supply control signal output PLL lock signal input RXC - O L Bluetooth receive clock output (1 MHz) - Bluetooth transmit clock input (1 MHz) When using a transmit clock by the clock (RXC) generated from the receive data, connect with RXC (Pin B2) by setting TXCSEL (pin A10) = H. TXC_IN Pull down I Description Power supply control signal output for transmission (To ML7050LA ML7050LA pin B6) Power supply control signal output for reception (To ML7050LA ML7050LA pin B3) TXCSEL - O L Pull down I - PCM data input PCMSYNC Pull down I/O - PCM sync signal (8 kHz) Input in beginning (can be switched by internal register). PCMCLK Reset - PCMIN Clock I PCMOUT PCM Pull down Bluetooth transmit clock setting pin L: Selects 1 MHz obtained by dividing with internal PLL. H: Select TXC_IN input signal. PCM data output Pull down I/O - PCM clock (64/128 kHz) Input in beginning (can be switched by internal register) SCLK - I - XCLK RESET RESET_out - - - I I O - - - SCLKSEL Pull down I - LSI control SCLKFSEL0 to 1 I - BBWSEL Memory control Pull down Pull down I - REMAP0 to 1 - I - 1­8 Master clock (12/13/16 MHz) input (Voltage level: CMOS level) User clock input pin Hardware reset (Reset = L) input Hardware reset (Reset = L) output System clock setting pin L: Selects clock obtained by dividing with internal PLL. H: Selects XCLK input signal. SCLK frequency setting pin SCLKFSEL = 0: 12 MHz 1: 13 MHz 2: 16 MHz 3: Reserve BANK0 area bit width setting pin L: 8 bits H: 16 bits REMAP at boot setting pin REMAP = 0: Reserve 1: Stacked flash ROM 2: External MCS1 device 3: External MCS0 device ML70511 ML70511 Family User's Manual Chapter 1 General Description Table 1-1 (4/4) Pin Description Symbol Internal pull up/down I/O Initial value TEST_L Classification - I - Description Test pin (input) TEST_H - I - Test pin (input) TEST_PU - I - Test monitor pin VTM Test - I - Internal flash ROM test pin NC - - No Connection - - - I/O power supply pin 3.3 V ± 0.3 V LVDD - - - I/O power supply pin (same potential as ML7050 ML7050 power supply) GND Power supply ground - VDD - - - Digital section ground pin AVDD - - - Analog section power supply pin 2.5 V ± 10% AGND - - - Analog section ground pin REGVDD - - - Regulator VDD (3.0 to 3.6 V) REGGND - - - Regulator GND REGVBG - - - Regulator reference voltage output REGOUT - - - Regulator output 1­9 ML70511 ML70511 Family User's Manual Chapter 1 General Description 1.5.2 Pin Configuration A simplified representation of pin configuration of the ML70511 ML70511 family is given in Table 1-2 and Figure 1-3. Figure 1-2 Pin Configuration Pin Configuration Symbol Type 1 RXD, SCLK, XCLK, REMAP0-1, SVCO0-1 Type 2 RSSI, PLLLOCK, TXC_IN, TXCSEL, SCLKSEL, SCLKFSEL0-1, BBWSEL, TDI, TRST, TMS, TCK, PCMIN Type 3 RESET Type 4 TXD, PLL_DATA, PLL_CLK, PLL_LE, PLL_OFF, PLL_POW, PX_POW, RX_POW, RSSI_CLK, PLL_PS, RXC, RESET_out, MA0 to 19, MWE, MRE, MCS0-1, MBS0-1, MOE0-1, TDO, PCMOUT Type 5 PCMSYNC, PCMCLK Type 6 MD0-15 MD0-15 Type 7 CIO0-15 CIO0-15 Type 1 Type 5 IN/ OUT IN 50 k Type 2 IN Type 6 50 k 50 k IN/ OUT Type 3 Type 7 50 k IN Type 4 OUT Figure 1-3 Pin Configuration Types 1 ­ 10 IN/ OUT ML70511 ML70511 Family User's Manual Chapter 1 General Description 1.5.3 Connection of Unused Pins Connection of interface pins when not used is as described in Table 1-3. Pins not shown in the table are all open. Table 1-3 Connection of Unused Pins RF I/F Symbol RSSI Pull down or ground PLLLOCK Pull down or ground TXC_IN Pull down or ground TXCSEL Remarks Connection when not used Pull down or ground Memory I/F Symbol Connection when not used Remarks When connected For 16-bit device · Open MA0 MA0 to 19 Open · Go on connecting from MA1 in order from A0 of connected device. For 8-bit device · Connect to each concerned address GPIO I/F Symbol Connection when not used GPIO0 Pull up or VDD GPIO1 Pull down or ground GPIO2/URXD Remarks Pull down or ground GPIO3/UTXD Pull up or VDD GPIO4/SRDXCLK Pull down or ground GPIO5/STDXCLK Pull down or ground GPIO6/SRXD Pull up or VDD GPIO7/STXD Pull up or VDD GPIO8/RI Pull up or VDD GPIO9/DTR Pull up or VDD GPIO10/DSR GPIO10/DSR Pull down or ground GPIO11/CTS GPIO11/CTS Pull down or ground GPIO12/RTS GPIO12/RTS Pull up or VDD GPIO13/DCD GPIO13/DCD Pull down or ground GPIO14/SIN GPIO14/SIN Pull up or VDD GPIO15/SOUT GPIO15/SOUT Pull up or VDD Note: The pins listed above can be used for two or more applications. These pins must be in the initial states (input states) when not used, so they should not be left open but should be connected as designated above. 1 ­ 11 ML70511 ML70511 Family User's Manual Chapter 1 General Description TEST I/F and Others Symbol Connection when not used TEST_L Pull down or GND TEST_PU Open TEST_H Pull up or VDD VTM Open RESET Pull up or VDD NC Open 1 ­ 12 Remarks Chapter 2 CPU ML70511 ML70511 Family User's Manual Chapter 2 CPU Chapter 2 CPU 2.1 General Description As a CPU of this LSI, the ML70511 ML70511 family uses the 32-bit ARM7TDMI of RISC (Reduced Instructions Set Computer) architecture developed by ARM. The ARM7TDMI can execute instructions in the following 2 operating states. ARM state: The CPU executes the 32-bit length instructions set (ARM instructions). (ARM originally stood for Advanced RISC Machines.) THUMB state: The CPU executes the 16-bit length instructions set (THUMB instructions), which is a sub-set of the ARM instructions. The CPU can execute a program by switching the two operating states according to the need. 2.2 CPU Operating States The ARM7TDMI can operate in any one of the ARM and THUMB states. The CPU operating mode and contents in the registers are not affected by the transition between these 2 operating states. ARM state: The CPU executes the ARM instructions placed in a 32-bit word boundary. THUMB state: The CPU executes the THUMB instructions placed in a 16-bit word boundary. 2.3 States Transition · · Transition to THUMB State It is possible to switch the CPU to THUMB state by setting the status bit (bit 0) in operand register and executing the BX command. If an exception has been generated in the THUMB state of CPU, the CPU automatically switches to the THUMB state when recovering also from the exception (IRQ, FIQ(*), UNDEF, SWI etc.). Transition to ARM State The CPU switches to the ARM state when: 1. The BX command is executed in the cleared state of the status bit in the operand register. 2. The CPU received the exception (IRQ, FIQ(*), UNDEF, SWI etc.). In this case, the PC (Program Counter) is put in link register of that exception mode and runs from the vector address of the exception. (*): ML70511 ML70511 family does not support the FIQ input pin. 2.4 Memory Format Memory is managed as an assembly of bytes numbered sequentially from zero. The memory stores word data of so-called the 1st word from byte 0 to byte 3, and the 2nd word from byte 4 to byte 7. Words in the memory are managed in the little Endian format. Upper address 31 11 7 3 24 23 10 6 2 16 15 9 5 1 8 7 8 4 0 0 Word address 8 4 0 Lower address · The lowest byte is put in the lower address. · A word is specified by the byte address of the lowest byte. Figure 2-1 Little Endian Address of Bytes in a Word Note: The ARM7TDMI architecture can manage words in the memory by selecting any one of the little or big Endian addresses. However, it is fixed to the little Endian address in this LSI. 2­1 ML70511 ML70511 Family User's Manual Chapter 2 CPU 2.5 Instruction Length The instructions are either 32-bit long (ARM state) or 16-bit long (THUMB state). 2.6 Data Type The ARM7TDMI supports data type that includes a byte (8 bits), half-word (16 bits) and word (32 bits). A word must be arranged in a 4-byte boundary and half-word in 2-byte boundary. 2.7 Operating Modes The CPU supports 6 operating modes mentioned below. User(usr): Normal program running state FIQ(*) (fiq): Designed to support data transfer or channel processing. IRQ(irq): Used to process a general-purpose interrupt. Supervisor(svc): Protect mode for the operating system Abort mode(abt): The CPU switches to the abort mode after the data/fetch instruction abort. System(sys): Privileged user mode for the operating system Undefined(und): The CPU switches to the undefined mode to execute an undefined instruction. The CPU mode is changed either by software, or by processing an interrupt or exception. Most of the application programs run in the user mode. The mode switches to non-user mode i.e., privileged mode, to process an interrupt, exception or to access a protected resource. (*): The ML70511 ML70511 family does not support the FIQ input pin. 2.8 Registers The CPU has 31 general-purpose 32-bit registers and 6 status registers. It is not possible to refer to all these registers one time. The CPU operating state and mode determine the registers that can be used in the program. 2.8.1 Registers Set in ARM State In ARM state, it is always possible to refer to the 16 general-purpose registers and 1 or 2 status register(s). In the privileged mode (non-user mode), the registers switch to a bank of registers peculiar to the mode. Figure 2-2 shows the set of registers used in each mode. A meshed box indicates a bank register. The set of registers in the ARM state includes 16 direct accessible R0 to R15 registers. All these registers, excluding R15, are the general-purpose registers. In addition, there is a 17th register to store the status information. Register 14: Register 15: Register 16: Used as a sub-routine register. When executing the branch linked (BL) instruction, this register receives a copy of R15 register. For other applications, R14 is handled as a general-purpose register. The respective R14_svc, R14_irq, R14_fiq and R14_und bank registers are used to store the R15 return values in the event of an interrupt or exception, or when executing the BL instruction in the interrupt or exception routine. It is a program counter (PC). In ARM state, bit [1:0] of R15 is zero and bit [31:2] is used as PC. In THUMB state, bit [0] is zero and bit [31:1] is used as PC. It is CPSR (Current Program Status Register). It includes the condition code flags and mode bits that indicate the current CPU operating mode. 2­2 ML70511 ML70511 Family User's Manual Chapter 2 CPU In FIQ(*) mode, there are 7 bank registers mapped to R8 to R14 (R8_fiq to R14_fiq). In the ARM state, it is not necessary for most FIQ handlers to save aside the registers. Each of the User, IRQ, Supervisor, Abort and Undefined modes has 2 bank registers mapped to R13 and R14, and each mode can have private stack pointers and link registers. (*): The ML70511 ML70511 family does not support the FIQ input pin. General-purpose Registers and Program Counters in ARM State System & User FIQ (*) Supervisor Abort IRQ Undefined R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 R8_fiq R8 R8 R8 R8 R9 R9_fiq R9 R9 R9 R9 R10 R10_fiq R10 R10 R10 R10 R11 R11_fiq R11 R11 R11 R11 R12 R12_fiq R12 R12 R12 R12 R13 R13_fiq R13_svc R13_abt R13_irq R13_und R14 R14_fiq R14_svc R14_abt R14_irq R14_und R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) Program Status Registers in ARM State CPSR CPSR CPSR CPSR CPSR CPSR SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und = Bank register (*): The ML70511 ML70511 family does not support the FIQ input pin. Figure 2-2 Configuration of the Registers in ARM State 2­3 ML70511 ML70511 Family User's Manual Chapter 2 CPU 2.8.2 Register Sets in THUMB State The set of registers in THUMB state are sub-sets of the set of registers in ARM state. The programmer has direct access to the 8 general-purpose registers R0 to R7, program counters (PCs), stack pointers (SPs), link registers (LRs), and CPSRs. There are stack pointers, link registers, and the store program status registers (SPSRs) of bank configuration for each privileged mode. Figure 2-3 shows the configuration of registers in THUMB state. General-purpose Registers and Program Counters in THUMB State System & User FIQ (*) Supervisor Abort IRQ Undefined R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 SP SP_eiq SP_svc SP_abt SP_irq SP_und LR LR_fiq LR_svc LR_abt LR_irq LR_und PC PC PC PC PC PC Program Status Registers in ARM State CPSR CPSR CPSR CPSR CPSR CPSR SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und = Bank of registers (*): The ML70511 ML70511 family does not support the FIQ input pin. Figure 2-3 Configuration of the Registers in THUMB State 2­4 ML70511 ML70511 Family User's Manual Chapter 2 CPU 2.8.3 Register Relationship in ARM and THUMB States Following is the relationship among the registers in the ARM and THUMB states: · R0 to R7 in THUMB state and R0 to R7 in ARM state are the same registers. · CPSR and SPSR in THUMB state and CPSR and SPSR in ARM state are the same registers. · SP in THUMB state corresponds to R13 in ARM state. · LR in THUMB state corresponds to R14 in ARM state. · Program counter in THUMB state corresponds to the program counter (R15) in ARM state. The relationship is shown in Figure 2-4. THUMB State ARM State R0 R0 R1 R1 R2 R2 R3 R3 R4 R4 R5 R5 R6 R6 R7 R7 Lower registers R8 R9 R10 R11 R12 Stack pointer (SP) Upper registers Stack pointer (R13) Link register (LR) Link register (R14) Program counter (PC) CPSR Program counter (R15) CPSR SPSR SPSR Figure 2-4 Mapping of Registers in THUMB State With Respect to Registers in ARM State 2.8.4 Access to Upper Registers in THUMB State In THUMB state, R8 to R15 registers (upper registers) are not a part of the standard set of registers. However, these registers can be used as high-speed temporary memories by performing a limited access to these registers using the assembly language. It is possible to transfer the values using the MOV special format instruction for the upper registers from any of R0 to R7 (lower registers), or for the lower registers from the upper registers. Upper register values can be compared with and added to the lower register values by respective CMP and ADD instructions. 2­5 ML70511 ML70511 Family User's Manual Chapter 2 CPU 2.9 Program Status Register The CPU has an internal current program status register (CPSR), and 5 store program status registers (SPSRs) which the exception handlers use. These registers perform the following functions: · Storing information that is related to ALU computation executed last · Interrupt permit/prohibit control · CPU operating mode setting Figure 2-5 shows the bit layout in the program status register. Condition code flags (Reserved) 31 30 29 28 27 26 25 24 23 N Z C V Control bits 8 7 I 6 F 5 T 4 3 2 1 0 M4 M3 M2 M1 M0 Overflow Carry/borrow/extension Zero Negative/below Mode bits State bit FIQ disable bit IRQ disable bit Figure 2-5 Program Status Register Format 2.9.1 Condition Code Flags The condition code flags have the N, Z, C, and V bits. These flags change according to the result of the arithmetic and logic operations, and are tested to determine whether or not an instruction is to be executed. In ARM state, all the instructions are executed conditionally. In THUMB state, only the branch instruction is executed conditionally. 2­6 ML70511 ML70511 Family User's Manual Chapter 2 CPU 2.9.2 Control Bits The lower 8 bits (I, F, T and M[4:0]) in PSR are collectively called the control bits. These bits change when an exception occurs. If the CPU is operating in the privileged mode, the bits can be manipulated by software. T bit: Interrupt prohibit bits: Mode bits: M[4:0] 10000 This bit is used to specify the CPU operating state. When this bit is set, the CPU runs in the THUMB state; and when this bit is cleared, the CPU runs in the ARM state. Please note that the software must not change the status of T bit in CPSR. If changed, the CPU may be in an unpredictable state. The I and F bits are used to inhibit the interrupts. When set, the bits will inhibit the IRQ interrupt and FIQ(*) interrupt, respectively. The M4, M3, M2, M1, and M0 bits (M[4:0]) are the mode bits. These bits are used to determine the CPU operating mode, as shown in Table 2-1. Since all combinations of the mode bits not always provide an effective CPU operating mode, please use the specified combinations only. Also note that if inappropriate values are programmed to the mode bits M[4:0], the CPU will be in an unpredictable state. Mode User Registers in THUMB state Registers in ARM state R7.R0, R14.R0, LR,SP, PC,CPSR PC,CPSR 10001 PC,CPSR,SPSR_fiq R12.R0, LR_irq,SP_irq, R14_irq.R13_irq, PC,CPSR,SPSR_irq PC,CPSR,SPSR_irq R14_abt.R13_abt, PC,CPSR,SPSR_abt R7.R0, R12.R0, LR_und,SP_und, R14_und.R13_und, PC,CPSR,SPSR_und PC,CPSR,SPSR_und R7.R0, R14.R0, LR,SP, System R12.R0, PC,CPSR,SPSR_abt 11111 PC,CPSR,SPSR_svc R7.R0, Undefined R14_svc.R13_svc, LR_abt,SP_abt, 11011 R12.R0, PC,CPSR,SPSR_svc Abort R7.R0, LR_svc,SP_svc, 10111 Supervisor R14_fiq.R8_fiq, R7.R0, IRQ R7.R0, PC,CPSR,SPSR_fiq 10011 R7.R0, LR_fiq,SP_fiq, 10010 FIQ (*) PC,CPSR PC,CPSR Reserved bits: The remaining PSR bits are reserved. Please note that these unused bits are not changed when changing the PSR flag or the control bits. (*): The ML70511 ML70511 family does not support the FIQ input pin. 2­7 ML70511 ML70511 Family User's Manual Chapter 2 CPU 2.10 Exceptions An exception occurs when a need arises to interrupt the normal flow of a program to process an interrupt from a peripheral device, for example. The current CPU status must be stored prior to processing the exception so that the original program can be resumed at the end of the handler routine. A number of exceptions may occur simultaneously. In this situation, the exceptions are processed in a determined sequence. Refer to section 2.10.10, Exception Priority Sequence. 2.10.1 Operation at the Start of Exception Processing an exception involves the following operations: 1. Storing address of the next instruction in the pertinent link register If an exception has occurred in the ARM state, address of the next instruction is copied to the link register. (The current PC value becomes PC+4 or PC+8, depending on the exception type. Refer to Table 2-2 "Exception Start/Stop" for the details.) If an exception has occurred in the THUMB state, the PC value with offset is written to the link register so that the program resumes from correct address when recovering from the exception. It signifies that it is not necessary for the exception handler to judge the state from which the exception occurred. In the case of SWI, for example, the SWI always returns to the next SWI instruction by executing MOVS PC, R14_svc regardless of whether SWI was executed in the ARM or THUMB state. 2. Copying CPSR to respective SPSR 3. Letting the CPSR mode bits be in conformity with the exception values 4. Setting the PC to fetch the next instruction from the pertinent exception vector Also, the interrupt inhibit flag is set in order to avoid the system control becoming non-functional due to the occurrence of multiple exceptions If the CPU is in THUMB state when an exception is generated, the CPU will automatically switch from the THUMB to ARM state when the exception vector address is loaded into PC. 2.10.2 End of Exception Operation The exception handler performs the following operations at the end of the exception: 1. Decrements the necessary offset portion only, and moves the link register contents to the PC. (The offset varies by the exception type.) 2. Copies back SPSR to CPSR. 3. Clears the interrupt inhibit flag, if set when the exception started. Note: Since the T bit is set to a value stored just before the start of the exception when recovering CPSR from SPSR, it is not necessary to return in advance to the THUMB state. 2­8 ML70511 ML70511 Family User's Manual Chapter 2 CPU 2.10.3 Exception Start/End Operations Table 2-2 shows the PC values stored in R14 at the start of exception, and the recovery instructions to end the exception handler. Table 2-2 Start/End of the Exceptions Previous state Recovery instruction BL SWI UDEF FIQ (*) ARM THUMB R14_x Note R14_x MOV PC , R14 PC+4 PC+2 1 MOVS PC , R14_svc PC+4 PC+2 1 MOVS PC , R14_und PC+4 PC+2 1 SUBS PC , R14_fiq , #4 PC+4 PC+4 2 IRQ SUBS PC , R14_irq , #4 PC+4 PC+4 2 PABT SUBS PC , R14_abt, #4 PC+4 PC+4 1 SUBS PC , R14_abt, #8 PC+8 PC+8 3 - - 4 DABT RESET NA Notes: 1. PC is the address of BL/SWI/undefined instructions. (*) 2. PC is an instruction that could not be executed because FIQ or IRQ was prioritized. 3. PC is an address of the load or store instruction that generated data abort. 4. An unspecified value is stored in R14_svc at the time of system reset. (*): The ML70511 ML70511 family does not support the FIQ input pin. 2.10.4 FIQ(*) FIQ(*) (fast interrupt request) exception is set to support data transfer or channel processing. Since enough private registers are provided in the ARM state, it is not necessary to save aside the registers. (Consequently, it minimizes the context switching overhead.) The FIQ(*) handler must execute the next instruction to end the interrupt regardless of whether the exception was generated in ARM or THUMB state: SUBS PC, R14_fiq,#4 The FIQ(*) can be inhibited by setting the F flag in CPSR. (However, please note that it is not possible to inhibit FIQ(*) in the User mode.) (*): The ML70511 ML70511 family does not support the FIQ input pin. 2.10.5 IRQ IRQ (interrupt request) exception is used as a normal request. The IRQ has lower priority than FIQ(*) and is masked when the FIQ(*) sequence starts. It is possible to inhibit IRQ any time by setting the I bit of CPSR. However, the IRQ can be inhibited in the privileged (non-User) mode only. The IRQ handler must execute the next instruction to end the interrupt regardless of whether the exception was generated in ARM or THUMB state: SUBS PC, R14_irq,#4 (*): The ML70511 ML70511 family does not support the FIQ input pin. 2­9 ML70511 ML70511 Family User's Manual Chapter 2 CPU 2.10.6 Abort Abort is generated if the current access to memory could not complete. The ARM7TDMI processor detects the abort during the memory access cycle. Abort has the following 2 types: Pre-fetch abort: Generated at the time of pre-fetch instruction. Data abort: Generated when accessing data Although the pre-fetched instruction is marked invalid when the pre-fetch abort is generated, the exception is not processed until the instruction has arrived at the top of pipeline. The abort is not generated if the instruction involving branching (a situation where the program's execution could follow one of two paths), as one of the reasons, could not be executed while the instruction is in the pipeline. 1. If write back has been set in the single data transfer instructions (LDR, STR), then the modified base register is written back. It is necessary for the abort handler to take note of this. 2. Aborted assuming that the swap instruction (SWP) could not be executed at all. 3. The block data transfer instructions (LDM, STM) end. The base register will update if the write back has been set. The overwriting can be avoided if the instructions have been set to overwrite the base register by data (if the base register is in transfer list). Overwriting of all the registers is avoided after the abort is performed. This means that R15 (always the last register to be transferred) is stored even if the LDM instruction in particular is aborted. When the cause of abort is removed, the abort handler need to execute the following instruction regardless of the state (ARM or THUMB) in which the abort was generated: Pre-fetch abort: SUBS PC, R14_abt,#4 Data abort: SUBS PC, R14_abt,#8 These instructions will recover both the PC and CPSR, and re-execute the aborted instructions. 2.10.7 Software Interrupt The software interrupt (SWI) sets the CPU to the Supervisor mode. Normally, SWI is used to request special supervisory functions. The SWI handler must execute the following instruction for recovery regardless of the state (ARM or THUMB). MOV PC, R14_svc The instruction will recover both the PC and CPSR, and the SWI is again ready for the next instruction. 2.10.8 Undefined Instructions The undefined instruction trap is generated if the CPU tried to execute an instruction that cannot be processed. This mechanism can be utilized to extend the THUMB and ARM instructions by software emulation. After the emulation of an instruction that failed to execute, the trap handler must execute the next instruction regardless of the state (ARM or THUMB): MOVS PC, R14_und This will recover CPSR, and return to the next instruction in the undefined instructions. 2 ­ 10 ML70511 ML70511 Family User's Manual Chapter 2 CPU 2.10.9 Exception Vectors Table 2-3 shows the addresses of the exception vectors. Table 2-3 Exception Vectors and Addresses Address Exception Start mode 0x00000000 Reset Supervisor 0x00000004 Undefined instruction Undefined 0x00000008 Software interrupt Supervisor 0x0000000C Pre-fetch abort Abort 0x00000010 Data abort Abort 0x00000014 Reserved Reserved 0x00000018 IRQ IRQ 0x0000001C FIQ (*) FIQ (*): The ML70511 ML70511 family does not support the FIQ input pin. 2.10.10 Exception Priority Sequence When a number of exceptions are generated simultaneously, a pre-determined priority sequence system will predict the order of processing the exceptions. Highest Priority: 1: Reset 2: FIQ(*) 3: IRQ Lowest Priority: 4: Undefined instructions, software interrupt All the exceptions do not generate at the same time. Since the undefined instructions and software interrupt correspond to the specific (non-overlap) decoding of each instruction, the exceptions are not generated at the same time. (*): The ML70511 ML70511 family does not support the FIQ input pin. 2.11 Reset After the system reset, the CPU performs the following operations: 1. Overwrites R14_svc and SPSR_svc by copying the PC and CPSR current values to R14_svc and SPSR_svc. The saved PC and SPSR values are undefined. 2. Sets M[4:0] to 10011 (Supervisor mode), sets I and F bits of CPSR, and clears T bit of CPSR. 3. Sets PC to fetch the next instruction from address 0x00. 4. The CPU resumes executing a program in the ARM state. 2 ­ 11 Chapter 3 Memory Control Function ML70511 ML70511 Family User's Manual Chapter 3 Memory Control Function Chapter 3 Memory Control Function 3.1 General Description A variety of memories and registers are arranged in 4 GB memory space. This memory space is partitioned into 32 banks (1 bank is 128 MB). The memory control function performs the cache on/off control for every bank and allows assignment to the boot bank (remap function). 3.2 Memory Map Figure 3-1 shows a memory map of the ML70511 ML70511 family. Bank 31 30 29 Cache 28 27 26 25 Address F800_0000H 0000H F000_0000H 0000H E800_0000H 0000H External memory 2 E000_0000H 0000H D800_0000H 0000H 10 9 D000_0000H 0000H C800_0000H 0000H C000_0000H 0000H B800_3000H 3000H External memory 1 Built-in flash memory SIO2 Timer2 B800_2000H 2000H B800_1000H 1000H Control2 B800_0000H 0000H B100_1000H 1000H Timer1 USB B100_0C00H 0C00H B100_0800H 0800H 24 23 C000_0000H 0000H B800_0000H 0000H 22 21 B000_0000H 0000H A800_0000H 0000H 20 19 A000_0000H 0000H 9800_0000H 0000H UART PIO B100_0400H 0400H B100_0000H 0000H 18 17 9000_0000H 0000H 8800_0000H 0000H SIO1 B000_1000H 1000H B000_0C00H 0C00H 16 8000_0000H 0000H BBC B000_0400H 0400H 15 14 7800_0000H 0000H 7000_0000H 0000H 13 12 11 6800_0000H 0000H 6000_0000H 0000H 5800_0000H 0000H 10 9 2 5000_0000H 0000H 4800_0000H 0000H 8 7 0800_0000H 0000H 0000_0000H 0000H AHBRAM(32KB) IRC 7830_0000H 0000H 7820_0000H 0000H 7810_0000H 0000H 7800_0000H 0000H 5800_0000H 0000H 1800_0000H 0000H 1000_0000H 0000H 1 0 Cache Control XMC 2800_0000H 0000H 2000_0000H 0000H 3 2 Control1 and WDT B000_0000H 0000H 8000_0000H 0000H 3000_0000H 0000H 5 4 AHB I/O 4000_0000H 0000H 3800_0000H 0000H 6 APB I/O 16 AHBRAM 5000_8000H 8000H 5000_0000H 0000H Reserved area *2 Boot bank Figure 3-1 ML70511 ML70511 Family Memory Map *1: The built-in flash memory is not mounted on ML70511 ML70511 (mounted on ML70Q511 ML70Q511). *2: Access to the reserved area generates an error interrupt. 3­1 ML70511 ML70511 Family User's Manual Chapter 3 Memory Control Function 3.2.1 Registers Table 3-1 shows a list of address ranges for every function. Table 3-1 Function Block Address Ranges Function block Address range IRC 7800_0000H 0000H to 780F_FFFFH XMC 7810_0000H 0000H to 781F_FFFFH Cache Control 7820_0000H 0000H to 782F_FFFFH Control1 and WDT B000_0000H 0000H to B000_03FFH 03FFH Bluetooth Baseband Controler B000_0400H 0400H to B000_0BFFH SIO1 B000_0C00H 0C00H to B000_0FFFH GPIO B100_0000H 0000H to B100_03FFH 03FFH UART B100_0400H 0400H to B100_07FFH 07FFH USB B100_0800H 0800H to B100_0BFFH TIMER1 B100_0C00H 0C00H to B100_0FFFH Control2 B800_0000H 0000H to B800_0FFFH TIMER2 B800_1000H 1000H to B800_1FFFH SIO2 B800_2000H 2000H to B800_2FFFH Note 1: Access to addresses outside the above-mentioned ranges will generate an error interrupt. Note 2: An address may not be continuous even if inside the above-mentioned ranges. Does not generate an error interrupt in the registers' unmounted area. 3.2.2 Memory Table 3-2 shows a list of the address ranges of each memory. Table 3-2 Memory Address Ranges Address range AHBRAM Built-in flash memory C800_0000H 0000H to C807_FFFFH *2 External memory 1 D000_0000H 0000H to D00F_FFFFH *2 External memory 2 *1: *2: 5000_0000H 0000H to 5000_7FFFH *1 F000_0000H 0000H to F00F_FFFFH *2 Accessing an address outside the range in the same bank will generate an error interrupt. Accessing an address outside the range in the same bank will not generate an error interrupt. 3­2 ML70511 ML70511 Family User's Manual Chapter 3 Memory Control Function 3.3 Description of Signals Table 3-3 Memory Control Function Pins Signal name I/O Initial value BBWSEL I Description - BANK0 area bit width setting pin L: 8 bits H: 16 bits REMAP setting pin at boot REMAP = 0: Reserved REMAP I 1: Stacked flash ROM - 2: External MCS1 device 3: External MCS0 device 3.4 List of Registers Table 3-4 Register of Memory Control Function Address Name Symbol R/W Initial value B800_0010H 0010H Remap control register RMPCON R/W 00H 3.5 Description of Registers 3.5.1 Remap Control Register (RMPCON) This register controls the remap. After writing 3CH, the register makes it possible to write each setting value by the write protect function. RMPCON Initial value 7 0 0 6 0 0 5 0 0 4 0 0 3 RMPM3 0 2 RMPM2 0 1 RMPM1 0 0 RMPM0 0 Address: B800-0010H B800-0010H R/W: R/W 0000 Depends on REMAP pin setting 1000 Remaps external memory 1 1010 Remaps AHBRAM Other than above Figure 3-2 RMPCON Configuration 3­3 Reserved ML70511 ML70511 Family User's Manual Chapter 3 Memory Control Function 3.6 Remap Function The remap function in the ML70511 ML70511 family rearranges each memory bank to bank 0 (0000_0000H 0000H to 07FF_FFFFH) that starts the program execution during boot. There are 2 means to realize remap function at boot: one depends on the REMAP0-1 pin, and the other by entering a value to the internal register with software. Method-1: At reboot, the remap function by REMAP0-1 pin operates as shown in Table 3-5. Table 3-5 Remap Function at Boot REMAP1 REMAP0 Bank to be remapped Area to be remapped L L - Reserved L H 25 Built-in flash memory H L 26 External memory 1 H H 30 External memory 2 Method-2: The remap function at boot operates by setting value of RMPM register (B800_0010H 0010H), as shown in Table 3-6, after the software has started to operate. Table 3-6 Remap Register Setting RMPM value Bank to be remapped 0000b (Initial value) Area to be remapped Depends on REMAP0-1 pin (Refer to Table 3-3.) 1000b 26 External memory 1 1010b 10 AHBRAM Other than the above - Reserved The remapped external memories 1 and 2 become unaccessible by the original addresses (internal flash memory: C800_0000H 0000H to external memory 1: D000_0000H 0000H to external memory 2: F000_0000H 0000H to .). The setting registers of each memory area are shown in Table 3-7. Table 3-7 Setting Registers for Each Memory Area RMPM 0000b 01b REMAP0, 1 Built-in flash memory Built-in flash memory 0000b 0000b 1000b 1010b 10b 11b Arbitrary Arbitrary External memory 1 External memory 2 External memory 1 AHBRAM BOOTROM Not usable Not usable ROM ROM External memory 1 SRAM BOOTROM SRAM SRAM SRAM External memory 2 I/O I/O BOOTROM I/O I/O BOOTROM BOOTROM BOOTROM SRAM Not settable Bank0 BOOTROM: ROM: SRAM: I/O: ROMAC, ROMPC, BBWSEL pins ROMAC, ROMPC, BWROM0-1 of BWC register, SRAMAC, SRAMPC, BXSRAM0-1 of BWC register IOAC1, IOAC2, BWIO0-1 of BWC register 3­4 ML70511 ML70511 Family User's Manual Chapter 3 Memory Control Function 3.7 Bus Width at Boot To boot by external memories 1 and 2, the BBWSEL pin is set to "L" if the bus width of booting external memories is 8 bits, and set to "H" if the bus width is 16 bits. However, in the case of booting from the built-in flash memory, the bus width is fixed to 16 bits regardless of the BBWSEL pin. Table 3-8 shows the bus width setting at boot. Table 3-8 Bus Width Setting at Boot BBWSEL Boot memory L H External memory 1 8 bits 16 bits External memory 2 8 bits 16 bits Built-in flash memory 16 bits 3­5 Chapter 4 LSI Control Function ML70511 ML70511 Family User's Manual Chapter 4 LSI Control Function Chapter 4 LSI Control Function 4.1 General Description The LSI