NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: SP305 SP305 Spartan-3 Development Platform User Guide UG216 UG216 (v1.1) March 3, 2006 UG216 UG216 (v1.1) March 3, 2006 SP305 SP305 Spartan-3 Development Platform User Guide www.xilinx.com R Xilinx is disclosing this Document and Intellectual Property (hereinafter "the Design") to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or t ... | Original |
43 pages, |
push button switch 2 pin rj45 to ps2 S01602DTR Lumex lcd 16 SP305 PIN DIAGRAM OF RJ45 to usb Xilinx Parallel Cable IV spartan-3 SPARTAN 6 ethernet datasheet cypress CY7C67300 spartan 3a pcb connector 2 pin push button mcp2515 source SP305 abstract |
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| Abstract: Boards ML320 ML320 ML321 ML321 ML323 ML325 ML325 ML421 ML421 ML423 ML423 References 1. Xilinx Aurora Web site ... | Original |
12 pages, |
UG-058 DS083 DS112 DS128 ML321 ML323 ML423 sp002 testbench of an aurora ML325 ML320 ML421 2310 fx DS128 abstract |
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| Abstract: port on the board and an additional serial port on the PC. There is only one serial port on the ML323. , PHY cards available for the ML323. SMA cables can be used to connect the MGT inputs and outputs to a , additional serial port on the PC. There is only one serial port on the ML323. This is used to connect to the , There is only one serial port on the ML323. This is used to connect to the PC. J52 must be fitted and , Demonstration ML310 ML310 (2VP30 2VP30) ML323 (2VP20 2VP20 & 2VP50 2VP50) ML401 ML401 (4LX25 4LX25) ML403 ML403 (4FX12 4FX12) Not Supported ... | Original |
37 pages, |
XAPP443 Gemac marvell ethernet switch sgmii ML310 ML323 ML401 V30 CPU block diagram of broadcom sgmii sfp virtex ML403 FPGA UART HW-AFX-SMA-SFP XAPP443 abstract |
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| Abstract: Application Note: Virtex-II Pro Family R RocketIO Transceiver Bit-Error Rate Tester Author: Dai Huang and Michael Matera XAPP661 XAPP661 (v2.0.2) May 24, 2004 Summary This application note describes the implementation of a RocketIOTM transceiver bit-error rate tester (BERT) reference design demonstrating a serial link (1.0 Gb/s to 3.125 Gb/s) between two RocketIO multi-gigabit transceivers (MGT) embedded in a single Virtex-II ProTM FPGA. To build a system, an IBM CoreConnectTM infrastru ... | Original |
32 pages, |
Xilinx Ethernet development PPC405 simple 32 bit LFSR using verilog verilog code 16 bit LFSR verilog code 8 bit LFSR verilog HDL program to generate PWM XAPP662 verilog code for 10 gb ethernet prbs using lfsr XAPP661 verilog code 16 bit LFSR in PRBS pattern generator datasheet abstract |
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| Abstract: BOT12 BOT12 ml321_2vp7/bit/ml321_2vp7_top0bot3.bit < > TOP56 < > BOT03 BOT03 BOT12 BOT12 BOT47 BOT47 < > BOT56 BOT56 , Reference Design User Guide UG064 UG064 (v2.4) P/N 0402272 May 28, 2004 < > < > XC2VP50 XC2VP50 -FF1517 -FF1517 TOP47 < > ML324 ML324 TOP12 < > XC2VP50 XC2VP50 -FF1152 -FF1152 TOP03 ml323_2vp50/bit ... | Original |
42 pages, |
XC5210 B11 toggle switches ML320 ML321 ML324 TOP47 ug063 XC2064 XC3090 XC4005 ACE FLASH UG064 UG064 abstract |
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| Abstract: Mesh Fabric Reference Design Application Note XAPP698 XAPP698 (v1.2) February 15, 2005 R R "Xilinx" and the Xilinx logo shown above are registered trademarks of Xilinx, Inc. Any rights not expressly granted herein are reserved. CoolRunner, RocketChips, Rocket IP, Spartan, StateBENCH, StateCAD, Virtex, XACT, XC2064 XC2064, XC3090 XC3090, XC4005 XC4005, and XC5210 XC5210 are registered trademarks of Xilinx, Inc. The shadow X shown above is a trademark of Xilinx, Inc. ACE Controller, ACE Flash, A.K.A. Speed, Alli ... | Original |
88 pages, |
XC5210 XC4005 XC3090 XC2VP40 XC2VP30 XC2VP20 XC2VP100 XC2064 XAPP698 XAPP698 abstract |
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| Abstract: Application Note: Virtex-II Pro Family R Configurable Physical Coding Sublayer Author: Dai Huang, Jack Lo, and Shalin Sheth XAPP759 XAPP759 (v1.1) March 4, 2005 Summary This application note describes a Configurable Physical Coding Sublayer (CPCS) reference design that extends the functionality of the Xilinx RocketIOTM multi-gigabit transceiver (MGT) blocks in the VirtexTM-II Pro FPGA family. Introduction The CPCS reference design provides a multi-mode PCS layer for Fibre Channel ( ... | Original |
36 pages, |
XAPP759 verilog code for fibre channel PPC405 CPCS BOARD POWER SUPPLY 1000BASE-X datasheet abstract |
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| Abstract: design. Implementation constraints files for ML310 ML310 and ML323 boards. Synthesis , file for implementing design on ML323 board. BMM file for EDK subsystem. www.xilinx.com 15 ... | Original |
19 pages, |
XAPP698 ML310 ML321 ML323 vhdl code for bram vhdl code for memory card vhdl code for memory in cam Virtex 5 for Network Card XAPP541 XAPP691 vhdl code for crossbar switch LocalLink single port ram testbench vhdl datasheet abstract |
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| Abstract: Pro ML320 ML320, ML321 ML321, ML323 Platform User Guide, http://www.xilinx.com/bvdocs/userguides/ug033.pdf ... | Original |
13 pages, |
XAPP572 vhdl code fc 2 verilog code of 8 bit comparator RXRECCLK on error correction code in fpga in vhd XAPP581 datasheet abstract |
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| Abstract: connections between the SDRAM daughter card and the ML320 ML320, ML321 ML321, and ML323 Development Platforms. Table 1 , ML321 ML321 ML323 1 DQ5 D2 A2 N2 2 DQ7 E2 C2 P2 3 DQ1 F2 D2 R2 , ML321 ML321 ML323 1 DQ3 E4 E4 K5 2 DQ6 F4 G4 L3 3 DQ4 F5 H4 M3 ... | Original |
13 pages, |
XC5210 XC4005 XC3090 XC2064 ML321 ML320 ML323 datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| #!xilperl #= # # File Name: build_all.pl # Version: 1.0.0 # Date: 2004-04-23 # Company: Xilinx, Inc. # # Disclaimer: LIMITED WARRANTY AND DISCLAIMER. # These designs are provided to you "as is". Xilinx and its # licensors make and you receive no warranties or conditions, # express, implied, statutory or otherwise, and Xilinx # www.datasheetarchive.com/download/23037380-996044ZC/xapp759.zip (build_all.pl) |
Xilinx | 26/04/2004 | 2752.08 Kb | ZIP | xapp759.zip |
| ##- ## ## File Name: cpcs_test_ml323_2vp50.ucf ## Project: Configurable PCS Reference Design ## Version: 1.0.0 ## Date: 2004-04-23 ## ## Company: Xilinx, Inc. ## Contributor: Embedded Networking Systems Engineering Group ## ## Disclaimer: LIMITED WARRANTY AND DISCLAIMER. ## These designs are provided to you "as is". Xilinx and its ## licensors m www.datasheetarchive.com/download/23037380-996044ZC/xapp759.zip (cpcs_test_ml323_2vp50.ucf) |
Xilinx | 26/04/2004 | 2752.08 Kb | ZIP | xapp759.zip |
| ##- ## ## File Name: README ## Project: Configurable PCS Reference Design ## Version: 1.0.0 ## Date: 2004-04-23 ## ## Company: Xilinx, Inc. ## Contributor: Embedded Networking Systems Engineering Group ## ## Contact: hotline@xilinx.com phone + 1 800 255 7778 ## ## Disclaimer: LIMITED WARRANTY AND DISCLAIMER. ## These designs are provided to you "as i www.datasheetarchive.com/download/23037380-996044ZC/xapp759.zip (readme) |
Xilinx | 26/04/2004 | 2752.08 Kb | ZIP | xapp759.zip |
| - - - File Name: cpcs_test.vhd - Project: Configurable PCS - Version: 1.0.0 - Date: 2004-04-23 - - Company: Xilinx, Inc. - Contributors: Embedded Networking Systems Engineering Group - - Disclaimer: LIMITED WARRANTY AND DISCLAIMER. - These designs are provided to you "as is". Xilinx and its - licensors make and you receive no warranties or conditions, - www.datasheetarchive.com/download/23037380-996044ZC/xapp759.zip (cpcs_test.vhd) |
Xilinx | 26/04/2004 | 2752.08 Kb | ZIP | xapp759.zip |
| #= # # File Name: Makefile # Version: 2.4 # Date: 2004-03-15 # Company: Xilinx, Inc. # # Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR # INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING # PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY # PROVIDING THIS DESIGN, CODE, OR INFORMATION AS # ONE POSSIBLE IMPLEMENTATION OF www.datasheetarchive.com/download/299812-996019ZC/xapp661.zip (Makefile) |
Xilinx | 27/05/2004 | 18173.45 Kb | ZIP | xapp661.zip |
| Systems Engineering Group: Reference System User Guide ML32X ML32X ML32X ML32X Virtex-II Pro RocketIO Transceiver BERT Reference System User Guide June 19, 2003 Revision: 2.2 www.xilinx.com 1 1-800-255-7778 Introduction The Virtex-II Pro™ RocketIO™ MGT (Multi-Gigabit Transceiver) BERT Reference System demonstrates a 2.5 Gb/s to 3.125 Gb/s serial link between two RocketIO transceiver ports, embedded within a single Virtex-II Pro FPGA. Figure 1 illustrates a block diagram of the RocketIO Transceiver BERT Reference www.datasheetarchive.com/download/299812-996019ZC/xapp661.zip (ml32x_bert_demo_ug_v_2_2.pdf) |
Xilinx | 27/05/2004 | 18173.45 Kb | ZIP | xapp661.zip |
| CompactFlash Image Content: RocketIO BERT Ref Design Demo ACE Files Platform: ml323-2vp20 Version: 2.3, Build: Nov 26, 2003 Addr 0: configuration top03 Addr 1: configuration top12 Addr 2: configuration bot03 Addr 3: configuration bot12 Addr 4: configuration top0bot3 www.datasheetarchive.com/download/299812-996019ZC/xapp661.zip (content.txt) |
Xilinx | 27/05/2004 | 18173.45 Kb | ZIP | xapp661.zip |
| #Automatically generated. PLEASE DO NOT MODIFY. dir = ml323; cfgaddr0 = rev0; cfgaddr1 = rev1; cfgaddr2 = rev2; cfgaddr3 = rev3; cfgaddr4 = rev4; www.datasheetarchive.com/download/299812-996019ZC/xapp661.zip (xilinx.sys) |
Xilinx | 27/05/2004 | 18173.45 Kb | ZIP | xapp661.zip |
| CompactFlash Image Content: RocketIO BERT Ref Design Demo ACE Files Platform: ml323-2vp50 Version: 2.3, Build: Nov 26, 2003 Addr 0: configuration top03 Addr 1: configuration top12 Addr 2: configuration top47 Addr 3: configuration top56 Addr 4: configuration bot03 Addr 5: configuration bot12 Addr 6: configuration bot47 Addr 7: configuration bot56 www.datasheetarchive.com/download/299812-996019ZC/xapp661.zip (content.txt) |
Xilinx | 27/05/2004 | 18173.45 Kb | ZIP | xapp661.zip |
| #Automatically generated. PLEASE DO NOT MODIFY. dir = ml323; cfgaddr0 = rev0; cfgaddr1 = rev1; cfgaddr2 = rev2; cfgaddr3 = rev3; cfgaddr4 = rev4; cfgaddr5 = rev5; cfgaddr6 = rev6; cfgaddr7 = rev7; www.datasheetarchive.com/download/299812-996019ZC/xapp661.zip (xilinx.sys) |
Xilinx | 27/05/2004 | 18173.45 Kb | ZIP | xapp661.zip |