ML2330 ML2330ES ML2330IS - Datasheet Archive

 

ML2330* Selectable Dual 3V/3.3V/5V 8-Bit DACs GENERAL DESCRIPTION FEATURES The ML2330 Selectable Dual 3V/3.3V/5V 8-bit DACs are

 

July 2000 ML2330 ML2330* Selectable Dual 3V/3.3V/5V 8-Bit DACs GENERAL DESCRIPTION FEATURES The ML2330 ML2330 Selectable Dual 3V/3.3V/5V 8-bit DACs are dual voltage output digital-to-analog converters which can be independently programmed, or powered down to conserve power. The devices are intended for use in portable or low power 3V systems where space is critical. s 3V ±10%, 3.3 ±10% or 5V ±10% operation s Low supply current (3.5mA max) Individual and full power down (down to 1µA) Programming access to the DACs is provided over a high speed (10Mb/s), 3-wire serial interface which is compatible to the SPITM and MicrowireTM data formats. In addition to independent programming of the DAC output voltages, each device may be powered down, independent of the other DAC, to conserve power. Each DAC draws 2mA maximum quiescent current when operating, and typically less than 1µA when powered down. s s 10Mb/s three-wire serial interface, compatible to SPI and Microwire s s 8-pin SOIC package Available in Extended Commercial temperature range (­20°C to 70°C) and Industrial temperture range (­40°C to 85°C) s Guaranteed monotonicity The device comes in an 8-pin SOIC package and in a special Extended Commercial temperature range (­20°C to 70°C) or Industrial temperture range (­40°C to 85°C). *Some Packages Are End Of Life Or Obsolete BLOCK DIAGRAM 8 VCC R E G 2 1 3 4 OUT A DAC A 7 20k SCLK DIN CS CONTROL AND TIMING VREF POWER DOWN DOUT R E G OUT B DAC B 6 20k GND 5 REV. 1.0 10/10/2000 ML2330 ML2330 PIN CONFIGURATION PIN DESCRIPTION PIN NAME ML2330 ML2330 FUNCTION 1 8 VCC SCLK 2 7 OUT A CS 3 6 OUT B DOUT 4 5 GND TOP VIEW 2 SCLK Serial Clock 3 CS Chip Select 4 DOUT Data Out 5 GND Ground 6 OUT B Output of DAC B OUT A Output of DAC A 8 1 Data In 7 DIN DIN 2 8-Pin SOIC (S08) VCC Positive Supply REV. 1.0 10/10/2000 ML2330 ML2330 ABSOLUTE MAXIMUM RATINGS OPERATING CONDITIONS Supply Voltage (VCC) . 6.0V GND . ­0.3V to VCC + 0.3V Logic Inputs . ­0.3V to VCC + 0.3V Input Current per Pin . ±25mA Storage Temperature . ­65°C to 150°C Package Dissipation at TA = 25°C . 750mW Lead Temperature (Soldering 10 sec.) SOIC . 150°C Supply Voltage (VCC) ML2330ES ML2330ES­2 . 3V ± 10% ML2330ES ML2330ES­3 . 3.3V ± 10% ML2330ES ML2330ES­5 . 5V ± 10% Temperature Range ML2330ES ML2330ES . ­20°C to 70°C ML2330IS ML2330IS . ­40°C to 85°C ELECTRICAL CHARACTERISTICS Unless otherwise specified, TA = TMIN to TMAX, VCC = Operating Supply Voltage Range, fCLK = 10MHz RL = 1k, (RL = 2k for VCC = 5V), CL = 100pF (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Converter Resolution 8 bits Integral Linearity Error ILE ±1.5 LSB Differential Linearity Error DLE ±1 LSB Offset Error VCC = 3.3V or 3.0V 10 20 30 mV I Suffix 5 20 35 mV E Suffix 15 25 35 mV I Suffix 10 25 40 mV ±5 VCC = 5V E Suffix %FS 2 mA Gain Error Analog Output Output Drive Current Power Supply Rejection Ratio IOUTPP PSRR Full scale output @00 & FF 40 dB Digital and DC Logic Input Low VIL VCC = 3V, 3.3V, or 5V 0.8 V Logic Input High VIH VCC = 3V or 3.3V 2.0 V VCC = 5V 2.8 V ­1 µA Logic Input Low Current IIL VIN = GND Logic Input High Current IIH VIN = VCC 1 µA Logic Output Low VOL I = 3.2mA 0.4 V Logic Output High VOH I = 0.4mA Supply Current ICC Power Down Current 2.4 RL = All digital inputs at static 0V or VCC V 2.5 3.5 mA VCC = 3V 3 µA VCC = 5V 5 µA 10 µs AC Performance Settling Time tS ±1/2 LSB 5 Slew Rate Crosstalk Note 1: 1.4 60 V/µs dB Limits are guaratneed by 100% testing, sampling or correlation with worst case test conditions. REV. 1.0 10/10/2000 3 ML2330 ML2330 TIMING CHARACTERISTICS (Serial Interface) VCC = Operating Supply Voltage Range, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Converter CS Fall to SCLK Setup Time tCSS 20 ns SCLK Rise to CS Rise Hold Time tCSH 50 ns DIN to SCLK Rise Setup Time tDS 20 ns DIN to SCLK Rise Hold Time tDH 20 ns SCLK Frequency fCLK 10 SCLK Duty Cycle MHz 40 SCLK to DOUT Valid tDO 60 % SCLK DIN DOUT CS 30 60 ns VCC = 3V ML2330 ML2330 VCC = 3.3V or 5V 45 90 ns ML2330 ML2330 MICROWIRE PORT 2 SK SO 1 DOUT DIN SPI PORT 4 MISO 1 MOSI 2 4 3 SCK SCLK SI CS I/O Figure 1a. Connections for Microwire. 3 I/O Figure 1b. Connections for SPI. CS SCLK DIN DOUT* A1 D0 A0 P1 P0 A1 A0 P1 D7 P0 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 *DOUT is the data from previous input. Figure 1c. Interface Timing 4 REV. 1.0 10/10/2000 ML2330 ML2330 CS tCSS tCSH SCLK tDS tDH DIN tDO DOUT Figure 2. Detail Interface Timing FUNCTIONAL DESCRIPTION SERIAL INTERFACE The ML2330 ML2330 communicates with microprocessors through a synchronous, full-duplex, 3-wire interface (figure 1A & B). At power on, the control registers are cleared and both DACs have high impedance outputs. Data timing shown in Figure 1C is sent MSB-first and can be transmitted in one 4-bit and one 8-bit packet or in one 12-bit word. If a 16-bit control word is used, the first four bits are ignored. The serial clock (SCLK) synchronizes the data transfer. Data is transmitted and received simultaneously. Figure 2 shows detailed serial interface timing. Note that the clock should be low between updates. DOUT does not go into a high impedance state if the clock idles or CS is high. Serial data is clocked into the data registers in MSB-first format, with the address and configuration information preceding the actual DAC data. Data is sampled on the SCLK's rising edge while CS is low. Data at DOUT is clocked out 12.5 clock cycles later, on the SCLK's falling edge. Chip Select (CS) must be low to enable the read or write operation. If CS is high, the interface is disabled and DOUT remains unchanged. CS must go low at least 10ns before the first clock pulse to properly clock in the first bit. With CS low, data is clocked into the ML2330 ML2330's internal shift register on the rising edge of the external serial clock. SCLK can be driven at rates up to 10MHz. SERIAL INPUT DATA FORMAT AND CONFIGURATION CODES The 12-bit serial input format shown in Figure 3 comprises two DAC address bits (A1, A0), two power down control bits (P1, P0) and eight bits of data (D7 . . . D0). DOUT A1 A0 P1 D7 . . . D0 DIN The 4-bit address/control code configures the DAC as shown in Table 1. A1 A0 Function 0 0 No operation 0 1 Select control bits and DAC A 1 0 Select control bits and DAC B 1 1 Select control bits and both DACs Table 1.1 Address Selection P1 P0 Function 0 0 Normal 0 1 Power down DAC A 1 0 Power down DAC B 1 1 Power down entire chip Table 1.2 Power Down Selection DAC OPERATION The DACs are implemented using an array of equal current sources that are decoded linearly for the four most significant bits to improve differential linearity and to reduce output glitch around major carries. A voltage difference between on-board bandgap reference voltage and GND is converted to a reference current using an internal resistor to set up the appropriate current level in the DACs. The DACs output current is then converted to a voltage output by an output buffer and a resistive network. The matching among the on-chip resistors preserves the gain accuracy between these conversions. Figure 3. Serial Input Format REV. 1.0 10/10/2000 5 ML2330 ML2330 VOLTAGE REFERENCE POWER DOWN MODE A bandgap voltage reference is incorporated on the ML2330 ML2330. It is trimmed for zero temperature coefficient at 25°C to minimize output voltage drift over the specified operating temperature range. There are three power-down modes in the ML2330 ML2330. By clearing the control bits P1-P0 (Table 3.2), the entire chip will be powered down with a supply current less than 5µA. Individual DACs can also be powered down to save power (1.75mA per DAC). OUTPUT BUFFER AND GAIN SETTING The output buffer converts the DAC output current to a voltage output using a resistive network. The outputs can swing from GND +0.02V to either 2.02V (3V) or 4.02V (5V). The DAC transfer function is: VOUT = K × DATA + 0.02 256 where K = 2 if VCC = 3V and K = 4 if VCC = 5V In the 3V operation, the amplifier outputs will settle to 1/2LSB in 10µs when loads are greater than 1k (2k for 5V operation) and capacitive loads smaller than 100pF. GAIN ERROR The graph below shows how gain error varies with temperature when VCC = 3.3V. Gain Error vs Temperature 0.4 0.3 0.2 0.1 GAIN ERROR (%) ­0.0 ­0.1 ­0.2 ­0.3 ­0.4 ­0.5 ­0.6 ­0.7 ­0.8 ­0.9 ­1.0 6 ­40 ­20 0 20 40 TEMPERATURE ( C) 60 80 100 REV. 1.0 10/10/2000 ML2330 ML2330 PHYSICAL DIMENSIONS inches (millimeters) Package: S08 8-Pin SOIC 0.189 - 0.199 (4.80 - 5.06) 8 PIN 1 ID 0.148 - 0.158 0.228 - 0.244 (3.76 - 4.01) (5.79 - 6.20) 1 0.017 - 0.027 (0.43 - 0.69) (4 PLACES) 0.050 BSC (1.27 BSC) 0.059 - 0.069 (1.49 - 1.75) 0º - 8º 0.055 - 0.061 (1.40 - 1.55) 0.012 - 0.020 (0.30 - 0.51) 0.004 - 0.010 (0.10 - 0.26) 0.015 - 0.035 (0.38 - 0.89) 0.006 - 0.010 (0.15 - 0.26) SEATING PLANE ORDERING INFORMATION PART NUMBER V CC TEMPERATURE RANGE PACKAGE ML2330ES ML2330ES­2 ML2330ES ML2330ES­3 (End Of Life) ML2330ES ML2330ES­5 (End Of Life) 3V 3.3V 5V ­20°C to 70°C ­20°C to 70°C ­20°C to 70°C 8-Pin SOIC (S08) 8-Pin SOIC (S08) 8-Pin SOIC (S08) ML2330IS ML2330IS­2 ML2330IS ML2330IS­3 (Obsolete) ML2330IS ML2330IS­5 3V 3.3V 5V ­40°C to 85°C ­40°C to 85°C ­40°C to 85°C 8-Pin SOIC (S08) 8-Pin SOIC (S08) 8-Pin SOIC (S08) DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com REV. 1.0 10/10/2000 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. © 2000 Fairchild Semiconductor Corporation 7