NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| MIPS64 20Kc | MIPS Technologies, Inc. | Microprocessor, 64-Bit Data Bus, 600|750MHz Processor, 352-BGA |
2 pages, |
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| MIPS645Kf | LSI Logic Corporation | Microprocessor, 64-bit Processor Core |
2 pages, |
Original | |
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| MIPS645Kf | MIPS Technologies, Inc. | 5Kf Processor Core |
45 pages, |
Original | |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: MIPS64 20Kc Processor Core TM Breakthrough 64-bit Performance for Revolutionary SOC Designs The drop-in MIPS64 20KcTM processor core delivers unprecedented integer, floating-point, and 3D , INNOVATION The exceptional integer and floating-point performance of the MIPS64 20Kc core greatly , high-performance SOCs through both foundry and traditional ASIC channels. · The MIPS64TM architecture is widely , U C T B R I E F MIPS64 20Kc Core ALU a ALU b Shifter Multi/Div ... | Original |
2 pages, |
R20K MIPS32 MIPS Technologies IEEE754 MIPS64 MIPS64 20Kc MIPS64 abstract |
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| Abstract: SR71010A SR71010A TM MIPS64 SUPERSCALAR MICROPROCESSOR ENGINES FOR THE DIGITAL AGE TM TM The SR71010A SR71010A is a true 2-way superscalar MIPS64 PC gen iTLB BHT buffer i-cache decode register , SR71010A SR71010A includes a high - per formance floating point unit (FPU) that is fully MIPS64 compliant. The FPU , High performance architecture · Fully MIPS64 Instruction Set Architecture (ISA) compliant True , High-performance floating point TM · Fully MIPS64 compliant · IEEE - 754 compatible · Decoupled from Integer ... | Original |
2 pages, |
SR71010 SR7101 line-locked MIPS64 ieee intelligent image processing L2 cache L3 cache SR71010A SR71010A abstract |
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| Abstract: RF-330 RF-330 Advanced Packet Optimizing card to enhance your x86 server with MIPS multi-core power Tremendous packet processing power with up to 16 MIPS64 processor cores n Rich built-in security features: compressiondecompression, encryption-decryption, regular expression, pattern matching , SPECIFICATION Processor Cavium OcteonTM CN38XX CN38XX series Multi-core MIPS64® SoCs Form Factor PCI-X board , RF-330 RF-330 - Temperature: -20 to 70°C - Humidity 5% to 95% RH (1) Cavium Processor MIPS64 ... | Original |
1 pages, |
Mini DIMM Socket CN3860 CAVIUM RF-330 MIPS64 CN3860-500 RF-330 abstract |
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| Abstract: ABOUT KiLIN KiLIN-6020 KiLIN-6030 Product Overview The wire speed performance in small packets, has been long attempted since day one. Portwell's Kilin family platforms achieve it by implementing the new generation MIPS64 technology from Cavium. To adapt this new technology, ISVs need time to , offers customers the opportunity to enjoy the synergy between x86 and MIPS64 technologies. No matter it , platforms equip all necessary security features in hardware based. Although there are up to sixteen MIPS64 ... | Original |
1 pages, |
secure wireless data communication KILIN-6005 data sheet for data voice system MIPS64 datasheet abstract |
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| Abstract: Supervisor mode operation · MIPS64-compatible instruction set Floating-point unit · Fully pipelined IEEE , 333 MHz MIPS64TM 5KfTM 64-bit Processor Core OVERVIEW FEATURES LSI Logic offers the MIPS64 5Kf processor core synthesized onto our Gflx 0.11 micron (drawn) high performance process , Gflx 0.11 micron (drawn) process technology · 64-bit Data and Address Path The MIPS64 5Kf is a , , printers, copiers, set-top boxes, digital television, and digital cameras. The Gflx MIPS64 5Kf core ... | Original |
2 pages, |
MIPS32 application MIPS32 cache architecture for MIPS 1 MIPS64 MIPS64TM MIPS64TM abstract |
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| Abstract: based on MIPS64® instruction set architecture (ISA) · DDR memory controller · Memory bandwidth , device is a MIPS64 processor core-based system-on-a-chip (SOC) that offers industry-leading performance , Broadcom SB-1 high-performance MIPS64 CPUs, a shared 1-MB L2 cache, a DDR memory controller, and an , system can be run in either big-endian or little-endian mode. Implementation of MIPS64 ISA The SB-1 CPU core is a high-performance implementation of the standard MIPS64 ISA that incorporates the MIPS-3D and ... | Original |
2 pages, |
MIPS64 memory bus architecture MIPS64 BCM1480 BCM1455 BCM1280 BCM1255 BCM1250 BCM112X 64-BIT BCM1280 abstract |
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| Abstract: Programming ease and flexibility based on MIPS64® instruction set architecture (ISA) Broad tools and , ) 1 Gbps BCM1255 BCM1255 Block Diagram The BCM1255 BCM1255 device is a MIPS64 processor core-based , chip multiprocessor (CMP) system consisting of two Broadcom SB-1 high-performance MIPS64 CPUs, a , run in either big-endian or little-endian mode. Implementation of MIPS64 ISA The SB-1 CPU core is a high-performance implementation of the standard MIPS64 ISA that incorporates the MIPS-3D and MIPS-MDMX ... | Original |
2 pages, |
BCM5841 BCM1280 BCM1255 BCM1250 BCM112X MIPS64 64-BIT BCM1255 abstract |
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| Abstract: MHz 800 MHz · MIPS64TM CPU pipeline; dual execute, dual memory pipes · Quad-issue in order · , on MIPS64 ISA · Scalable system architecture · Broad tools and system software support · , intelligent systems on a chip consisting of a Broadcom SB-1 high performance MIPS64 CPU, a shared 256-KB 256-KB L2 , 31-mm BGA packages. Implementation of MIPS64 ISA The SB-1 CPU core is a high-performance implementation of the standard MIPS64 Instruction Set Architecture (ISA), and incorporates the MIPS-3D and ... | Original |
2 pages, |
MIPS64 DSLAM ALU BCM5421 BCM1250 BCM112X BCM1125H BCM1125 BCM112X abstract |
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| Abstract: RMI XLR700 XLR700 Processor Series Next Generation Multiprocessing PRODUCT BRIEF Throughput Optimized MIPS64® Multiprocessors Scalable Processor Solutions Product Overview Block Diagram RMI's 700 , XLR732 XLR732 and XLR716 XLR716 processors integrate up to 32 fine-grain threads from eight MIPS64® CPUs, three full , MIPS64® ISA with enhanced instructions · Up to 8 cores - 4-way multi-threaded · Up to 32 fine-grain , internationally. MIPS and MIPS64 are registered trademarks of MIPS Technologies. Other company, product or service ... | Original |
2 pages, |
SHA-256 MIPS64 memory bus architecture XLR700 MIPS64 XLR716 RMI processor XLR732 XLR700 abstract |
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| Abstract: flexibility based on MIPS64TM instruction set architecture (ISA) · Software compatible with BCM1250 BCM1250 and , FIFO 4x GMII 8b/16b FIFO 8 Gbps The BCM1255 BCM1255 device is an MIPS64 processor core-based , multiprocessor (CMP) system consisting of two Broadcom SB-1 high-performance MIPS64 CPUs, a shared 512-KB 512-KB L2 , of MIPS64 ISA The SB-1 CPU core is a high-performance implementation of the standard MIPS64 ISA ... | Original |
2 pages, |
MIPS64 BCM5841 BCM1455 BCM1280 BCM1255 BCM1250 64-BIT BCM1255 abstract |
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| Abstract: KiLIN-6005 1U network appliance with Cavium Octeon 31XX series CPU n n n MIPS64 Cavium Octeon processor with 2 cores and up to 500MHz Security, Regular expression and compression/decompression functions inside Up to Six Gigabit Ethernet ports with one bypass segments n Two DDR2 667/533 memory slots and option up to 256MB 256MB DFA RAM on-board Up to one 32bit 3.3V PCI expansion slots n 65W PSU n SPECIFICATION CPU Board - Cavium Octeon CN3120 CN3120 series with various function ... | Original |
1 pages, |
octeon CAVIUM ddr2 ram ethernet switch 100M 4 port 31XX KILIN-6005 MIPS64 LCD 2X16 Gigabit CN3120 datasheet abstract |
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| Abstract: REFERENCE TABLE < MIPS 64 Architecture > MODEL KiLIN-6030 KiLIN-6020 Sub-Model -4101 Processor Cavium Octeon CN5860 CN5860 Cavium Octeon CN3860 CN3860 CPU (Max.) 750MHz, 16 cores RAM (Max.) 8GB -2700 -2701 -0351 KiLIN-6005 -1270 -3270 CAM-0100 CAM-0100 -7611 -7616 Cavium Octeon CN3120 CN3120 series CN5010 CN5010 CN5020 CN5020 500MHz, 8 cores 500MHz, 2 cores 500MHz, 1 core 500MHz, 2 cores 8GB 4GB 1G Ethernet Fiber 0 0 4 0 0 0 ... | Original |
1 pages, |
VGA fiber transistor w 431 PDF Datasheets sAta to ide sata connector datasheet sata 2.5 hdd ezio KILIN-6005 atx front panel power connector CN31 3270 transistor octeon sata 2,5 hdd CN3120 datasheet abstract |
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| Abstract: KiLIN-6030 2U rack-mount network server with Cavium Octeon processor and redundant PSU n 4101 n n n 2701 n MIPS64 Cavium Octeon processor with 16 cores and up to 750MHz Security, Regular expression and Decom/ compression functions inside Up to Sixteen Gigabit Ethernet ports with five bypass segments in KiLIN-6030 SPI4.2 interface for possible 10G solution or additional extensions Four DDR2/400 DDR2/400 memory slots and 256MB 256MB RLDRM on-board n Up to two PCI-X expansion slots n ... | Original |
1 pages, |
VGA fiber transistor w 431 PDF Datasheets MIPS64 CN58607 circuit psu 350w atx octeon CAVIUM datasheet abstract |
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| Abstract: KiLIN-6020 1U rack-mount network server with Cavium Octeon processor and up to eight Gigabit Ethernet ports FEATURE n n n n n MIPS64 Cavium Octeon processor with 8 cores and up to 500MHz Security, Regular expression and Decom/ compression functions inside SPI4.2 interface for possible 10G solution or fiber bypass function Four DDR2/400 DDR2/400 memory slots and 64MB RLDRM on-board One PCI-X expansion slot supports SPECIFICATION CPU Board - Cavium Octeon CN3840 CN3840 and CN3600 CN3600 series ... | Original |
1 pages, |
VGA fiber transistor w 431 PDF Datasheets octeon MIPS64 CN3860-500 CN3860 h a 431 transistor CAVIUM datasheet abstract |
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| Abstract: and software drivers High functional integration Programming ease and flexibility based on MIPS64 , SB-1 high-performance MIPS64 CPU, a shared 128-KB 128-KB L2 cache, a DDR memory controller, and an , 31-mm BGA package that is pin-compatible with the BCM1125H BCM1125H. Implementation of MIPS64 ISA The SB-1 CPU core is a high-performance implementation of the standard MIPS64 Instruction Set Architecture (ISA ... | Original |
2 pages, |
MIPS64 DDR PHY ASIC BCM5461 bcm546 BCM1250 BCM1125H BCM1122 MIPS64TM BCM1122 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */ .section .init,"ax",@progbits .globl _init .type _init,@function _init: #ifdef _mips64 daddu $sp,$sp,-48 sd $31,40($sp) #else addu $sp,$sp,-32 sw $31,20($sp) #endif .section .fini,"ax",@progbits .globl _fini .type _fini,@function _fini: #ifdef _mips64 daddu $sp,$sp,-48 sd $31,40($sp) #else addu $sp,$sp,-32 sw $31,20($sp) #endif www.datasheetarchive.com/download/79262054-393174ZC/mplabc30v2_05.tgz |
Microchip | 09/11/2006 | 27045.95 Kb | TGZ | mplabc30v2_05.tgz |
| /* 4 slots for argument spill area. 1 for cpreturn, 1 for stack. Return spill offset of 40 and 20. Aligned to 16 bytes for n32. */ #ifdef _mips16 #define RA $7 #else #define RA $31 #endif .section .init,"ax",@progbits #ifdef _mips64 ld RA,40($sp) daddu $sp,$sp,48 #else lw RA,20($sp) addu $sp,$sp,32 #endif j RA .section .fini,"ax",@progbits #ifdef _mips64 ld RA,40($sp) daddu $sp,$sp,48 #else lw RA,20($sp) addu $sp,$sp,32 #endif j RA www.datasheetarchive.com/download/79262054-393174ZC/mplabc30v2_05.tgz |
Microchip | 09/11/2006 | 27045.95 Kb | TGZ | mplabc30v2_05.tgz |
| MIPS64 Architecture MIPS64 Architecture CAR-4000 CAR-4000 CAR-4000 CAR-4000 www.datasheetarchive.com/files/portwell/cas/cas.html |
Portwell | 22/02/2010 | 21.92 Kb | HTML | cas.html |
| _mips64 #define _va_rounded_size(_TYPE) \ (sizeof (_TYPE) + 8 - 1) / 8) * 8) #else #define _va_rounded_size(_TYPE) \ (sizeof (_TYPE) + sizeof (int) - 1) / sizeof (int) * sizeof (int) #endif #ifdef _mips64 #define _va _soft_float) && ! defined (_mips_single_float) #ifdef _mips64 #define va_start(_AP, _LASTARG) \ (_AP ._fp_regs = _AP._gp_regs - _AP._fp_left * _va_reg_size) #else /* ! defined (_mips64) */ #define va , \ _AP._fp_regs = (char *) (int) _AP._fp_regs & -8) #endif /* ! defined (_mips64) */ #else tar:gwww.datasheetarchive.com/files/motorola/devtools/mcore/gnusolar.gz!/gnusolar!/mtcgnu4.0/lib/gcc-lib/mcore-elf/egcs-2.91.60/include/va-mips.h |
Motorola | 16/02/2000 | 29468.49 Kb | GZ | gnusolar.gz |
| _mips64 #define _va_rounded_size(_TYPE) \ (sizeof (_TYPE) + 8 - 1) / 8) * 8) #else #define _va_rounded_size(_TYPE) \ (sizeof (_TYPE) + sizeof (int) - 1) / sizeof (int) * sizeof (int) #endif #ifdef _mips64 #define _va _soft_float) && ! defined (_mips_single_float) #ifdef _mips64 #define va_start(_AP, _LASTARG) \ (_AP ._fp_regs = _AP._gp_regs - _AP._fp_left * _va_reg_size) #else /* ! defined (_mips64) */ #define va , \ _AP._fp_regs = (char *) (int) _AP._fp_regs & -8) #endif /* ! defined (_mips64) */ #else www.datasheetarchive.com/download/46713865-484035ZC/gnu_tsc.bz2 |
Motorola | 16/02/2000 | 22032.79 Kb | BZ2 | gnu_tsc.bz2 |
| _AC_OPTION_WARNINGS # Ensure a reasonable default simulator is constructed: (DEPRECATED) case "${target}" in mips64 _SUBST(SIM_SUBTARGET) # # Select the byte order of the target # mips_endian= default_endian= case "${target}" in mips64 _AC_OPTION_ENDIAN($mips_endian,$default_endian) # # Select the bitsize of the target # case "${target}" in mips64*-*-*) mips_bitsize=64 ; mips mips64*-*-*) mips_fpu=HARD_FLOATING_POINT ; mips16*-*-*) mips " case "${target}" in mips64vr5*-*-*) sim_default_gen=IGEN sim_use_gen=IGEN sim www.datasheetarchive.com/download/46713865-484035ZC/gnu_tsc.bz2 |
Motorola | 16/02/2000 | 22032.79 Kb | BZ2 | gnu_tsc.bz2 |
| _target=m88k ; mips64*-big-*) gdb_target=bigmips64 ; mips*-big-*) gdb_target=bigmips ; mips*-dec-mach3*) gdb_target=mach3 ; mips*-dec-*) gdb_target=decstation ; mips64*el-*-ecoff*) gdb_target=embedl64 ; mips64*-*-ecoff*) gdb_target=embed64 ; mips64*vr4300*el-*-elf*) gdb_target=vr4300el ; mips64*vr4300*-*-elf*) gdb_target=vr4300 ; mips64*vr4100*el-*-elf*) gdb_target=vr4300el ; mips64*vr4100*-*-elf*) gdb_target=vr4300 ; mips64*vr5000*el-*-elf*) gdb_target=vr5000el ; mips64*vr5000*-*-elf*) gdb_target=vr5000 www.datasheetarchive.com/download/46713865-484035ZC/gnu_tsc.bz2 |
Motorola | 16/02/2000 | 22032.79 Kb | BZ2 | gnu_tsc.bz2 |
| / MIPS64 instruction sets definitions * MIPS ISAs are no longer subsets of each other. Therefore 4 #define _MIPS_ISA_MIPS5 5 #define _MIPS_ISA_MIPS32 MIPS32 MIPS32 MIPS32 6 #define _MIPS_ISA_MIPS64 7 /* * Subprogram www.datasheetarchive.com/download/49104857-995987ZC/xapp542.zip (sgidefs.h) |
Xilinx | 11/11/2004 | 9180.01 Kb | ZIP | xapp542.zip |
| MIPS64 Architecture MIPS64 Architecture www.datasheetarchive.com/files/portwell/cas/cas_solution_guide.html |
Portwell | 22/02/2010 | 27.13 Kb | HTML | cas_solution_guide.html |
| // Build don't link: // prms-id: 12475 // excess errors test - XFAIL alpha*-*-* mips64*-*-* enum huh { start =-2147483648, next }; // WARNING - , XFAIL sparc64-*-* alpha*-*-* www.datasheetarchive.com/download/46713865-484035ZC/gnu_tsc.bz2 |
Motorola | 16/02/2000 | 22032.79 Kb | BZ2 | gnu_tsc.bz2 |