500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
QLX4270RIQSR Intersil Corporation DisplayPort Lane Extender; QFN46; Temp Range: 0° to 70° visit Intersil Buy
QLX4600LIQSR Intersil Corporation Quad Lane Extender; QFN46; Temp Range: 0° to 70° visit Intersil Buy
ISL36111DRZ-T7 Intersil Corporation 11.1Gb/s Lane Extender; QFN16; Temp Range: 0° to 70° visit Intersil Buy
ISL36411DRZ-TS Intersil Corporation Quad Lane Extender; QFN46; Temp Range: 0° to 70° visit Intersil Buy
QLX4300SIQT7 Intersil Corporation Quad Lane Extender; QFN46; Temp Range: 0° to 70° visit Intersil Buy
QLX4600SIQSR Intersil Corporation Quad Lane Extender; QFN46; Temp Range: 0° to 70° visit Intersil Buy

MIPI 4 lanes

Catalog Datasheet MFG & Type PDF Document Tags

MIPI 4 lanes

Abstract: 4 016 F2.0 6 pcs. 64 RAW 3.0/2.5/ (Mipi, 4 lanes) 1.8/1.1 12.0 x 12.0 x 6.52 1 , 656 x 3 496 F1.94 5 pcs. 64 RAW 2.8/2.7/ (Mipi, 4 lanes) 1.8/1.2 9.5 x 9.5 x 6.15 , 3.0/2.7/ 1.8/1.0 9.5 x 9.5 x 5.18 F1.94 5 pcs. 66 RAW 3.0/2.7/ (Mipi, 4 lanes) 1.8 , pcs. 67 RAW 2.8/1.8/ (Mipi, 2 lanes) 1.2 8.5 x 8.5 x 4.05 F2.2 4 pcs. 77 RAW 2.8/1.8/ (Mipi, 2 lanes) 1.2 6.5 x 6.5 x 3.5 4 pcs. 80 2.8/1.8/ 1.2 4.5 x 5.0 x
Sharp
Original

RJ2361

Abstract: 4 016 F2.0 6 pcs. 64 RAW 3.0/2.5/ (Mipi, 4 lanes) 1.8/1.1 12.0 x 12.0 x 6.52 1 , 656 x 3 496 F1.94 5 pcs. 64 RAW 2.8/2.7/ (Mipi, 4 lanes) 1.8/1.2 9.5 x 9.5 x 6.15 , 3.0/2.7/ 1.8/1.0 9.5 x 9.5 x 5.18 F1.94 5 pcs. 66 RAW 3.0/2.7/ (Mipi, 4 lanes) 1.8 , pcs. 67 RAW 2.8/1.8/ (Mipi, 2 lanes) 1.2 8.5 x 8.5 x 4.05 F2.2 4 pcs. 77 RAW 2.8/1.8/ (Mipi, 2 lanes) 1.2 6.5 x 6.5 x 3.5 4 pcs. 80 2.8/1.8/ 1.2 4.5 x 5.0 x
Sharp
Original

rj2361

Abstract: LR0G956 x H) (V) TYP. TYP. (mm) 64 3.0/2.7/ 1.8/1.0 59 2.7/1.8/ 1.05 RAW (Mipi, 4 lanes , x 5.53 8.5 x 8.5 x 5.53 2.8/1.8 8.52 x 8.52 FPC type RAW (I/O: 1.8 x 5.8 (Mipi, 2 lanes) or 2.8) 63 RAW (Mipi, 2 lanes) F2.4 9.5 x 9.5 x 5.18 2.7/1.8/ 1.2 7.0 x 7.0 x 4.7 , 2.99 RAW (Mipi, 2 lanes) F2.4 3 pcs. 61 F2.8 2 pcs. 47 UYVY (Mipi, 1 lane , RJ64VC100 8M 1/3.2 type 0.42 cc 1/4 type 0.23 cc 1/4 type 0.29 cc Built-in auto focus function
-
Original
rj2361 LR0G956 TV SHARP driver LR35503 sharp CCD Image Sensor LR35501 RJ63AC400 RJ63AC500 RJ63ACL00 RJ63AC100 RJ63AC200 RJ63VC200

Laser Diode 405 nm Sharp

Abstract: LR388K4 4 016 F2.0 6 pcs. 64 RAW 3.0/2.5/ (Mipi, 4 lanes) 1.8/1.1 12.0 x 12.0 x 6.52 1 , 656 x 3 496 F1.94 5 pcs. 64 RAW 2.8/2.7/ (Mipi, 4 lanes) 1.8/1.2 9.5 x 9.5 x 6.15 , 3.0/2.7/ 1.8/1.0 9.5 x 9.5 x 5.18 F1.94 5 pcs. 66 RAW 3.0/2.7/ (Mipi, 4 lanes) 1.8 , pcs. 67 RAW 2.8/1.8/ (Mipi, 2 lanes) 1.2 8.5 x 8.5 x 4.05 F2.2 4 pcs. 77 RAW 2.8/1.8/ (Mipi, 2 lanes) 1.2 6.5 x 6.5 x 3.5 4 pcs. 80 2.8/1.8/ 1.2 4.5 x 5.0 x
Sharp
Original
Laser Diode 405 nm Sharp LR388K4 Laser Diodes 405 nm catalog LR36B15 PQ1LAxx5MSPQ Series JQA-QM8688 JQA-QM3776 HT9A23E

RGB MIPI 4 lanes

Abstract: image sensor MIPI output Parallel 8 bits, 10 bits/ MIPI 2 lanes Communication and control signals I2C fast mode , ISX005 ISX006 Diagonal 3.6 mm (Type 1/5) 3M-Pixel and Diagonal 4.5 mm (Type 1/4) 5M-Pixel CMOS , and MIPI interfaces Scalado's SpeedTagsTM technology AWB, AE, and AF Camera System Functions , . Parallel and MIPI Interfaces These devices include a parallel interface that supports a wide variety of , include a CSI-2 (Camera Serial Interface) as stipulated by the Mobile Industry Processor Interface (MIPI
Scalado
Original
RGB MIPI 4 lanes image sensor MIPI sony exmor 5M cmos camera CAMERA PARALLEL RGB TO MIPI CSI-2 Sony CMOS

MIPI DSI LCD panel driver

Abstract: RGB to MIPI DSI LCD the industry's lowest power consumption. Standard Compliance MIPI DSI V1.02, MIPI D-PHY 1.0 MIPI Features - Up to 8bpp input - Up to 4 lanes configuration - Up to 1.2Gbps/lane - Burst/non-burst operation , controller 2 lanes DisplayPortTM Timing controller 4 lanes DisplayPortTM Timing controller Copyright ©2012 , Product Brief ANX1413 Low Power MIPI Timing controller The ANX1812 is an ultra low power , ., creators of USB Technology. MIPI and the MIPI logo are the trademarks or the registered trademarks of
Analogix Semiconductor
Original
MIPI DSI LCD panel driver RGB to MIPI DSI LCD HDMI TO MIPI MIPI DSI TFT HDMI input MIPI DSI output displayport TO MIPI 100KH 112-TBGA
Abstract: C = Commercial Pb-free Package Type: BZ = 121-ball BGA X = 4 for up to 2 MIPI CSI-2 lanes X = 5 for up to 4 MIPI CSI-2 lanes Density: Base part number for USB 3.0 Marketing Code: USB = USB , -2 Receiver with the following features: 1. It can receive clock and data in 1, 2, 3, or 4 lanes ,  VDD_MIPI: MIPI CSI-2 clock and data lanes Document Number: 001-87516 Rev. *H Page 7 of 29 , Information Table 15. Ordering Information Ordering Code MIPI CSI-2 Lanes Package Type Temperature Cypress Semiconductor
Original
CYUSB306X CYUSB3065 CYUSB3064

displayport 1.3 STANDARD

Abstract: DPCD Receiver ï'² MIPI DSI: v1.01 / MIPI D-PHY: v0.90 Compliant. ï'² Up to four (4) Data Lanes with , . ● The inputs are driven by a DSI Host with 4-Data Lanes, upto1 Gbps/lane or DPI Host with 16/18 , — The inputs are driven by a DSI Host with 4-Data Lanes, upto1 Gbps/lane or DPI Host with 16/18/24 bit , D-PHY: v0.90 Compliant. ï'² Up to four (4) Data Lanes with Bi-direction support on Data Lane 0. ï , a Host (application or baseband processor) over MIPI DSI or DPI link to drive DisplayPort display
Toshiba
Original
TC358767AXBG displayport 1.3 STANDARD DPCD edp transmitter P-VFBGA81-0505-0

Product Brief

Abstract: rgb888 to rgb666 . Features DSI Receiver · MIPI DSI: v1.01 / MIPI D-PHY: v1.0 compliant. · Up to four (4) data lanes with , Application Processors with a Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) or Display Pixel Interface (DPI). · Solutions based on the latest versions of the industry standard MIPI DSI 1.01 to ensure high speed data rates of up to 1 Gbps per lane and MIPI DPI 2.0 to ensure speed of 154 , Mobile Industry Processor Interface (MIPI) Display Serial Interface (DSI) or Display Pixel Interface (DPI
Toshiba
Original
Product Brief rgb888 to rgb666 MIPI DSI to RGB TC358766
Abstract: -channel TDM output mode available Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) transmitter 4-lane transmitter with 4 lanes, 2 lanes, and 1 lane muxing options for HDMI/MHL/digital input , INTRQ1 TO INTRQ3 AUDIO OUTPUT FORMATTER I2S_MCLK I2S_LRCLK I2S_SCLK I2S_SDATA 4-LANE MIPI , the CP) or the 8-bit digital input port. The main features of the 4-lane MIPI transmitter , . 17 Detailed Functional Block Diagram . 4 HDMI Analog Devices
Original
ADV7480 ADV7480WBBCZ ADV7480WBBCZ-RL 100-B BC-100-4 ADV7480W

TC358764

Abstract: TC358765 . 25 2014-05-29 4 / 26 Rev.1.281 TC358764XBG/TC358765XBG ● MIPI is registered , . 4. 5. 6. 7. 8. 9. MIPI D-PHY, â'DRAFT MIPI Alliance Specification for D-PHY Version 0.91.00 , up to 4 data lanes, and outputs to Single-Link LVDS. TC358765XBG: In BGA64 package, it supports DSI-RX with up to 4 data lanes, and outputs to Dual-Link LVDS. 1.1. Scope This document details the , Transmitter Supply Current Parameter Symbol Transmitter supply current (Clk + 4 data lanes) ITCCW (75MHz
Toshiba
Original
TC358764 TC358765 TC358764XBG RGB565 RGB666 RGB888

MIPI bridge toshiba

Abstract: TC358748XBG data lane ï'² Supports up to 4 data lanes ï'² Supports video data formats - RX: RAW8/10/12/14 , trademarks of MIPI Alliance, Inc. 3 / 21 2014-05-29 TC358746AXBG/TC358748XBG 1 2 3 4 5 6 7 , 4 / 21 2014-05-29 TC358746AXBG/TC358748XBG REFERENCES 1. MIPI D-PHY , translate serial transfers to parallel transfers. I2C TC358746AXBG MIPI Link Quad Data Lanes , MIPI Link Parallel Port Quad Data Lanes MIPI Application Processor Or Baseband Converter
Toshiba
Original
TC358748XBG MIPI bridge toshiba MIPI CSI-2 to Parallel MIPI CSI-2 Parallel bridge RGB mipi bridge MIPI CSI2 4 lane parallel P-VFBGA72-0505-0 YUV422 RGB888/666/565 YUV444 P-VFBGA80-0707-0

LVDS to mipi bridge

Abstract: RGB MIPI dsi features a dual-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at , LVDS lanes = 2x(3 data lanes + 1 CLK lane) (b) number of DSI lanes = 2x(4 data lanes + 1 CLK lane (c , lanes are bit and byte aligned. Figure 14 illustrates the lane merging function for each channel; 4 , SN65DSI85 www.ti.com SLLSEB9C ­ SEPTEMBER 2012 ­ REVISED DECEMBER 2012 MIPI® DSI BRIDGE TO , SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI® Ultra-Low Power State (ULPS
Texas Instruments
Original
LVDS to mipi bridge RGB MIPI dsi MARKING 3D SOT-32 RGB TO MIPI DSI MHz MIPI ISO/TS16949

TC358779

Abstract: MIPI DSI to RGB 1080P 4 data lanes @1Gbps/lane ï'² Supports video data formats - RGB888 or RGB666 ● I2C Slave , : I2S, TDM or IEC60958 (pins are multiplexed) ï'² I2S Audio Interface - Up to 4 data lanes for 8 , — MIPI and SLIMbus are registered trademarks of MIPI Alliance, Inc. © 2014 Toshiba Corporation 4 , 2014-04-10 TC358779XBG REFERENCES 1. 2. 3. 4. 5. 6. 7. MIPI D-PHY , '² Supports up to 4 data lanes @1Gbps/lane ï'² Supports video data formats - RGB888 or RGB666 ● I2C Slave
Toshiba
Original
TC358779 MIPI DSI to RGB 1080P TC358749XBG 1080P CEA-861-D

MIPI HDMI bridge

Abstract: MIPI csi2 . The TC358743XBG supports a MIPI CSI-2 interface to the Host with configurable 1, 2, 3, or 4 data , 1.01 Revision 0.04 ­ 2 April 2009) ­ Supports up to 4 data lanes · Supports up to 1 Gbps per data lane , Product Brief TC358743 Camera Serial Interface Converter Chipset (HDMI to MIPI®) Highlights R · HDMI video and audio streams into MIPI CSI-2 data to enable Application Processors with MIPI CSI , standards for HDMI 1.4 and MIPI CSI-2 1.01 interfaces. · Support for common 3D formats and compatible
Toshiba Matsushita Display Technology
Original
MIPI HDMI bridge MIPI csi2

1 to 2 MIPI buffer IC

Abstract: Tablet PC schematic features a dual-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at , LVDS lanes = 2x(3 data lanes + 1 CLK lane) (b) number of DSI lanes = 2x(4 data lanes + 1 CLK lane (c , lanes are bit and byte aligned. Figure 14 illustrates the lane merging function for each channel; 4 , SN65DSI85 www.ti.com SLLSEB9B ­ SEPTEMBER 2012 ­ REVISED DECEMBER 2012 MIPI® DSI BRIDGE TO , SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI® Ultra-Low Power State (ULPS
Texas Instruments
Original
1 to 2 MIPI buffer IC Tablet PC schematic LVDS to MIPI DSI DSI mipi MIPI D-PHY
Abstract: FlatLinkTM bridge features a dual-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per , data and clock lanes are in ultra-low power state (ULPS) EN = 0 mA k MIPI DSI INTERFACE LP , DSI lanes = 2x(4 data lanes + 1 CLK lane (c) LVDS CLK OUT = 81.6M (d) DSI CLK = 490M (e) RGB888 , SN65DSI85 www.ti.com SLLSEB9D ­ SEPTEMBER 2012 ­ REVISED SEPTEMBER 2013 MIPI® DSI BRIDGE TO , SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI® Ultra-Low Power State (ULPS Texas Instruments
Original

TC358778XBG

Abstract: BGA80 1 Gbps per data lane ï'² Supports1,2,3 or 4 data lanes ï'² Supports video data formats - RGB888 , '² Supports1,2,3 or 4 data lanes ï'² Supports video data formats RGB888/666/565 ● RGB Interface ï , Core (3) NA 4 mA VDD for the MIPI (2) NA 4 mA 4 mA VDDIO is for IO power supply (4 , SYSTEM 4 MIPI-DSI 10 I2C IF 2 GPIO 2 Parallel Port IF 28 POWER 9 IO, MIPI and Core Power , . 14 4. Package
Toshiba
Original
TC358778XBG BGA80 DSI to rgb bridge MIPI+DSI+4+lane TC358768AXBG/TC358778XBG TC358768AXBG

MIPI 1080p LCD

Abstract: single chip converter for HDMI to cvbs -channel TDM output mode available 2 Mobile Industry Processor Interface (MIPI) Camera Serial Interface 2 (CSI-2) transmitters 4-lane transmitter with 4 lanes, 2 lanes, and 1 lane muxing options for HDMI/SDP , I2S_SDATA 4-LANE MIPI CSI-2 TRANSMITTER CLKAP/CLKAN DA0P/DA0N TO DA3P/DA3N SD CORE 1-LANE MIPI CSI-2 TRANSMITTER DIAGNOSTIC CLKBP/CLKBN DB0P/DB0N 12047-001 RXCP/RXCN Figure 1 , detection Up to 4 V common-mode input range solution Vertical blanking interval (VBI) data slicer
Analog Devices
Original
MIPI 1080p LCD single chip converter for HDMI to cvbs ADV7482 ADV7482WBBCZ ADV7482WBBCZ-RL ADV7482W D12047-0-6/14

LVDS to mipi bridge

Abstract: LVDS to MIPI DSI ® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and , lanes are bit and byte aligned. Figure 14 illustrates the lane merging function for each channel; 4 , SN65DSI84 www.ti.com SLLSEC2C ­ SEPTEMBER 2012 ­ REVISED DECEMBER 2012 MIPI® DSI BRIDGE TO , Output Voltage Swing, Common Mode, and MIPI® Ultra-Low Power State (ULPS) Support LVDS Channel SWAP, LVDS
Texas Instruments
Original
MIPI DSI to lvds LVDS to MIPI DSI Bridge Arasan LVDS to MIPI MIPI to LVDS bridge lvds wuxga
Showing first 20 results.