NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: interface interoperates with RS-422 RS-422, RS-232 RS-232 or supports 31 transmitters as in MIL-STD-1553B · RF ... | Original |
1 pages, |
t827 rs-422 to 1553B NTDS MIL-STD-1553B URT-23 11/TADIL-A AN/URT-23F 11/TADIL-A abstract |
|
|||
| Abstract: 0x0043 meets all requirements for MIL-STD-1553B Notice 2 Four data buffer modes for subaddress transmit and , stored with message data words for all transacted messages In compliance with MIL-STD-1553B Notice 2 , ) interface between a host and a MIL-STD-1553B dual redundant data bus. It automatically handles all aspects ... | Original |
157 pages, |
MIL-STD-1553B DS6120 HI-6121 HI-6120 hi6121 Holt 1553 Controller - HI6110 Holt 1553 Controller HI6110 HOLT INC HI-6110 MIL-STD-1553 HI-6120 abstract |
|
|||
| Abstract: CT1999 CT1999 Remote Terminal and/or Bus Controller for MIL-STD-1553B Features · Performs the Complete Dual-Redundant Remote Terminal and Bus Controller Protocol Functions of MIL-STD-1553B · Automatic Switchover to Superseding Input Commands · MIL-PRF-38534 MIL-PRF-38534 Compliant Circuits Available · 750 mw , design incorporates ASIC and five Octal Buffers that accomplish the dual redundant MIL-STD1553B Remote , of the most confusing aspects of MIL-STD-1553B. This is because much of their use is optional, and ... | Original |
25 pages, |
MIL-STD-1553B CT1999 1553B CT1602 MIL-PRF-38534 CT1999 abstract |
|
|||
| Abstract: microprocessor/subsystem. The serial bus for the BCRT or BCRTM is MIL-STD-1553B. The BCRTMP allows interface to , , MIL-STD-1553B does not support the command and the RT automatically illegalizes this command. 5.0 REMOTE , MIL-STD-1553B, the remote terminal can detect various Message Error conditions. Error checking occurs on , implement MIL-STD-1553B fail safe timer (760�s pulse). CJA/B Output BCRTF Output SSYSF , MIL-STD-1553B bus and processes it either by the primary or secondary decoder. Each decoder checks for the ... | Original |
18 pages, |
UT1750AR UT1553B MIL-STD-1553B 25D8 MIL-STD-1553B abstract |
|
|||
| Abstract: Features The S MMIT Remote Terminal (SRT) conforms to the requirements of MIL-STD-1553B, Notice II. In , sequence. 1.1.5 Broadcast Designed to meet the requirements of MIL-STD-1553B Notice II, the SRT can store , Terminal (SMT) is a full-featured MILSTD-1553B bus monitor designed to monitor all or selected remote , interface are MIL-STD-1553A MIL-STD-1553A and MIL-STD-1553B. To meet IT may be configured through an these protocols , ), Remote Terminal (RT), and Monitor Terminal (MT) r MIL-STD-1553B, Notice II RT - Internal command ... | Original |
5 pages, |
UT69151 MIL-STD-1553B 1553B MIL-STD-1553 MIL-STD1553 MIL-STD-1553 abstract |
|
|||
| Abstract: MIL-STD-1553B, Notice II RT - Internal command illegalization - 16-bit read/write time-tag with user-defined , Features The S然MIT Remote Terminal (RTE) conforms to the requirements of MIL-STD-1553B, Notice II. In , Specifically, two of the protocols that the S然MIT RTE may interface are MIL-STD-1553A MIL-STD-1553A and MIL-STD-1553B. To , internal memory is memory mapped. 1.1.5 Broadcast Designed to meet the requirements of MIL-STD-1553B ... | Original |
2 pages, |
UT69151 MIL-STD-1553B block diagram of remote control 1553B MIL-STD-1553 MIL-STD-1553 abstract |
|
|||
| Abstract: solution to the requirements of the dual-redundant MIL-STD-1553B interface as specified by MIL-STD-1760A MIL-STD-1760A. , microprocessor system. The RTS's MIL-STD-1553B interface includes encoding/ decoding logic, error detection , associated data words as defined in MIL-STD-1553B. The remaining 960 words of memory contain receive , select a register. The Control Register toggles bits in the MIL-STD-1553B status word, Subaddress , internal illegal command decoding for reserved MIL-STD-1553B mode codes. These definitions are extracted ... | Original |
46 pages, |
UTI760A RTS-14 MIL-STD-1553B F801 mil-std-1760a MIL-STD-1760A UTI760A abstract |
|
|||
| Abstract: resistors. Figure 27. Transceiver Test Circuit MIL-STD-1553B SuMMIT RTE 83 VDIS (Overshoot ... | Original |
2 pages, |
zero crossing MIL-STD-1553B datasheet abstract |
|
|||
| Abstract: s (MIL-STD1553A MIL-STD1553A) or in 15 s (MIL-STD-1553B). Assertion of this bit forces the SMT to declare a , performed after a monitor block is entered. Monitor Time-Out: MIL-STD-1553A MIL-STD-1553A = 9 s MIL-STD-1553B = 15 s , , two of the protocols that the S MMIT may be interfaced to are MIL-STD-1553A MIL-STD-1553A and MIL-STD-1553B. To ... | Original |
13 pages, |
MIL-STD-1553B 1553B 000D datasheet abstract |
|
|||
| Abstract: MIL-STD-1553B dual-redundant Ë Ë Ë Ë 64K addressability Ë Internal wraparound self-test Ë Time , provides the system designer with an intelligent solution to MIL-STD-1553B multiplexed serial data bus , MIL-STD-1553B functions - Bus Controller and Remote Terminal. Designed to reduce host CPU overhead, the BCRT's , requirements of MIL-STD-1553B. MCLK 65 C5 TI - Memory Clock. This is the input clock , for MIL-STD-1553B applications aid processor off-loading. The host needs only to establish the ... | Original |
58 pages, |
UT1553B MIL-STD-1553B 1553B 12MHZ UT1553B abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| NonFlashWeb PI960MX-JXV PI960MX-JXV PI960MX-JXV PI960MX-JXV JIAWG Execution Vehicle Engenuity Systems Architecture: Type : Last Update: i960(R) Processor Military Processors Vendor Information Tool Description: Features Intel's superscalar microprocessor chosen by JIAWG as a 32-bit processor standard. The i960 MM/MX processor can decode and execute multiple instructions per clock cycle, resulting in a performance greater than 20 mi www.datasheetarchive.com/files/intel/design/i960/devtools/4f366_~1.htm |
Intel | 31/01/1997 | 3.52 Kb | HTM | 4f366_~1.htm |
| NonFlashWeb VME960MX-SBC VME960MX-SBC VME960MX-SBC VME960MX-SBC and VME960MC-SBC VME960MC-SBC VME960MC-SBC VME960MC-SBC Single-Board Computers Engenuity Systems Architecture: Type : Last Update: i960(R) Processor Military Processors Vendor Information Tool Description: Features Intel's 20 MHz i960 MX/MM superscalar microprocessor, the newest member of Intel's military family of i960 embedded microprocessors. Using advanced RISC technology and five parallel execution units, www.datasheetarchive.com/files/intel/design/i960/devtools/4f36a_~1.htm |
Intel | 31/01/1997 | 3.73 Kb | HTM | 4f36a_~1.htm |
| NonFlashWeb VME960MX-SBC VME960MX-SBC VME960MX-SBC VME960MX-SBC and VME960MC-SBC VME960MC-SBC VME960MC-SBC VME960MC-SBC Single-Board Computers Engenuity Systems Architecture: Type : Last Update: i960(R) Processor Military Processors Vendor Information Tool Description: Features Intel's 20 MHz i960 MX/MM superscalar microprocessor, the newest member of Intel's military family of i960 embedded microprocessors. Using advanced RISC technology and five parallel executio www.datasheetarchive.com/files/intel/products/design/i960/devtools/3f0fa_~1.htm |
Intel | 23/10/1996 | 4.08 Kb | HTM | 3f0fa_~1.htm |
| NonFlashWeb PI960MX-JXV PI960MX-JXV PI960MX-JXV PI960MX-JXV JIAWG Execution Vehicle Engenuity Systems Architecture: Type : Last Update: i960(R) Processor Military Processors Vendor Information Tool Description: Features Intel's superscalar microprocessor chosen by JIAWG as a 32-bit processor standard. The i960 MM/MX processor can decode and execute multiple instructions per clock cycle, resulting in a performance greater th www.datasheetarchive.com/files/intel/products/design/i960/devtools/3f0f6_~1.htm |
Intel | 23/10/1996 | 3.87 Kb | HTM | 3f0f6_~1.htm |