MIC502 MIC502BN MIC502BM R25/R50 R0/R50 RL2010-54 1K-138-D1 2N2222A PN2222A - Datasheet Archive

 

Micrel MIC502 Fan Management IC Final Information General Description Features The MIC502 is a thermal and fan management IC

 

MIC502 MIC502 Micrel MIC502 MIC502 Fan Management IC Final Information General Description Features The MIC502 MIC502 is a thermal and fan management IC which supports the features for NLX/ATX power supplies and other control applications. Fan speed is determined by an external temperature sensor, typically a thermistor-resistor divider, and (optionally) a second signal, such as the NLX "FanC" signal. The MIC502 MIC502 produces a low-frequency pulse-width modulated output for driving an external motor drive transistor. Low-frequency PWM speed control allows operation of standard brushless dc fans at low duty cycle for reduced acoustic noise and permits the use of a very small power transistor. The PWM time base is determined by an external capacitor. An open-collector overtemperature fault output is asserted if the primary control input is driven above the normal control range. The MIC502 MIC502 features a low-power sleep mode with a userdetermined threshold. Sleep mode completely turns off the fan and occurs when the system is asleep or off (both control inputs very low). A complete shutdown or reset can also be initiated by external circuitry as desired. The MIC502 MIC502 is available as 8-pin plastic DIP and SOIC packages in the ­40°C to +85°C industrial temperature range. · · · · · · · · · Temperature-proportional fan speed control Low-cost, efficient PWM fan drive 4.5V to 13.2V IC supply range Controls any voltage fan Overtemperature detection with fault output Integrated fan startup timer Automatic user-specified sleep mode Supports low-cost NTC/PTC thermistors 8-pin DIP and SOIC packages Applications · · · · · · · · NLX and ATX power supplies Personal computers File servers Telecom and networking hardware Printers, copiers, and office equipment Instrumentation Uninterruptable power supplies Power amplifiers Ordering Information Part Number Temperature Range Package MIC502BN MIC502BN ­40°C to +85°C 8-pin Plastic DIP MIC502BM MIC502BM ­40°C to +85°C 8-pin SOIC Typical Application 12V T1 R1 R3 2 R2 3 4 R4 Fan MIC502 MIC502 1 VT1 VDD CF OUT VSLP OTF GND VT2 CF 8 7 RBASE Q1 6 5 Overtemperature Fault Output Secondary Fan-control Input Micrel, Inc. · 1849 Fortune Drive · San Jose, CA 95131 · USA · tel + 1 (408) 944-0800 · fax + 1 (408) 944-0970 · http://www.micrel.com March 2003 1 MIC502 MIC502 MIC502 MIC502 Micrel Pin Configuration VT1 1 8 VDD CF 2 7 OUT VSLP 3 6 OTF GND 4 5 VT2 8-Pin SOIC (M) 8-Pin DIP (N) Pin Description Pin Number Pin Name 1 VT1 Thermistor 1 (Input): Analog input of approximately 30% to 70% of VDD produces active duty cycle of 0% to 100% at driver output (OUT). Connect to external thermistor network (or other temperature sensor). Pull low for shutdown. 2 CF PWM Timing Capacitor (External Component): Positive terminal for the PWM triangle-wave generator timing capacitor. The recommended CF is 0.1µF for 30Hz PWM operation. 3 VSLP Sleep Threshold (Input): The voltage on this pin is compared to VT1 and VT2. When VT1 < VSLP and VT2 < VSLP the MIC502 MIC502 enters sleep mode until VT1 or VT2 rises above VWAKE. (VWAKE = VSLP + VHYST.) Grounding VSLP disables the sleep-mode function. 4 GND Ground 5 VT2 Thermistor 2 (Input): Analog input of approximately 30% to 70% of VDD produces active duty cycle of 0% to 100% at driver output (OUT). Connect to motherboard fan control signal or second temperature sensor. 6 /OTF Overtemperature Fault (Output): Open-collector output (active low). Indicates overtemperature fault condition (VT1 > VOT) when active. 7 OUT Driver Output: Asymmetical-drive active-high complimentary PWM output. Typically connect to base of external NPN motor control transistor. 8 VDD Power Supply (Input): IC supply input; may be independent of fan power supply. MIC502 MIC502 Pin Function 2 March 2003 MIC502 MIC502 Micrel Absolute Maximum Ratings (Note 1) Operating Ratings (Note 2) Supply Voltage (VDD) . +14V Output Sink Current (IOUT(sink) . 10mA Output Source Current (IOUT(source) . 25mA Input Voltage (any pin) . ­0.3V to VDD +0.3V Junction Temperature (TJ) . +125°C Storage Temperature (TA) . ­65°C to +150°C Lead Temperature (Soldering, 5 sec.) . 260°C ESD, Note 3 Supply Voltage (VDD) . +4.5V to +13.2V Sleep Voltage (VSLP). GND to VDD Temperature Range (TA) . ­40°C to +85°C Power Dissipation at 25°C SOIC . 800mW DIP . 740mW Derating Factors SOIC . 8.3mW/°C Plastic DIP . 7.7mW/°C Electrical Characteristics 4.5V VDD 13.2V, Note 4; TA = 25, bold values indicate ­40°C TA +85°C; unless noted Symbol Parameter Condition IDD Supply Current, Operating IDD(slp) Min Typ Max Units VSLP = GND, OTF, OUT = open, CF = 0.1µF, VT1 = VT2 = 0.7 VDD 1.5 mA Supply Current, Sleep VT1 = GND, VSLP, OTF, OUT = open CF = 0.1µF 500 µA tR Output Rise Time, Note 5 IOH = 10mA 50 µs tF Output Fall Time, Note 5 IOL = 1mA 50 µs IOL Output Sink Current VOL = 0.5V 0.9 mA IOH Output Source Current 4.5V VDD 5.5V, VOH = 2.4V 10 mA 10.8V VDD 13.2V, VOH = 3.2V 10 mA Driver Output IOS Sleep-Mode Output Leakage VOUT = 0V µA 1 Thermistor and Sleep Inputs VPWM(max) 100% PWM Duty Cycle Input Voltage 67 70 73 %VDD VPWM(span) VPWM(max) ­ VPWM(min) 37 40 43 %VDD VHYST Sleep Comparator Hysteresis 8 11 14 %VDD VIL VT1 Shutdown Threshold 0.7 V VIH VT1 Startup Threshold VOT VT1 Overtemperature Fault Threshold IVT, IVSLP VT1, VT2, VSLP Input Current tRESET Reset Setup Time minimum time VT1 < VIL, to guarantee reset, Note 5 30 Oscillator Frequency, Note 7 4.5V VDD 5.5V, CF = 0.1µF 24 27 30 Hz 10.8V VDD 13.2V, CF = 0.1µF 27 30 33 Hz Note 7 15 90 Hz 1.1 Note 6 74 V 77 %VDD 1 ­2.5 80 µA µs Oscillator f fMIN, fMAX Oscillator Frequency Range tSTARTUP Startup Interval March 2003 64/f 3 s MIC502 MIC502 MIC502 MIC502 Micrel Symbol Parameter Condition Min Typ Max Units 0.3 V Overtemperature Fault Output VOL Active (Low) Output Voltage IOL = 2mA IOH Off-State Leakage V/OTF = VDD µA 1 Note 1. Exceeding the absolute maximum rating may damage the device. Note 2. The device is not guaranteed to function outside its operating rating. Note 3. Devices are ESD sensitive. Handling precautions recommended. Note 4: Part is functional over this VDD range; however, it is characterized for operation at 4.5V VDD 5.5V and 10.8V VDD 13.2V ranges. These ranges correspond to nominal VDD of 5V and 12V, respectively. Note 5. Guaranteed by design. Note 6. VOT is guaranteed by design to always be higher than VPWM(max). Note 7. Logic time base and PWM frequency. For other values of CF, f(Hz) = 30Hz 0.1µF , where C is in µF. C Timing Diagrams VOT 100% 0.7VDD 80% VT1 VT2 Input Signal Range 70% 50% 40% 40% VSLP 30% 0% 0.3VDD VIH VIL 0V VOTF VOH VOL 0V F VOUT VOH A tPWM B C D tSTARTUP E G VOL 0V 50% 80% 40% 70% 0% 100% 40% Output Duty Cycle Figure 1. Typical System Behavior Note A. Output duty-cycle is initially determined by VT1, as it is greater than VT2. Note B. PWM duty-cycle follows VT1 as it increases. Note C. VT1 drops below VT2. VT2 now determines the output duty-cycle. Note D. The PWM duty-cycle follows VT2 as it increases. Note E. Both VT1 and VT2 decrease below VSLP but above VIL. The device enters sleep mode. Note F. The PWM `wakes up' because one of the control inputs (VT1 in this case) has risen above VWAKE. The startup timer is triggered, forcing OUT high for 64 clock periods. (VWAKE = VSLP + VHYST. See "Electrical Characteristics.") Note G. Following the startup interval, the PWM duty-cycle is the higher of VT1 and VT2. MIC502 MIC502 4 March 2003 MIC502 MIC502 Micrel VOT 100% 0.7VDD VT1 PWM Range 60% VT2 30% 40% VSLP 20% 0% 0.3VDD VIH VIL 0V VOTF VOUT L VOH M VOL 0V VOH H tSTARTUP I tPWM J K O N VOL 0V 100% 40% 60% 100% 30% 0% Output Duty Cycle VDD VDD 0V Figure 2. MIC502 MIC502 Typical Power-Up System Behavior Note H. At power-on, the startup timer forces OUT on for 64 PWM cycles of the internal timebase (tPWM). This insures that the fan will start from a dead stop. Note I. The PWM duty-cycle follows the higher of VT1 and VT2, in the case, VT1. Note J. The PWM duty-cycle follows VT1 as it increases. Note K. PWM duty-cycle is 100% (OUT constantly on) anytime VT1 > VPWM(max). Note L. /OTF is asserted anytime VT1 > VOT. (The fan continues to run at 100% duty-cycle.) Note M. /OTF is deasserted when VT1 falls below VOT; duty-cycle once again follows VT1. Note N. Duty-cycle follows VT1 until VT1 < VT2, at which time VT2 becomes the controlling input signal. Note that VT1 is below VSLP but above VIH; so normal operation continues. (Both VT1 and VT2 must be below VSLP to active sleep mode.) Note O. All functions cease when VT1 < VIL; this occurs regardless of the state of VT2. March 2003 5 MIC502 MIC502 MIC502 MIC502 Micrel Typical Characteristics Supply Current vs. Temperature 0.9 0.8 VDD = 12V 0.6 0.5 VDD = 5V 0.4 IDDSLEEP(mA) 0.6 0.5 0.4 0.3 0.3 0.2 0.2 0.1 0.1 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) 0 IDDSLEEP vs. Supply Voltage 0.3 0 0.15 2 4 6 8 10 VDD (V) 12 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) 14 VOL vs. Supply Voltage 0.14 0.12 25 0.10 0.08 2 4 0.02 I = 0.9mA OL 0 0 2 4 6 8 10 VDD (V) 6 8 10 12 14 VDD (V) VOL vs. IOL 1.2 1 12 0 0 14 VDD =5V 0.6 0.10 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) VOH (V) VOH(V) 2 1.5 1 MIC502 MIC502 4 VDD =12V 3.5 3 3 0.5 I = 100µA OH 0 0 2 4 6 8 10 VDD (V) 0 0 4 2.5 3 VDD =5V 2.5 2 0 3 2 4 6 8 10 VDD (V) VOH vs. Temperature VDD = 12V VDD = 5V 2.5 2 1 0.5 0.5 14 14 IOH = 10mA 1.5 1.5 1 12 12 VOH vs. Supply Voltage 2 4.5 3.5 3.5 14 1.5 VOH vs. IOH 4 12 2.5 0.5 VOH vs. Supply Voltage 6 8 10 VDD (V) 1 0.05 VOH(V) 4.5 4 3 VDD =12V 0.15 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 IOL (mA) 2 3.5 0.4 0.2 IOL = 100µA 4 VDD = 5V 0.20 VOL(V) VOL (V) 0.8 15 5 VOL vs. Temperature 0.25 VDD =12V 20 10 VOH(V) 0 0 30 0.06 0.04 0.05 VOL vs. Supply Voltage 35 VOL(mV) 0.2 0.1 VDD = 5V 0.1 0.18 0.16 VOL(V) 0.25 IDDSLEEP(mA) 0.2 0.05 0.20 0.15 VDD = 12V 0.25 0.7 IDD (mA) 0.7 IDD(mA) 0.3 0.9 0.8 IDDSLEEP vs. Temperature Supply Current vs. Supply Voltage 5 7 9 11 13 15 17 19 IOH (mA) 6 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) March 2003 MIC502 MIC502 Micrel PWM Frequency (normalized) vs. Temperature PWM Frequency(Normalized) vs. Supply Voltage 1.2 3000 1 0.8 0.6 0.4 VDD = 12V 1000 VDD = 5V 0.8 0.6 0.4 FREQUENCY (Hz) 1 FPWM(NORMALIZED) 100 10 0.2 0.2 0 0 9 8 2 4 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) 6 8 10 12 14 VDD (V) 6 4 3 VDD = 5V VPWM (V) VPWM(MAX)(V) 7 2 1 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) 8 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 0 10 2 4 6 8 10 12 14 VDD (V) 0 2 4 6 8 10 VDD (V) 12 14 VOT vs. Temperature 9 8 VOT(V) 1 10 9 10 9 8 7 VDD =12V 0.01 0.1 CAPACITANCE (µF) VOT vs. Supply Voltage VPWM(max) vs. Supply Voltage VPWM(max) vs. Temperature 5 1 0.001 VOT (V) FPWM(NORMALIZED) 1.2 PWM Frequency vs. Timing Capacitor Value V DD = 12V 7 6 5 4 VDD = 5V 3 2 1 0 -40 -20 0 20 40 60 80 100 TEMPERATURE (°C) March 2003 7 MIC502 MIC502 MIC502 MIC502 Micrel Functional Diagram VT2 PWM 5 Driver OUT 7 VT1 1 CF CLK Start-Up Timer OUT RESET Oscillator 2 Sleep VSLP Sleep Control 3 VDD 8 Power-On Reset Bias Reset ENABLE VIL Overtemperature OTF 6 4 MIC502 MIC502 8 GND March 2003 MIC502 MIC502 Micrel Once in sleep mode, all device functions cease (/OTF inactive, PWM output off) unless VT1 or VT2 rise above VWAKE. (VWAKE = VSLP + VHYST.) VHYST is a fixed amount of hysteresis added to the sleep comparator which prevents erratic operation around the VSLP operating point. The result is stable and predictable thermostatic action: whenever possible the fan is shut down to reduce energy consumption and acoustic noise, but will always be activated if the system temperature rises. If the device powers-up or exits its reset state, the fan will not start unless VT1 or VT2 rises above VWAKE. Functional Description Oscillator A capacitor connected to CF determines the frequency of the internal time base which drives the state-machine logic and determines the PWM frequency. This operating frequency will be typically 30Hz to 60Hz. (CF = 0.1µF for 30Hz.) Pulse-Width Modulator A triangle-wave generator and threshold detector comprise the internal pulse-width modulator (PWM). The PWM's output duty-cycle is determined by the higher of VT1 or VT2. A typical voltage range of 30% to 70% of VDD applied to the VT1 and VT2 pins corresponds to 0% to 100% duty-cycle. Since at least one of the control voltage inputs is generally from a thermistor-resistor divider connected to VDD, the PWM output duty cycle will not be affected by changes in the supply voltage. Driver Output OUT is a complementary push-pull digital output with asymmetric drive (approximately 10mA source, 1mA sink-see "Electrical Characteristics"). It is optimized for directly driving an NPN transistor switch in the fan's ground-return. See "Applications Information" for circuit details. Shutdown/Reset Internal circuitry automatically performs a reset of the MIC502 MIC502 when power is applied. The MIC502 MIC502 may be shut down at any time by forcing VT1 below its VIL threshold. This is typically accomplished by connecting the VT1 pin to open-drain or open-collector logic and results in an immediate and asynchronous shutdown of the MIC502 MIC502. The OUT and /OTF pins will float while VT1 is below VIL. If VT1 then rises above VIH, a device reset occurs. Reset is equivalent to a power-up condition: the state of /OTF is cleared, a startup interval is triggered, and normal fan operation begins. Startup Interval Any time the fan is started from the off state (power-on or coming out of sleep mode or shutdown mode), the PWM output is automatically forced high for a startup interval of 64 × tPWM. Once the startup interval is complete, PWM operation will commence and the duty-cycle of the output will be determined by the higher of VT1 or VT2. Overtemperature Fault Output /OTF is an active-low, open-collector logic output. An overtemperature condition will cause /OTF to be asserted. An overtemperature condition is determined by VT1 exceeding the normal operating range of 30% to 70% of VDD by > 7% of VDD. Note that VOT is guaranteed by design to always be higher than VPWM(max). Sleep Mode When VT1 and VT2 fall below VSLP, the system is deemed capable of operating without fan cooling and the MIC502 MIC502 enters sleep mode and discontinues fan operation. The threshold where the MIC502 MIC502 enters sleep mode is determined by VSLP. Connecting the VSLP pin to ground disables sleep mode. March 2003 System Operation Power Up · · · · · A complete reset occurs when power is applied. OUT is off (low) and /OTF is inactive (high/floating). If VT1 < VIL, the MIC502 MIC502 remains in shutdown. The startup interval begins. OUT will be on (high) for 64 clock cycles (64 × tPWM). Following the startup interval, normal operation begins. POWER ON Reset Startup Timer; Deassert /OTF; OUT Off (Low). YES VT1 < VIL ? NO VT1 > VOT ? NO YES Assert /OTF While VT1 > VOT NO OUT Held On (High) During Startup Interval. Startup Interval Finished ? YES Deassert OUT (OUT = Low) NORMAL OPERATION Figure 3. Power-Up Behavior 9 MIC502 MIC502 MIC502 MIC502 Micrel Normal Operation Sleep Mode Normal operation consists of the PWM operating to control the speed of the fan according to VT1 and VT2. Exceptions to this otherwise indefinite behavior can be caused by any of three conditions: VT1 exceeding VOT, an overtemperature condition; VT1 being pulled below VIL initiating a device shutdown and reset; or both VT1 and VT2 falling below VSLP, activating sleep mode. Each of these exceptions is treated as follows: During normal operation, if VT1 and VT2 fall below VSLP, the device will go into sleep mode and fan operation will stop. The MIC502 MIC502 will exit sleep mode when VT1 or VT2 rise above VSLP by the hysteresis voltage, VHYST. When this occurs, normal operation will resume. The resumption of normal operation upon exiting sleep is indistinguishable from a power-on reset. (See "Sleep: Normal Operation," above.) NORMAL OPERATION Reset? VT1 < VIL ? SLEEP YES POWER ON YES SLEEP Disable PWM NO VT1 and VT2 < VSLEEP ? Reset Initiated VT1 < VIL ? NO NO YES Overtemp? VT1 > VOT ? YES Assert /OTF while VT1 > VOT NO NO Reset Released VT1 > VIH ? OUT Duty Cycle Proportional to Greater of VT1, VT2 YES Wake Up? VT1 or VT2 > VSLP+VHYST ? YES Figure 4. Normal System Behavior · Overtemperature: If the system temperature rises typically 7% above the 100% duty-cycle operating point, /OTF will be activated to indicate an overtemperature fault. (VT1 > VOT) Overtemperature detection is essentially independent of other operations-the PWM continues its normal behavior; with VT1 > VPWM(max), the output duty-cycle will be 100%. If VT1 falls below VOT, the overtemperature condition is cleared and /OTF is no longer asserted. It is assumed that in most systems, the /OTF output will initiate power supply shutdown. · Shutdown/Reset: If VT1 is driven below VIL an immediate, asynchronous shutdown occurs. While in shutdown mode, OUT is off (low), and /OTF is unconditionally inactive (high/floating). If VT1 subsequently rises above VIH, a device reset will occur. Reset is indistinguishable from a power-up condition. The state of /OTF is cleared, a startup interval is triggered, and normal fan operation begins. · Sleep: If VT1 and VT2 fall below VSLP, the device enters sleep mode. All internal functions cease unless VT1 or VT2 rise above VWAKE. (VWAKE = VSLP + VHYST.) The /OTF output is unconditionally inactive (high/floating) and the PWM is disabled during sleep. (OUT will float.) MIC502 MIC502 NO POWER ON Figure 5. Sleep-Mode Behavior 10 March 2003 MIC502 MIC502 Micrel since Applications Information VPWM(max) = 70% of VDD 100% RPM The Typical Application drawing on page 1 illustrates a typical application circuit for the MIC502 MIC502. Interfacing the MIC502 MIC502 with a system consists of the following steps: 1. Selecting a temperature sensor 2. Interfacing the temperature sensor to the VT1 input 3 Selecting a fan-drive transistor, and base-drive current limit resistor 4. Deciding what to do with the Secondary Fan-Control Input 5. Making use of the Overtemperature Fault Output. Temperature Sensor Selection Temperature sensor T1 is a negative temperature coefficient (NTC) thermistor. The MIC502 MIC502 can be interfaced with either a negative or positive tempco thermistor; however, a negative temperature coefficient thermistor typically costs less than its equivalent positive tempco counterpart. While a variety of thermistors can be used in this application, the following paragraphs reveal that those with an R25 rating (resistance at 25°C) of from about 50k to 100k lend themselves nicely to an interface network that requires only a modest current drain. Keeping the thermistor bias current low not only indicates prudent design; it also prevents selfheating of the sensor from becoming an additional design consideration. It is assumed that the thermistor will be located within the system power supply, which most likely also houses the speed-controlled fan. Temperature Sensor Interface As shown by the Electrical Characteristics table, the working voltage for input VT1 is specified as a percentage of VDD. This conveniently frees the designer from having to be concerned with interactions resulting from variations in the supply voltage. By design, the operating range of VT1 is from about 30% of VDD to about 70% of VDD. VPWM(min) = VPWM(max) ­ VPWM(span) When VT1 = VPWM(max) 0.7VDD, a 100% duty-cycle motor drive signal is generated. Conversely, when VT1 = VPWM(min) 0.3VDD, the motor-drive signal has a 0% duty cycle. Resistor voltage divider R1 || T1, R2 in the Typical Application diagram is designed to preset VT1 to a value of VPWM that corresponds to the slowest desired fan speed when the resistance of thermistor T1 is at its highest (cold) value. As temperature rises the resistance of T1 decreases and VT1 increases because of the parallel connection of R1 and T1. Since VT1 = VPWM(min) represents a stopped fan (0% dutycycle drive), and since it is foreseen that at least some cooling will almost always be required, the lowest voltage applied to the VT1 input will normally be somewhat higher than 0.3VDD (or >VPWM(min). It is assumed that the system will be in sleep mode rather than operate the fan at a very low duty cycle (