MFRC523 RS232 HVQFN32 MFRC52301HN1/TRAYB MFRC52301HN1/TRAYBM 64-BYTE CRC16 - Datasheet Archive

 

Contactless reader IC Rev. 3.5 - 24 September 2010 115235 Product data sheet PUBLIC 1. Introduction This document describes the

 

MFRC523 MFRC523 Contactless reader IC Rev. 3.5 - 24 September 2010 115235 Product data sheet PUBLIC 1. Introduction This document describes the functionality and electrical specifications of the contactless reader/writer MFRC523 MFRC523. Remark: The MFRC523 MFRC523 supports all variants of the MIFARE Mini, MIFARE 1K and MIFARE 4K RF identification protocols. To aid readability throughout this data sheet, the MIFARE Mini, MIFARE 1K and MIFARE 4K products and protocols have the generic name MIFARE. 2. General description The MFRC523 MFRC523 is a highly integrated reader/writer for contactless communication at 13.56 MHz. The MFRC523 MFRC523 reader supports ISO/IEC 14443 A/MIFARE mode. The MFRC523 MFRC523's internal transmitter is able to drive a reader/writer antenna designed to communicate with ISO/IEC 14443 A/MIFARE cards and transponders without additional active circuitry. The receiver module provides a robust and efficient implementation for demodulating and decoding signals from ISO/IEC 14443 A/MIFARE compatible cards and transponders. The digital module manages the complete ISO/IEC 14443 A framing and error detection (parity and CRC) functionality. All protocol layers of the ISO/IEC 14443 A and ISO/IEC 14443 B communication standards are supported provided: · additional components, such as the oscillator, power supply, coil etc are correctly applied · standardized protocols, such as ISO/IEC 14443-4 and/or ISO/IEC 14443 B anticollision are correctly implemented Using this NXP Semiconductors' device according to ISO/IEC 14443 B may infringe third party patent rights. The MFRC523 MFRC523 supports contactless communication using MIFARE higher baud rates (see Section 8.3.4.11 on page 22) at transfer speeds up to 848 kBd in both directions. The following host interfaces are provided: · Serial Peripheral Interface (SPI) · Serial UART (similar to RS232 RS232 with voltage levels dependent on pin voltage supply) · I2C-bus interface MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 3. Features and benefits Highly integrated analog circuitry to demodulate and decode responses Buffered output drivers for connecting an antenna with the minimum number of external components Supports ISO/IEC 14443 A/MIFARE Supports ISO/IEC 14443 B Read/Write modes Typical operating distance in Read/Write mode up to 50 mm depending on the antenna size and tuning Supports MIFARE Mini, MIFARE 1K and MIFARE 4K encryption in Read/Write mode Supports ISO/IEC 14443 A higher transfer speed communication at 212 kBd, 424 kBd and 848 kBd Supports MFIN/MFOUT Additional internal power supply to the smart card IC connected via MFIN/MFOUT Supported host interfaces SPI up to 10 Mbit/s I2C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode RS232 RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin voltage supply FIFO buffer handles 64 byte send and receive Flexible interrupt modes Hard reset with low power function Power-down by software mode Programmable timer Internal oscillator for connection to 27.12 MHz quartz crystal 2.5 V to 3.3 V power supply CRC coprocessor Programmable I/O pins Internal self-test 4. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions VDDA analog supply voltage VDDD digital supply voltage VDD(PVDD) VDDA = VDDD = VDD(TVDD); VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V Min [3] VDD(PVDD) PVDD supply voltage VDD(SVDD) SVDD supply voltage power-down current Unit 3.6 V 3.3 3.6 V 3.3 3.6 V 1.6 1.8 3.6 V 1.6 VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V Ipd Max 3.3 2.5 VDD(TVDD) TVDD supply voltage Typ 2.5 2.5 [1][2] - 3.6 V - - 5 A VDDA = VDDD = VDD(TVDD) = VDD(PVDD) = 3 V hard power-down; pin NRSTPD set LOW soft power-down; RF level detector on IDDD digital supply current MFRC523 MFRC523_34 Product data sheet PUBLIC [4] [4] pin DVDD; VDDD = 3 V All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 - - 10 A - 6.5 9 mA © NXP B.V. 2010. All rights reserved. 2 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 1. Quick reference data .continued Symbol Parameter Conditions Min Typ Max Unit IDDA analog supply current pin AVDD; VDDA = 3 V, CommandReg register's RcvOff bit = 0 - 7 10 mA pin AVDD; receiver switched off; VDDA = 3 V, CommandReg register's RcvOff bit = 1 - 3 5 mA [5] - - 40 mA [6][7][8] - 60 100 mA -25 - +85 °C IDD(PVDD) PVDD supply current pin PVDD IDD(TVDD) TVDD supply current pin TVDD; continuous wave Tamb ambient temperature HVQFN32 HVQFN32 [1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance. [2] VDDA, VDDD and VDD(TVDD) must always be the same voltage. [3] VDD(PVDD) must always be the same or lower voltage than VDDD. [4] Ipd is the total current for all supplies. [5] IDD(PVDD) depends on the overall load at the digital pins. [6] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2. [7] During typical circuit operation, the overall current is below 100 mA. [8] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz. 5. Ordering information Table 2. Ordering information Type number Package Name MFRC52301HN1/TRAYB MFRC52301HN1/TRAYB[1] Description Version HVQFN32 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5 × 5 × 0.85 mm SOT617-1 MFRC52301HN1/TRAYBM MFRC52301HN1/TRAYBM[2] HVQFN32 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminal; body 5 × 5 × 0.85 mm SOT617-1 [1] Delivered in one tray. [2] Delivered in five trays. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 3 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 6. Block diagram The analog interface manages the modulation and demodulation of the analog signals. The contactless UART manages the protocol requirements for the communication protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data transfers to/from the host and the contactless UART. Various host interfaces are implemented to meet different customer requirements. REGISTER BANK ANTENNA ANALOG INTERFACE CONTACTLESS UART FIFO BUFFER SERIAL UART SPI I2C-BUS HOST 001aaj627 Fig 1. MFRC523 MFRC523_34 Product data sheet PUBLIC Simplified block diagram of the MFRC523 MFRC523 All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 4 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC D6/ADR_0/ D4/ADR_2 MOSI/MX D5/ADR_1/ D7/SCL/ D3/ADR_3 SCK/DTRQ MISO/TX D2/ADR_4 SDA/NSS/RX 24 EA I2C 32 D1/ADR_5 1 25 26 28 27 29 30 PVDD PVSS 31 2 5 3 VOLTAGE MONITOR AND POWER ON DETECT SPI, UART, I2C-BUS INTERFACE CONTROL 4 15 18 FIFO CONTROL DVDD DVSS AVDD AVSS STATE MACHINE 64-BYTE 64-BYTE FIFO BUFFER COMMAND REGISTER RESET CONTROL PROGRAMABLE TIMER POWER-DOWN CONTROL CONTROL REGISTER BANK 6 23 INTERRUPT CONTROL MIFARE CLASSIC UNIT IRQ CRC16 CRC16 GENERATION AND CHECK RANDOM NUMBER GENERATOR NRSTPD PARALLEL/SERIAL CONVERTER BIT COUNTER PARITY GENERATION AND CHECK FRAME GENERATION AND CHECK BIT DECODING BIT ENCODING 7 8 SERIAL DATA SWITCH 9 21 ANALOG TO DIGITAL CONVERTER REFERENCE VOLTAGE ANALOG TEST MULTIPLEXOR AND DIGITAL TO ANALOG CONVERTER 16 19 20 VMID AUX1 AUX2 Fig 2. I-CHANNEL AMPLIFIER MFOUT SVDD OSCILLATOR TEMPERATURE SENSOR 22 OSCIN OSCOUT Q-CHANNEL AMPLIFIER I-CHANNEL DEMODULATOR CLOCK GENERATION, FILTERING AND DISTRIBUTION Q-CLOCK GENERATION AMPLITUDE RATING MFIN Q-CHANNEL DEMODULATOR TRANSMITTER CONTROL 17 RX 10, 14 TVSS 11 TX1 13 TX2 12 TVDD 001aak602 Detailed block diagram of the MFRC523 MFRC523 MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 5 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 25 D1/ADR_5 26 D2/ADR_4 27 D3/ADR_3 28 D4/ADR_2 29 D5/ADR_1/SCK/DTRQ 30 D6/ADR_0/MOSI/MX 31 D7/SCL/MISO/TX 32 EA 7. Pinning information I2C 1 24 SDA/NSS/RX PVDD 2 23 IRQ DVDD 3 22 OSCOUT DVSS 4 PVSS 5 NRSTPD 6 19 AUX1 MFIN 7 18 AVSS MFOUT 8 17 RX 21 OSCIN VMID 16 20 AUX2 AVDD 15 TVSS 14 TX2 13 TVDD 12 TX1 11 9 SVDD TVSS 10 MFRC523 MFRC523 001aal155 Transparent top view Fig 3. Pinning configuration HVQFN32 HVQFN32 (SOT617-1) 7.1 Pin description Table 3. Pin description Pin Symbol Type[1] Description 1 I2C I[2] I2C-bus enable input 2 PVDD P pin power supply 3 DVDD P digital power supply digital ground 4 DVSS G[3] 5 PVSS G pin power supply ground 6 NRSTPD I reset and power-down input: reset: enabled by a positive edge power-down: enabled when LOW; internal current sinks are switched off, the oscillator is inhibited and the input pins are disconnected from the outside world 7 MFIN I MIFARE signal input 8 MFOUT O MIFARE signal output 9 SVDD P MFIN and MFOUT pin power supply 10 TVSS G transmitter output stage 1 ground 11 TX1 O transmitter 1 modulated 13.56 MHz energy carrier output 12 TVDD P transmitter power supply: supplies the output stage of transmitters 1 and 2 13 TX2 O transmitter 2 modulated 13.56 MHz energy carrier output 14 TVSS G transmitter output stage 2 ground 15 AVDD P analog power supply MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 6 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 3. Pin description .continued Pin Symbol Type[1] Description 16 VMID P internal reference voltage 17 RX I RF signal input 18 AVSS G analog ground 19 AUX1 O auxiliary outputs for test purposes 20 AUX2 O auxiliary outputs for test purposes 21 OSCIN I crystal oscillator inverting amplifier input; also the input for an externally generated clock (fclk = 27.12 MHz) 22 OSCOUT O crystal oscillator inverting amplifier output 23 IRQ O interrupt request output: indicates an interrupt event 24 SDA[2] I/O I2C-bus serial data line input/output NSS[2] I SPI signal input RX[2] I UART address input D1[2] I/O test port ADR_5[2] I/O I2C-bus address 5 input D2 I/O test port ADR_4[2] I I2C-bus address 4 input D3 I/O test port ADR_3[2] I I2C-bus address 3 input D4 I/O test port ADR_2[2] I I2C-bus address 2 input D5 I/O test port ADR_1[2] I I2C-bus address 1 input SCK[2] I SPI serial clock input 25 26 27 28 29 DTRQ[2] O UART request to send output to microcontroller D6 I/O test port ADR_0[2] I I2C-bus address 0 input MOSI[2] 30 I/O SPI master out, slave in MX[2] UART output to microcontroller I/O test port SCL[2] I/O I2C-bus clock input/output MISO[2] I/O SPI master in, slave out TX[2] O UART data output to microcontroller EA[2] 32 O D7 31 I external address input for coding I2C-bus address [1] Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground. [2] The pin functionality of these pins is explained in Section 8.3 "Digital interfaces". [3] Connection of heatsink pad on package underside is not necessary. Optional connection to pin DVSS is possible. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 7 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 8. Functional description The MFRC523 MFRC523 transmission module supports ISO/IEC 14443 A and ISO/IEC 14443 B Read/Write mode at various transfer speeds and modulation protocols. BATTERY MFRC523 MFRC523 ISO/IEC 14443 A CARD MICROCONTROLLER contactless card reader/writer Fig 4. 001aal156 MFRC523 MFRC523 Read/Write mode 8.1 ISO/IEC 14443 A functionality The physical level communication is shown in Figure 5. (1) ISO/IEC 14443 A READER ISO/IEC 14443 A CARD (2) MFRC523 MFRC523 001aal157 (1) Reader to card (MFRC523 MFRC523 sends data to a card). (2) Card to reader (card sends data to the MFRC523 MFRC523). Fig 5. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram The physical parameters are described in Table 4. Table 4. Communication overview for ISO/IEC 14443 A reader/writer Communication direction Signal type Reader to card (MFRC523 MFRC523 sends data to a card) Card to reader (card sends data to the MFRC523 MFRC523) Transfer speed 106 kBd 212 kBd 424 kBd 848 kBd reader side modulation 100 % ASK 100 % ASK 100 % ASK 100 % ASK bit encoding modified Miller encoding modified Miller encoding modified Miller encoding modified Miller encoding bit length 128 (13.56 s) 64 (13.56 s) 32 (13.56 s) 16 (13.56 s) card side modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier load modulation subcarrier frequency 13.56 MHz / 16 13.56 MHz / 16 13.56 MHz / 16 13.56 MHz / 16 bit encoding Manchester encoding BPSK BPSK BPSK The MFRC523 MFRC523's contactless UART and dedicated external host must manage the ISO/IEC 14443 A protocol. Figure 6 shows the data coding and framing according to ISO/IEC 14443 A. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 8 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC ISO/IEC 14443 A framing at 106 kBd start 8-bit data 8-bit data odd parity start bit is 1 8-bit data odd parity odd parity ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd start 8-bit data even parity 8-bit data odd parity start bit is 0 burst of 32 subcarrier clocks 8-bit data odd parity even parity at the end of the frame 001aak585 Fig 6. Data coding and framing according to ISO/IEC 14443 A The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A part 3 and handles parity generation internally based on the transfer speed. Automatic parity generation can be switched off using the ManualRCVReg register's ParityDisable bit. 8.2 ISO/IEC 14443 B functionality The MFRC523 MFRC523 reader IC fully supports the ISO 14443 international standard which includes the communication schemes ISO 14443 A and ISO 14443 B. Refer to the ISO 14443 reference documents Identification cards - Contactless integrated circuit cards - Proximity cards (parts 1 to 4). Remark: NXP Semiconductors does not offer a software library to enable design-in of the ISO 14443 B protocol. 8.3 Digital interfaces 8.3.1 Automatic microcontroller interface detection The MFRC523 MFRC523 supports direct interfacing to hosts using SPI, I2C-bus or serial UART interfaces. The MFRC523 MFRC523 resets its interface and checks the current host interface type automatically after performing a power-on or hard reset. The MFRC523 MFRC523 identifies the host interface by sensing the logic levels on the control pins after the reset phase. This is done using a combination of fixed pin connections. Table 5 shows the different pin connection configurations. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 9 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 5. Connection protocol for detecting different interface types Pin Interface type UART (input) SPI (output) I2C-bus (I/O) SDA RX NSS SDA I2C 0 0 1 EA 0 1 EA D7 TX MISO SCL D6 MX MOSI ADR_0 D5 DTRQ SCK ADR_1 D4 - - ADR_2 D3 - - ADR_3 D2 - - ADR_4 D1 - - ADR_5 8.3.2 Serial Peripheral Interface The 5-wire Serial Peripheral Interface (SPI) is supported and enables high-speed communication with the host. The interface can manage data speeds up to 10 Mbit/s. When communicating with a host, the MFRC523 MFRC523 acts as a slave. As such, it receives data from the external host for register settings, sends and receives data relevant for RF interface communication. An interface compatible with SPI enables high-speed serial communication between the MFRC523 MFRC523 and a microcontroller. The implemented interface meets with the SPI standard. The timing specification is given in Section 14.1 on page 75. MFRC523 MFRC523 SCK MOSI MISO NSS SCK MOSI MISO NSS 001aal159 Fig 7. SPI connection to host The MFRC523 MFRC523 acts as a slave during SPI communication and is timed using the SPI clock signal (SCK) generated by the master. Data communication from the master to the slave uses the MOSI line. The MISO line is used to send data from the MFRC523 MFRC523 to the master. Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI and MISO lines must be stable on the rising edge of the clock and can be changed on the falling edge. Data is sent by the MFRC523 MFRC523 on the falling clock edge and is stable during the rising clock edge. 8.3.2.1 SPI read data Reading data using SPI requires the byte order shown in Table 6 to be used. It is possible to read out up to n-data bytes. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 10 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC The first byte sent defines both the mode and the address. Table 6. MOSI and MISO byte order Line Byte 0 MOSI address 0 address 1 address 2 MISO X[1] data 0 data 1 [1] Byte 1 Byte 2 To Byte n Byte n + 1 . address n 00 . data n - 1 data n X = Do not care. Remark: The MSB must be sent first. 8.3.2.2 SPI write data To write data to the MFRC523 MFRC523 using SPI requires the byte order shown in Table 7. It is possible to write up to n-data bytes by only sending one address byte. The first send byte defines both the mode and the address byte. Table 7. MOSI and MISO byte order Line Byte 0 Byte 1 Byte 2 To Byte n Byte n + 1 MOSI address 0 data 0 data 1 . data n - 1 data n MISO X[1] X[1] X[1] . X[1] X[1] [1] X = Do not care. Remark: The MSB must be sent first. 8.3.2.3 SPI Read and Write address byte The read address byte must meet the following criteria: · the Most Significant Bit (MSB) of the first byte sets the mode. To read data from the MFRC523 MFRC523, the MSB is set to logic 1; see Table 8 · bits [6:1] define the address · the Least Significant Bit (LSB) should be set to logic 0 Table 8. Address (MOSI) byte 0 MFRC523 MFRC523_34 Product data sheet PUBLIC SPI read address Bit 7 (MSB) 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 address address address address address address All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 Bit 0 (LSB) 0 © NXP B.V. 2010. All rights reserved. 11 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC The write address byte must meet the following criteria: · the MSB of the first byte sets the mode. To write data to the MFRC523 MFRC523, the MSB is set to logic 0; see Table 9 · bits [6:1] define the address · the LSB should be set to logic 0 Table 9. SPI write address Address line (MOSI) Bit 7 (MSB) byte 0 Bit 6 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) address address address address address address 0 8.3.3 UART interface 8.3.3.1 Connection to a host MFRC523 MFRC523 RX RX TX TX DTRQ DTRQ MX MX 001aal158 Fig 8. UART connection to microcontrollers Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register's RS232LineEn bit. 8.3.3.2 Selectable UART transfer speeds The internal UART interface is compatible with the RS232 RS232 serial interface. The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller must write a value for the new transfer speed to the SerialSpeedReg register. Bits BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the SerialSpeedReg register. The BR_T0[2:0] and BR_T1[4:0] settings are described in Table 10. Examples of different transfer speeds and the relevant register settings are given in Table 11. Table 10. BR_T0 and BR_T1 settings BR_Tn Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 1 1 2 4 8 16 32 64 BR_T1 range Product data sheet PUBLIC Bit 1 BR_T0 factor MFRC523 MFRC523_34 Bit 0 1 to 32 33 to 64 33 to 64 33 to 64 All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 33 to 64 33 to 64 33 to 64 33 to 64 © NXP B.V. 2010. All rights reserved. 12 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 11. Selectable UART transfer speeds Transfer speed (kBd) SerialSpeedReg value Decimal Transfer speed accuracy (%)[1] Hexadecimal 7.2 250 FAh -0.25 9.6 235 EBh 0.32 14.4 218 DAh -0.25 19.2 203 CBh 0.32 38.4 171 ABh 0.32 57.6 154 9Ah -0.25 115.2 122 7Ah -0.25 128 116 74h -0.06 230.4 90 5Ah -0.25 460.8 58 3Ah -0.25 921.6 28 1Ch 1.45 1228.8 21 15h 0.32 [1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds. The selectable transfer speeds shown in Table 11 are calculated according to the following equations: If BR_T0[2:0] = 0: 6 27.12 × 10 transfer speed = -( BR_T0 + 1 ) (1) If BR_T0[2:0] > 0: 27.12 × 10 6 transfer speed = - ( BR_T1 + 33 ) - 2 ( BR_T0 ­ 1 ) (2) Remark: Transfer speeds above 1228.8 kBd are not supported. 8.3.3.3 UART framing Table 12. Bit UART framing Length Value Start 1-bit 0 Data 8-bit data Stop 1-bit 1 Remark: The LSB for data and address bytes must be sent first. No parity bit is used during transmission. To read data using the UART interface, the flow shown in Table 13 must be used. The first byte sent defines both the mode and the address. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 13 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 13. Read data byte order Pin Byte 0 Byte 1 RX address - TX - data 0 ADDRESS RX SA A0 A1 A2 A3 A4 A5 (1) R/W SO DATA TX SA D0 D1 D2 D3 D4 D5 D6 D7 SO MX DTRQ 001aak588 (1) Reserved. Fig 9. UART read data timing diagram To write data to the MFRC523 MFRC523 using the UART interface, the structure shown in Table 14 must be used. The first byte sent defines both the mode and the address. Table 14. Write data byte order Pin address 0 data 0 TX Product data sheet PUBLIC Byte 1 RX MFRC523 MFRC523_34 Byte 0 - address 0 All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 14 of 97 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors MFRC523 MFRC523_34 Product data sheet PUBLIC ADDRESS DATA RX SA A0 A1 A2 A3 A4 A5 (1) R/W SO SA D0 D1 D2 D3 D4 D5 D6 D7 SO All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 ADDRESS TX SA A0 A1 A2 A3 A4 A5 (1) R/W SO MX DTRQ 001aak589 Fig 10. UART write data timing diagram MFRC523 MFRC523 Remark: The data byte can be sent directly after the address byte on pin RX. Contactless reader IC 15 of 97 © NXP B.V. 2010. All rights reserved. (1) Reserved. MFRC523 MFRC523 NXP Semiconductors Contactless reader IC The address byte must meet the following formats: · the MSB of the first byte sets the mode used ­ the MSB is set to logic 0 to write data to the MFRC523 MFRC523 ­ the MSB is set to logic 1 to read data from the MFRC523 MFRC523 · bit 6 is reserved for future use · bits [5:0] define the address; see Table 15 Table 15. Address byte 0 register; address MOSI Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) 1 or 0 reserved address address address address address address 8.3.4 I2C Bus Interface An I2C-bus interface is supported and enables implementation of a low-cost, low pin count serial bus interface to the host. The I2C-bus interface is implemented based on NXP Semiconductors' I2C-bus interface specification, rev. 2.1, January 2000. The interface can only act in slave mode. Therefore the MFRC523 MFRC523 does not perform clock generation or access arbitration. PULL-UP NETWORK PULL-UP NETWORK MFRC523 MFRC523 SDA SCL MICROCONTROLLER I2C CONFIGURATION WIRING EA ADR_[5:0] 001aal160 Fig 11. I2C-bus interface The MFRC523 MFRC523 can act as a slave receiver or slave transmitter in Standard mode, Fast mode and High-speed mode. SDA is a bidirectional line connected to a positive supply voltage using a current source or a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The MFRC523 MFRC523 has a 3-state output stage to perform the wired-AND function. Data on the I2C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to 400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode. If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDA as defined in the I2C-bus interface specification. See Table 154 on page 76 for timing requirements. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 16 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 8.3.4.1 Data validity Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW state of the data line must only change when the clock signal on SCL is LOW. SDA SCL data line stable; data valid change of data allowed mbc621 Fig 12. Bit transfer on the I2C-bus 8.3.4.2 START and STOP conditions To manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions are defined. · A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is HIGH. · A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is HIGH. The I2C-bus master always generates the START and STOP conditions. The bus is busy after the START condition. The bus is free again a certain time after the STOP condition. The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. The START (S) and repeated START (Sr) conditions are functionally identical. Therefore, S is used as a generic term to represent both the START (S) and repeated START (Sr) conditions. SDA SDA SCL SCL S P START condition STOP condition mbc622 Fig 13. START and STOP conditions 8.3.4.3 Byte format Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first; see Figure 16. The number of transmitted bytes during one data transfer is unrestricted but must meet the read/write cycle format. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 17 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 8.3.4.4 Acknowledge An acknowledge must be sent at the end of one data byte. The acknowledge-related clock pulse is generated by the master. The transmitter of data, either master or slave, releases the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the SDA line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse. The master can then generate either a STOP (P) condition to stop the transfer or a repeated START (Sr) condition to start a new transfer. A master-receiver indicates the end of data to the slave-transmitter by not generating an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter releases the data line to allow the master to generate a STOP (P) or repeated START (Sr) condition. data output by transmitter not acknowledge data output by receiver acknowledge SCL from master 1 2 8 9 S clock pulse for acknowledgement START condition mbc602 Fig 14. Acknowledge on the I2C-bus P SDA acknowledgement signal from slave MSB acknowledgement signal from receiver Sr byte complete, interrupt within slave clock line held LOW while interrupts are serviced SCL S or Sr 1 2 7 8 9 1 2 ACK 3-8 9 ACK Sr or P STOP or repeated START condition START or repeated START condition msc608 Fig 15. Data transfer on the I2C-bus MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 18 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 8.3.4.5 7-Bit addressing During the I2C-bus address procedure, the first byte after the START condition is used to determine which slave will be selected by the master. Several address numbers are reserved. During device configuration, the designer must ensure that collisions with these reserved addresses cannot occur. Check the I2C-bus specification for a complete list of reserved addresses. The I2C-bus address specification is dependent on the definition of pin EA. Immediately after releasing pin NRSTPD or after a power-on reset, the device defines the I2C-bus address according to pin EA. If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by NXP Semiconductors and set to 0101b for all MFRC523 MFRC523 devices. The remaining 3 bits (ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer to prevent collisions with other I2C-bus devices. If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins according to Table 5 on page 10. ADR_6 is always set to logic 0. In both modes, the external address coding is latched immediately after releasing the reset condition. Further changes at the used pins are not taken into consideration. Depending on the external wiring, the I2C-bus address pins can be used for test signal outputs. MSB bit 6 LSB bit 5 bit 4 bit 3 bit 2 slave address bit 1 bit 0 R/W 001aak591 Fig 16. First byte following the START procedure 8.3.4.6 Register write access To write data from the host controller using the I2C-bus to a specific register in the MFRC523 MFRC523 the following frame format must be used. · The first byte of a frame indicates the device address according to the I2C-bus rules. · The second byte indicates the register address followed by up to n-data bytes. In one frame, all data bytes are written to the same register address. This enables fast FIFO buffer access. The Read/Write (R/W) bit is set to logic 0. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 19 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 8.3.4.7 Register read access To read out data from a specific register address in the MFRC523 MFRC523, the host controller must use the following procedure: · Firstly, a write access to the specific register address must be performed as indicated in the frame that follows · The first byte of a frame indicates the device address according to the I2C-bus rules · The second byte indicates the register address. No data bytes are added · The Read/Write bit is 0 After the write access, read access can start. The host sends the device address of the MFRC523 MFRC523. In response, the MFRC523 MFRC523 sends the content of the read access register. In one frame all data bytes can be read from the same register address. This enables fast FIFO buffer access or register polling. The Read/Write (R/W) bit is set to logic 1. write cycle I2C-BUS S SLAVE ADDRESS [A7:A0] 0 (W) A 0 JOINER REGISTER ADDRESS [A5:A0] 0 A [0:n] DATA [7:0] A P read cycle S I2C-BUS SLAVE ADDRESS [A7:A0] 0 (W) A 0 JOINER REGISTER ADDRESS [A5:A0] 0 A P optional, if the previous access was on the same register address [0:n] I2C-BUS SLAVE ADDRESS [A7:A0] 1 (R) A [0:n] DATA [7:0] A DATA [7:0] S A P sent by master S A not acknowledge stop condition W write cycle A sent by slave start condition P acknowledge R read cycle 001aak592 Fig 17. Register read and write access MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 20 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 8.3.4.8 High-speed mode In High-speed mode (HS mode), the device can transfer information at data rates of up to 3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard modes (F/S modes) for bidirectional communication in a mixed-speed bus system. 8.3.4.9 High-speed transfer To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to I2C-bus operation. · The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger on the SDA and SCL inputs and different timing constants when compared to F/S mode · The output buffers of the device in HS mode incorporate slope control of the falling edges of the SDA and SCL signals with different fall times compared to F/S mode 8.3.4.10 Serial data transfer format in HS mode The HS mode serial data transfer format meets the Standard mode I2C-bus specification. HS mode can only start after all of the following conditions (all of which are in F/S mode): 1. START condition (S) 2. 8-bit master code (00001 XXXb) 3. Not-acknowledge bit (A) When HS mode starts, the active master sends a repeated START condition (Sr) followed by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from the selected MFRC523 MFRC523. Data transfer continues in HS mode after the next repeated START (Sr), only switching back to F/S mode after a STOP condition (P). To reduce the overhead of the master code, a master links a number of HS mode transfers, separated by repeated START conditions (Sr). HS mode (current-source for SCL HIGH enabled) F/S mode S MASTER CODE A Sr SLAVE ADDRESS R/W A DATA F/S mode A/A P (n-bytes + A) HS mode continues Sr SLAVE ADDRESS 001aak749 Fig 18. I2C-bus HS mode protocol switch MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 21 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC A 8-bit master code 0000 1xxx S t1 tH SDA high SCL high 1 6 2 to 5 7 8 9 F/S mode R/W 7-bit SLA Sr n + (8-bit data A + A/A) Sr P SDA high SCL high 1 2 to 5 6 7 8 9 1 2 to 5 6 7 8 9 If P then F/S mode HS mode If Sr (dotted lines) then HS mode tH tFS = Master current source pull-up msc618 = Resistor pull-up Fig 19. I2C-bus HS mode protocol frame 8.3.4.11 Switching between F/S mode and HS mode After reset and initialization, the MFRC523 MFRC523 is in Fast mode (which is in effect F/S mode as Fast mode is downward-compatible with Standard mode). The connected MFRC523 MFRC523 recognizes the "S 00001XXX 00001XXX A" sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting. The following actions are taken: 1. Adapt the SDA and SCL input filters according to the spike suppression requirement in HS mode. 2. Adapt the slope control of the SDA output stages. It is possible for system configurations that do not have other I2C-bus devices involved in the communication to switch to HS mode permanently. This is implemented by setting Status2Reg register's I2CForceHS bit to logic 1. In permanent HS mode, the master code is not required to be sent. This is not defined in the specification and must only be used when no other devices are connected on the bus. In addition, spikes on the I2C-bus lines must be avoided because of the reduced spike suppression. 8.3.4.12 MFRC523 MFRC523 in lower speed modes MFRC523 MFRC523 is fully downward-compatible and can be connected to an F/S mode I2C-bus system. The device stays in F/S mode and communicates at F/S mode speeds because a master code is not transmitted in this configuration. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 22 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 8.4 Analog interface and contactless UART 8.4.1 General The integrated contactless UART supports the external host online with framing and error checking of the protocol requirements up to 848 kBd. An external circuit can be connected to the communication interface pins MFIN and MFOUT to modulate and demodulate the data. The contactless UART manage the protocol requirements for the communication protocols in cooperation with the host. Protocol handling generates bit and byte-oriented framing. In addition, it manages error detection such as parity and CRC, based on the various supported contactless communication protocols. Remark: The size and tuning of the antenna and the power supply voltage have an important impact on the achievable operating distance. 8.4.2 TX p-driver The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an envelope signal. It can be used to drive an antenna directly using a few passive components for matching and filtering; see Section 15 on page 78. The signal on pins TX1 and TX2 can be configured using the TxControlReg register; see Section 9.2.2.5 on page 47. The modulation index can be set by adjusting the impedance of the drivers. The impedance of the p-driver can be configured using registers CWGsPReg and ModGsPReg. The impedance of the n-driver can be configured using the GsNReg register. The modulation index also depends on the antenna design and tuning. The TxModeReg and TxSelReg registers control the data rate and framing during transmission and the antenna driver setting to support the different requirements at the different modes and transfer speeds. Table 16. Register and bit settings controlling the signal on pin TX1 Bit Bit Bit Tx1RFEn Force InvTx1RFOn 100ASK 100ASK Bit Envelope Pin InvTx1RFOff TX1 GSPMos GSNMos Remarks 0 X[1] X[1] X[1] X[1] X[1] X[1] X[1] not specified if RF is switched off 1 0 0 X[1] 0 RF pMod nMod 1 RF pCW nCW 0 1 X[1] 0 RF pMod nMod 100 % ASK: pin TX1 pulled to logic 0, independently of the InvTx1RFOff bit 1 RF pCW nCW 1 1 X[1] 0 0 pMod nMod 1 RF_n pCW nCW [1] X = Do not care. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 23 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 17. Register and bit settings controlling the signal on pin TX2 Bit Tx1RFEn Bit Bit Force Tx2CW 100ASK 100ASK Bit Bit Envelope Pin InvTx2RFOn InvTx2RFOff TX2 GSPMos GSNMos Remarks 0 X[1] X[1] X[1] X[1] X[1] X[1] X[1] X[1] not specified if RF is switched off 1 0 0 0 X[1] 0 RF pMod nMod - 1 RF pCW nCW 0 RF_n pMod nMod pCW nCW 1 1 pCW nCW X[1] RF_n pCW nCW X[1] 0 0 pMod nMod 1 RF pCW nCW X[1] 0 0 pMod nMod 1 RF_n pCW nCW 0 X[1] X[1] RF pCW nCW 1 [1] RF X[1] 1 1 X[1] 0 0 X[1] 1 1 RF_n 0 1 X[1] X[1] X[1] RF_n pCW nCW conductance always CW for the Tx2CW bit 100 % ASK: pin TX2 pulled to logic 0 (independent of the InvTx2RFOn/Inv Tx2RFOff bits) X = Do not care. The following abbreviations have been used in Table 16 and Table 17: · · · · · RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2 RF_n: inverted 13.56 MHz clock GSPMos: conductance, configuration of the PMOS array GSNMos: conductance, configuration of the NMOS array pCW: PMOS conductance value for continuous wave defined by the CWGsPReg register · pMod: PMOS conductance value for modulation defined by the ModGsPReg register · nCW: NMOS conductance value for continuous wave defined by the GsNReg register's CWGsN[3:0] bits · nMod: NMOS conductance value for modulation defined by the GsNReg register's ModGsN[3:0] bits · X = Do not care Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and GsNReg registers are used for both drivers. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 24 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 8.4.3 Serial data switch Two main blocks are implemented in the MFRC523 MFRC523. The digital block comprises the state machines, encoder/decoder logic. The analog block comprises the modulator and antenna drivers, the receiver and amplifiers. It is possible for the interface between these two blocks to be configured so that the interfacing signals are routed to pins MFIN and MFOUT. This topology allows the analog block of the MFRC523 MFRC523 to be connected to the digital block of another device. The serial signal switch is controlled by the TxSelReg and RxSelReg registers. Figure 20 shows the serial data switch for TX1 and TX2. DriverSel[1:0] 3-state INTERNAL CODER INVERT IF InvMod = 1 envelope 00 01 10 1 MFIN INVERT IF PolMFin = 0 11 to driver TX1 and TX2 0 = impedance = modulated 1 = impedance = CW 001aak593 Fig 20. Serial data switch for TX1 and TX2 8.4.4 MFIN and MFOUT interface support The MFRC523 MFRC523 is divided into a digital circuit block and an analog circuit block. The digital block contains state machines, encoder and decoder logic, etc. The analog block contains the modulator and antenna drivers, receiver and amplifiers. The interface between these two blocks can be configured to enable the interfacing signals to be routed to pins MFIN and MFOUT; see Figure 21 on page 26. This configuration is implemented using TxSelReg register's MFOutSel[3:0]/DriverSel[1:0] bits and RxSelReg register's UARTSel[1:0] bits. This topology allows some parts of the analog block to be connected to the digital block of another device. Switch MFOutSel in the TxSelReg register can be used to measure MIFARE and ISO/IEC14443 ISO/IEC14443 A related signals. This is especially important during the design-in phase or for testing purposes as it enables checking of the transmitted and received data. The most important use of pins MFIN and MFOUT is found in the active antenna concept. An external active antenna circuit can be connected to the MFRC523 MFRC523's digital block. Switch MFOutSel must be configured so that the internal Miller encoded signal is sent to pin MFOUT (MFOutSel = 100b). UARTSel[1:0] must be configured to receive a Manchester signal with subcarrier from pin MFIN (UARTSel[1:0] = 01). It is possible to connect a passive antenna to pins TX1, TX2 and RX (using the appropriate filter and matching circuit) and an active antenna to pins MFOUT and MFIN at the same time. In this configuration, two RF circuits can be driven (one after another) by a single host processor. Remark: Pins MFIN and MFOUT have a dedicated supply on pin SVDD with the ground on pin PVSS. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 25 of 97 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors MFRC523 MFRC523_34 Product data sheet PUBLIC MFOUT Rev. 3.5 - 24 September 2010 115235 All information provided in this document is subject to legal disclaimers. TX bit stream 3-state LOW HIGH test bus internal envelope TX serial data stream reserved RX serial data stream MILLER CODER DIGITAL MODULE MFRC523 MFRC523 RX bit stream MANCHESTER DECODER UART Sel[1:0] 0 1 2 3 0 1 2 3 4 5 6 7 MFOutSel[3:0] 3-state internal envelope envelope from pin MFIN HIGH TX2 MODULATOR DRIVER TX1 ANALOG MODULE MFRC523 MFRC523 SUBCARRIER LOW DEMODULATOR Manchester with subcarrier internal modulated NRZ coding without subcarrier (> 106 kBd) DEMODULATOR MFIN RX 001aal161 MFRC523 MFRC523 Contactless reader IC © NXP B.V. 2010. All rights reserved. 26 of 97 Fig 21. Overview of MFIN and MFOUT signal routing 0 1 2 DRIVER 3 Sel[1:0] MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 8.4.5 CRC coprocessor The following CRC coprocessor parameters can be configured: · The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on the ModeReg register's CRCPreset[1:0] bits setting · The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1 · The CRCResultReg register indicates the result of the CRC calculation. This register is split into two 8-bit registers representing the higher and lower bytes. · The ModeReg register's MSB first bit indicates that data will be loaded with the MSB first. Table 18. CRC coprocessor parameters Parameter Value CRC register length 16-bit CRC CRC algorithm algorithm according to ISO/IEC 14443 A and ITU-T CRC preset value 0000h, 6363h, A671h or FFFFh depending on the setting of the ModeReg register's CRCPreset[1:0] bits 8.5 FIFO buffer An 8 × 64 bit FIFO buffer is used in the MFRC523 MFRC523. It buffers the input and output data stream between the host and the MFRC523 MFRC523's internal state machine. This makes it possible to manage data streams up to 64 bytes long without the need to take timing constraints into account. 8.5.1 Accessing the FIFO buffer The FIFO buffer input and output data bus is connected to the FIFODataReg register. Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO buffer write pointer. Reading from this register shows the FIFO buffer contents stored in the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance between the write and read pointer can be obtained by reading the FIFOLevelReg register. When the microcontroller starts a command, the MFRC523 MFRC523 can, while the command is in progress, access the FIFO buffer according to that command. Only one FIFO buffer has been implemented which can be used for input and output. The microcontroller must ensure that there are not any unintentional FIFO buffer accesses. 8.5.2 Controlling the FIFO buffer The FIFO buffer pointers can be reset by setting FIFOLevelReg register's FlushBuffer bit to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg register's BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer accessible allowing the FIFO buffer to be filled with another 64 bytes. 8.5.3 FIFO buffer status information The host can get the following FIFO buffer status information: · Number of bytes stored in the FIFO buffer: FIFOLevelReg register's FIFOLevel[6:0] · FIFO buffer almost full warning: Status1Reg register's HiAlert bit MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 27 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC · FIFO buffer almost empty warning: Status1Reg register's LoAlert bit · FIFO buffer overflow warning: ErrorReg register's BufferOvfl bit. The BufferOvfl bit can only be cleared by setting the FIFOLevelReg register's FlushBuffer bit. The MFRC523 MFRC523 can generate an interrupt signal when: · ComIEnReg register's LoAlertIEn bit is set to logic 1. It activates pin IRQ when Status1Reg register's LoAlert bit changes to logic 1. · ComIEnReg register's HiAlertIEn bit is set to logic 1. It activates pin IRQ when Status1Reg register's HiAlert bit changes to logic 1. If the maximum number of WaterLevel[5:0] bits (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to Equation 3: HiAlert = ( 64 ­ FIFOLength ) WaterLevel (3) If the number of WaterLevel[5:0] bits (as set in the WaterLevelReg register) or less are stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to Equation 4: LoAlert = FIFOLength WaterLevel (4) 8.6 Interrupt request system The MFRC523 MFRC523 indicates certain events by setting the Status1Reg register's IRq bit and, if activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its interrupt handling capabilities. This allows the implementation of efficient host software. 8.6.1 Interrupt sources overview Table 19 shows the available interrupt bits, the corresponding source and the condition for its activation. The ComIrqReg register's TimerIRq interrupt bit indicates an interrupt set by the timer unit which is set when the timer decrements from 1 to 0. The ComIrqReg register's TxIRq bit indicates that the transmitter has finished. If the state changes from sending data to transmitting the end of the frame pattern, the transmitter unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg register's CRCIRq bit after processing all the FIFO buffer data which is indicated by CRCReady bit = 1. The ComIrqReg register's RxIRq bit indicates an interrupt when the end of the received data is detected. The ComIrqReg register's IdleIRq bit is set if a command finishes and the Command[3:0] value in the CommandReg register changes to idle (see Table 148 on page 67). The ComIrqReg register's HiAlertIRq bit is set to logic 1 when the Status1Reg register's HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits. The ComIrqReg register's LoAlertIRq bit is set to logic 1 when the Status1Reg register's LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level indicated by the WaterLevel[5:0] bits. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 28 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC The ComIrqReg register's ErrIRq bit indicates an error detected by the contactless UART during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg. Table 19. Interrupt sources Interrupt flag Interrupt source Trigger action TimerIRq timer unit the timer counts from 1 to 0 TxIRq transmitter a transmitted data stream ends CRCIRq CRC coprocessor all data from the FIFO buffer has been processed RxIRq receiver a received data stream ends IdleIRq ComIrqReg register command execution finishes HiAlertIRq FIFO buffer the FIFO buffer is almost full LoAlertIRq FIFO buffer the FIFO buffer is almost empty ErrIRq contactless UART an error is detected 8.7 Timer unit The MFRC523A MFRC523A has a timer unit which the external host can use to manage timing tasks. The timer unit can be used in one of the following timer/counter configurations: · · · · · Timeout counter Watchdog counter Stop watch Programmable one shot Periodic trigger The timer unit can be used to measure the time interval between two events or to indicate that a specific event occurred after a specific time. The timer can be triggered by events explained in the paragraphs below. The timer does not influence any internal events, for example, a time-out during data reception does not automatically influence the reception process. In addition, several timer-related bits can be used to generate an interrupt. The timer has an input clock of 13.56 MHz derived from the 27.12 MHz quartz crystal oscillator. The timer consists of two stages: prescaler and counter. The prescaler (TPrescaler) is a 12-bit counter. The reload values (TReloadVal_Hi[7:0] and TReloadVal_Lo[7:0]) for TPrescaler can be set between 0 and 4095 in the TModeReg register's TPrescaler_Hi[3:0] bits and TPrescalerReg register's TPrescaler_Lo[7:0] bits. The reload value for the counter is defined by 16 bits between 0 and 65535 in the TReloadReg register. The current value of the timer is indicated in the TCounterValReg register. When the counter reaches 0, an interrupt is automatically generated, indicated by the ComIrqReg register's TimerIRq bit setting. If enabled, this event can be indicated on pin IRQ. The TimerIRq bit can be set and reset by the host. Depending on the configuration, the timer will stop at 0 or restart with the value set in the TReloadReg register. The timer status is indicated by the Status1Reg register's TRunning bit. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 29 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC The timer can be started manually using the ControlReg register's TStartNow bit and stopped using the ControlReg register's TStopNow bit. The timer can also be activated automatically to meet any dedicated protocol requirements, by setting the TModeReg register's TAuto bit to logic 1. The delay time of a timer stage is set by the reload value + 1. The total delay time (td) is calculated using Equation 5: ( TPrescaler × 2 + 1 ) × ( TReloadVal + 1 ) t d = -13.56 MHz (5) or if the TPrescalEven bit is set, using Equation 6: ( TPrescaler × 2 + 2 ) × ( TReloadVal + 1 ) t d = -13.56 MHz (6) An example of calculating total delay time (td) is shown in Equation 7, where the TPrescaler value = 4095 and TReloadVal = 65535: 39.59 s = ( 4095 × 2 + 1 ) × ( 65535 + 1 ) -13.56 MHz (7) Example: To give a delay time of 25 s requires 339 clock cycles to be counted and a TPrescaler value of 169. This configures the timer to count up to 65535 time-slots for every 25 s period. 8.8 Power reduction modes 8.8.1 Hard power-down Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current sinks including the oscillator. All digital input buffers are separated from the input pins and clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or LOW level. 8.8.2 Soft power-down mode Soft power-down mode is entered immediately after the CommandReg register's PowerDown bit is set to logic 1. All internal current sinks are switched off, including the oscillator buffer. However, the digital input buffers are not separated from the input pins and keep their functionality. The digital output pins do not change their state. During soft power-down, all register values, the FIFO buffer content and the configuration keep their current contents. After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately clear it. It is automatically cleared by the MFRC523 MFRC523 when Soft power-down mode is exited. Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to become stable. This is because the internal oscillator is supplied by VDDA and any clock cycles will not be detected by the internal logic until VDDA is stable. It is recommended for the serial UART, to first send the value 55h to the MFRC523 MFRC523. The oscillator must be stable MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 30 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC for further access to the registers. To ensure this, perform a read access to address 0 until the MFRC523 MFRC523 answers to the last read command with the register content of address 0. This indicates that the MFRC523 MFRC523 is ready. 8.8.3 Transmitter Power-down mode The Transmitter Power-down mode switches off the internal antenna drivers and the RF field. Transmitter Power-down mode is entered by setting either the TxControlReg register's Tx1RFEn bit or Tx2RFEn bit to logic 0. 8.9 Oscillator circuit MFRC523 MFRC523 OSCOUT OSCIN 27.12 MHz 001aal162 Fig 22. Quartz crystal connection The clock applied to the MFRC523 MFRC523 provides a time basis for the synchronous system's encoder and decoder. The stability of the clock frequency is an important factor for correct operation. To obtain optimum performance, clock jitter must be reduced as much as possible. This is best achieved using the internal oscillator buffer with the recommended circuitry. If an external clock source is used, the clock signal must be applied to pin OSCIN. In this case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock quality has been verified. 8.10 Reset and oscillator start-up time 8.10.1 Reset timing requirements The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset, the signal must be LOW for at least 100 ns. 8.10.2 Oscillator start-up time If the MFRC523 MFRC523 has been set to a Power-down mode or is powered by a VDDX supply, the start-up time for the MFRC523 MFRC523 depends on the oscillator used and is shown in Figure 23. The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator start-up time is defined by the crystal. The time (td) is the internal delay time of the MFRC523 MFRC523 when the clock signal is stable before the MFRC523 MFRC523 can be addressed. MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 31 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC The delay time is calculated by: 1024 t d = - = 37.74 s 27 s (8) The time (tosc) is the sum of td and tstartup. device activation oscillator clock stable clock ready tstartup td tosc t 001aak596 Fig 23. Oscillator start-up time 9. MFRC523 MFRC523 registers 9.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle, bits with same behavior are grouped in common registers. The access conditions are described in Table 20. Table 20. Behavior of register bits and their designation Abbreviation Behavior Description R/W D These bits can be written and read by the microcontroller. Nevertheless, they can also be written automatically by internal state machines, for example the CommandReg register changes its value automatically after the execution of the command. read only These register bits hold values which are determined by internal states only, for example the CRCReady bit cannot be written externally but shows internal states. W write only Reading these register bits always returns zero. reserved - Registers which are indicated as being reserved must not be changed. However, in the case of a write access, it is recommended that 0 is always written. - Product data sheet PUBLIC dynamic R MFRC523 MFRC523_34 read and write These bits can be written and read by the microcontroller. Since they are used only for control purposes, their content is not influenced by internal state machines, for example the ComIEnReg register can be written and read by the microcontroller. It will also be read by internal state machines but never changed by them. Registers which are indicated as being reserved for future use or are for production tests must not be changed. All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 32 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 9.1.1 MFRC523 MFRC523 register overview Table 21. MFRC523 MFRC523 register overview Subaddress (Hex) Register name Function Refer to Page 0: Command and status 00h Reserved reserved for future use Table 22 on page 36 01h CommandReg starts and stops command execution Table 24 on page 36 02h ComlEnReg enable and disable interrupt request control bits Table 26 on page 37 03h DivlEnReg enable and disable interrupt request control bits Table 28 on page 37 04h ComIrqReg interrupt request bits Table 30 on page 38 05h DivIrqReg interrupt request bits Table 32 on page 39 06h ErrorReg error bits showing the error status of the last command executed Table 34 on page 39 07h Status1Reg communication status bits Table 34 on page 39 08h Status2Reg receiver and transmitter status bits Table 36 on page 40 09h FIFODataReg input and output of 64 byte FIFO buffer Table 38 on page 41 0Ah FIFOLevelReg number of bytes stored in the FIFO buffer Table 40 on page 41 0Bh WaterLevelReg level for FIFO underflow and overflow warning Table 42 on page 42 0Ch ControlReg miscellaneous control registers Table 44 on page 42 0Dh BitFramingReg adjustments for bit-oriented frames Table 46 on page 43 0Eh CollReg bit position of the first bit-collision detected on the RF interface Table 48 on page 43 0Fh Reserved reserved for future use Table 50 on page 44 Page 1: Command 10h Reserved reserved for future use Table 52 on page 44 11h ModeReg defines general modes for transmitting and receiving Table 54 on page 45 12h TxModeReg defines transmission data rate and framing Table 56 on page 46 13h RxModeReg defines reception data rate and framing Table 58 on page 46 14h TxControlReg controls the antenna driver pins TX1 and TX2 Table 60 on page 47 15h TxASKReg controls the setting of the transmission modulation Table 62 on page 48 16h TxSelReg selects the internal sources for the antenna driver Table 64 on page 48 17h RxSelReg selects internal receiver settings Table 66 on page 49 18h RxThresholdReg selects thresholds for the bit decoder Table 68 on page 50 19h DemodReg defines demodulator settings Table 70 on page 50 1Ah Reserved reserved for future use Table 72 on page 51 1Bh Reserved reserved for future use Table 74 on page 51 1Ch MfTxReg controls MIFARE communication transmit parameters Table 76 on page 51 1Dh MfRxReg controls MIFARE communication receive parameters Table 78 on page 52 1Eh TypeBReg controls the ISO/IEC 14443 B functionality Table 80 on page 52 1Fh SerialSpeedReg selects the speed of the serial UART interface Table 82 on page 53 MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 33 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 21. MFRC523 MFRC523 register overview .continued Subaddress (Hex) Register name Function Refer to Page 2: Configuration 20h Reserved reserved for future use Table 84 on page 54 21h CRCResultReg shows the MSB and LSB values of the CRC calculation Table 86 on page 54 22h CRCResultReg shows the MSB and LSB values of the CRC calculation Table 88 on page 54 23h Reserved reserved for future use Table 90 on page 55 24h ModWidthReg controls the ModWidth setting Table 92 on page 55 25h Reserved reserved for future use Table 94 on page 55 26h RFCfgReg configures the receiver gain Table 96 on page 56 27h GsNReg selects the conductance of the antenna driver pins TX1 and TX2 for modulation Table 98 on page 56 28h CWGsPReg defines the conductance of the p-driver output when not active Table 100 on page 57 29h ModGsPReg defines the conductance of the p-driver output during modulation Table 102 on page 57 2Ah TModeReg defines settings for the internal timer 2Bh TPrescalerReg 2Ch TReloadReg defines the 16-bit timer reload value Table 108 on page 59 2Dh TReloadReg defines the 16-bit timer reload value Table 110 on page 59 2Eh TCounterValReg shows the 16-bit timer value Table 112 on page 59 2Fh TCounterValReg shows the 16-bit timer value Table 114 on page 60 Table 104 on page 57 Table 106 on page 58 Page 3: Test register 30h Reserved reserved for future use Table 116 on page 60 31h TestSel1Reg general test signal configuration Table 118 on page 60 32h TestSel2Reg general test signal configuration and PRBS control Table 120 on page 61 33h TestPinEnReg enables pin output driver on pins D1 to D7 Table 122 on page 61 34h TestPinValueReg defines the values for D1 to D7 when it is used as an I/O bus Table 124 on page 62 35h TestBusReg shows the status of the internal test bus Table 126 on page 62 36h AutoTestReg controls the digital self-test Table 128 on page 62 37h VersionReg shows the software version Table 130 on page 63 38h AnalogTestReg controls the pins AUX1 and AUX2 Table 132 on page 63 39h TestDAC1Reg defines the test value for TestDAC1 Table 134 on page 65 MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 34 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 21. MFRC523 MFRC523 register overview .continued Subaddress (Hex) Register name Function Refer to 3Ah TestDAC2Reg defines the test value for TestDAC2 Table 136 on page 65 3Bh TestADCReg shows the value of ADC I-channel and Q-channel Table 138 on page 65 3Ch to 3Fh Reserved reserved for production tests Table 140 to Table 146 on page 66 MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 35 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 9.2 Register descriptions 9.2.1 Page 0: Command and status 9.2.1.1 Reserved register 00h Functionality is reserved for future use. Table 22. Reserved register (address 00h); reset value: 00h bit allocation Bit 7 6 5 4 3 Symbol 0 - Table 23. Bit Reserved register bit descriptions Symbol Value Description 7 to 0 reserved 9.2.1.2 1 reserved Access 2 - reserved for future use CommandReg register Starts and stops command execution. Table 24. CommandReg register (address 01h); reset value: 20h bit allocation Bit 7 6 5 4 3 2 1 Symbol: 00 RcvOff PowerDown Command[3:0] Access: - R/W D 0 D Table 25. Bit CommandReg register bit descriptions Symbol Value Description 7 to 6 00 0 reserved 5 RcvOff 1 analog part of the receiver is switched off 4 PowerDown 1 Soft Power-down mode entered 0 MFRC523 MFRC523 starts the wake up procedure during which this bit is read as a logic 1; it is read as a logic 0 when the MFRC523 MFRC523 is ready; see Section 8.8.2 on page 30 Remark: The PowerDown bit cannot be set when the SoftReset command is activated 3 to 0 Command[3:0] - MFRC523 MFRC523_34 Product data sheet PUBLIC activates a command based on the Command value; reading this register shows which command is executed; see Section 10.3 on page 67 All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 36 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 9.2.1.3 ComIEnReg register Control bits to enable and disable the passing of interrupt requests. Table 26. ComIEnReg register (address 02h); reset value: 80h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol IRqInv TxIEn RxIEn IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn Access R/W R/W R/W R/W R/W R/W R/W R/W Table 27. ComIEnReg register bit descriptions Bit Symbol Value Description 7 1 signal on pin IRQ is inverted with respect to the Status1Reg register's IRq bit 0 signal on pin IRQ is equal to the IRq bit; in combination with the DivIEnReg register's IRqPushPull bit, the default value of logic 1 ensures that the output level on pin IRQ is 3-state IRqInv 6 - allows the transmitter interrupt request (TxIRq bit) to be propagated to pin IRQ 5 RxIEn - allows the receiver interrupt request (RxIRq bit) to be propagated to pin IRQ 4 IdleIEn - allows the idle interrupt request (IdleIRq bit) to be propagated to pin IRQ 3 HiAlertIEn - allows the high alert interrupt request (HiAlertIRq bit) to be propagated to pin IRQ 2 LoAlertIEn - allows the low alert interrupt request (LoAlertIRq bit) to be propagated to pin IRQ 1 ErrIEn - allows the error interrupt request (ErrIRq bit) to be propagated to pin IRQ 0 9.2.1.4 TxIEn TimerIEn - allows the timer interrupt request (TimerIRq bit) to be propagated to pin IRQ DivIEnReg register Control bits to enable and disable the passing of interrupt requests. Table 28. DivIEnReg register (address 03h); reset value: 00h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol IRQPushPull reserved MfinActIEn reserved CRCIEn reserved Access R/W - R/W - R/W - Table 29. DivIEnReg register bit descriptions Bit Symbol Value Description 7 IRQPushPull 1 pin IRQ is a standard CMOS output pin 0 pin IRQ is an open-drain output pin 6 to 5 reserved - reserved for future use 4 - allows the MFIN active interrupt request to be propagated to pin IRQ MfinActIEn 3 Product data sheet PUBLIC - reserved for future use CRCIEn - allows the CRC interrupt request, indicated by the DivIrqReg register's CRCIRq bit, to be propagated to pin IRQ 1 to 0 reserved MFRC523 MFRC523_34 reserved 2 - reserved for future use All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 37 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 9.2.1.5 ComIrqReg register Interrupt request bits. Table 30. ComIrqReg register (address 04h); reset value: 14h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol Set1 TxIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq ErrIRq TimerIRq Access W D D D D D D D Table 31. ComIrqReg register bit descriptions All bits in the ComIrqReg register are cleared by software. Bit Symbol Value Description 7 1 indicates that the marked bits in the ComIrqReg register are set 0 indicates that the marked bits in the ComIrqReg register are cleared Set1 6 TxIRq 1 set immediately after the last bit of the transmitted data was sent out 5 RxIRq 1 receiver has detected the end of a valid data stream if the RxModeReg register's RxNoErr bit is set to logic 1, the RxIRq bit is only set to logic 1 when data bytes are available in the FIFO 4 IdleIRq 1 if a command terminates, for example, when the CommandReg changes its value from any command to the Idle command (see Table 148 on page 67) if an unknown command is started, the CommandReg register Command[3:0] value changes to the idle state and the IdleIRq bit is set the microcontroller starting the Idle command does not set the IdleIRq bit 3 HiAlertIRq 1 the Status1Reg register's HiAlert bit is set the HiAlertIRq bit stores this event and can only be reset as indicated by the Set1 bit in this register 2 LoAlertIRq 1 Status1Reg register's LoAlert bit is set the LoAlertIRq bit stores this event and can only be reset as indicated by the Set1 bit in this register 1 Product data sheet PUBLIC 1 any error bit in the ErrorReg register is set 0 MFRC523 MFRC523_34 ErrIRq TimerIRq 1 the timer decrements the timer value in register TCounterValReg to zero All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 38 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 9.2.1.6 DivIrqReg register Interrupt request bits. Table 32. DivIrqReg register (address 05h); reset value: x0h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol Set2 reserved MfinActIRq reserved CRCIRq reserved Access W - D - D - Table 33. DivIrqReg register bit descriptions All bits in the DivIrqReg register are cleared by software. Bit Symbol Value Description 7 Set2 1 indicates that the marked bits in the DivIrqReg register are set 0 indicates that the marked bits in the DivIrqReg register are cleared - reserved for future use 6 to 5 reserved 4 MFIN is active; this interrupt is set when either a rising or falling signal edge is detected 3 reserved - reserved for future use 2 CRCIRq 1 the CalcCRC command is active and all data is processed 1 to 0 reserved 9.2.1.7 MfinActIRq 1 - reserved for future use Status1Reg register Contains status bits of the CRC, interrupt and FIFO buffer. Table 34. Status1Reg register (address 07h); reset value: 21h bit allocation Bit 7 Symbol 5 reserved CRCOk CRCReady Access Table 35. 6 - R 4 IRq R 3 2 TRunning reserved R R - 1 0 HiAlert LoAlert R R Status1Reg register bit descriptions Bit Symbol Value Description 7 reserved - reserved for future use 6 CRCOk 1 the CRC result is zero the CRCOk bit is undefined for data transmission and reception: use the ErrorReg register's CRCErr bit indicates the status of the CRC coprocessor, during calculation the value changes to logic 0, when the calculation is done correctly the value changes to logic 1 5 CRCReady 1 the CRC calculation has finished; only valid for the CRC coprocessor calculation using the CalcCRC command 4 IRq - indicates if any interrupt source requests attention with respect to the setting of the interrupt enable bits: see the ComIEnReg and DivIEnReg registers 3 TRunning 1 MFRC523 MFRC523's timer unit is running, i.e. the timer will decrement the TCounterValReg register with the next timer clock Remark: in gated mode, the TRunning bit is set to logic 1 when the timer is enabled by TModeReg register's TGated[1:0] bits; this bit is not influenced by the gated signal MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 39 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 35. Status1Reg register bit descriptions .continued Bit Symbol Value Description 2 reserved - reserved for future use 1 HiAlert 1 the alert level for the number of bytes in the FIFO buffer (FIFOLength[6:0]) is: HiAlert = ( 64 ­ FIFOLength ) WaterLevel otherwise value = logic 0 Example: FIFOLength = 60, WaterLevel = 4 then HiAlert = logic 1 FIFOLength = 59, WaterLevel = 4 then HiAlert = logic 0 0 LoAlert 1 the alert level for number of bytes in the FIFO buffer (FIFOLength[6:0]) is: LoAlert = FIFOLength WaterLevel otherwise value = logic 0 Example: FIFOLength = 4, WaterLevel = 4 then LoAlert = logic 1 FIFOLength = 5, WaterLevel = 4 then LoAlert = logic 0 9.2.1.8 Status2Reg register Contains status bits of the receiver, transmitter and data mode detector. Table 36. Status2Reg register (address 08h); reset value: 00h bit allocation Bit 7 6 Symbol TempSensClear I2CForceHS reserved MFCrypto1On ModemState[2:0] Access R/W R/W - D R Table 37. 5 4 3 2 1 0 Status2Reg register bit descriptions Bit Symbol Value Description 7 TempSensClear 1 clears the temperature error if the temperature is below the alarm limit of 125 °C 6 I2CForceHS I2C-bus input filter settings: 1 the I2C-bus input filter is set to the High-speed mode independent of the I2C-bus protocol 0 the I2C-bus input filter is set to the I2C-bus protocol used 5 to 4 Product data sheet PUBLIC - reserved 3 MFRC523 MFRC523_34 reserved MFCrypto1On - indicates that the MIFARE Crypto1 unit is switched on and all data communication with the card is encrypted; this bit is cleared by software; can only be set to logic 1 by a successful execution of the MFAuthent command only valid in Read/Write mode for MIFARE standard cards All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 40 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 37. Status2Reg register bit descriptions .continued Bit Symbol Value Description 2 to 0 ModemState[2:0] - shows the state of the transmitter and receiver state machines: 000 idle 001 wait for the BitFramingReg register's StartSend bit 010 TxWait: wait until RF field is present if the TModeReg register's TxWaitRF bit is set to logic 1. The minimum time for TxWait is defined by the TxWaitReg register 011 transmitting 100 RxWait: wait until RF field is present if the TModeReg register's TxWaitRF bit is set to logic 1. The minimum time for RxWait is defined by the RxWaitReg register 101 9.2.1.9 wait for data 110 receiving FIFODataReg register Input and output of 64 byte FIFO buffer. Table 38. Bit FIFODataReg register (address 09h); reset value: xxh bit allocation 7 6 5 4 3 Symbol 1 0 FIFOData[7:0] Access 2 D Table 39. Symbol 7 to 0 9.2.1.10 FIFODataReg register bit descriptions Bit FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer. FIFO buffer acts as parallel in/parallel out converter for all serial data stream inputs and outputs Description FIFOLevelReg register Indicates the number of bytes stored in the FIFO. Table 40. FIFOLevelReg register (address 0Ah); reset value: 00h bit allocation Bit 7 6 5 4 3 Symbol FlushBuffer W 1 0 FIFOLevel[6:0] Access 2 R Table 41. FIFOLevelReg register bit descriptions Bit Symbol Value Description 7 FlushBuffer 1 immediately clears the internal FIFO buffer's read and write pointer and ErrorReg register's BufferOvfl bit. Reading this bit always returns 0 - indicates the number of bytes stored in the FIFO buffer. Writing to the FIFODataReg register increments and reading decrements the FIFOLevel value 6 to 0 FIFOLevel[6:0] MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 41 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 9.2.1.11 WaterLevelReg register Defines the level for FIFO under- and overflow warning. Table 42. Bit WaterLevelReg register (address 0Bh); reset value: 08h bit allocation 7 6 5 4 3 2 1 Symbol reserved WaterLevel[5:0] Access - 0 R/W Table 43. WaterLevelReg register bit descriptions Bit Symbol Description 7 to 6 reserved reserved for future use 5 to 0 WaterLevel[5:0] defines a warning level to indicate a FIFO buffer overflow or underflow: Status1Reg register's HiAlert bit is set to logic 1 if the remaining number of bytes in the FIFO buffer space is equal to, or less than the defined number of WaterLevel[5:0] bits Status1Reg register's LoAlert bit is set to logic 1 if equal to, or less than the WaterLevel[5:0] bits in the FIFO buffer Remark: to calculate values for HiAlert and LoAlert, see Section 9.2.1.8 on page 40. 9.2.1.12 ControlReg register Miscellaneous control bits. Table 44. Bit ControlReg register (address 0Ch); reset value: 10h bit allocation 7 Symbol 6 TStopNow TStartNow Access W Table 45. 5 4 3 2 1 reserved RxLastBits[2:0] - 0 R W ControlReg register bit descriptions Bit Symbol Value Description 7 TStopNow 1 timer stops immediately 6 TStartNow 1 timer starts immediately. Reading this bit always returns it to 0 5 to 3 MFRC523 MFRC523_34 Product data sheet PUBLIC reserved - reserved for future use 2 to 0 RxLastBits[2:0] - indicates the number of valid bits in the last received byte. If this value is zero, the whole byte is valid All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 42 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 9.2.1.13 BitFramingReg register Adjustments for bit-oriented frames. Table 46. Bit BitFramingReg register (address 0Dh); reset value: 00h bit allocation 7 6 5 4 3 2 1 0 Symbol StartSend RxAlign[2:0] reserved TxLastBits[2:0] Access W R/W - R/W Table 47. BitFramingReg register bit descriptions Bit Symbol Value Description 7 StartSend 1 starts the transmission of data only valid in combination with the Transceive command 6 to 4 RxAlign[2:0] used for reception of bit-oriented frames: defines the bit position for the first bit received to be stored in the FIFO buffer example: 0 LSB of the received bit is stored at bit position 0, the second received bit is stored at bit position 1 1 LSB of the received bit is stored at bit position 1, the second received bit is stored at bit position 2 7 LSB of the received bit is stored at bit position 7, the second received bit is stored in the next byte that follows at bit position 0 These bits are only to be used for bitwise anticollision at 106 kBd, for all other modes they are set to 0 3 9.2.1.14 reserved - reserved for future use 2 to 0 TxLastBits[2:0] - used for transmission of bit oriented frames: defines the number of bits of the last byte that will be transmitted. 000b indicates that all bits of the last byte will be transmitted CollReg register Defines the first bit-collision detected on the RF interface. Table 48. CollReg register (address 0Eh); reset value: xxh bit allocation Bit 7 6 5 Symbol ValuesAfterColl reserved CollPosNotValid CollPos[4:0] Access R/W - R R Table 49. 4 3 2 1 0 CollReg register bit descriptions Bit Symbol Value Description 7 ValuesAfterColl 0 all received bits will be cleared after a collision only used during bitwise anticollision at 106 kBd, otherwise it is set to logic 1 6 Product data sheet PUBLIC - reserved for future use 5 MFRC523 MFRC523_34 reserved CollPosNotValid 1 no collision detected or the position of the collision is out of the range of CollPos[4:0] All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 43 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 49. Bit CollReg register bit descriptions .continued Symbol Value Description 4 to 0 CollPos[4:0] - shows the bit position of the first detected collision in a received frame only data bits are interpreted example: 00h indicates a bit-collision in the 32nd bit 01h indicates a bit-collision in the 1st bit 08h indicates a bit-collision in the 8th bit these bits will only be interpreted if the CollPosNotValid bit is set to logic 0 9.2.1.15 Reserved register 0Fh Functionality is reserved for future use. Table 50. Bit Reserved register (address 0Fh); reset value: 00h bit allocation 7 6 5 4 3 Symbol 1 0 1 0 reserved Access 2 - Table 51. Reserved register bit descriptions Bit Symbol Description 7 to 0 reserved reserved for future use 9.2.2 Page 1: Communication 9.2.2.1 Reserved register 10h Functionality is reserved for future use. Table 52. Bit Reserved register (address 10h); reset value: 00h bit allocation 7 6 5 4 3 Symbol reserved Access - Table 53. Reserved register bit descriptions Bit Product data sheet PUBLIC Symbol Description 7 to 0 MFRC523 MFRC523_34 2 reserved reserved for future use All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 44 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 9.2.2.2 ModeReg register Defines general mode settings for transmitting and receiving. Table 54. Bit ModeReg register (address 11h); reset value: 3Fh bit allocation 7 Symbol 6 5 4 MSBFirst reserved TxWaitRF reserved Access R/W Table 55. - R/W 3 2 PolMFin reserved CRCPreset[1:0] R/W - R/W - 1 0 ModeReg register bit descriptions Bit Symbol Value Description 7 MSBFirst 1 CRC coprocessor calculates the CRC with MSB first. In the CRCResultReg register the values for the CRCResultMSB[7:0] bits and the CRCResultLSB[7:0] bits are bit reversed Remark: during RF communication this bit is ignored 6 reserved - reserved for future use 5 TxWaitRF 1 transmitter can only be started if an RF field is generated 4 reserved - reserved for future use 3 PolMFin defines the polarity of pin MFIN Remark: the internal envelope signal is encoded active LOW, changing this bit generates a MFinActIRq event 1 0 2 reserved 1 to 0 polarity of pin MFIN is active HIGH polarity of pin MFIN is active LOW CRCPreset [1:0] - reserved for future use defines the preset value for the CRC coprocessor for the CalcCRC command Remark: during any communication, the preset values are selected automatically according to the definition of bits in the RxModeReg and TxModeReg registers 00 A671h 11 Product data sheet PUBLIC 6363h 10 MFRC523 MFRC523_34 0000h 01 FFFFh All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 45 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC 9.2.2.3 TxModeReg register Defines the data rate during transmission. Table 56. Bit TxModeReg register (address 12h); reset value: 00h bit allocation 7 6 5 4 3 2 1 0 Symbol TxCRCEn TxSpeed[2:0] InvMod TxFraming Access R/W D R/W D Table 57. TxModeReg register bit descriptions Bit Symbol Value Description 7 TxCRCEn 1 enables CRC generation during data transmission Remark: can only be set to logic 0 at 106 kBd 6 to 4 TxSpeed[2:0] defines the bit rate during data transmission the MFRC523 MFRC523 handles transfer speeds up to 848 kBd 000 001 848 kBd 100 reserved 101 reserved 110 reserved 111 2 to 0 424 kBd 011 InvMod 212 kBd 010 3 106 kBd reserved 1 modulation of transmitted data is inverted TxFraming[1:0] defines the framing used for data transmission 00 reserved 10 reserved 11 9.2.2.4 ISO/IEC 14443 A/MIFARE 01 ISO/IEC 14443 B RxModeReg register Defines the data rate during reception. Table 58. Bit RxModeReg register (address 13h); reset value: 00h bit allocation 7 6 5 4 3 2 1 0 Symbol RxCRCEn RxSpeed[2:0] RxNoErr RxMultiple RxFraming Access R/W D R/W R/W D Table 59. RxModeReg register bit descriptions Bit Symbol Value Description 7 RxCRCEn 1 enables the CRC calculation during reception Remark: can only be set to logic 0 at 106 kBd MFRC523 MFRC523_34 Product data sheet PUBLIC All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 46 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 59. RxModeReg register bit descriptions .continued Bit Symbol 6 to 4 RxSpeed[2:0] Value Description defines the bit rate while receiving data. The MFRC523 MFRC523 manages transfer speeds up to 848 kBd 000 106 kBd 001 212 kBd 010 424 kBd 011 848 kBd 100 reserved 101 reserved 110 reserved 111 reserved 3 RxNoErr 1 an invalid received data stream (less than 4 bits received) will be ignored and the receiver remains active 2 RxMultiple 0 receiver is deactivated after receiving a data frame 1 able to receive more than one data frame only valid for data rates above 106 kBd in order to handle the polling command after setting this bit, the Receive and Transceive commands will not terminate automatically. Multiple reception can only be deactivated by writing any command (except the Receive command) to the CommandReg register, or by the host clearing the bit if set to logic 1, an error byte is added to the FIFO buffer at the end of a received data stream which is a copy of the ErrorReg register value 1 to 0 RxFraming defines the expected framing for data reception 00 01 reserved 10 reserved 11 9.2.2.5 ISO/IEC 14443 A/MIFARE ISO/IEC 14443 B TxControlReg register Controls the logical behavior of the antenna driver pins TX1 and TX2. Table 60. TxControlReg register (address 14h); reset value: 80h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol InvTx2RF InvTx1RF InvTx2RF InvTx1RF Tx2CW reserved Tx2RFEn Tx1RFEn On On Off Off Access Table 61. R/W R/W R/W R/W R/W - R/W TxControlReg register bit descriptions Bit Symbol Value Description 7 output signal on pin TX2 inverted when driver TX2 is enabled InvTx1RFOn 1 output signal on pin TX1 inverted when driver TX1 is enabled 5 InvTx2RFOff 1 output signal on pin TX2 inverted when driver TX2 is disabled 4 Product data sheet PUBLIC InvTx2RFOn 1 6 MFRC523 MFRC523_34 R/W InvTx1RFOff 1 output signal on pin TX1 inverted when driver TX1 is disabled All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 47 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 61. TxControlReg register bit descriptions .continued Bit Symbol Value Description 3 1 output signal on pin TX2 continuously delivers the unmodulated 13.56 MHz energy carrier 0 Tx2CW bit is enabled to modulate the 13.56 MHz energy carrier Tx2CW 2 - reserved for future use Tx2RFEn 1 output signal on pin TX2 delivers the 13.56 MHz energy carrier modulated by the transmission data 0 9.2.2.6 reserved 1 Tx1RFEn 1 output signal on pin TX1 delivers the 13.56 MHz energy carrier modulated by the transmission data TxASKReg register Controls transmit modulation settings. Table 62. Bit TxASKReg register (address 15h); reset value: 00h bit allocation 7 Symbol 6 5 Access - Table 63. 3 2 1 0 reserved R/W - TxASKReg register bit descriptions Bit Symbol Value Description 7 reserved - 6 Force100ASK 1 5 to 0 reserved 9.2.2.7 4 reserved Force100ASK reserved for future use forces 100 % ASK modulation independently of the ModGsPReg register setting - reserved for future use TxSelReg register Selects the internal sources for the analog module. Table 64. Bit TxSelReg register (address 16h); reset value: 10h bit allocation 7 6 5 4 3 2 1 Symbol: reserved DriverSel[1:0] MFOutSel[3:0] Access: - R/W 0 R/W Table 65. Bit TxSelReg register bit descriptions Symbol Value Description 7 to 6 reserved - reserved for future use 5 to 4 DriverSel[1:0] - selects the input of drivers TX1 and TX2 00 01 modulation signal (envelope) from pin MFIN 11 Product data sheet PUBLIC modulation signal (envelope) from the internal encoder, Miller pulse encoded 10 MFRC523 MFRC523_34 3-state; in soft power-down the drivers are only in 3-state mode if the DriverSel[1:0] value is set to 3-state mode HIGH; the HIGH level depends on the setting of bits InvTx1RFOn/InvTx1RFOff and InvTx2RFOn/InvTx2RFOff All information provided in this document is subject to legal disclaimers. Rev. 3.5 - 24 September 2010 115235 © NXP B.V. 2010. All rights reserved. 48 of 97 MFRC523 MFRC523 NXP Semiconductors Contactless reader IC Table 65. TxSelReg register bit descriptions .continued Bit Symbol 3 to 0 MFOutSel[3:0] Value Description selects the input for pin MFOUT 0000 3-state 0001 LOW 0010 test bus signal as defined by the TestSel1Reg register's TstBusBitSel[2:0] value 0100 modulation signal (envelope) from the internal encoder, Miller pulse encoded 0101 serial data stream to be transmitted, data stream before Miller encoder 0110 reserved 0111 serial data stream received, data stream after Manchester decoder 1000 to 111