MF1567-01 S1K70000 S1X70000 S1K70000/S1X70000 S1K/S1X70000 - Datasheet Archive

 

STANDARD CELL / EMBEDDED ARRAY S1K70000 / S1X70000 Series 5V Tolerant DESIGN GUIDE NOTICE No part of this material may be

 

MF1567-01 MF1567-01 STANDARD CELL / EMBEDDED ARRAY S1K70000 S1K70000 / S1X70000 S1X70000 Series 5V Tolerant DESIGN GUIDE NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. MS-DOS and Windows are registered trademarks of Microsoft Corporation, U.S.A. PC/AT, PS/2, PC-DOS, VGA, EGA and IBM are registered trademarks of International Business Machines Corporation, U.S.A. Verilog-XL is a registered trademark of Cadence Design Systems Corporation, U.S.A. VSS is a registered trademark of Synopsys of INC., U.S.A. ModelSim is a registered trademark of Model Technology Corp., U.S.A. All other product names mentioned herein are trademarks and/or registered trademarks of their respective owners. ©SEIKO EPSON CORPORATION 2003, All rights reserved. Configuration of product number DEVICES S1 K 70843 F 00A0 00 Packing specifications (*3) Specifications Shape (*2) Model number Model name (*1) Product classification (S1:semiconductors) *1: Model name K Standard Cell L Gate Array X Embedded Array *2: Shape B Assembled on board, COB, BGA C Plastic DIP D Bare Chip F Plastic QFP H Ceramic DIP L Ceramic QFP 3: Packing Specifications 14th 15th Packing Specifications 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 A B C D E F G H J K L M N P Q R 9 Besides tape & reel TCP BL 2 directions Tape & reel Back TCP BR 2 directions TCP BT 2 directions TCP BD 2 directions Tape & reel FRONT TCP BT 4 directions TCP BD 4 directions TCP SL 2 directions TCP SR 2 directions Tape & reel LEFT TCP ST 2 directions TCP SD 2 directions TCP ST 4 directions TCP SD 4 directions Tape & reel RIGHT Specs not fixed M R T 2 3 Plastic SOP TAB­QFP Tape Carrier (TAB) TSOP (Standard Bent) TSOP (Reverse Bent) Table of Contents S1K70000 S1K70000 Series Table of Contents Chapter 1 Overview . 1 1.1 1.2 1.3 1.4 Features . 1 1.1.1 Outline of the S1K70000 S1K70000 Series .1 1.1.2 Internal Structure of the S1K70000 S1K70000 Series.3 1.1.3 Structure and Types of MSIs .3 1.1.4 Structure of the 5-V Tolerant Fail-Safe Cell .4 Electrical Characteristics and Specifications . 4 1.2.1 When Using 3.3-V Input/Output Buffers .4 Estimating the Quiescent Current . 11 1.3.1 Quiescent Current in the Random Logic Part (IQBC) .11 1.3.2 Quiescent Current of Basic Cell-Type RAM (IQBM).11 1.3.3 Quiescent Current of Cell Based-Type RAM (IQCM) .12 1.3.4 Quiescent Current of Input/Output Buffers (IQIO).12 1.3.5 Temperature Characteristics of Quiescent Current.14 Product Development Flow . 15 Chapter 2 Estimating the Gate Density. 17 2.1 2.2 2.3 Dividing Up Logic Between Chips . 17 Determining Gate Size . 18 2.2.1 Estimating Bulk from the Number of Pads .18 2.2.2 Estimating the Number of Gates Used in Basic Cell-Type MSI Cell .19 2.2.3 Estimating the Number of Gates Used in Cell Based-Type MSI Cell.22 2.2.4 Estimating the Number of Gates Used in Basic Cell-Type RAM.24 2.2.5 Estimating the Number of Gates Used in Cell Based-Type RAM .24 2.2.6 Estimating Bulk from the Implemented Circuit Size .24 Estimating the Number of Input/Output Pins. 24 Chapter 3 MSI Cells. 25 3.1 3.2 Naming Rules for MSI . 25 MSI Cell Types . 26 Chapter 4 Types of Input/Output Buffers and Their Use. 28 4.1 4.2 4.3 Selecting Input/Output Buffers . 28 4.1.1 Naming Rules for Input/Output Buffers.28 4.1.2 Bus-Hold Circuit.29 Dual-Power-Supply Input/Output Buffers. 30 4.2.1 Input Buffers .30 4.2.2 Output Buffers.32 4.2.3 Bi-directional Buffers .36 4.2.4 Fail Safe Cells.41 4.2.5 Gated Cells .44 4.2.6 Cutoff Cells .45 4.2.7 5-V Tolerant Fail-Safe Cells .47 Dual Power Supplies Guidelines. 50 4.3.1 Method of Adapting to Dual Power Supplies.50 4.3.2 Power Supplies for Dual Power Operation.50 4.3.3 Turning On/Off Dual Power Supplies .51 4.3.4 Interfacing with External Devices .51 Chapter 5 Memory Blocks . 53 5.1 Basic Cell-Type RAM . 53 5.1.1 Features.53 5.1.2 Word/Bit Configurations of RAM and Cell Names.53 STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON i Table of Contents 5.2 5.3 5.4 5.5 5.6 5.7 5.1.3 RAM Sizes . 55 5.1.4 Functional Description . 56 5.1.5 Timing Charts. 60 5.1.6 Delay Parameters . 62 5.1.7 Power Consumption of RAM . 110 High-Density-Type 1-port RAM . 114 5.2.1 Features . 114 5.2.2 RAM Sizes . 114 5.2.3 Input Signals and Block Diagrams. 114 5.2.4 Truth Table of Device Operation. 116 5.2.5 Timing Charts. 117 5.2.6 Electrical Characteristics. 118 5.2.7 Power Consumption. 119 High-Density-Type Dual-Port RAM . 120 5.3.1 Features . 120 5.3.2 RAM Sizes . 120 5.3.3 Input Signals and Block Diagrams. 120 5.3.4 Truth Table of Device Operation. 123 5.3.5 Timing Charts. 125 5.3.6 Electrical Characteristics. 127 5.3.7 Power Consumption. 128 Large-Capacity-Type 1-port RAM . 129 5.4.1 Features . 129 5.4.2 RAM Sizes . 129 5.4.3 Input/Output Signals and Block Diagrams . 130 5.4.4 Truth Table of Device Operation. 131 5.4.5 Timing Charts. 133 5.4.6 Electrical Characteristics. 134 5.4.7 Power Consumption. 135 High-Density Large-Capacity-Type 1-port RAM. 136 5.5.1 Features . 136 5.5.2 RAM Sizes . 136 5.5.3 Input/Output Signals and Block Diagrams . 137 5.5.4 Truth Table of Device Operation. 138 5.5.5 Timing Charts. 140 5.5.6 Electrical Characteristics. 141 5.5.7 Power Consumption. 142 ROM . 143 5.6.1 Features . 143 5.6.2 ROM Sizes . 143 5.6.3 Input/Output Signals and Block Diagrams . 143 5.6.4 Truth Table of Device Operation. 144 5.6.5 Timing Charts. 145 5.6.6 Electrical Characteristics. 146 5.6.7 Power Consumption. 146 Access to Nonexistent Addresses Inhibited . 147 Chapter 6 Estimating Various Characteristic Values . 148 6.1 6.2 ii Calculation of Power Consumption . 148 6.1.1 Internal Cells (Pint) . 148 6.1.2 Input Buffers (Pi) . 150 6.1.3 Output Buffers (Po). 150 6.1.4 Example of Calculation of the Approximate Amount of Power Consumption. 151 6.1.5 Limitations on Power Consumption . 153 Propagation Delay Time. 155 6.2.1 Accuracy of the Propagation Delay Time . 155 6.2.2 Calculating the Propagation Delay Time . 155 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Table of Contents 6.3 6.4 6.2.3 Virtual Wiring Capacitance .156 6.2.4 Setup and Hold Times of the Flip-Flop (FF) .161 Input/Output Buffer Characteristics (Normal Cell). 164 6.3.1 Input Buffer Characteristics .164 6.3.2 Output Buffer Characteristics .171 Input/Output Buffer Characteristics (5-V Tolerant Fail-Safe Cells) . 206 6.4.1 Input Buffer Characteristics .206 6.4.2 Output Buffer Characteristics .206 Chapter 7 Circuit Design . 227 7.1 Basic Circuit Configuration. 227 7.1.1 Inserting Input/Output Buffers.227 7.1.2 Limitations on Logic Gate Output Load .227 7.1.3 Wired Logic Forbidden .227 7.1.4 Synchronized Design Recommended .228 7.2 Use of Differentiating Circuits Forbidden . 229 7.3 Clock Tree Synthesis . 230 7.3.1 Overview.230 7.3.2 Design Flow .231 7.3.3 Applying Clock Tree Synthesis.232 7.3.4 Limitations and Notes .234 7.3.5 Clock Tree Synthesis Checksheet.235 7.3.6 Attached Materials .237 7.4 Designing Fast-Operating Circuits . 241 7.5 Metastable State . 242 7.6 Configuration of the Internal Bus . 243 7.7 Preventing Contention with External Buses. 245 7.8 Oscillation Circuits. 246 7.8.1 Configuration of Oscillation Circuits.246 7.8.2 Notes Regarding the Use of Oscillation Circuits .248 7.9 Hazard Protection . 249 7.10 Restrictions and Constraints on VHDL/Verilog-HDL Netlist. 250 7.10.1 Common Restrictions and Constraints .250 7.10.2 Restrictions and Constraints for Verilog Netlist .251 7.10.3 Restrictions and Constraints on VHDL Netlist.252 7.10.4 Description of Oscillation Cell and AC/DC Test Circuit Cell L1TCIR2 .252 7.10.5 Clock Buffer Description .253 7.11 Pin Layout and Simultaneous Operation . 255 7.11.1 Estimating the Number of Power-Supply Pins .255 7.11.2 Simultaneous Operation and Adding Power Supplies.257 7.11.3 Cautions and Notes Regarding the Pin Layout .262 7.11.4 Example of the Recommended Pin Layout .268 7.12 About Power Supply Cutoff . 269 7.12.1 Cell Types Usable during Power Supply Cut-off .269 Chapter 8 Circuit Design that Takes Testability into Account . 272 8.1 8.2 8.3 8.4 Consideration Regarding Circuit Initialization . 272 Consideration Regarding Compressing the Test Patterns . 272 Test Circuit Which Simplifies DC and AC Testing . 273 8.3.1 Circuit Configuration When Output Buffers with a Test Circuit are Used.273 8.3.2 Circuit Configuration When Output Buffers without a Test Circuit are Used.278 RAM and ROM Test Circuit. 281 8.4.1 Basic-Cell-Type RAM .281 8.4.2 High-Density-Type 1-Port RAM .284 8.4.3 High-Density-Type Dual-Port RAM.285 8.4.4 Large-Capacity-Type RAM .285 8.4.5 Mask ROM.285 STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON iii Table of Contents 8.5 Memory BIST Design . 287 8.5.1 Outline of the Memory BIST Circuit Block . 287 8.5.2 Outline of the Memory-BIST-Circuit Test Sequence . 288 8.5.3 Types of Memory Suitable for Memory BIST. 289 8.5.4 Estimating the Memory BIST Circuit Size. 289 8.5.5 About Memory BIST Circuit Design . 290 8.5.6 Other . 292 8.6 Function Cell Test Circuits . 297 8.6.1 Test Circuit Structures . 297 8.6.2 Test Patterns. 297 8.6.3 Test Circuit Data . 298 8.7 Scan Design . 299 8.7.1 About the Scan Circuit . 299 8.7.2 Scan Design Flow . 300 8.7.3 Design Rules. 301 Scan Design Checksheet (1/2). 309 Scan Design Checksheet (2/2). 310 8.8 Boundary Scan Design. 311 8.8.1 Boundary-Scan Design Flow . 311 8.8.2 Instructions. 312 8.8.3 Estimating the Number of Gates. 312 8.8.4 Design Rules. 312 Chapter 9 Test Pattern Generation. 317 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 iv Testability Consideration . 317 Usable Waveform Modulations . 317 Constraints on Test Patterns. 318 9.3.1 Test Rate and Event Counts. 318 9.3.2 Input Delay. 318 9.3.3 Pulse Width . 318 9.3.4 Input Waveform Format . 318 9.3.5 Strobes. 319 Notes Regarding DC Testing . 319 Notes Regarding the Use of Oscillation Circuits . 321 Regarding AC Testing . 322 9.6.1 Constraints Regarding Measurement Events . 322 9.6.2 Constraints on the Measurement Location for AC Testing. 322 9.6.3 Constraints Regarding the Path Delay Which is Tested. 322 9.6.4 Other Constraints. 322 Test Patterns Constraints for Bi-directional Pins. 323 Notes on Device in a High-Impedance State . 323 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 1 Overview Chapter 1 Overview Epson's S1K70000 S1K70000 series consists of ultra-high-speed, super-integrated CMOS-type standard cells manufactured by the 0.18-µm process. The MSI (Basic Cell type) available in this series in particular may be chosen to create conventional embedded arrays. 1.1 1.1.1 Features Outline of the S1K70000 S1K70000 Series · Integration 55.3k gates/mm2 (Basic Cell type) 75.1k gates/mm2 (Cell-Based type) · Operating Speed Internal gates INV, F/O = 1, VDD = 1.8 V, Typ.Condition Type of Transistor Basic Cell Type Cell-Based Type Unit Standard 1 25.9 26.5 ps Standard 2 24.8 24.9 ps High-Performance 21.4 23.2 ps Low-Leakage TBD TBD ps Basic Cell Type Cell-Based Type Unit Standard 1 33.7 34.4 ps Standard 2 30.5 30.2 ps High-Performance 25.5 27.2 ps Low-Leakage TBD TBD ps Basic Cell Type Cell-Based Type Unit Standard 1 43.6 38.9 ps Standard 2 43.2 38.8 ps High-Performance 36.0 33.1 ps Low-Leakage TBD TBD ps Basic Cell Type Cell-Based Type Unit Standard 1 57.7 51.6 ps Standard 2 53.7 48.2 ps High-Performance 43.3 39.9 ps Low-Leakage TBD TBD ps INV, F/O = 1, VDD = 1.5 V, Typ.Condition Type of Transistor NA2, F/O = 1, VDD = 1.8 V, Typ.Condition Type of Transistor NA2, F/O = 1, VDD = 1.5 V, Typ.Condition Type of Transistor STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 1 Chapter 1 Overview Input buffers F/O = 2, Standard Wiring Load, Typ. Condition Operating Speed Voltage 3.3-V Input Buffer (HIBCTF) 5-V Input Buffer (HIFVTF) Unit 3.3 V/1.8 V 181 199 ps 2.5 V/1.8 V 193 222 ps Output buffers CL = 15pF, Typ.Condition Operating Speed Voltage 3.3-V Input Buffer (HOB3ATF) 5-V Input Buffer (HOF3ATF) Unit 3.3 V/1.8 V 1.51 1.71 ns 2.5 V/1.8 V 1.67 1.96 ns · Process 0.18 µm, 3/4/5/6-layered metalization · Interface Levels 3.3-V buffers LVCMOS-, LVTTL-compatible · Input Modes 3.3-V buffers LVCMOS, LVTTL, LVCMOS Schmitt PCI-3 V, Gated input, Fail Safe input 5-V tolerant Fail-Safe input May be provided with internal pull-up and pull-down resistors (two resistance values for each) · Output Modes Normal, 3-state, Bi-directional, and Fail Safe outputs 5-V tolerant Fail-Safe output · Drive Output 3.3-V buffers IOL = 2, 4, 8, or 12 mA selectable IOL = 1.5, 3, 6, or 9 mA selectable IOL = 1, 2, 4, or 6 mA selectable IOL = 0.75, 1.5,3, or 4.5 mA selectable · Memory (HVDD = 3.3 V) (HVDD = 2.5 V) (LVDD = 1.8 V) (LVDD = 1.5 V) Basic Cell-type RAM Synchronous, 1 port; Synchronous, 2 ports High-Density-type RAM Synchronous, 1 port; Synchronous, dual ports Large Capacity-type RAM Synchronous, 1 port ROM Synchronous · Built-in level shifter for operation with dual supply voltages Internal logic: Operates with low voltage Input/output buffers: Can be interfaced with high and low voltages 2 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 1 Overview 1.1.2 Internal Structure of the S1K70000 S1K70000 Series The S1K70000 S1K70000 series is constructed with an MSI cell area and an input/output buffer circuit area, as shown in Figure 1-1. RAM ROM Largecapacity RAM MSI cell area Input/output buffer circuit area Figure 1-1 Outline Structure of the S1K70000 S1K70000 Series Various MSI cells and memory blocks can be located in the MSI cell area, depending on the desired circuit. These cells can be interconnected in order to implement the desired circuit. The input/output buffer area contains input buffers, output buffers, bi-directional buffers, and power-supply cells. In this area, signals are exchanged between external circuits and the units of the S1K70000 S1K70000 series. 1.1.3 Structure and Types of MSIs The S1K70000 S1K70000 series is available in two types: Basic Cell-type MSI for E/A (embedded arrays) and Cell Based-type MSI for S/C (standard cells). Embedded arrays (E/A) excel in that they feature a short development period and allow circuit changes to be responded easily, while the standard cells (S/C) feature high integration and low power consumption. Either type can be selected in accordance with customer needs (however, these two types of MSIs cannot be used at the same time). Furthermore, four MSI libraries are available to choose from: a Standard 1 library suitable for low-leakage-current (quiescent current) applications, a Standard 2 library suitable for applications that require high-speed operation, a High-Performance library suitable for applications that require ultra-high-speed operation, and a Low-Leakage library suitable for ultra-low-leakage current (quiescent current) applications. This wide availability enables the selection of a library best suited to customer needs (however, these four libraries basically cannot be used in combination). Memory is also available in various types in addition to the Basic Cell-type RAM (Standard 1 type, High-Performance type, and Low-Leakage type). These include a highly integrated Cell Based-type RAM (with 1 port, 2 ports, or 1 large-capacity port, all of which are available only for the Standard 1 type) and a ROM (only for Standard 1). The most suitable memory type can be selected in accordance with customer needs. For details on MSI cell types, refer to Chapter 3, "MSI Cells." For details on memory, refer to Chapter 5, "Memory Block." STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 3 Chapter 1 Overview 1.1.4 Structure of the 5-V Tolerant Fail-Safe Cell The 5-V tolerant Fail-Safe cells in the S1K70000 S1K70000 series allow 5.0-V signals to be interfaced directly without the need for a dedicated power supply. Note, however, that if 5.0-V signals are to be interfaced in cut-off mode for reasons of the circuit structure, the following power supply specifications must be met. (1) If 5.0-V signals are applied while the power supply is not cut off HVDD/LVDD = 3.3 V/1.8 V, 3.3 V/1.5 V, 2.5 V/1.8 V, 2.5 V/1.5 V (2) If 5.0-V signals are applied while HVDD is cut off (LVDD cannot be cut off) HVDD/LVDD = 3.3 V/1.8 V, 2.5 V/1.8 V Refer to Chapter 4, "Types of Input/Output Buffers and Their Use," for details about the input/output buffers. 1.2 1.2.1 Electrical Characteristics and Specifications When Using 3.3-V Input/Output Buffers Table 1-1 Absolute Maximum Ratings (for Dual Power Supplies) (VSS = 0 [V]) Parameter Limits Unit HVDD*3 Power-Supply Voltage Symbol -0.3 to 4.0 LVDD*3 -0.3 to 2.5 HVI Output Voltage -0.3 to HVDD + 0.5 LVI -0.3 to LVDD + 0.5*2 HVO Input Voltage *1 -0.3 to HVDD + 0.5*1 LVO *2 -0.3 to LVDD + 0.5 Output Current/Pin IOUT ± 10 mA Storage Temperature TSTG -65 to 150 °C Notes *1: Possible to use -0.3 V to 4.0 V of N channel open drain bi-directional buffers and input buffers. For 5-V tolerant Fail-Safe cells, voltages ranging from -0.3 V to 5.5 V are allowable, provided that LVDD is 1.8 V. *2: Possible to use -0.3 V to 4.0 V of N channel open drain bi-directional buffers, input buffers, and Fail Safe cells. *3: HVDD LVDD 4 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 1 Overview Table 1-2 Recommended Operating Conditions (for Dual Power Supplies) (VSS = 0 [V]) Parameter Symbol Min. Typ. Max. Unit Power-Supply Voltage (High Voltage) HVDD 3.00 3.30 3.60 V Power-Supply Voltage (Low Voltage) LVDD 1.65 1.80 1.95 HVI VSS - HVDD*1 V VSS - *2 DD V 0 25 70*3 -40 25 85*4 Input Voltage LVI Ambient Temperature Ta LV °C Normal Input Rising Time tri - - 50 ns Normal Input Falling Time tfa - - 50 ns Schmitt Input Rising Time tri - - 5 ms Schmitt Input Falling Time tfa - - 5 ms Notes *1: Possible to use up to 3.6 V of N channel open drain bi-directional buffers and input buffers. For 5-V tolerant Fail-Safe cells, voltages up to 5.5 V are allowable, provided that LVDD is 1.8 V. *2: Possible to use up to 3.6 V of N channel open drain bi-directional buffers, input buffers, and Fail Safe cells. *3: The ambient temperature range is recommended for Tj = 0 to 85[°C]. *4: The ambient temperature range is recommended for Tj = -40 to 125[°C]. Table 1-3 Recommended Operating Conditions (for Dual Power Supplies) (VSS = 0 [V]) Parameter Symbol Min. Typ. Max. Unit Power-Supply Voltage (High Voltage) HVDD 3.00 3.30 3.60 V Power-Supply Voltage (Low Voltage) LVDD 1.40 1.50 1.60 HVI VSS - HVDD*1 V VSS - *2 DD V 0 25 70*3 -40 25 85*4 Input Voltage LVI LV °C Ambient Temperature Ta Normal Input Rising Time tri - - 50 ns Normal Input Falling Time tfa - - 50 ns Schmitt Input Rising Time tri - - 5 ms Schmitt Input Falling Time tfa - - 5 ms Notes *1: Possible to use up to 3.6 V of N channel open drain bi-directional buffers and input buffers. Please note, however, that 5-V tolerant Fail-Safe cells cannot be used in Fail-Safe mode under these voltage conditions. *2: Possible to use up to 3.6 V of N channel open drain bi-directional buffers, input buffers, and Fail Safe cells. *3: The ambient temperature range is recommended for Tj = 0 to 85[°C]. *4: The ambient temperature range is recommended for Tj = -40 to 125[°C]. STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 5 Chapter 1 Overview Table 1-4 Electrical Characteristics (HVDD = 3.3 V ± 0.3 V, VSS = 0 V, Ta = -40 to 85°C) Parameter Input Leakage Current Off State Leakage Current Input Leakage Current (5-V tolerant Fail-Safe cells) Off-State Leakage Current (5-V tolerant Fail-Safe cells) High Level Output Voltage (Normal cell) High Level Input Voltage (5-V tolerant Fail-Safe cells) Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Symbol ILI VOH VOH VOL PPD High Level Output Current *1 IOH3 6 -5 - 5 µA -10 - 10 µA -10 - 10 µA HVDD -0.4 - - V HVDD -1.0 - - V - - 0.4 V 2.2 1.4 0.6 0.3 2.0 - 1.8 - 25 50 25 50 -36 - 48 - - - - - - - - - - 50 100 50 100 - - - - - 0.8 2.7 1.8 - - 0.8 - 0.9 120 240 120 240 - -115 - 137 V V V V V k k k k - - -20 µA - - 17 µA -350 - - µA 300 - - µA - - 10 pF f = 1 MHz, HVDD = 0 V - - 10 pF f = 1 MHz, HVDD = 0 V - - 10 pF VIN = 5.5 V Pull-down Resistance Note Unit µA IOZF PPU Low Level Output Current *1 High Level Maintenance Current Low Level Maintenance Current High Level Reversal Current Low Level Reversal Current Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance Max. 5 VIN = 5.5 V Pull-up Resistance Low Level Input Voltage High Level Input Voltage Typ. - ILIF Low Level Input Voltage Hysteresis Voltage High Level Input Voltage Min. -5 IOZ VIH1 VIL1 VT1+ VT1VH1 VIH2 VIL2 VIH3 VIL3 High Level Input Voltage Low Level Input Voltage Conditions - - IOL3 IBHH IBHL IBHHO IBHLO CI CO CIO IOH = -2 mA (Type 1), -4 mA (Type 2) -8 mA (Type 3), -12 mA (Type 4) HVDD = Min. IOH = -2 mA (Type 1), -4 mA (Type 2) -8 mA (Type 3), -12 mA (type 4) HVDD = Min. IOL = 2 mA (Type 1), 4 mA (Type 2) 8 mA (Type 3), 12 mA (Type 4) HVDD = Min. LVCMOS Level, HVDD = Max. LVCMOS Level, HVDD = Min. LVCMOS Schmitt LVCMOS Schmitt LVCMOS Schmitt LVTTL Level, HVDD = Max LVTTL Level, HVDD = Min PCI Level, HVDD = Max PCI Level, HVDD = Min Type 1 VI = 0 V Type 2 Type 1 VI = HVDD Type 2 PCI VOH = 0.90 V, HVDD = Min. Response VOH = 2.52 V, HVDD = Max. PCI VOL = 1.80 V, HVDD = Min. Response VOL = 0.65 V, HVDD = Max. Bus Hold VIN = 2.0 V Response HVDD = Min. Bus Hold VIN = 0.8 V Response HVDD = Min. Bus Hold VIN = 0.8 V Response HVDD = Max. Bus Hold VIN = 2.0 V Response HVDD = Max. f = 1 MHz, HVDD = 0 V mA mA *1: Compliant with PCI Standard Rev. 2.2 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 1 Overview Table 1-5 Recommended Operating Conditions (for Dual Power Supplies) (VSS = 0 [V]) Parameter Symbol Min. Typ. Max. Unit Power-Supply Voltage (High Voltage) HVDD 2.30 2.50 2.70 V Power-Supply Voltage (Low Voltage) LVDD 1.65 1.80 1.95 HVI VSS - HVDD*1 V VSS - *2 DD V 0 25 70*3 -40 25 85*4 Input Voltage LVI Ambient Temperature Ta LV °C Normal Input Rising Time tri - - 50 ns Normal Input Falling Time tfa - - 50 ns Schmitt Input Rising Time tri - - 5 ms Schmitt Input Falling Time tfa - - 5 ms Notes *1: Possible to use up to 3.6 V of N channel open drain bi-directional buffers and input buffers. For 5-V tolerant Fail-Safe cells, voltages up to 5.5 V are allowable, provided that LVDD is 1.8 V. *2: Possible to use up to 3.6 V of N channel open drain bi-directional buffers, input buffers, and Fail Safe cells. *3: The ambient temperature range is recommended for Tj = 0 to 85[°C]. *4: The ambient temperature range is recommended for Tj = -40 to 125[°C]. Table 1-6 Recommended Operating Conditions (for Dual Power Supplies) (VSS = 0 [V]) Parameter Symbol Min. Typ. Max. Unit Power-Supply Voltage (High Voltage) HVDD 2.30 2.50 2.70 V Power-Supply Voltage (Low Voltage) LVDD 1.40 1.50 1.60 *1 DD V V HVI VSS - HV LVI Input Voltage VSS - LVDD*2 *3 0 Ambient Temperature Ta 25 70 -40 25 85*4 °C Normal Input Rising Time tri - - 50 ns Normal Input Falling Time tfa - - 50 ns Schmitt Input Rising Time tri - - 5 ms Schmitt Input Falling Time tfa - - 5 ms Notes *1: Possible to use up to 3.6 V of N channel open drain bi-directional buffers and input buffers. Please note, however, that 5-V tolerant Fail-Safe cells cannot be used in Fail-Safe mode under these voltage conditions. *2: Possible to use up to 3.6 V of N channel open drain bi-directional buffers, input buffers, and Fail Safe cells. *3: The ambient temperature range is recommended for Tj = 0 to 85[°C]. *4: The ambient temperature range is recommended for Tj = -40 to 125[°C]. STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 7 Chapter 1 Overview Table 1-7 Electrical Characteristics (HVDD = 2.5 V ± 0.2 V, VSS = 0 V, Ta = -40 to 85°C) Symbol Conditions Min. Typ. Max. Unit Input Leakage Current ILI - -5 - 5 µA Off State Leakage Current IOZ -5 - 5 µA -10 - 10 µA -10 - 10 µA - - V - - V - - 0.4 V Parameter Input Leakage Current (5-V tolerant Fail-Safe cells) Off-State Leakage Current (5-V tolerant Fail-Safe cells) High Level Output Voltage (Normal cell) High Level Input Voltage (5-V tolerant Fail-Safe cells) ILIF IOZF VOH - VIN = 5.5V VIN = 5.5V IOH = -1.5 mA (Type 1), -3 mA (Type 2) -6 mA (Type 3), -9 mA (Type 4) -0.4 HVDD = Min. VOH HVDD IOH -1.5 mA (Type 1), -3 mA (Type 2) HVDD -6 mA (Type 3), -9 mAType 4 -0.8 HVDD = Min. IOL = 1.5 mA (Type 1), 3 mA (Type 2) 6 mA (Type 3), 9 mA (Type 4) Low Level Output Voltage VOL High Level Input Voltage VIH1 LVCMOS Level, HVDD = Max. 1.7 - - V Low Level Input Voltage VIL1 LVCMOS Level, HVDD = Min. - - 0.7 High Level Input Voltage VT1+ LVCMOS Schmitt 0.8 - 1.9 V Low Level Input Voltage VT1- LVCMOS Schmitt 0.5 - 1.3 Hysteresis Voltage VH1 LVCMOS Schmitt 0.1 - V Type 1 35 70 175 k Pull-up Resistance PPU VI = 0 V Type 2 70 140 350 k Type 1 35 70 175 k PPD VI = HVDD Type 2 70 140 350 k High Level Maintenance Current IBHH Bus Hold Response VIN = 1.7 V HVDD = Min. - - -5 µA Low Level Maintenance Current IBHL Bus Hold Response VIN = 0.7 V HVDD = Min. - - 5 µA High Level Reversal Current IBHHO Bus Hold Response VIN = 0.7 V HVDD = Max. -280 - - µA Low Level Reversal Current IBHLO Bus Hold Response VIN = 1.7 V HVDD = Max. 240 - - µA f = 1 MHz, HVDD = 0 V - - 10 pF f = 1 MHz, HVDD = 0 V - - 10 pF f = 1 MHz, HVDD = 0 V - - 10 pF Pull-down Resistance HVDD = Min. Input Terminal Capacitance CI Output Terminal Capacitance CO Input/Output Terminal Capacitance CIO 8 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 1 Overview Table 1-8 Electrical Characteristics (LVDD = 1.8 V ± 0.15 V, VSS = 0 V, Ta = -40 to 85°C) Symbol Conditions Min. Typ. Max. Unit Input Leakage Current ILI - -5 - 5 µA Off State Leakage Current IOZ -5 - 5 µA - - V - - 0.4 V Parameter High Level Output Voltage VOH - IOH = -1 mA (Type 1), -2 mA (Type 2) -4 mA (Type 3), -6 mA (Type 4) VDD -0.4 VDD = Min. IOL = 1 mA (Type 1), 2 mA (Type 2) 4 mA (Type 3), 6 mA (Type 4) Low Level Output Voltage VOL High Level Input Voltage VIH1 LVCMOS Level, VDD = Max. 1.27 - - V Low Level Input Voltage VIL1 LVCMOS Level, VDD = Min. - - 0.57 High Level Input Voltage VT1+ LVCMOS Schmitt 0.6 - 1.4 V Low Level Input Voltage VT1- LVCMOS Schmitt 0.3 - 1.1 Hysteresis Voltage VH1 LVCMOS Schmitt 0.02 - - V Type 1 24 60 150 k Pull-up Resistance PPU VI = 0 V Type 2 48 120 300 k VI = VDD or LVDD Type 1 24 60 150 k PPD Type 2 48 120 300 k High Level Maintenance Current IBHH Bus Hold Response VIN = 1.27 V VDD = Min. - - -2 µA Low Level Maintenance Current IBHL Bus Hold Response VIN = 0.57 V VDD = Min. - - 2 µA High Level Reversal Current IBHHO Bus Hold Response VIN = 0.57 V VDD = Max. -100 - - µA Low Level Reversal Current IBHLO Bus Hold Response VIN = 1.27 V VDD = Max. 100 - - µA f = 1 MHz, VDD = 0 V - - 10 pF f = 1 MHz, VDD = 0 V - - 10 pF f = 1 MHz, VDD = 0 V - - 10 pF Pull-down Resistance VDD = Min. Input Terminal Capacitance CI Output Terminal Capacitance CO Input/Output Terminal Capacitance CIO STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 9 Chapter 1 Overview Table 1-9 Electrical Characteristics (LVDD = 1.8 V ± 0.15 V, VSS = 0 V, Ta = -40 to 85°C) Symbol Conditions Min. Typ. Max. Unit Input Leakage Current ILI - -5 - 5 µA Off State Leakage Current IOZ -5 - 5 µA - - V - - 0.4 V Parameter - VOH IOH = -0.75 mA (Type 1), -1.5 mA (Type 2) -3 mA (Type 3), -4.5 mA (Type 4) VDD VDD = Min. High Level Output Voltage -0.4 IOL = 0.75 mA (Type 1), 1.5 mA (Type 2) 3 mA (Type 3), 4.5 mA (Type 4) Low Level Output Voltage VOL High Level Input Voltage VIH1 LVCMOS Level, VDD = Max. 1.04 - - V Low Level Input Voltage VIL1 LVCMOS Level, VDD = Min. - - 0.49 High Level Input Voltage VT1+ LVCMOS Schmitt 0.5 - 1.1 V Low Level Input Voltage VT1- LVCMOS Schmitt 0.2 - 1.0 Hysteresis Voltage VH1 LVCMOS Schmitt 0.01 - - V Type 1 36 90 234 k Pull-up Resistance PPU VI = 0 V Type 2 72 180 468 k VI = VDD or LVDD Type 1 36 90 234 k PPD Type 2 72 180 468 k High Level Maintenance Current IBHH Bus Hold Response VIN = 1.04 V VDD = Min. - - -2 µA Low Level Maintenance Current IBHL Bus Hold Response VIN = 0.49 V VDD = Min. - - 2 µA High Level Reversal Current IBHHO Bus Hold Response VIN = 0.49 V VDD = Max. -80 - - µA Low Level Reversal Current IBHLO Bus Hold Response VIN = 1.04 V VDD = Max. 80 - - µA f = 1 MHz, VDD = 0 V - - 10 pF f = 1 MHz, VDD = 0 V - - 10 pF f = 1 MHz, VDD = 0 V - - 10 pF -65 to 150 - - - °C Pull-down Resistance VDD = Min. Input Terminal Capacitance CI Output Terminal Capacitance CO Input/Output Terminal Capacitance CIO Storage Temperature Tstg Notes *1: For N-channel open-drain bidirectional buffers and input buffers, as well as 5-V tolerant Fail-Safe cells, voltages ranging from -0.3 V to 3.0 V are allowable. 10 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 1 Overview 1.3 Estimating the Quiescent Current The quiescent current for cells in the S1K70000 S1K70000 series can be roughly estimated using the equation shown below. When calculating the quiescent current, please assume ambient temperature (Ta) = chip temperature (Tj). The quiescent current depends on the off current of each transistor. Because the quiescent current for the entire chip cannot easily be calculated simultaneously, divide the chip into several blocks in the calculation of the quiescent current, and use the sum total of all blocks as the chip's quiescent current. IDDS (Tj 85°C) IQBCIQBM IQCM IQIO 1.3.1 Quiescent Current in the Random Logic Part (IQBC) The S1K70000 S1K70000 series is available in two types of MSI cells: Basic Cell-type MSI cells, which are equivalent to the conventional gate-array type, and Cell Based-type MSI cells. The quiescent current is calculated differently for each type of MSI cell. Table 1-10 lists the quiescent-current values per 1k gate of each MSI cell type. Table 1-10 Quiescent Current per 1k Gate (VDD = 1.95 V, Tj = 85°C) Standard 1 Basic Cell Type Cell-Based Type 1.3.2 Standard 2 HighPerformance Low-Leakage Unit 1.06 x 10-6 3.14 x 10-5 6.38 x 10-4 2.95 x 10-8 A -7 -5 -4 -8 A 6.81 x 10 1.77 x 10 3.72 x 10 2.28 x 10 Quiescent Current of Basic Cell-Type RAM (IQBM) The quiescent-current values of the primary Basic Cell-type RAMs in the S1X70000 S1X70000 series are listed in Table 1-11. (For the quiescent-current values of RAMs not listed here, use the quiescent-current value of the RAM that is closest in structure to those RAMs. If more detailed information on quiescent-current values is required, please contact the sales division of Epson.) STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 11 Chapter 1 Overview Table 1-11 Quiescent-Current Values of Basic Cell-Type RAM for Each Transistor Type (Common to 1-port RAM and 2-Port RAM, VDD = 1.95 V, Tj = 85°C) Standard 1 64 Word 128 Word -6 192 Word -6 A 2.22 x 10 3.88 x 10 16 Bit 3.30 x 10-6 5.76 x 10-6 8.23 x 10-6 10.70 x 10-6 A 24 Bit -6 7.65 x 10 -6 10.94 x 10 -6 14.22 x 10 -6 A 9.54 x 10 -6 13.64 x 10 -6 17.74 x 10 -6 A 128 Word 192 Word 2.49 x 10 -3 3.56 x 10 -3 -3 5.43 x 10 -3 -6 32 Bit 5.44 x 10 7.18 x 10 Unit -6 8 Bit 4.37 x 10 5.53 x 10 256 Word -6 High-Performance 64 Word -3 8 Bit 1.42 x 10 -3 256 Word Unit 4.63 x 10 -3 A 7.07 x 10 -3 A 16 Bit 2.14 x 10 3.78 x 10 24 Bit 2.87 x 10-3 5.08 x 10-3 7.30 x 10-3 9.51 x 10-3 A 32 Bit -3 -3 -3 -3 A 3.59 x 10 6.38 x 10 9.16 x 10 11.95 x 10 Low-Leakage 64 Word 8 Bit 66.64 x 10 128 Word -9 -9 192 Word 117.35 x 10 -9 179.64 x 10 -9 256 Word 168.07 x 10 -9 257.97 x 10 -9 Unit 218.78 x 10 -9 A 336.29 x 10 -9 A 16 Bit 101.32 x 10 24 Bit 136.00 x 10-9 241.94 x 10-9 347.87 x 10-9 453.80 x 10-9 A 32 Bit -9 -9 -9 -9 A 1.3.3 170.69 x 10 304.23 x 10 437.77 x 10 571.31 x 10 Quiescent Current of Cell Based-Type RAM (IQCM) The quiescent-current values of the Cell Based-type RAMs and ROMs in the S1K70000 S1K70000 series vary depending on the word/bit structure. Therefore, please contact the sales division of Epson for details. 1.3.4 Quiescent Current of Input/Output Buffers (IQIO) The quiescent-current values flowing in input/output buffers can be roughly estimated by using the values listed in Table 1-12 for the calculation formula shown on the next page. (Make sure the input signals for the input and bi-directional buffers are fixed to VSS or VDD (LVDD or HVDD). If buffers with pull-up and pull-down resistors have been selected, leave the pins open.) For systems with dual power supplies, calculate the quiescent current for the H- and L-voltage buffers separately. 12 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 1 Overview Table 1-12 Quiescent-Current Value per Input/Output Buffer (Tj = 85° C) Quiescent-Current Value Unit VDD = 3.60 V 450 x 10-9 A VDD = 2.70 V 105 x 10-9 A 75 x 10 VDD = 1.60 V A 75 x 10 VDD = 1.95 V -9 -9 A Quiescent-current value of input / output buffer = (values in Table 1-12) x (number of output cells + number of bi-directional cells + number of VDD (HVDD or LVDD) power-supply cells) Calculation example: Find the quiescent-current value for the following case. · Power-supply voltage : HVDD / LVDD = 3.3 V / 1.8 V · Type of transistor used : Standard 1 · I/O cells VSS HVDD LVDD H-voltage input cells H-voltage output cells H-voltage bi-directional cells L-voltage input cells L-voltage output cells L-voltage bi-directional cells : 12 : 12 : 12 : 30 : 40 : 60 : 30 : 20 : 40 · Basic Cell-type 2-port RAM : 256 words x 16 bits, 4 pcs. 128 words x 8 bits, 6 pcs. · Cell-Based Logic : 1240k gates Because this is a dual-power-supply system, first find the quiescent current for the LDDD system. From Table 1-10, the quiescent-current value of the Cell-Based Logic is IQBC = 9.62 x 10-7 x 1240 = 1192.9 x 10-6 [A] (VDD = 1.95 V, Tj = 85°C) Next, find the quiescent-current value of the Basic Cell-type RAMs. From Table 1-11, the quiescent-current value per piece of RAM is 256 Word x 16 Bit . 10.70 x 10-6 [A] 128 Word x 8 Bit . 3.88 x 10-6 [A] Therefore, the quiescent-current value of the Basic Cell-type RAMs is IQBM = (10.70 x 10-6 x 4) + (3.88 x 10-6 x 6) = 42.8 x 10-6 + 23.28 x 10-6 = 66.08 x 10-6 [A] (VDD = 1.95 V, Tj = 85°C) STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 13 Chapter 1 Overview Next, find the quiescent-current value of the input/output buffers using the equation for quiescent-current values shown above. IQIO = 75 x 10-9 x (20 + 40 + 12) = 5.40 x 10-6 [A] From the quiescent-current values obtained thus far, find the quiescent-current value of the LVDD system. IQ (LVDD) = IQBC + IQBM + IQIO = 844.4 x 10-6 + 66.08 x 10-6 + 5.4 x 10-6 = 915.88 x 10-6 [A] Next, find the quiescent-current value of the HVDD system. To find the quiescent-current value of the HVDD system, simply calculate the quiescent current flowing in the input/output buffers. IQ (HVDD) = 450 x 10-9 x (40 + 60 + 12) = 50.40 x 10-6 [A] From the above calculation results, the quiescent-current values to be obtained in this example are IQ (LVDD) = 915.88 x 10-6 [A] IQ (HVDD) = 50.40 x 10-6 [A] 1.3.5 Temperature Characteristics of Quiescent Current The quiescent-current values at temperatures other than Tj = 85[°C] can be approximately calculated using the equation shown below. IDDS (T j) = IDDS (T j= 85°C) x 0.0317e(0.0406 x Tj ) (where, Tj = 0 to 125°C) Calculation example: In cases in which the quiescent-current value at Tj = 85[°C] is 3000 [µA], the approximate value of the quiescent current at Tj = 50[°C] is IDDS (Tj = 50°C) = IDDS (Tj = 85°C) x 0.0317e (0.0406 x 50) = 3000 x 0.24 = 720 [µA] 14 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 1 Overview 1.4 Product Development Flow The standard cells and embedded arrays are developed jointly by customers and Epson. Customers perform work based on the cell libraries and various design materials supplied by Epson. This work includes system design, circuit design, and pattern design. Before these designs can be interfaced to Epson, customers are requested to check them based on the data-release checklist included herein. After completion of that check, the necessary data and documentation may be presented to Epson. Customers conduct simulations of said designs using EDA software or Auklet* available on hand, and Epson undertakes subsequent work following placement and routing. Note *Auklet is an ASIC design assistance system from Epson that can be run on an MS-Windows 95/98 or NT platform. Currently, the following types of EDA software can be used for simulation: · Verilog-XL(*1) · VSS(*2) · ModelSim(*3) Note *1: Verilog-XL is a registered trademark of Cadence Design Systems Corporation, USA. *2: VSS is a registered trademark of Synopsys of Inc., USA. *3: ModelSim is a registered trademark of Model Technology Corp., USA. For more information, please contact the sales division of Epson. STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 15 Chapter 1 Overview The process flow of the standard-cell / embedded-array development process is shown below. Customer Distributor (Interface) EPSON Product Plan Functional Spec. Circuit Design Test Pattern Design Logic Check (Simulation) NG Verification Standard-cell Development Request Simulation File Delay Time Analysis Schematic Pin Assignment Timing Wave Form Marking-diagram P/O Timing Check (Simulation) NG Verification* OK Automatic Place & Rout Delay Time Analysis Simulation List NG Verification OK (Post Simulation) Customer Spec. Sign Off Make Masks NG TS (Test Sample) Fabrication Functional Evaluation ES (Engineering Sample) Fabrication OK NG Overall Evaluation OK ES (TS) Approval Notification ES (TS) Prototype-Evaluation Approval Notification Delivery Spec. Delivery Spec. Approval MP Setup Delivery Spec. Publication Delivery Spec. Approval Notification MP Operations enclosed in ( ) are performed only when so requested by customers. 16 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 2 Estimating the Gate Density Chapter 2 Estimating the Gate Density This chapter describes the procedure for estimating the circuit size after cutting out circuits from the customer's system, and then estimating an approximate bulk size. The precautions to be taken when performing this work are also described. 2.1 Dividing Up Logic Between Chips When cutting out circuits from the customer's system, care must be taken with respect to the following points. · Precautions to be taken (1) Logic size to be integrated (Gate count) (2) Number of I/O pins required (Pin count) (3) Package to be used (4) Power consumption Generally speaking, as the circuit size increases, so does the power consumption of the circuit and the number of input/output pins on it. If the circuit size is significantly large, the circuit may be divided into multiple chips rather than being integrated into a single chip. This helps reduce the total cost and the power consumption of the circuit. STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 17 Chapter 2 2.2 Estimating the Gate Density Determining Gate Size The number of gates used in the S1K70000 S1K70000 series MSI cells may be estimated from the number of pads or from the size of the circuit implemented. 2.2.1 Estimating Bulk from the Number of Pads Table 2-1 lists the primary bulks in the S1K/S1X70000 S1K/S1X70000 series with respect to the number of pads. Table 2-1 Typical Pad Counts and Total BC Counts Cell Based Type*2 Basic Cell Type Total BC Count X Total BC Count Y X PAD Count *1 (four sides) Y A 128154 689 186 175000 625 280 88 B 165148 779 212 224190 705 318 100 C 272816 1003 272 370872 909 408 128 D 353090 1139 310 479312 1033 464 144 E 425340 1251 340 578850 1135 510 160 F 524286 1387 378 711462 1257 566 176 G 575388 1453 396 780848 1319 592 184 H 725940 1635 444 986346 1481 666 208 I 789264 1701 464 1070842 1543 694 216 J 1109350 2017 550 1503438 1829 822 256 H 1568946 2399 654 2129106 2177 978 304 L 2076272 2761 752 2818378 2503 1126 352 M 2540096 3053 832 3450174 2769 1246 388 N 2970900 3301 900 4028578 2993 1346 420 O 3385920 3527 960 4597286 3197 1438 448 P 3878644 3773 1028 5271420 3423 1540 480 Q 4358910 3999 1090 5919264 3627 1632 508 R 4764060 4179 1140 6456456 3789 1704 532 S 5230914 4381 1194 7103724 3973 1788 556 Notes *1: For pin counts less than 88, the number of pads is omitted. *2: In the "S1K70000 S1K70000 Series MSI Cell Library", the size of each Cell Based-type cell is expressed in grid units. Cell sizes in grid units may be converted into BC counts at a rate of 1 BC = 3.0 grids. 18 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 2 Estimating the Gate Density 2.2.2 Estimating the Number of Gates Used in Basic Cell-Type MSI Cell Before the number of gates used in the S1K70000 S1K70000 series Basic Cell-type MSI cell can be estimated, the following pieces of information must be available. · Circuit size : G0 (gate or BC) · Maximum operating frequency in the circuit : f (MHz) · Percentage of circuit operating at f MHz : (%) · Number of metalizations used :M The rules for reinforced power supplies are determined from the above information (depending on the width of the reinforced power-supply line, one of two sets of rules applies). Because no logic circuits can be placed below reinforced power supplies, the area required for reinforced power supplies must be added to the above circuit size, G0 gates. Here, the necessary BC count, GA, where reinforced power supplies are considered, is defined as GA = G0 + (area required for the reinforced power supply) . (1) Further, the following is defined. G0 / GA = (%) Effective gate rate . (2) The effective gate rates are summarized in Tables 2-2 and 2-3. Table 2-2 Effective Gate Rates (1 BC) (%) Metalization Layers Operating Frequency (MHz) 100 125 150 175 200 89.4 87.7 84.6 - - - - 60% 88.3 85.6 80.2 - - - - 87.1 83.3 - - - - - 40% 90.9 90.3 89.8 89.3 88.7 88.0 87.5 60% 90.4 89.7 88.9 88.0 87.1 86.3 85.1 80% 90.0 89.0 87.9 86.8 85.6 84.0 83.3 100% 89.6 88.3 86.8 85.6 84.0 82.5 80.2 40% 91.2 90.9 90.6 90.3 90.0 89.7 89.3 60% 90.9 90.5 90.0 89.6 89.1 88.6 88.1 80% 90.7 90.1 89.5 88.9 88.3 87.7 86.8 100% AL6 layered 75 80% AL4 or 5 layered 50 40% AL3 layered Circuit Percentage 90.4 89.7 89.0 88.1 87.3 86.6 85.6 Note: Combinations left blank in the above table are not available. STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 19 Chapter 2 Estimating the Gate Density Table 2-3 Effective Gate Rates (2 BCs) (%) Metalization Layers Operating Frequency (MHz) 100 125 150 175 200 83.8 83.3 82.8 82.2 81.6 80.9 80.4 60% 83.4 82.6 81.8 80.9 80.2 - - 83.0 82.0 80.9 - - - - 40% 84.3 84.1 83.9 83.7 83.5 83.3 83.1 60% 84.1 83.8 83.5 83.2 82.9 82.6 82.3 80% 83.9 83.5 83.1 82.7 82.3 81.9 81.5 100% 83.7 83.3 82.7 82.3 81.7 81.2 80.6 40% 84.4 84.3 84.1 84.0 83.9 83.8 83.6 60% 84.3 84.1 83.9 83.7 83.5 83.3 83.2 80% 84.2 83.9 83.7 83.4 83.2 82.9 82.7 100% AL6 layered 75 80% AL4 or 5 layered 50 40% AL3 layered Circuit Percentage 84.0 83.7 83.4 83.1 82.8 82.5 82.1 Note: Combinations left blank in the above table are not available. From Tables 2-2 or 2-3, find the effective gate rate: (%) corresponding to the maximum operating frequency: f (MHz), circuit percentage: (%), and number of metalizations used: M. If the relevant operating frequency or circuit percentage does not exist, find the closest applicable value. When the effective gate rate, (%), is found, the necessary BC count, with reinforced power supplies considered, GA, may be obtained from Equation (2) as follows: GA = G0 / ( / 100) . (3) For the actual chip, however, the wiring area used for P&R is required, in addition to the above. Here, let us define G = GA + (wiring area required for P&R) . (4) and further GA / G = P (%) . (5) The effective rates of wiring are summarized in Table 2-4. Using Table 2-4, find the effective rate of wiring: P (%) that corresponds to circuit size: G0 and number of metalized layers: M. When calculating this effective rate of wiring, note that the circuit size: G0 supplied by the customer, and not the GA obtained above, is used as a parameter for the gate size. If the relevant circuit size does not exist, use the closest applicable value. When the effective rate of wiring, P (%), is found, the value of G may be obtained from Equation (5) as follows: G = GA / (P / 100) . (6) The resulting G (gates or BCs) is the number of Basic Cells to be obtained. 20 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 2 Estimating the Gate Density Table 2-4 Effective Rate of Wiring (%) Gate AL3 Layered AL4 Layered AL5 Layered AL6 Layered 100k 75 80 85 90 200k 75 80 85 90 300k 70 75 80 85 400k 70 75 80 85 500k 65 70 75 80 600k 65 70 75 80 700k 65 70 75 80 800k 60 65 70 75 900k 60 65 70 75 1000k 60 65 70 75 1100k 55 60 65 70 1200k 55 60 65 70 1300k 55 60 65 70 1400k 55 60 65 70 1500k 55 60 65 70 1600k 55 60 65 70 1700k 55 60 65 70 1800k 55 60 65 70 1900k 55 60 65 70 2000k 55 60 65 70 Calculation example: Estimate the number of gates used in MSI cells under the following conditions. · Circuit size : 500k gates · Maximum operating frequency : 66 MHz · Circuit operating at 66 MHz : Approx. 200k gates · Metalized layers used : 5 layers First, determine the wiring width of reinforced power supplies. Using the values in Tables 2-2 and 2-3, determine whether the 1 BC or 2 BC type of reinforced power supply should be used. For the present example, the following applies: · Operating frequency: 66 MHz substituted with 75 MHz · AL5-layered product · Circuit percentage operating at 66 MHz () = Circuit operating at f MHz / Circuit size x 100 = 200k / 500k x 100 = 40* (%) STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 21 Chapter 2 Estimating the Gate Density * This value represents a percentage in cases in which cells are laid out evenly throughout the chip. If cells are laid out unevenly so as to be concentrated in a specific location, the percentage should be increased to 60% or 80%. Therefore, the effective gate rates may be obtained from Tables 2-2 and 2-3 as follows: 1 BC reinforced power supplies . Effective gate rate = 90.3% 2 BC reinforced power supplies . Effective gate rate = 84.1% Thus, choose 1BC reinforced-power-supply rules, which have a better effective gate rate. From Equation (3), the necessary BC count, with reinforced power supplies considered, is GA = 500k / 0.903 = 553.7k (BCs) Next, determine the wiring efficiency. From Table 2-4, we know that the effective rate of wiring for circuit size = 500k gates with an AL5-layered product is 75%. Therefore, substitute that value in Equation (6), and the following results: G = 553.7k / 0.75 = 738.27k Thus, the estimated number of gates used in the Basic Cell-type MSI cell is 739k (BCs). 2.2.3 Estimating the Number of Gates Used in Cell Based-Type MSI Cell The number of gates used in the Cell Based-type MSI cell may be estimated with the same method shown in Section 2.2.2, "Estimating the Number of Gates Used in Basic Cell-Type MSI Cell." In this case, however, note that the effective gate rates given in Tables 2-5 and 2-6 apply. Table 2-5 Effective Gate Rates (1 BC) (%) Metalization Layers Operating Frequency (MHz) 75 100 125 150 175 200 90.6 89.7 88.1 85.1 80.2 - - 60% 90.0 88.6 85.9 82.5 - - - 80% 89.4 87.5 84.0 - - - - 40% 91.3 91.0 90.7 90.5 90.2 89.8 89.6 60% 91.1 90.7 90.3 89.8 89.4 89.0 88.4 80% 90.9 90.3 89.8 89.3 88.6 87.9 87.5 100% AL5 or 6 layered 50 40% AL3 or 4 layered Circuit Percentage 90.6 90.0 89.3 88.6 87.9 87.1 85.9 Note: Combinations left blank in the above table are not available. 22 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 2 Estimating the Gate Density Table 2-6 Effective Gate Rates (2 BCs) (%) Metalization Layers Operating Frequency (MHz) 75 100 125 150 175 200 84.2 84.0 83.7 83.4 83.1 82.8 82.5 60% 84.0 83.6 83.2 82.8 82.4 81.8 81.4 80% 83.8 83.3 82.8 82.1 81.6 80.8 80.4 40% 84.4 84.3 84.2 84.1 84.0 83.9 83.8 60% 84.4 84.2 84.1 83.9 83.8 83.6 83.4 80% 84.3 84.1 83.9 83.7 83.5 83.3 83.1 100% AL5 or 6 layered 50 40% AL3 or 4 layered Circuit Percentage 84.2 83.9 83.7 83.4 83.2 82.9 82.6 Note: Combinations left blank in the above table are not available. Calculation example: Estimate the number of gates used in MSI cells under the following conditions. · Circuit size : 500k gates · Maximum operating frequency : 150 MHz · Circuit operating at 150 MHz : Approx. 300k gates · Metalized layers used : 4 layers First, determine the wiring width of reinforced power supplies. Use the values in Tables 2-5 and 2-6 to determine whether the 1 BC or 2 BC type of reinforced power supply should be used. For the present example, the following applies: · Operating frequency: 150 MHz · AL4-layered product · Circuit percentage operating at 150 MHz () = Circuit operating at f MHz / Circuit size x 100 = 300k / 500k x 100 = 60* (%) * This value represents a percentage in cases in which cells are laid out evenly throughout the chip. If cells are laid out unevenly so as to be concentrated on a specific location, the percentage should be increased to 80%. Therefore, the effective gate rates may be obtained from Tables 2-5 and 2-6 as follows: 1 BC reinforced power supplies . Effective gate rate = Not applicable 2 BC reinforced power supplies . Effective gate rate = 82.4% Because 1 BC reinforced power supplies are not applicable, choose 2 BC reinforcedpower-supply rules. From Equation (3) in Section 2.2.2, "Estimating the Number of Gates Used in Basic Cell-Type MSI Cell," the necessary BC count, with reinforced power supplies considered, is GA = 500k / 0.824 = 606.8k (BCs) Next, determine the wiring efficiency. STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 23 Chapter 2 Estimating the Gate Density From Table 2-4, we know that the effective rate of wiring for circuit size = 500k gates with an AL4-layered product is 70%. Therefore, substitute that value in Equation (6) in Section 2.2.2, "Estimating the Number of Gates Used in Basic Cell-Type MSI Cell." The following results: G = 606.8k / 0.70 = 866.85k Thus, the estimated number of gates used in the Cell Based-type MSI cell is 867k (BCs). 2.2.4 Estimating the Number of Gates Used in Basic Cell-Type RAM For details on estimating the number of gates used in the S1K70000 S1K70000 series Basic Cell-type RAM, refer to Section 5.1.3, "RAM Sizes." 2.2.5 Estimating the Number of Gates Used in Cell Based-Type RAM For details on estimating the number of gates used in the S1K70000 S1K70000 series Cell Based-type RAM and ROM, please consult the sales division of Epson. 2.2.6 Estimating Bulk from the Implemented Circuit Size Find the sum total of all gate counts that have been obtained in Sections 2.2.2 through 2.2.5; an approximate bulk size can be predicted from Table 2-1 based on that result. 2.3 Estimating the Number of Input/Output Pins After the number of gates used in cells has been estimated, calculate the number of actually used input/output pins. When performing this calculation, make sure the test pins and power-supply pins on Basic Cell-type RAM and Cell Based-type RAM and ROM are included in the pin counts. To estimate the number of power-supply pins, use the method described in Section 7.11, "Pin Placement and Simultaneous Operation." 24 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 3 Chapter 3 3.1 MSI Cells MSI Cells Naming Rules for MSI With the S1K70000 S1K70000 series, the Basic Cell and Cell-Based types of MSI cells are available for multiple types of transistors. These types of MSI cells are functionally identified using the following naming rules: K 1 N A 2 X 4 . Cell Base/type of transistor: STD 1/2-input NAND/x4 output Drivability (For details, refer to the cell libraries.) Functionality Library classification Basic Cell Type L1* K1* Standard 1 L2* K2* High-Performance L3* K3* Low-Leakage L4* STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Cell-Based Type K4* Standard 2 EPSON Type of Transistor 25 Chapter 3 3.2 MSI Cells MSI Cell Types Below is a list of the functions of the MSI cell types in the S1K70000 S1K70000 series. The functions of all of these cells are common to L1 through L4 or K1 through K4. For more information, please contact the sales division of Epson. List of cell functions in the S1K70000 S1K70000 series · BUFFER · INVERTER · DELAY LINE · AND GATE INPUT2/3/4 /INPUT2/3/4with Inverted Input1/2/3 INPUT5/6/8 · NAND GATE INPUT2/3/4 /INPUT2/3/4with Inverted Input1/2/3 INPUT5/6/8 · OR GATE INPUT2/3/4 /INPUT2/3/4with Inverted Input1/2/3 INPUT5/6/8 · NOR GATE INPUT2/3/4 /INPUT2/3/4with Inverted Input1/2/3 INPUT5/6/8 · EXCLUSIVE OR/NOR INPUT2/3 · AND-OR GATES 2-AND-OR INPUT3/4/5/6/8 3-AND-OR INPUT4/5/6 4-AND-OR INPUT8 · OR-AND GATES 2-OR-AND INPUT3/4/5/6/8 3-OR-AND INPUT4/5/6 4-OR-AND INPUT8 · MULTI-FUNCTION GATES 2-OR 2-AND 4-INPUT OR GATE 2-AND 2-OR 4-INPUT AND GATE · MAJORITY GATES 2 of 3/Inverted 2 of 3 · CLOCK TREE ROOT BUFFER BUFFER/INVERTER 26 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 3 MSI Cells · GATED CLOCK 2-INPUT AND GATE 2-INPUT OR GATE 2-INPUT NAND GATE 2-INPUT NOR GATE INVERTER SELECTOR/MULTIPLEXER · FLIP FLOPS D-FLIP FLOP SET/RESET SYNCHRONOUS ENABLE OUTPUT Q NEGATIVE CLOCK SCAN JK-FLIP FLOP SET/RESET OUTPUT Q SCAN RS-FLIP FLOP NAND-TYPE/NOR-TYPE · LATCHES PRESET/RESET OUTPUT M NEGATIVE CLOCK · ADDER · DECODERS 2-LINE to 4-LINE ENABLE · SELECTORS/MULTIPLEXERS 2-LINE to 1-LINE 4-LINE to 1-LINE ENABLE QUADRUPLE 2-LINE to 1-LINE ENABLE NEGATIVE OUTPUT · BUS CELLS LATCH 3-STATE BUFFER -LOW ENABLE/HIGH ENABLE STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 27 Chapter 4 Types of Input/Output Buffers and Their Use Chapter 4 Types of Input/Output Buffers and Their Use This chapter describes in detail how the input buffers, output buffers, and bi-directional buffers are constructed. 4.1 Selecting Input/Output Buffers 4.1.1 Naming Rules for Input/Output Buffers The S1K70000 S1K70000 series uses the following naming rules to identify the functionality of input/output buffers (except for some buffers). H B B C 2 A D 1 T F H: HVDD system of dual power supplies L: LVDD system of dual power supplies I: Input buffer B: Bi-directional buffer O: Output buffer T: Three-state buffer B: Ordinary buffer F: Fail-Safe type D: Open drain type 28 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 4 Types of Input/Output Buffers and Their Use C: LVCMOS level H: LVCMOS Schmitt level T: LVTTL level A: Gated V: Cutoff 1A: Type 1 High speed 2A: Type 2 High speed 3A: Type 3 High speed 4A: Type 4 High speed 1B: Type 1 Low noise 2B: Type 2 Low noise 3B: Type 3 Low noise 4B: Type 4 Low noise D1: Pull-down resistor (Type 1) D2: Pull-down resistor (Type 2) P1: Pull-up resistor (Type 1) P2: Pull-up resistor (Type 2) H: Bus hold None: Without pull-up/pull-down resistors and bus hold T: Test pins included None: Without test pins X: 2.5-V input/output buffers Y: 3.3-V input/output buffers F: 5-V tolerant Fail-Safe compatible 3.3-V input/output buffer library 4.1.2 Bus-Hold Circuit To ensure that the output pins and bi-directional pins will not enter a high-impedance state, the S1K70000 S1K70000 series has available an input/output buffer that comes equipped with a bus-hold facility to hold the data at the output pins. However, because the bus-hold circuit's retention capability is suppressed so as not to adversely affect the ordinary operation of the cell, do not use the output data held by the circuit as valid data. The retained data may easily change state when any data is supplied from an external circuit. For the bus-hold circuit's output retention current, refer to Table 1-4, Table 1-7 through 1-9. STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 29 Chapter 4 4.2 Types of Input/Output Buffers and Their Use Dual-Power-Supply Input/Output Buffers If your system uses dual power supplies, use input/output buffers designed exclusively for operation with dual power supplies. (In this case, be careful not to use input/output buffers designed for operation with a single power supply.) (1) HVDD input/output buffers The HVDD input/output buffers are available in several types. These include input buffers that accept as input 3.3-V (or 2.5-V) signals, output buffers that output 3.3-V (or 2.5-V) amplitude signals, and bi-directional buffers that accept as input 3.3-V (or 2.5-V) signals or output 3.3-V (or 2.5-V) amplitude signals. In addition, 5-V tolerant Fail-Safe cells are available that allow 5.0-V amplitude signals to be applied. (2) LVDD input/output buffers The LVDD input/output buffers are available in several types. These include input buffers that accept as input 1.8-V (or 1.5-V) signals, output buffers that output 1.8-V (or 1.5-V) amplitude signals, and bi-directional buffers that accept as input 1.8-V (or 1.5-V) signals or output 1.8-V (or 1.5-V) amplitude signals. For LVDD input or bi-directional buffers with pull-up resistors, do not apply voltages above LVDD. This is due to the fact that, if HVDD signals are supplied to those buffers, an excessive current flows in their internal protective diode, causing their quality to degrade (in such a case, use the Fail Safe cells described in Section 4.2.4, "Fail Safe Cells"). 4.2.1 (1) Input Buffers HVDD input buffers The input buffers are configured using only input cells. The HVDD input buffers consist of a first input stage configured with an HVDD input circuit and a next stage configured with an LVDD circuit, so that HVDD signals are converted into LVDD signals before being fed into the MSI cell (internal cell area). Table 4-2 lists the HVDD input buffers. Table 4-1 Rated Pull-up/Pull-down-Resistance Values at Each Voltage Resistance Value Type of Pull-up/Pull-down Resistor Unit HVDD = 3.3 V HVDD = 2.5 V Type 1 50 70 k Type 2 100 140 k 30 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 4 Types of Input/Output Buffers and Their Use Table 4-2 Cell Name*1, *2 HVDD Input Buffers List Input Level Whether Pull-up/Pull-down Resistors are Included HIBCF HIBCP#TF HIBCD#TF LVCMOS LVCMOS LVCMOS None Pull-up resistor Pull-down resistor HIBTF HIBTP#TF HIBTD#TF LVTTL LVTTL LVTTL None Pull-up resistor Pull-down resistor HIBHF HIBHP#TF HIBHD#TF LVCMOS Schmitt LVCMOS Schmitt LVCMOS Schmitt None Pull-up resistor Pull-down resistor PCI-3 V PCI-3 V PCI-3 V None Pull-up resistor Pull-down resistor HIBPCIF HIBPCIP#TF HIBPCID#TF Notes *1: The # denotes 1 or 2, with the pull-up/pull-down-resistance values corresponding to Type 1 and Type 2, respectively (for details, refer to Table 4-1). *2: In addition to the configurations shown in Table 4-2, the HVDD input buffers may be configured without test pins. Customers desiring to use such configurations should direct inquiries to Epson. (2) LVDD input buffers The input buffers are configured using only input cells. input buffers. Table 4-3 Table 4-4 lists the LVDD Rated Pull-up/Pull-down-Resistance Values at Each Voltage Resistance Value Type of Pull-up/Pull-down Resistor Unit LVDD = 1.8 V LVDD = 1.5 V Type 1 60 90 k Type 2 120 180 k Table 4-4 Cell Name*1, *2 LVDD Input Buffers List Input Level Whether Pull-up/Pull-down Resistors are Included LIBCF LIBCP#TF LIBCD#TF LVCMOS LVCMOS LVCMOS None Pull-up resistor Pull-down resistor LIBHF LIBHP#TF LIBHD#TF LVCMOS Schmitt LVCMOS Schmitt LVCMOS Schmitt None Pull-up resistor Pull-down resistor Notes *1: The # denotes 1 or 2, with the pull-up/pull-down resistance values corresponding to Type 1 and Type 2, respectively (for details, refer to Table 4-3). *2: In addition to the configurations shown in Table 4-4, the LVDD input buffers may be configured without test pins. Customers desiring to use such configurations should direct inquiries to Epson. STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 31 Chapter 4 Types of Input/Output Buffers and Their Use 4.2.2 Output Buffers (1) HVDD output buffers Tables 4-6 and 4-8 list the HVDD output buffers. Table 4-5 Rated IOH and IOL Values at Each Voltage IOH*1/IOL*2 Type of Output Current Unit HVDD = 3.3 V HVDD = 2.5 V Type 1 -2/2 -1.5/1.5 mA Type 2 -4/4 -3/3 mA Type 3 -8/8 -6/6 mA Type 4 -12/12 -9/9 mA Notes *1: VOH = HVDD - 0.4 V *2: VOL = 0.4 V Table 4-6 HVDD Output Buffers List IOL/IOH Cell Name*1, *2 Normal output for high speed Type 1 Type 2 Type 3 Type 4 HOB#ATF Normal output for low noise Type 1 Type 2 Type 3 Type 4 HOB#BTF Normal output for PCI PCI-3 V HOBPCITF*3 3-state output for high speed Type 1 Type 2 Type 3 Type 4 HTB#ATF 3-state output for low noise Type 1 Type 2 Type 3 Type 4 HTB#BTF 3-state output for PCI PCI-3 V HTBPCITF*3 3-state output for high speedBus hold circuit Type 1 Type 2 Type 3 Type 4 HTB#AHTF 3-state output for low noiseBus hold circuit Type 1 Type 2 Type 3 Type 4 HTB#BHTF Function Notes *1: The # denotes 1, 2, 3, or 4, with the IOH/IOL values corresponding to Type 1, Type 2, Type 3, and Type 4, respectively (for details, refer to Table 4-5). *2: In addition to the configurations shown in Table 4-6, the HVDD output buffers may be configured without test pins. Customers desiring to use such configurations should direct inquiries to Epson. *3: PCI-3 V cells use two input/output-buffer areas. 32 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 4 Types of Input/Output Buffers and Their Use Table 4-7 Rated IOL Values at Each Voltage IOL*1 Type of Output Current Unit HVDD = 3.3 V HVDD = 2.5 V Type 1 2 1.5 mA Type 2 4 3 mA Type 3 8 6 mA Type 4 12 9 mA Note *1: VOL = 0.4 V Table 4-8 HVDD N channel Open drain Output Buffers List IOL Cell Name*1, *2 Normal output for high speed Type 1 Type 2 Type 3 Type 4 HOD#ATF Normal output for low noise Type 1 Type 2 Type 3 Type 4 HOD#BTF Function Notes *1: The # denotes 1, 2, 3, or 4, with the IOL values corresponding to Type 1, Type 2, Type 3, and Type 4, respectively (for details, refer to Table 4-7). *2: In addition to the configurations shown in Table 4-8, the HVDD N channel open drain output buffers may be configured without test pins. Customers desiring to use such configurations should direct inquiries to Epson. (2) LVDD output buffers Tables 4-10 and 4-12 list the LVDD output buffers. Table 4-9 Rated IOH and IOL Values at Each Voltage IOH*1/IOL*2 Type of Output Current Unit LVDD = 1.8 V LVDD = 1.5 V Type 1 -1/1 -0.75/0.75 mA Type 2 -2/2 -1.5/1.5 mA Type 3 -4/4 -3/3 mA Type 4 -6/6 -4.5/4.5 mA Notes *1: VOH = LVDD - 0.4 V *2: VOL = 0.4 V STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 33 Chapter 4 Types of Input/Output Buffers and Their Use Table 4-10 LVDD Output Buffers List IOH/IOL Cell Name*1, *2 Normal output for high speed Type 1 Type 2 Type 3 Type 4 LOB#ATF Normal output for low noise Type 1 Type 2 Type 3 Type 4 LOB#BTF 3-state output for high speed Type 1 Type 2 Type 3 Type 4 LTB#ATF 3-state output for low noise Type 1 Type 2 Type 3 Type 4 LTB#BTF 3-state output for high speedBus hold circuit Type 1 Type 2 Type 3 Type 4 LTB#AHTF 3-state output for low noiseBus hold circuit Type 1 Type 2 Type 3 Type 4 LTB#BHTF Function Notes *1: The # denotes 1, 2, 3, or 4, with the IOH/IOL values corresponding to Type 1, Type 2, Type 3, and Type 4, respectively (for details, refer to Table 4-9). *2: In addition to the configurations shown in Table 4-10, the LVDD output buffers may be configured without test pins. Customers desiring to use such configurations should direct inquiries to Epson. Table 4-11 Rated IOL Values at Each Voltage IOL*1 Type of Output Current Unit LVDD = 1.8 V LVDD = 1.5 V Type 1 1 0.75 mA Type 2 2 1.5 mA Type 3 4 3 mA Type 4 6 4.5 mA Note 34 *1: VOL = 0.4 V EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 4 Types of Input/Output Buffers and Their Use Table 4-12 LVDD N channel Open drain Output Buffers List IOL Cell Name*1, *2 Normal output for high speed Type 1 Type 2 Type 3 Type 4 LOD#ATF Normal output for low noise Type 1 Type 2 Type 3 Type 4 LOD#BTF Function Notes *1: The # denotes 1, 2, 3, or 4, with the IOL values corresponding to Type 1, Type 2, Type 3, and Type 4, respectively (for details, refer to Table 4-11). *2: In addition to the configurations shown in Table 4-12, the LVDD N channel open drain output buffers may be configured without test pins. Customers desiring to use such configurations should direct inquiries to Epson. STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 35 Chapter 4 4.2.3 (1) Types of Input/Output Buffers and Their Use Bi-directional Buffers HVDD bi-directional buffers Tables 4-13 and 4-14 list the HVDD bi-directional buffers. Table 4-13 HVDD Bi-directional Buffers List (1/2) IOH/IOL Cell Name*1, *2 Bi-directional output for high speed Type 1 Type 2 Type 3 Type 4 HBBT#ATF Bi-directional output for low noise Type 1 Type 2 Type 3 Type 4 HBBT#BTF Bi-directional output for high speed Type 1 Type 2 Type 3 Type 4 HBBC#ATF Bi-directional output for low noise Type 1 Type 2 Type 3 Type 4 HBBC#BTF Bi-directional output for PCI PCI-3 V HBBPCITF*3 Bi-directional output for high speed Type 1 Type 2 Type 3 Type 4 HBBH#ATF Bi-directional output for low noise Input Level Type 1 Type 2 Type 3 Type 4 HBBH#BTF Function LVTTL LVCMOS PCI LVCMOS Schmitt Notes *1: The # denotes 1, 2, 3, or 4, with the IOH/IOL values corresponding to Type 1, Type 2, Type 3, and Type 4, respectively (for details, refer to Table 4-5). *2: In addition to the configurations shown in Table 4-13, the HVDD bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. Customers desiring to use such configurations should direct inquiries to Epson. *3: PCI-3 V cells use two input/output-buffer areas. 36 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 4 Types of Input/Output Buffers and Their Use Table 4-13 List of HVDD Bi-directional Buffers List (2/2) Function IOH/IOL Cell Name*1, *2 Bi-directional output for high speedBus hold circuit Type 1 Type 2 Type 3 Type 4 HBBT#AHTF Bi-directional output for low noiseBus hold circuit Type 1 Type 2 Type 3 Type 4 HBBT#BHTF Bi-directional output for high speedBus hold circuit Type 1 Type 2 Type 3 Type 4 HBBC#AHTF Bi-directional output for low noiseBus hold circuit Type 1 Type 2 Type 3 Type 4 HBBC#BHTF Bi-directional output for high speedBus hold circuit Type 1 Type 2 Type 3 Type 4 HBBH#AHTF Bi-directional output for low noiseBus hold circuit Type 1 Type 2 Type 3 Type 4 HBBH#BHTF Input Level LVTTL LVCMOS LVCMOS Schmitt Notes *1: The # denotes 1, 2, 3, or 4, with the IOH/IOL values corresponding to Type 1, Type 2, Type 3, and Type 4, respectively (for details, refer to Table 4-5). *2: In addition to the configurations shown in Table 4-13, the HVDD bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. Customers desiring to use such configurations should direct inquiries to Epson. STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 37 Chapter 4 Types of Input/Output Buffers and Their Use Table 4-14 HVDD N channel Open drain Bi-directional Buffers List IOL Cell Name*1, *2 Bi-directional output for high speed Type 1 Type 2 Type 3 Type 4 HBDT#ATF Bi-directional output for low noise Type 1 Type 2 Type 3 Type 4 HBDT#BTF Bi-directional output for high speed Type 1 Type 2 Type 3 Type 4 HBDC#ATF Bi-directional output for low noise Type 1 Type 2 Type 3 Type 4 HBDC#BTF Bi-directional output for high speed Type 1 Type 2 Type 3 Type 4 HBDH#ATF Bi-directional output for low noise Input Level Type 1 Type 2 Type 3 Type 4 HBDH#BTF Function LVTTL LVCMOS LVCMOS Schmitt Notes *1: The # denotes 1, 2, 3, or 4, with the IOL values corresponding to Type 1, Type 2, Type 3, and Type 4, respectively (for details, refer to Table 4-7). *2: In addition to the configurations shown in Table 4-14, the HVDD N channel open drain bi-directional buffers may be configured without test pins. Customers desiring to use such configurations should direct inquiries to Epson. 38 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 4 Types of Input/Output Buffers and Their Use (2) LVDD bi-directional buffers Tables 4-15 and 4-16 list the LVDD bi-directional buffers. Table 4-15 LVDD Bi-directional Buffers List IOH/IOL Cell Name*1, *2 Bi-directional output for high speed Type 1 Type 2 Type 3 Type 4 LBBC#ATF Bi-directional output for low noise Type 1 Type 2 Type 3 Type 4 LBBC#BTF Bi-directional output for high speed Type 1 Type 2 Type 3 Type 4 LBBH#ATF Bi-directional output for low noise Type 1 Type 2 Type 3 Type 4 LBBH#BTF Bi-directional output for high speedBus hold circuit Type 1 Type 2 Type 3 Type 4 LBBC#AHTF Bi-directional output for low noiseBus hold circuit Type 1 Type 2 Type 3 Type 4 LBBC#BHTF Bi-directional output for high speedBus hold circuit Type 1 Type 2 Type 3 Type 4 LBBH#AHTF Bi-directional output for low noiseBus hold circuit Type 1 Type 2 Type 3 Type 4 LBBH#BHTF Input Level Function LVCMOS LVCMOS Schmitt LVCMOS LVCMOS Schmitt Notes *1: The # denotes 1, 2, 3, or 4, with the IOH/IOL values corresponding to Type 1, Type 2, Type 3, and Type 4, respectively (for details, refer to Table 4-9). *2: In addition to the configurations shown in Table 4-15, the LVDD bi-directional buffers may be configured with pull-up/pull-down resistors or without test pins. Customers desiring to use such configurations should direct inquiries to Epson. STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE EPSON 39 Chapter 4 Types of Input/Output Buffers and Their Use Table 4-16 LVDD N channel Open drain Bi-directional Buffers List IOL Cell Name*1, *2 Bi-directional output for high speed Type 1 Type 2 Type 3 Type 4 LBDC#ATF Bi-directional output for low noise Type 1 Type 2 Type 3 Type 4 LBDC#BTF Bi-directional output for high speed Type 1 Type 2 Type 3 Type 4 LBDH#ATF Bi-directional output for low noise Input Level Type 1 Type 2 Type 3 Type 4 LBDH#BTF Function LVCMOS LVCMOS Schmitt Notes *1: The # denotes 1, 2, 3, or 4, with the IOL values corresponding to Type 1, Type 2, Type 3, and Type 4, respectively (for details, refer to Table 4-11). *2: In addition to the configurations shown in Table 4-16, the LVDD N channel open drain bi-directional buffers may be configured without test pins. Customers desiring to use such configurations should direct inquiries to Epson. 40 EPSON STANDARD CELL/EMBEDDED ARRAY S1K70000/S1X70000 S1K70000/S1X70000 SERIES 5V TOLERANT DESIGN GUIDE Chapter 4 Types of Input/Output Buffers and Their Use 4.2.4 Fail Safe Cells 4.2.4.1 Outline The 5-V tolerant Fail-Safe cells in the S1K70000 S1K70000 series allow signals with voltage levels higher than that of the power supply to be interfaced even while the power supply is on. Furthermore, because no leakage current flows in the cell (even when signals are interfaced while the power supply remains cut off), there is greater freedom than ever in circuit design. (Dual-power supplies operate as LVDD cells.) 4.2.4.2 Features (1) There are no limitations on cell counts and cell placement; these can be placed anywhere in the circuit. (2) No input leakage current occurs even when input signals with voltage levels higher than that of the power supply are applied while the power supply is on. (For input buffers or bi-directional buffers with pull-up resistors, however, a small input leakage current of approximately 30 µA occurs due to circuit structure.) (3) No input leakage current occurs even when input signals are applied from the outside with the power supply off. (4) There are two input levels available to choose from: LVCMOS level and LVCMOS Schmitt level. (5) Because the cells are built using CMOS process technology, the power consumption in the circuit can be reduced. 4.2.4.3 (1) Usage Precautions About input I/O cells · For input buffers with no resistors or with pull-down resistors, ordinary input buffers may be used directly as Fail-Safe cells. · If input buffers with pull-up resistors are needed, a