S1R72801F00A MF1385-04 IEEE1394 SPC7281F0A E0C33000 S1C33000 E0C33208/204/202 - Datasheet Archive

 

MF1385-04 Technical Manual IEEE1394 Controller S1R72801F00A Technical Manual S1R72801F00A Technical Manual ELECTRONIC DEVICES

 

S1R72801F00A S1R72801F00A MF1385-04 MF1385-04 Technical Manual IEEE1394 IEEE1394 Controller S1R72801F00A S1R72801F00A Technical Manual S1R72801F00A S1R72801F00A Technical Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ This manual was made with recycle paper, and printed using soy-based inks. First issue December,2000 Printed March,2001 in Japan H A 4.5mm In pursuit of "Saving" Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers' dreams. Epson IS energy savings. NOTICE No parts of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind aristing out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export licence from teh Ministry of International Trade and Industry or other approval from another government agency. © SEIKO EPSON CORPORATION 2001, All rights reserved. All other product names mentioned herein are trademarks and/or registered trademarkes of their respective companies. 4.5mm The information of the product number change Starting April 1, 2001 the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number qDEVICES S1 R 72801 F 00A1 00 Packing specification Specifications Shape (F:QFP) Model number Model name (R:Exclusive use controller, Peripheral) Product classification (S1:Semiconductors) Comparison table between new and previous number Previous number SPC7281F0A SPC7281F0A E0C33000 E0C33000 New number S1R72801F00A S1R72801F00A S1C33000 S1C33000 SPC7281F0A SPC7281F0A Contents 1. DESCRIPTION . 1 2. FEATURES . 1 3. INTERNAL BLOCK DESCRIPTION . 3 3.1 BLOCK DIAGRAM . 3 3.2 BLOCK DIAGRAM DESCRIPTION . 3 4. INTERNAL CONNECTION DIAGRAM . 4 5. PIN ASSIGNMENT DIAGRAM . 5 6. PIN DESCRIPTION . 6 7. FUNCTIONAL DESCRIPTION . 10 7.1 MEMORY MAP . 10 7.1.1 All Memory Space . 10 7.1.2 IEEE1394LINK/Transaction Controller xCSBUF Area (SRAM) . 11 7.2 IEEE1394 IEEE1394 PACKET FORMAT . 12 7.2.1 Transmit Packet Format . 12 7.2.2 Receive Packet Format. 14 7.3 IEEE1394 IEEE1394 HARDWARE SBP-2 CONTROL . 17 7.4 IDE INTERFACE CONTROL . 17 7.5 BUILT-IN CPU . 17 7.6 FLASH CONTROLLER . 18 8. INTERNAL REGISTER . 19 8.1 IEEE1394 IEEE1394 LINK CONTROLLER REGISTER MAPPING . 19 8.1.1 Register Table . 19 8.1.2 Register/Bit Table . 22 8.1.3 Register Map . 26 8.1.4 Detail Description of Register . 42 8.2 FLASH ROM CONTROL REGISTER . 88 9. ELECTRICAL CHARACTERISTICS . 91 9.1 ABSOLUTE MAXIMUM RATINGS . 91 9.2 RECOMMENDED OPERATING CONDITION . 91 9.3 DC CHARACTERISTICS (ACCORDING TO RECOMMENDED OPERATING CONDITION) . 92 9.4 AC CHARACTERISTICS . 94 9.4.1 Clock Timing . 94 9.4.2 PHY-LINK Interface Timing . 95 9.4.3 IDE Interface Timing . 96 9.4.4 CPU Interface Timing . 102 10. EXAMPLES OF EXTERNAL CONNECTION FOR REFERENCE PURPOSES . 103 11. SHAPE OF PACKAGE . 106 EPSON i S1R72801F00A S1R72801F00A 1. DESCRIPTION 2. FEATURES The S1R72801F00A S1R72801F00A is a LINK/Transaction controller based on the IEEE Std. 1394-1955, P1394a Draft 2.0. It integrates a built-in CPU and Flash ROM, and also integrates a part of transaction functions into hardware. If you set a PageTable address and its size, it can automatically fetch subsequent PageTables and transmit data. It can offer a 1394 interface optimum to computer peripherals in combination with the Cable PHY Transceiver Arbiter based on the above standard. q LINK/Transaction Controller LINK Layer Ready for all two-way data transfer in Asynchronous and Isochronous modes. The built-in SRAM realized stable two-way data transfer up to max. payload of 100Mbps, 200Mbps, and 400Mbps. Can automatically detect the Isochronous Resource Manager by hardware. Transaction Layer Integrates a part of transaction functions into hardware to prevent deterioration of actual data transmission rate due to the overhead of firmware (assure a special area). A header area is distinguished from a data area to simplify communications with a higher rank layer. Furthermore, it segments a data area to a stream area and ORB area. Adopts a ring buffer to the receive header area, receive data area (receive stream area, receive ORB area) and transmit data area (transmit stream area). Can arbitrarily set the size of each area. Automatically controls the Busy when hardware receives data. q SBP-2 Support Can set an PageTable address and its size for the SBP-2 to automatically perform subsequent Page Table fetches and data transfers. q PHY/LINK Interface Ready for the P1394a. Ready for the data transfer rate of 100/200/400Mbps. Ready for isolation (bus holder integrated) q IDE Interface Ready for the PIO mode 0/1/2/3/4, multi-word DMA mode 0/1/2, Ultra-DMA mode 0/1/2. Usable as a general port interface as well. EPSON 1 S1R72801F00A S1R72801F00A q Built-in CPU Integration of a CPU eliminated the necessity of an external CPU to control this IC. CPU core: 32-bit RISC CPU S1C33000 S1C33000 Harvard architecture (Concurrency of a fetch and load/store) High speed/high performance: Ready for operation with 50MHz Command set: 16-bit fixed length, 105 types of basic commands Execution cycle: Execution at one cycle/command regarding a main command AND/OR (MAC) operation: 16 bits × 16 bits + 64 bits, 2 clocks/ MAC (25 MOPS at 50MHz) CPU Register: 16 32-bit general registers and 5 32bit special registers Memory space:Linear space where 256-Mbyte (28bit) code, data, and I/O can be mapped. External bus interface: Directly connects the external memory of the memory area. Programmable wait cycle (7 cycles, Max.) Enables handshake through the XWAIT terminal. Interrupt: Ready for reset, NMI, max. 128 external interrupts, 4 software interrupts, and 2 exceptions Reset, boot: Cold reset, hot reset Built-in RAM: 8Kbytes 2 q Flash ROM Integration of a Flash ROM eliminated the necessity of a ROM to externally store programs. · Memory structure: Memory size 512K (32K × 16) bits · Sector size: 512 words/sector · Unit of erase: Per chip or sector · Unit of write: Writing with words · Erase/write time: Chip erase time 100ms (Standard) Sector erase time 20ms (Standard) Write time: 15µs (Standard) · Access time: 90nsec. (Max.) · Reliability: No. of erase/write 1,000 times Data retention: 10 years q Others A Boot ROM (4MBbytes, Max.) is connectable to outside of this IC. Supply voltage, 5.0V ± 10% and 3.3V ± 0.3V 184PinQFP (0.4mm pitch) Not radiation resistant. The CPU core built into this IC is an original 32-bit RISC CPU from SEIKO EPSON. Regarding the CPU core, refer to the E0C33208/204/202 E0C33208/204/202 TECHNICAL MANUAL. The built-in RAM is 8Kbytes. Note: In the built-in CPU core, a DMA controller and A/D converter are not integrated; this part is different from the description on the DMA controller and A/D converter given in TECHNICAL MANUAL (and Macro Manual). A low speed oscillation circuit (OSC1) is not available. EPSON S1R72801F00A S1R72801F00A 3. INTERNAL BLOCK DESCRIPTION 3.1 BLOCK DIAGRAM Intenal Packet Memory (8KByte) D [7:0] CTL [1:0] LREQ Buffer I/F Maneger LPS HDD [15:0] HDMARQ XHIOR XHIOW XHDMACK HIORDY HINTRQ IDE I/F TRAN & SBP2 Control XHPDIAG HDA [2:0] XCS [1:0] DMA for ATF IDE FIFO IsoTx FIFO SCLK 1394 LINK & TRAN Core 1394 PHY/LINK I/F Rx FIFO DMA for RF XHDASP BHEN XISO DMA for ITF IDE DMA LINKON AsyncTx FIFO XHRST ICEMD DSIO X2SPD XNMI XREST TVEP FLASH ROM 64KByte (32KWord X 16bit) CORE PAD Register for LINK&TRAN Register for 1394Tx/Rx C33_CORE (CPU, BCU, ITC, CLG, DBG) C33_SBUS Internal RAM (8KByte) C33 Core Block C33_PERI (Prescaaler, 8-bit timer, 16bit timer, Clock timer, Serial interface, Ports) PERI PAD OSC4 OSC3 PLLS1 PLLS0 Register for TRAN&SBP2 C33 Internal Memory Block Register for IDE C33 peripheral Block C33 Macro Block AD [23:0] DT [15:0] XCE10 XCE10_EX XCE [9:4] EA10MD EA10MD [1:0] XWAIT EXT_MD XRD XWR XWRH BCLK P[14:04] SRDY SCLK SOUT SIN Fig. 3.1 Block diagram 3.2 BLOCK DIAGRAM DESCRIPTION q C33 CORE Block The C33 CORE Block consists of the function blockC33_CORE- that includes the CPU, BCU (bus control unit), ITC (interrupt controller), CLG (clock generator), and DBG (debug unit), the external interface I/O pad block-PAD_CORE, PAD_CORE_OPTION-, and the block to interface with the peripheral circuits on the chip -SBUS-. q Internal RAM Block SRAM for the built-in memory area (Area 0). q C33_PERI Block (C33 peripheral circuit block) The C33_PERI Block consists of the PSC (prescaler), q Internal Flash Block Flash for the built-in memory area (Area 10). 6-channel T8 (8-bit programmable timer), WDT (watch dog timer), 6-channel T16 with an event counter (16-bit programmable timer), 4-channel SIO (serial interface), input and I/O ports, and CTM (clock timer). EPSON 3 S1R72801F00A S1R72801F00A BHEN XISO LINKON LPS LREQ CTL D SCLK MonxInt MonxWait P20 P21 P22 P23 LPS(P35) PD(P34) CNA(K64) K66 K67 4. INTERNAL CONNECTION DIAGRAM XRESET U_AD U_DT xCSREG xCSBUF xCSFREG xCSFLS xWRL xRD xWait xRST xINT(K65) SLEEP(P33) AD DT XCE10EX XCE10EX XCE9 XCE8 XCE6 U_AD U_DT xCSREG xCSBUF xWRL xRD xWait xRST xINT SLEEP 1394LINK 1394LINK Core XRD XWRL XWRH C33 Core BCLK XNMI X2SPDX ICEMD U_AD U_DT xCSFREG xWRL xRD DSIO OSC3 OSC4 PLLC PLLS1 PLLS0 U_AD U_DT xCS xRD EA10MD2 EA10MD2 EA10MD1 EA10MD1 FLASH Controller Flash ROM (64KB) P00 P01 P02 P03 P04 P05 P06 P07 P10 P11 P12 P13 P14 EA10MD0 EA10MD0 Fig. 4.1 Internal connection diagram 4 EPSON HDD HDA XHCS XHRST XHIOW XHIOR HDMARQ XHDMACK HIORDY XHPDIAG XHDASP HINTRQ S1R72801F00A S1R72801F00A 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 VSS N.C. P21 P20 XCE10EX XCE10EX XCE9 MonxWait XCE6 HVDD TO0 TO1 TO2 TO3 TO4 TO5 TO6 TO7 TI8 MonxInt VSS VSS VSS VSS LREQ LVDD SCLK VSS CNA XISO BHEN CTL0 CTL1 D0 D1 D2 LVDD D3 D4 D5 D6 D7 PD LPS LINKON N.C. LVDD 5. PIN ASSIGNMENT DIAGRAM EPSON S1R72801F00A S1R72801F00A TOP View INDEX 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 VSS N.C. XHRST HDD7 HDD8 HDD6 HDD9 HDD5 HDD10 HDD10 HVDD HDD4 HDD11 HDD11 HDD3 HDD12 HDD12 HDD2 HDD13 HDD13 HDD1 VSS HDD14 HDD14 HDD0 HDD15 HDD15 HDMARQ XHIOW XHIOR HIORDY HVDD XHDMACK HINTRQ HDA1 XHPDIAG HDA0 HDA2 XHCS0 XHCS1 TVEP VSS XHDASP FLSTST AD23 AD22 AD21 AD20 AD19 AD18 N.C. LVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 LVDD N.C. DT0 DT1 HVDD DT2 DT3 DT4 DT5 DT6 DT7 DT8 VSS DT9 DT10 DT11 DT12 DT13 DT14 DT15 HVDD XWRH XWRL XRD AD0 AD1 AD2 AD3 VSS AD4 AD5 AD6 AD7 AD8 AD9 AD10 HVDD AD11 AD12 AD13 AD14 AD15 AD16 AD17 N.C. VSS LVDD N.C. P22 P23 K66 K67 XWAIT P00 P01 VSS P02 P03 P04 P05 P06 P07 X2SPDX RAMTST VSS PLLC VSS PLLS0 PLLS1 EA10MD0 EA10MD0 EA10MD1 EA10MD1 EA10MD2 EA10MD2 HVDD P14 P13 P12 P11 VSS OSC3 OSC4 VSS P10 DSIO HVDD XNMI XRESET ICEMD VSS HCLK BCLK N.C. VSS EPSON 5 S1R72801F00A S1R72801F00A 6. PIN DESCRIPTION Control signals with an "X" as the first character of a pin name are low active. (Excluding X2SPD) Pin Name PIN I/O Reset Pin Function 1394PHY 1394PHY interface (LVDD ) D7 98 B Hi-Z (MSB) D6 99 B Hi-Z D5 100 B Hi-Z D4 101 B Hi-Z Data Bus with PHY D3 102 B Hi-Z D2 104 B Hi-Z D1 105 B Hi-Z D0 106 B Hi-Z (LSB) CTL1 107 B Hi-Z CTL0 108 B Hi-Z LREQ LPS LINKON XISO 115 96 95 110 O O I I BHEN 109 I CNA 111 I PD 97 O SCLK 113 I IDE Interface (HVDD) HDD15 HDD15 72 B HDD14 HDD14 74 B HDD13 HDD13 77 B HDD12 HDD12 79 B HDD11 HDD11 81 B HDD10 HDD10 84 B HDD9 86 B HDD8 88 B HDD7 89 B HDD6 87 B HDD5 85 B HDD4 82 B HDD3 80 B HDD2 78 B HDD1 76 B HDD0 73 B HDMARQ 71 B XHIOW 70 B XHIOR 69 B HIORDY 68 I XHDMACK 66 B HINTRQ 65 I XHPDIAG 63 I 6 Lo Lo ­ ­ ­ ­ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z ­ Hi-Z ­ ­ Remarks Try State Output Drive ability 12mA Schmitt Input (Bus Holder) Tray State Output Drive Ability 12mA Schmitt Input (Bus Holder) Drive Ability 12mA Drive Ability 12mA Schmitt Input (Bus Holder) CMOS Input LINK Request Signal to PHY LINK Power Status Signal to PHY LINK ON Signal from PHY Selects Connection to PHY (L: Annex-J Isolarion) Bus Holder Enable Signal (H: Enable) CMOS Schmitt Input Cabele Not Active Power Down Enable Clock Signal from PHY (49.152MHz) Schmitt Input (Bus Holder) (MSB) IDE Data Bus (LSB) IDE DMA Request Signal IDE Write Signal IDE Read Signal IDE IORDY Signal IDE DMA Acknowledge Signal IDE Interrupt Signal IDE PDIAG Signal EPSON Drive Ability 3mA Drive Ability 6mA Drive Ability 3mA Drive Ability 3mA S1R72801F00A S1R72801F00A Pin Name PIN I/O Reset IDE Interface (HVDD ) HDA2 61 Otr Hi-Z HDA1 64 Otr Hi-Z HDA0 62 Otr Hi-Z XHCS1 59 Otr Hi-Z XHCS0 60 Otr Hi-Z XHDASP 56 I ­ XHRST 90 Otr Hi-Z C33 External Interface (HVDD) AD23 54 O Lo AD22 53 O Lo AD21 52 O Lo AD20 51 O Lo AD19 50 O Lo AD18 49 O Lo AD17 44 O Lo AD16 43 O Lo AD15 42 O Lo AD14 41 O Lo AD13 40 O Lo AD12 39 O Lo AD11 38 O Lo AD10 36 O Lo AD9 35 O Lo AD8 34 O Lo AD7 33 O Lo AD6 32 O Lo AD5 31 O Lo AD4 30 O Lo AD3 28 O Lo AD2 27 O Lo AD1 26 O Lo AD0 25 O Lo DT15 20 B Hi-Z DT14 19 B Hi-Z DT13 18 B Hi-Z DT12 17 B Hi-Z DT11 16 B Hi-Z DT10 15 B Hi-Z DT9 14 B Hi-Z DT8 12 B Hi-Z DT7 11 B Hi-Z DT6 10 B Hi-Z DT5 9 B Hi-Z DT4 8 B Hi-Z DT3 7 B Hi-Z DT2 6 B Hi-Z DT1 4 B Hi-Z DT0 3 B Hi-Z Pin Function (MSB) IDE Address Signal (LSB) IDE Chip Select Signal IDE Chip Select Signal IDE DASP Signal IDE Reset Signal Remarks Drive Ability 3mA Drive Ability 6mA (MSB) CPU Address Bus (LSB) (MSB) CPU Data Buss (LSB) EPSON 7 S1R72801F00A S1R72801F00A Pin Name PIN I/O Reset C33 External Interface (HVDD) P07 154 B P06 153 B P05 152 B P04 151 B SRDY(P03) 150 B SCLK(P02) 149 B SOUT(P01) 147 B SIN(P00) 146 B K67 144 I K66 143 I P23 142 B P22 141 B P21 136 B P20 135 B XCE10 XCE10_EX 134 O Hi XCE9 133 O Hi XCE6 131 O Hi EA10M2 EA10M2 164 I EA10M1 EA10M1 163 I EA10M0 EA10M0 162 I XWAIT 145 I XRD 24 O Hi XWRH 22 O Hi XWRL 23 O Hi BCLK 182 O Hi C33 External Interface (LV DD) P14 166 B Lo P13 167 B Lo P12 168 B Lo P11 169 B Lo P10 174 B Lo DSIO 175 B Clock Generator Pin OSC4 172 O OSC3 171 I PLLS1 PLLS0 PLLC 8 161 160 158 I I ­ Pin Function General I/O Port 07 General I/O Port 06 General I/O Port 05 General I/O Port 04 Serial I/F Ready Signal Input Pin-cum-General I/O Port 03 Serial I/F Clock Input Pin-cum-General I/O Port 02 Serial I/F Data Output Pin-cum-General I/O Port 01 Serial I/F Data Input Pin-cum-General I/O Port 00 Remarks Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated Pull Up Resistor Integrated External Memory Area 10 Chip Enable Area 9 Chip Enable Area 6 Chip Enable Area 10 Boot Mode Select 2 Area 10 Boot Mode Select 1 Area 10 Boot Mode Select 0 Wait Cycle Input Read Signal Higher Order Byte Write Signal Lower Order Byte Write Signal Bus Clock Signal General I/O Port 14 (For ICD) General I/O Port 13 (For ICD) General I/O Port 12 (For ICD) General I/O Port 11 (For ICD) General I/O Port 10 (For ICD) Serial I/O Pin for Debug: Use for communication with ICD33 ICD33. Pull Up Resister Integrated High Speed Oscillation Output High Speed Oscillation Output (XTAL/Ceramic Oscillation or External Clock Input) PLL Set Pin 1 PLL Circuit is not usable. PLL Set Pin 0 Connect to GND. Capacitor Connection Pin for PLL Non-Connect Pin EPSON S1R72801F00A S1R72801F00A Pin Name Other Pins ICEMD PIN I/O Reset 179 I X2PSDX 155 I XNMI XRESET HCLK TVEP Test Pin TI8 TO7 TO6 TO5 TO4 TO3 TO2 TO1 TO0 FLSTST RAMTST MonxWait MonxInt Power Pin HVDD 177 178 181 58 I I O ­ 121 122 123 124 125 126 127 128 129 55 156 132 120 I O O O O O O O O I I O O ­ P LV DD ­ P VSS ­ P N.C. Pin N.C. ­ ­ Pin Function Remarks Pull Down Resistor Integrated Hi-Impedance Control: Set Hi-Z for all outputs. Bus Speed Mode Set Pin HIGH : BCLK = CPU Clock LOW : BCLK = Half CPU Clock NMIInput Pin Initial Reset Half SCLK Frequency Division Output Flash Test Pin Connect to HV DDwhen it is mounted. Schmitt Input (Bus Holder) ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ (MSB) (LSB) Built-in Flash Test Pin Built-in SRAM Test Pin Internal Logic xWait Monitor Pin Internal Logic xINT Monitor Pin Pull Down Resistor Integrated Pull Down Resistor Integrated HIGH HIGH Power (5V) 5,21,37,67,83,130,165,176 (8 Pins) LOW LOW Power (3.3V) 1,47,93,103,114,139 (6 Pins) GND 148,157,159,170,173,180,184 13,29,46,57,75,92,112,116,117, 118,119,138 (19 Pins) 2,45,48,91,94,137,140,183 (8 Pins) Table 6.1 Settings of EA10M2 EA10M2, EA10M1 EA10M1, and EA10M0 EA10M0 (Area 10 Boot Mode) P_EA10M2 EA10M2 P_EA10M1 EA10M1 P_EA10M0 EA10M0 Function 1 1 1 Built-in Flash Boot Mode 0 1 1 External ROM Mode Note) Other settings are not available on this IC. EPSON 9 S1R72801F00A S1R72801F00A 7. FUNCTIONAL DESCRIPTION 7.1 MEMORY MAP 7.1.1 All Memory Space Area Area 0 Address 0x000000 CPU-integrated RAM (8KB) 0x002000 (Mirror of CPU-integrated RAM) 0x030000 (Mirror of CPU-integrated Peripheral Circuit Control Register) 0x040000 CPU-integrated Peripheral Circuit Control Register 0x050000 (Mirror of CPU-integrated Peripheral Circuit Control Register) Area 2 0x060000 Reserved Area 3 Area 4 0x080000 0x100000 Reserved IEEE1394LINK/Transaction Controller Area 1 x CSREG Area (Control Register) 0x100080 Reserved 0x200000 Flash ROM Control Register 0x200008 Reserved Area 6 0x300000 Reserved Area 7 0x400000 IEEE1394LINK/Transaction Controller xCSBUF Area (SRAM: 8KB) 0x402000 Reserved Area 8 0x600000 Reserved Area 9 0x800000 Reserved Area 10 0xC00000 Area 5 Internal Flash ROM (64KB) 0xC10000 External ROM Reserved 0xFFFFFF 10 EPSON (4MB) S1R72801F00A S1R72801F00A 7.1.2 IEEE1394LINK/Transaction Controller xCSBUF Area (SRAM) 8KBytes 0x400000 HW_PageTableArea 0x4000C0 HW_RxHeaderArea 0x4000E0 HW_TxHeaderArea 0x400100 (RxHeaderAreaStart) HW_RxHeaderArea RxORBAreaStart RxHeaderArea (RingBuffer) TxHeaderAreaStart RxORBArea (RingBuffer) (TxHeaderAreaStart + 0x0040) TxHeaderArea (2 Headers) TxStreamAreaStart IDE ­> 1394 DMA Area TxORBArea (RingBuffer) TxStreamAreaEnd NotUsed RxStreamAreaStart 1394 ­> IDE DMA Area RxStreamArea (RingBuffer) 0x401FFF TxHeaderArea used Isocronouse used Asyncronouse only TxAreaStart + 0x20 TxAreaStart AsyTxPktHdr 0 + 0x20 + 0x30 + 0x40 AsyTxPktHdr 1 + 0x40 AsyTxPktHdr 0 IsoTxPktHdr 0 IsoTxPktHdr 1 · All RAM areas are accessible from the CPU by direct addressing. TxStreamAreaStart, TxStreamAreaEnd, and RxStreamAreaStart.) · Hardware DMA is possible to the IDE I/F for the RxStreamArea and TXStreamArea. · The TxStreamArea and RxStreamArea is usable as one StreamArea by overlaying them. · HW_PageTableArea (the equivalent of 24 pages) and HW_RxHeaderArea and HW_TXHeaderArea (the equivalent of 1 header, respectively) are assured. The RxORB and TxORB areas are usable by firmware alone. · The Post*Ptr and Used*Ptr of the RxHeaderArea, RxORBArea, TxStreamArea, and RxStreamArea monitor the used condition in each Area. (In the case of the Rx of 1394, the free space of the above two is monitored and the busy_A, B, X is controlled by hardware.) · The RxHeaderArea, RxORBArea, TxORB, TXStreamArea and RxStreamArea are RingBuffers. Even at the time of execution of data transmission/ reception according to 1394 or IDE DMA, data among the areas are guaranteed by hardware . (The size of each RingBuffer is variable by settings on the · By controlling the above functions from the TRAN & SBP2 Control Block, a PageTable fetch and data transfer according to SBP-2 are executable by hardware. EPSON 11 S1R72801F00A S1R72801F00A 7.2 IEEE1394 IEEE1394 PACKET FORMAT 7.2.1 Transmit Packet Format (1) TxAsyncronousePacket QuadReadReq, WriteResp b.31 24 23 ­ 0 1 2 3 4 5 6 7 Sbid 16 15 ­ 87 speed tl rt b.0 tcode (MSB) PacketTypeSpecInfo DestinationID pri (LSB) reserved ­ 1 QuadReadReq (tcode : 0x4) DestinationID 1 2 2 WriteResp 1 2 ACK (MSB) DestinationOffset (tcode : 0x2) DestinationID (LSB) rcode reserved (2) TxAsyncronousePacket QuadWriteReq, QuadReadResp, BlockReadReq b.31 0 1 2 3 4 5 6 7 1 QuadWriteReq 1 2 3 2 QuadReadResp 1 2 3 3 BlockReadReq 1 2 3 12 24 23 ­ Sbid 16 15 ­ DestinationID speed tl (MSB) PacketTypeSpecInfo PacketTypeSpecQuadletData 87 rt b.0 tcode pri (LSB) reserved ­ (tcode : 0x0) DestinationID (tcode : 0x6) DestinationID (tcode : 0x5) DestinationID ACK (MSB) DestinationOffset QuadletData (LSB) rcode reserved QuadletData (MSB) DestinationOffset DataLength (LSB) ExtendedTcode EPSON S1R72801F00A S1R72801F00A (3) TxAsyncronousePacket BlockWriteReq, BlockReadResp, LockReq, LockResp b.31 24 23 ­ 0 1 2 3 4 5 6 7 16 15 ­ Sbid 87 speed tl rt b.0 tcode pri (MSB) PacketTypeSpecInfo DestinationID (LSB) DataLength ExtendedTcode *DataPointer reserved ­ 1 BlockWriteReq LockReq 1 2 (tcode : 0x1) (tcode : 0x9) DestinationID 2 BlockReadResp LockResp 1 2 ACK (tcode : 0x7) (tcode : 0xB) DestinationID (MSB) DestinationOffset (LSB) rcode reserved (4) TxAsyncronousePhyPacket (tcode : 0xE) b.31 24 23 ­ 0 1 2 3 4 5 6 7 Sbid 16 15 ­ 0x0 PhyPacket 87 reserved tcode (0xE) b.0 reserved reserved (5) TxIsocoronousePacket (tcode : 0xA) b.31 24 23 ­ 0 1 2 3 Sbid 16 15 ­ speed tag DataLength 87 channel tcode (0xA) reserved b.0 sy *DataPointer reserved Transmit Packet Common Format Name speed Sbid Name ACK Bit count 3 1 Bit count 4 Description Speed Code 3'b000 3'b001 3'b010 All Other Value Souce Bus ID S100 S200 S400 Reserved 0:3FFh, 1:Source ID Description Received AckCode 4'h1 4'h2 4'h4 4'h5 4'h6 4'hB 4'hC 4'hD 4'hE 4'hF All Other Value ask_complete ask_pending ask_busy_X ask_busy_A ask_busy_B ask_tardy ask_confilict_error ask_data_error ask_type_error ask_address_error Reserved EPSON 13 S1R72801F00A S1R72801F00A 7.2.2 Receive Packet Format (1) RxAsyncronousePacket QuadReadReq, WriteResp b.31 24 23 ­ DestinationID SourceID 0 1 2 3 4 5 6 7 16 15 87 ­ speed tl AS BT 0 rt b.0 BC 0 tcode (MSB) PacketTypeSpecInfo ACK pri (LSB) reserved 1 QuadReadReq 2 3 2 WriteResp 2 3 (tcode : 0x4) SourceID (MSB) DestinationOffset (tcode : 0x2) SourceID (LSB) rcode reserved (2) RxAsyncronousePacket QuadWriteReq, QuadReadResp, BlockReadReq b.31 0 1 2 3 4 5 6 7 24 23 ­ DestinationID SourceID speed 87 ­ tl AS BT 0 rt b.0 BC 0 tcode (MSB) PacketTypeSpecInfo PacketTypeSpecQuadData ACK pri (LSB) reserved 1 QuadWriteReq 2 3 4 (tcode : 0x0) SourceID 2 QuadReadResp 2 3 4 (tcode : 0x6) SourceID 3 BlockReadReq 2 3 4 (tcode : 0x5) SourceID 14 16 15 (MSB) DestinationOffset QuadletData (LSB) rcode reserved QuadletData (MSB) DestinationOffset DataLength (LSB) ExtendedTcode EPSON S1R72801F00A S1R72801F00A (3) RxAsyncronousePacket BlockWriteReq, BlockReadResp, LockReq, LockResp b.31 24 23 16 15 ­ DestinationID SourceID 0 1 2 3 4 5 6 7 87 ­ speed tl AS BT 0 rt b.0 BC 0 tcode (MSB) PacketTypeSpecInfo DataLength ACK pri (LSB) ExtendedTcode *DataPointer reserved 1 BlockWriteReq LockReq (tcode : 0x1) (tcode : 0x9) SourceID 2 3 2 BlockReadResp LockResp 2 3 (MSB) DestinationOffset (tcode : 0x7) (tcode : 0xB) SourceID (LSB) rcode reserved (4) RxAsyncronousePhyPacket Normal (tcode : 0xE) b.31 24 23 16 15 ­ 0 1 2 3 4 5 6 7 87 ­ 0x0 reserved b.0 ­ AS BT 0 1 0 tcode (0xE) ACK reserved PhyPacket reserved (5) SelfIDPacket Received SelfID packets between BusReset and 1st-ArbRstGap (tcode : 0xE) b.31 0 1 2 3 4 5 6 7 24 23 16 15 DataLength 87 ­ reserved AS BT 1 1 0 ­ tcode (0xE) b.0 ACK reserved *DataPointer reserved EPSON 15 S1R72801F00A S1R72801F00A (6) RxIsocronousePacket (tcode : 0xA) b.31 0 1 2 3 4 5 6 7 24 23 16 15 speed ­ DataLength 87 ­ tag *DataPointer AS BT 0 channel b.0 1 0 ­ tcode (0xA) ACK sy reserved Receive Packet Common Format b.31 0 24 23 ­ Name speed AS BT SI BC HC ACK PSTS Bit count 3 1 1 1 1 1 4 4 16 15 speed 87 ­ ­ BC HC ACK Description Speed Code (Note 1) AreaStatus bit (1: StreamArea, 0: ORBArea) Bit which toggles during the BusReset period. Whether the received packet is a Self ID packet Whether the received packet is a Broadcast packet. Presence/absence of the Header CRC error (1: Packet disabled) Transmitted AckCode (Note 2) AckCode which was scheduled to be transmitted (Note 2) (Note 1) Refer to the Transmit Packet Common spd (speed code). (Note 2) Refer to the Transmit Packet Common Ack (AckCode). 16 AS BT SI b.0 EPSON S1R72801F00A S1R72801F00A 7.3 IEEE1394 IEEE1394 HARDWARE SBP-2 CONTROL The hardware SBP2 of this IC automatically executes a PageTable fetch and data transfer according to the Serial Bus Protocol 2 after receiving specifications of its PageTable Size and Address. The control of the SBP2 is performed by accessing the internal register. Data transfer is controlled by the transmission and reception of signals to and from the PHY-LINK interface and the transmission/reception of a series of packets are automatically executed by having access to the internal SRAM area. The functions of this block are as follows. This Block, (1) Receives specifications of a Page Table Size, Page Table Address, Speed Code, and Max Payload Size, etc. to automatically execute a PageTable fetch and data transfer according to the Serial Bus Protocol 2. (3) Allows you to perform the pause, resume, or reset during data transfer. Though the register value is retained even after the reset, the state machine is restored to the initial state. You can check transfer condition through the register any time. (4) Immediately enters the error pause when an error arises during data transfer by which you can check an error cause through the register. The resume from the error pause will pick up the transaction where the error arose. (5) Allows you to transfer data if you specify the omission of the PageTable fetch or Page Element No. to start data. (2) Can transfer data the equivalent of max. 24-page elements at one time. If no PageTable exists, you can transfer data by directly specifying a data length as a Page Table Size. 7.4 IDE INTERFACE CONTROL 7.5 BUILT-IN CPU This IC contains a block to control the IDE interface. Its functions are as follows. Regarding the built-in CPU, refer to the E0C33208/204/ E0C33208/204/ 202 TECHNICAL MANUAL (and E0C33 E0C33 Family ASIC Macro Manual). This block, (1) Accesses the IDE bus by having access to the Program mode of the CPU. The access to the data port of the CPU is available only in PIO mode. (2) Can monitor various kinds of signals of the IDE interface. In the built-in CPU core, however, a DMA controller and A/D converter are not integrated; this part is different from the description on the DMA controller and A/D converter given in TECHNICAL MANUAL (and Macro Manual). A low speed oscillation circuit (OSC1) is not available. (3) Controls the link-up of function blocks in accordance with the control signals and operation end signal from the DMA control circuit. (4) Manages the condition of data transfer in DMA mode of the IDE by the HDMARQ/XHDMACK signal. (5) Reads and writes the data of data bus DD15-0 DD15-0 of IDE from and to the FIFO in the 1394LINKCORE 1394LINKCORE by the XHIOR/XHIOW signal. If the FIFO becomes full or empty to disable data transfer, this block suspends data transfer with specified timing. EPSON 17 S1R72801F00A S1R72801F00A 7.6 FLASH CONTROLLER This IC is provided with a function to perform Erase and Write to the Flash ROM. (1) Chip Erase According to a specified sequence, you can erase all memory cells in the built-in Flash ROM to put them in "1" status. After erasing the chip, check that the data of all memory cells is "1". (2) Sector Erase This IC is ready for the Sector Erase in the unit of 512 words/sector. According to a specified sequence, you can erase all 18 memory cells in the built-in Flash ROM to put them in "1" status. After erasing the chip, check that the data of all memory cells is "1". (3) Write Write is complete if you continue writing Write data in the unit of word until writing of all sectors (512 words) finishes. On completion of the Sector Write, compare all data in the sectors with original data for confirmation. You cannot change the data of the memory cell from "0" to "1" by writing. EPSON S1R72801F00A S1R72801F00A 8. INTERNAL REGISTER 8.1 IEEE1394 IEEE1394 LINK CONTROLLER REGISTER MAPPING 8.1.1 Register Table (The base address of this register is 0x100000.) Address Register Name R/W Function 0x00 0x01 MainIntStat SubIntStat R(W) R(W) Main Interrupt Status Register Sub-Interrupt Status Register 0x02 0x03 (Reserved) DmaIntStat R(W) DMA Interrupt Status Register 0x04 0x05 LinkIntStat1 LinkIntStat0 R(W) R(W) LINK Core Interrupt Status Register 1 LINK Core Interrupt Status Register 0 0x06 0x07 PhyIntStat (Reserved) R(W) PHY Interrupt Status Register 0x08 0x09 MainIntEnb SubIntEnb R/W R/W Main Interrupt Enable Flag Register Sub-Interrupt Enable Flag Register 0x0A 0x0B (Reserved) DmaIntEnb R/W DMA Interrupt Enable Flag Register 0x0C 0x0D 0x0E LinkIntEnb1 LinkIntEnb0 PhyIntEnb R/W R/W R/W LINK Core Interrupt Enable Flag Register 1 LINK Core Interrupt Enable Flag Register 0 PHY Interrupt Enable Flag Register 0x0F 0x10 (Reserved) ChipCtl 0x11 0x12 HW_Revision (Reserved) 0x13 0x14 (Reserved) (Reserved) 0x15 0x16 (Reserved) (Reserved) 0x17 0x18 Relation R/W Chip Control Register R/W Hardware Revision Register (Reserved) LinkCtl_H R/W LINK Core Control Register Higher Rank 0x19 0x1A LinkCtl_L LinkStat R/W R LINK Core Control Register LINK Core Status Read Register Lower Rank 0x1B 0x1C PriReqCnt RetryLimit_H R R/W Priority Request Count Register Dual Retry Time Set Register 0x1D 0x1E RetryLimit_L MaxRetry R/W R/W Dual Retry Time Set Register Single Retry Number Set Register 0x1F 0x20 IRM_Stat NODE_IDS_H R/W R/W IRM Status Register Node IDS Status Register Higher Rank 0x21 0x22 NODE_IDS_L (Reserved) R/W Node IDS Status Register Lower Rank 0x23 0x24 (Reserved) PhyAccCtl_H R/W LINK Core Control Register Middle Rank 0x25 0x26 PhyAccCtl_L PhyRdstat_H R/W R LINK Core Control Register LINK Core Status Read Register Lower Rank 0x27 0x28 PhyRdstat_L ChnlIndex R/W R/W Priority Request Count Register ISO Async Stream Channel Index Register 0x29 0x2A ChnlWindow CmprIndex R/W R/W ISO Async Stream Channel Window Register Compare Offset Address Index Register 0x2B 0x2C CmpRW indow CYCLE_TIME_H R/W R/W Compare Offset Address Window Register Cycle Time Register EPSON Higher Rank Lower Rank Higher Rank 19 S1R72801F00A S1R72801F00A Address R/W Function 0x2D 0x2E CYCLE_TIME_MH CYCLE_TIME_ML R/W R/W Cycle Time Register Cycle Time Register 0x2F 0x30 CYCLE_TIME_L HwSBP2Ctl R/W R/W Cycle Time Register Hardware SBP2 Control Register 0x31 0x32 HwSBP2Stat HwSBP2IntStat R/W R(W) Hardware SBP2 Status Read Register Hardware SBP2 Interrupt Status Register 0x33 0x34 HwSBP2Index HwSBP2Window_H R/W R/W Hardware SBP2 Index Register Hardware SBP2 Window Register Higher Rank 0x35 0x36 HwSBP2Window_L PayloadSize_H R/W R/W Hardware SBP2 Window Register Hardware SBP2 Payload Size Set Register Lower Rank Higher Rank 0x37 0x38 PayloadSize_L PageTableSize_H R/W R/W Hardware SBP2 Payload Size Set Register Hardware PageTable Size Set Register Lower Rank Higher Rank 0x39 0x3A PageTableSize_L PageTableAdrs0 R/W R/W Hardware PageTable Size Set Register Hardware SBP2 PageTable Address Set Register Lower Rank Higher Rank 0x3B 0x3C PageTableAdrs1 PageTableAdrs2 R/W R/W Hardware SBP2 PageTable Address Set Register Hardware SBP2 PageTable Address Set Register 0x3D 0x3E PaqeTableAdrs3 PageTableAdrs4 R/W R/W Hardware SBP2 PageTable Address Set Register Hardware SBP2 PageTable Address Set Register 0x3F 0x40 PageTableAdrs5 LinkRxHdrPtr_H R/W R/W Hardware SBP2 PageTable Address Set Register Receive Header LINK Pointer Register Lower Rank Higher Rank 0x41 0x42 LinkRxHdrPtr_L LinkRxORBPtr_H R/W R/W Receive Header LINK Pointer Register Receive ORB Data LINK Pointer Register Lower Rank Higher Rank 0x43 0x44 LinkRxORBPtr_L LinkRxStreamPtr_H R/W R/W Receive ORB Data LINK Pointer Register Receive Stream Data LINK Pointer Register Lower Rank Higher Rank 0x45 0x46 LinkRxStreamPtr_L LinkTxStreamPtr_H R/W R Receive Stream Data LINK Pointer Register Receive Stream Data LINK Pointer Register Lower Rank Higher Rank 0x47 0x48 0x49 LinkTxStreamPtr_L UsedRxHdrPtr_H UsedRxHdrPtr_L R R/W R/W Receive Stream Data LINK Pointer Register Used Receive Header Pointer Register Used Receive Header Pointer Register Lower Rank Higher Rank Lower Rank 0x4A 0x4B UsedRxORBPtr_H UsedRxORBPtr_L R/W R/W Used Receive ORB Data Pointer Register Used Receive ORB Data Pointer Register Higher Rank Lower Rank 0x4C 0x4D IDE_RxStreamPtr_H IDE_RxStreamPtr_L R/W R/W Receive Stream Data IDE Pointer Register Receive Stream Data IDE Pointer Register Higher Rank Lower Rank 0x4E 0x4F IDE_TxStreamPtr_H IDE_TxStreamPtr_L R/W R/W Receive Stream Data IDE Pointer Register Receive Stream Data IDE Pointer Register Higher Rank Lower Rank 0x50 0x51 BufControl BufMonitor R/W R Buffer Control Register Buffer Monitor Register 0x52 0x53 AsyDmaCtl IsoDmaCtl R/W R/W Async TxDMA Control Register ISO TxDMA Control Register 0x54 0x55 RxDmaCtl AreaIndex R/W R/W RxDMA Control Register Memory Map Area Set Index Register 0x56 0x57 AreaWindow_H AreaWindow_L R/W R/W Memory Map Area Set Window Register Memory Map Area Set Window Register Higher Rank Lower Rank 0x58 0x59 BRstHdrPtr_H BRstHdrPtr_L R R Bus Reset Header Pointer Register Bus Reset Header Pointer Register Higher Rank Lower Rank 0x5A 0x5B BRstORBPtr_H BRstORBPtr_L R R Bus Reset ORB Pointer Register Bus Reset ORB Pointer Register Higher Rank Lower Rank 0x5C 0x5D (Reserved) (Reserved) 0x5E 0x5F 20 Register Name MaintCtl_H MaintCtl_L Maintenance Control Register Maintenance Control Register Higher Rank Lower Rank R/W R/W EPSON Relation Lower Rank S1R72801F00A S1R72801F00A Address Register Name R/W Function 0x60 0x61 IDE_Config0 IDE_Config1 R/W R/W IDE Configuration Register IDE Configuration Register 0x62 0x63 IDE_RegAccCyc IDE_PioDmaCyc R/W R/W IDE Register Access Cycle Register IDE PIO/DMA Cycle Register 0x64 0x65 IDE_UltraDmaCyc IDE_DmaCtl R/W R/W IDE Ultra DMA Cycle Register IDE DMA Control Register 0x66 0x67 IDE_BusStat IDE_DmaStat R/W R/W IDE Bus Status Read Register IDE DMA Status Register 0x68 0x69 IDE_ByteCount0 IDE_ByteCount1 R/W R/W IDE Byte Count Set Register IDE Byte Count Set Register 0x6A 0x6B IDE_ByteCount2 IDE_ByteCount3 R/W R/W IDE Byte Count Set Register IDE Byte Count Set Register Lower Rank 0x6C 0x6D IDE_CRC0 IDE_CRC1 CRC Read Register CRC Read Register Higher Rank Lower Rank 0x6E 0x6F (Reserved) (Reserved) 0x70 0x71 IDE_CS00 IDE_CS01 R/W R/W IDE Command Block Register IDE Command Block Register 0x72 0x73 IDE_CS02 IDE_CS03 R/W R/W IDE Command Block Register IDE Command Block Register 0x74 0x75 IDE_CS04 IDE_CS05 R/W R/W IDE Command Block Register IDE Command Block Register 0x76 0x77 IDE_CS06 IDE_CS07 R/W R/W IDE Command Block Register IDE Command Block Register 0x78 0x79 IDE_CS10 IDE_CS11 R/W R/W IDE Command Control Register IDE Command Control Register 0x7A 0x7B 0x7C IDE_CS12 IDE_CS13 IDE_CS14 R/W R/W R/W IDE Command Control Register IDE Command Control Register IDE Command Control Register 0x7D 0x7E IDE_CS15 IDE_CS16 R/W R/W IDE Command Control Register IDE Command Control Register 0x7F IDE_CS17 R/W IDE Command Control Register R R EPSON Relation Higher Rank 21 S1R72801F00A S1R72801F00A 8.1.2 Register/Bit Table The base address of this register is 0x100000. Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 22 Register Name MainIntStat SubIntStat (Reserved) DmaIntStat LinkIntStat1 LinkIntStat0 PhyIntStat (Reserved) MainIntEnb SubIntEnb (Reserved) DmaIntEnb LinkIntEnb1 UltraDmaMode PhyIntEnb (Reserved) ChipCtl HW_Revision ApetusTestOutPut_H ApetusTestOutPut_L LCTestIndex LCTestWindow SBP2TestIndex SBP2TestWindow LinkCtl_H LinkCtl_L LinkStat PriReqCnt RetryLimit_H RetryLimit_L MaxRetry IRM_Stat NODE_IDS_H NODE_IDS_L (Reserved) (Reserved) PhyAccCtl_H PhyAccCtl_L PhyRdstat_H PhyRdstat_L ChnlIndex ChnlWindow CmprIndex CmprWindow CYCLE_TIME_H CYCLE_TIME_MH CYCLE_TIME_ML CYCLE_TIME_L bit7 SubIntStat SelfIDdone bit6 TxIsoCmp SelfIDerr bit5 bit4 bit3 bit2 RxDmaCmp TxAsyCmp HwSBP2Cmp IDE_DmaCm HwSBP2Err HwSBP2BRs LinkIntStat1 LinkIntStat0 TxAsyRtyGo TxAsyBCSent RxDmaFaild UnExpCh SubGap DupliCh ArbGap IsoArbFaild CycTooLong TxAsyFaild RxOnTardy CycOverFlw TxIsoFaild RxHcrcErr CycEvent Phy_int bit1 IDE_INTRQ PhyIntStat bit0 BusReset DmaIntStat TxAsyBRAbort RxUnkTcode CycLost PhyWrDone TxAsyMiss TxRtyExced CycArbFail PhyRdDone EnSubIntStat EnTxIsoCmp EnRxDmaCmp EnTxAsyCmp EnHwSBP2Cm EnIDE_DmaC EnIDE_INTRQ EnBusReset EnSelfIDdone EnSelfIDerr EnHwSBP2Err EnHwSBP2BRst EnLinkIntStat1 EnLinkIntStat0 EnPhyIntStat EnDmaIntStat EnTxAsyRtyGo EnTxAsyBCSe EnRxDmaFaild EnTxAsyFaild EnTxIsoFaild EnTxAsyBRAb EnTxAsyMiss EnRxOnTardy EnRxHcrcErr EnRxUnkTcod EnTxRtyExced EnUnExpCh EnDupliCh EnIsoArbFaild EnCycTooLon EnCycOverFlw EnCycEvent EnCycLost EnCycArbFail EnSubGap EnArbGap EnPhy_int EnPhyWrDone EnPhyRdDone Suspend IDE_MdlRst SendTardy SoftReset HW_Revision[7:0] Chip Test Register PassSelfID EnLink PassPhyPkt PassBrPkt PLIFrst EnPosWB IgnrBChdr APHY EnAcc RxBusyMode DualRtyEnb ID_Valid Root Priority Budget Request Count [5:0] CycLimit[12:8] CycLimit[7:0] MaxRetry[3:0] IRM_ID[5:0] BusID[9:2] Physical ID[5:0] SecLimit[2:0] NoIRM WonIRM BusID[1:0] RdReq EnPosWQ IgnrBCdata WrReq Cmstr SinglRtyEnb CablPwSts Request Address[3:0] Write Data[7:0] Read Address[3:0] Read Data[7:0] Channel Index Channel Window Compare Address Index Compare Address Window Cycle Second[6:0] Cycle Count[11:4] Cycle Count[3:0] Cycle Offset[11:8] Cycle Offset[7:0] EPSON CycCnt[12] S1R72801F00A S1R72801F00A Address 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F Register Name HwSBP2Ctl HwSBP2Stat HwSBP2IntStat HwSBP2Index HwSBP2Window_H HwSBP2Window_L PayloadSize_H PayloadSize_L PageTableSize_H PageTableSize_L PageTableAdrs0 PageTableAdrs1 PageTableAdrs2 PaqeTableAdrs3 PageTableAdrs4 PageTableAdrs5 LinkRxHdrPtr_H LinkRxHdrPtr_L LinkRxORBPtr_H LinkRxORBPtr_L LinkRxStreamPtr_H LinkRxStreamPtr_L LinkTxStreamPtr_H LinkTxStreamPtr_L UsedRxHdrPtr_H UsedRxHdrPtr_L UsedRxORBPtr_H UsedRxORBPtr_L IDE_RxStreamPtr_H IDE_RxStreamPtr_L IDE_TxStreamPtr_H IDE_TxStreamPtr_L BufControl BufMonitor AsyDmaCtl IsoDmaCtl RxDmaCtl AreaIndex AreaWindow_H AreaWindow_L BRstHdrPtr_H BRstHdrPtr_L BRstORBPtr_H BRstORBPtr_L (Reserved) (Reserved) MaintCtl_H MaintCtl_L bit7 bit6 PtNotPresen HOSTtoDev FwPause ErrPause SplitTimeOut TxAckedIlleg bit5 FromStream TxAckMiss (MSB) (MSB) (MSB) bit4 bit3 bit2 bit1 bit0 HwSBP2Rst HwSBP2Rsu HwSBP2Pau HwSBP2Star WaitPLRead HwSBP2Exe PTaskExec StTaskExec TranExec BRAbort RxNotRespCm RxBroadCast RxAckDataErr HwSBP2 Index HwSBP2 Window (LSB) Payload Size (LSB) Page Table Size (LSB) (MSB) Page Table Offset Address (LSB) LinkRxHdrPtr[12:8] LinkRxHdrPtr[7:5] LinkORBPointer[12:8] LinkRxORBPtr[7:2] LinkRxStreamPtr[12:8] LinkRxStreamPtr[7:2] LinkTxStreamPtr[12:8] LinkTxStreamPtr[7:2] UsedRxHdrPtr[12] UsedRxHdrPtr[7:5] UsedRxORBPtr[12:8] UsedRxORBPtr[7:2] IDE_RxStreamPtr[12:8] IDE_RxStreamPtr[7:2] IDE_TxStreamPtr[12:8] TxStreamClr RxStreamClr RxPayldRdy TxPayldRdy AsyChnlSel IsoChnlSel IDE_TxStreamPtr[7:2] RxORBClr RxHdrClr UpdLinkTxStrm RxHdrRemain RxORBFull RxStreamFull RxHdrFull BlkWrAreaSel AsyFIFOEpty AsyFIFOClr AsyTxMon AsyStart SelTxPtr IsoFIFOEpty IsoFIFOClr IsoTxMon IsoStart RxFIFOEpty RxFIFOClr RxMon ForceBusy Memory Map Area Index Memory Map Area Window (LSB) BusReset Header Pointer[12:8] (MSB) BusResetHeaderPointer[7:5] BusResetORBPointer[12:8] BusResetORBPointer[7:2] E_Hcrc E_Dcrc No_Pkt F_Ack N_ack Ack[7:0] EPSON 23 S1R72801F00A S1R72801F00A Address 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F Register Name bit7 bit6 bit5 IDE_Config0 UltraDmaMode DmaMode ActPort IDE_Config1 IDE_Reset IDE_RegAccCyc Assert Pulse[3:0] IDE_PioDmaCyc Assert Pulse[3:0] IDE_UltraDmaCyc IDE_DmaCtl IDE_BusStat DMARQ DMACK INTRQ IDE_DmaStat IDE_ByteCount0 (MSB) IDE_ByteCount1 IDE_ByteCount2 IDE_ByteCount3 IDE_CRC0 (MSB) IDE_CRC1 IDE_TestIndex IDE_TestWindow IDE_CS00 Command Block register IDE_CS01 Command Block register IDE_CS02 Command Block register IDE_CS03 Command Block register IDE_CS04 Command Block register IDE_CS05 Command Block register IDE_CS06 Command Block register IDE_CS07 Command Block register IDE_CS10 Control Block Register IDE_CS11 Control Block Register IDE_CS12 Control Block Register IDE_CS13 Control Block Register IDE_CS14 Control Block Register IDE_CS15 Control Block Register IDE_CS16 Control Block Register IDE_CS17 Control Block Register bit4 IDE_Slave CRC_Clear IORDY bit3 DMARQ_Leve FIFO_Clear bit2 Swap bit1 Negate Pulse[3:0] Negate Pulse[3:0] Cycle Time[3:0] IDE_Abort IDE_Directio DIAG DmaPause bit0 DmaStart DASP DmaRun IDE DMA xfer Byte Count (LSB) Ultra DMA CRC Value (LSB) Chip Test Register R- Data R- Error R- Sector Count R- Sector Number/LBA[bit0-7] R- Cylinder Low/LBA[bit8-15] R- Cylinder High/LBA[bit[16-23] R- Device/Head,LBA[bit24-27] R- Status R- Data Bus Hi-Impedence R- Data Bus Hi-Impedence R- Data Bus Hi-Impedence R- Data Bus Hi-Impedence R- Data Bus Hi-Impedence R- Data Bus Hi-Impedence R- Alternate Status R- (obsolete) W- Data W- Features W- Sector Count W- Sector Number/LBA[bit0-7] W- Cylinder Low/LBA[bit8-15] W- Cylinder High/LBA[bit[16-23] W- Device/Head,LBA[bit24-27] W- Command W- Not Used W- Not Used W- Not Used W- Not Used W- Not Used W- Not Used W- Device Control W- Not Used LinkChnnel Index/Window Register ChnlIndex ChnlWindow 0x00 ChannelAvailableH0 0x01 ChannelAvailableH1 0x02 ChannelAvailableH2 0x03 ChannelAvailableH3 0x04 ChannelAvailableL0 0x05 ChannelAvailableL1 0x06 ChannelAvailableL2 0x07 ChannelAvailableL3 0x08 ReceiveChannel0 0x09 ReceiveChannel1 0x0A ReceiveChannel2 0x0B ReceiveChannel3 0x0C ReceiveChannel4 0x0D ReceiveChannel5 0x0E ReceiveChannel6 0x0F ReceiveChannel7 24 bit7 ch08 ch16 ch24 ch32 ch40 ch48 ch56 ch00 ch08 ch16 ch24 ch32 ch40 ch48 ch56 bit6 ch01 ch09 ch17 ch25 ch33 ch41 ch49 ch57 ch01 ch09 ch17 ch25 ch33 ch41 ch49 ch57 bit5 ch02 ch10 ch18 ch26 ch34 ch42 ch50 ch58 ch02 ch10 ch18 ch26 ch34 ch42 ch50 ch58 bit4 ch03 ch11 ch19 ch27 ch35 ch43 ch51 ch59 ch03 ch11 ch19 ch27 ch35 ch43 ch51 ch59 EPSON bit3 ch04 ch12 ch20 ch28 ch36 ch44 ch52 ch60 ch04 ch12 ch20 ch28 ch36 ch44 ch52 ch60 bit2 ch05 ch13 ch21 ch29 ch37 ch45 ch53 ch61 ch05 ch13 ch21 ch29 ch37 ch45 ch53 ch61 bit1 ch06 ch14 ch22 ch30 ch38 ch46 ch54 ch62 ch06 ch14 ch22 ch30 ch38 ch46 ch54 ch62 bit0 ch07 ch15 ch23 ch31 ch39 ch47 ch55 ch63 ch07 ch15 ch23 ch31 ch39 ch47 ch55 ch63 S1R72801F00A S1R72801F00A Compare Address Index/Window Register CmprIndex 0x00 0x01 0x02 0x03 0x04 0x05 0x06 : 0x0F ChnlWindow CompareDOffset0 CompareDOffset1 CompareDOffset2 CompareDOffset3 CompareDOffset4 CompareDOffset5 (Reserved) (Reserved) (Reserved) bit7 (MSB) bit6 bit5 bit4 bit3 bit2 bit1 bit0 Compare Destination Offset Address[47:0] (LSB) H/W SBP2 Index Chnnel/Window Register SBP2Index SBP2Window_H/L 0x00 PageBoundary PageElementNunber 0x01 PgElmentRemain_H PgElmentRemain_L 0x02 SpeedCode MaxPayload 0x03 DestinationID_H DestinationID_L 0x04 SplitTime_H SplitTime_L 0x05 (Reserved) : (Reserved) 0x0F (Reserved) bit7 bit6 bit5 (MSB) bit4 bit3 bit2 bit1 bit0 PageBoundary[2:0] PageElementNumber[4:0] Page Element Remain Length (Bytes) (LSB) SpeedCode[2:0] MaxPayload[3:0] (MSB) Destination_ID Value Second[2:0] (LSB) Cycle Count[12:8] Cycle Count[7:0] Memory Map Area Index/Window Register AreaIndex AreaWindow_H/L 0x00 RxORBAreaStart_H RxORBAreaStart_L 0x01 TxHdrAreaStart_H TxHdrAreaStart_L 0x02 TxStreamAreaStart_H TxStreamAreaStart_L 0x03 TxStreamAreaEnd_H TxStreamAreaEnd_L 0x04 RxStreamAreaStart_H RxStreamAreaStart_L 0x05 (Reserved) : (Reserved) 0x0F (Reserved) bit7 bit6 bit5 bit4 (MSB) RxORBAreaStart[7:2] (MSB) TxHdrAreaStart[7:2] (MSB) TxStreamAreaStart[7:2] (MSB) TxStreamAreaEnd[7:2] (MSB) RxStreamAreaStart[7:2] EPSON bit3 bit2 bit1 RxORBAreaStart[12:8] (LSB) TxHdrAreaStart[12:8] (LSB) TxStreamAreaStart[12:8] (LSB) TxStreamAreaEnd[12:8] (LSB) RxStreamAreaStart[12:8] (LSB) bit0 25 S1R72801F00A S1R72801F00A 8.1.3 Register Map (The base address of this register is 0x100000.) Address Register Name 0x00 0x01 MainIntStat SubIntStat UltraDmaMode 0x02 0x03 0x04 0x05 0x06 0x07 26 (Reserved) DmaIntStat LinkIntStat1 LinkIntStat0 PhyIntStat (Reserved) Bit Symbol R/W 7:SubIntStat 6: TxIsoCmp 5: RxDmaCmp 4: TxAsyCmp 3: HwSBP2Cmp 2: IDE_DmaCmp 1: IDE_INTRQ 0: BusReset R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Sub Interrupt Occurred 1: ISO Pkt Transmit Done 1: Packet Reception 1: AckCode Reception 1: HwSBP2 Process Complete 1: IDE DMA Transmit Complete 1: IDE Interface Interrupt 1: Bas Reset Detected 7: SelfIDdone 6: SelfIDerr 5: HwSBP2Err 4: HwSBP2BRst 3: LinkIntStat1 2: LinkIntStat0 1: PhyIntStat 0: DmaIntStat R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Self-ID Phase Done 1: Self-ID Packet Error 1: Hw SBP2 Error 1: BusReset in process HwSBP 1: Link1 Interrupt Occurred 1: Link0 Interrupt Occurred 1: PHY Interrupt Occurred 1: Dma Interrupt Occurred 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 0: 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: 1: Async Tx Retry Go 1: AsyncTxBroadcast Sent 1: Rx DMA Failed 1: Async Tx Failed 1: ISO Tx Failed 1: Async Tx BusReset Abort 1: AsyncTxAckCodeMissing 0: 0: 0: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: TxAsyRtyGo 5: TxAsyBCSent 4: RxDmaFaild 3: TxAsyFaild 2: TxIsoFaild 1: TxAsyBRAbort 0: TxAsyMiss R(W) R(W) R(W) R(W) R(W) R(W) R(W) Description 7: 6: 5: 4: 3: RxOnTardy 2: RxHcrcErr 1: RxUnkTcode 0: TxRtyExced R(W) R(W) R(W) R(W) 0: None 0: None 0: None 0: None 1: 1: 1: 1: 1: Ack_tardy Sent 1: Rx Packet Header CRC Err 1: Rx Packet Tcode Unknown 1: Tx Retry Exceeded 7: UnExpCh 6: DupliCh 5: IsoArbFaild 4: CycTooLong 3: CycOverFlw 2: CycEvent 1: CycLost 0: CycArbFail R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Unknown Expected Channel 1: DuplicateChannelDetected 1: Iso Arbtration Failed 1: ISO Arbitration Failed 1: Cycle Timer Over Fullow 1: Local Cycle Event Occured 1: Cycle Start Packet Lost 1: CycleStartPkt Arbtration Fail 7: SubGap 6: ArbGap 5: 4: 3: 2: Phy_int 1: PhyWrDone 0: PhyRdDone R(W) R(W) 0: None 0: None 0: 0: 0: 0: None 0: None 0: None 1: Sub Action Gap Detected 1: ArbtrationResetGapDetected 1: 1: 1: 1: PHY Interrupt Detected 1: PHY Register Write Done 1: PHY Register Read Done 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 7: 6: 5: 4: 3: 2: 1: 0: R(W) R(W) R(W) EPSON H.Rst S.Rst B.Rst 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ S1R72801F00A S1R72801F00A Address 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Register Name MainIntEnb SubIntEnb (Reserved) DmaIntEnb LinkIntEnb1 LinkIntEnb0 PhyIntEnb (Reserved) Bit Symbol R/W 7: EnSubIntStat 6: EnTxIsoCmp 5: EnRxDmaCmp 4: EnTxAsyCmp 3: EnHwSBP2Cmp 2: EnIDE_DmaCmp 1: EnIDE_INTRQ 0: EnBusReset R/W R/W R/W R/W R/W R/W R/W R/W 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 7: EnSelfIDdone 6: EnSelfIDerr 5: EnHwSBP2Err 4: EnHwSBP2BRst 3: EnLinkIntStat1 2: EnLinkIntStat0 1: EnPhyIntStat 0: EnDmaIntStat R/W R/W R/W R/W R/W R/W R/W R/W 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: R/W R/W R/W R/W R/W R/W R/W 0: 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 7: 6: 5: 4: 3: EnRxOnTardy 2: EnRxHcrcErr 1: EnRxUnkTcode 0: EnTxRtyExced R/W R/W R/W R/W 0: 0: 0: 0: 0: Disable 0: Disable 0: Disable 0: Disable 1: 1: 1: 1: 1: Enable 1: Enable 1: Enable 1: Enable 7: EnUnExpCh 6: EnDupliCh 5: EnIsoArbFaild 4: EnCycTooLong 3: EnCycOverFlw 2: EnCycEvent 1: EnCycLost 0: EnCycArbFail R/W R/W R/W R/W R/W R/W R/W R/W 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 0: Disable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 1: Enable 7: EnSubGap 6: EnArbGap 5: 4: 3: 2: EnPhy_int 1: EnPhyWrDone 0: EnPhyRdDone R/W 0: Disable R/W 0: Disable 0: 0: 0: R/W 0: Disable R/W 0: Disable R/W 0: Disable 1: Enable 1: Enable 1: 1: 1: 1: Enable 1: Enable 1: Enable 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: EnTxAsyRtyGo 5: EnTxAsyBCSent 4: EnRxDmaFaild 3: EnTxAsyFaild 2: EnTxIsoFaild 1: EnTxAsyBRAbort 0: EnTxAsyMiss 7: 6: 5: 4: 3: 2: 1: 0: Description 0: 0: 0: 0: 0: 0: 0: 0: EPSON 1: 1: 1: 1: 1: 1: 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 27 S1R72801F00A S1R72801F00A Address 0x10 0x11 Register Name ChipCtl HW_Revision UltraDmaMode 0x12 0x13 0x14 0x15 0x16 0x17 28 (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) Bit Symbol 7: Suspend 6: 5: 4: 3: 2: IDE_MdlRst 1: SendTardy 0: SoftReset 7: HW_Revision[7] 6: HW_Revision[6] 5: HW_Revision[5] 4: HW_Revision[4] 3: HW_Revision[3] 2: HW_Revision[2] 1: HW_Revision[1] 0: HW_Revision[0] 7: 6: 5: 4: 3: 2: 1: 0: R/W Description H.Rst R/W 0: Resume 1: Suspend 0: 1: 0: 1: 0: 1: 0x00 0: 1: W 0: None 1: IDE_Module Reset R/W 0: None 1: Send Ack_tardy W 0: None 1: Reset Start R Indicate Hard Ware Revison Number 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 7: 6: 5: 4: 3: 2: 1: 0: 7: 6: 5: 4: 3: 2: 1: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 1: 7: 6: 5: 4: 3: 2: 1: 0: 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: EPSON S.Rst B.Rst 0x00 ­ 0x03 0x03 0x03 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ S1R72801F00A S1R72801F00A Address Register Name Bit Symbol 0x18 LinkCtl_H 7: PassSelfID 6: PassPhyPkt 5: PassBrPkt 4: EnPosWB 3: EnPosWQ 2: APHY 1: EnAcc 0: Cmstr 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F LinkCtl_L LinkStat PriReqCnt RetryLimit_H RetryLimit_L MaxRetry IRM_Stat 7: EnLink 6: 5: PLIFrst 4: IgnrBChdr 3: IgnrBCdata 2: RxBusyMode 1: DualRtyEnb 0: SinglRtyEnb 7: 6: 5: 4: 3: 2: ID_Valid 1: Root 0: CablPwSts 7: 6: 5: PriReq[5] 4: PriReq[4] 3: PriReq[3] 2: PriReq[2] 1: PriReq[1] 0: PriReq[0] 7: SecLimit[2] 6: SecLimit[1] 5: SecLimit[0] 4: CycLimt[12] 3: CycLimt[11] 2: CycLimt[10] 1: CycLimt[9] 0: CycLimt[8] 7: CycLimt[7] 6: CycLimt[6] 5: CycLimt[5] 4: CycLimt[4] 3: CycLimt[3] 2: CycLimt[2] 1: CycLimt[1] 0: CycLimt[0] 7: 6: 5: 4: 3: maxRty[3] 2: maxRty[2] 1: maxRty[1] 0: maxRty[0] 7: NoIRM 6: WonIRM 5: IRMID[5] 4: IRMID[4] 3: IRMID[3] 2: IRMID[2] 1: IRMID[1] 0: IRMID[0] R/W R R R 1: Enable Link 1: 1: Reset PHY/Link I/F 1: Ignore BC Packet 1: Ignore BC­Data 1: Single 1: Dual Retry Enable 1: Single Retry Enable 1: 1: 1: 1: 1: 1: PhyID Valid 1: Self Node = Root 1: Cable Power Status OK 0: 0: W R/W R/W R/W R/W R/W 0: Disable Link 0: 0: NONE 0: BC Pkt to DMA FIFO 0: BC Data to DMA FIFO 0: Dual 0: Dual Retry Disable 0: Single Retry Disable 0: 0: 0: 0: 0: 0: PhyID Invalid 0: Self Node = Not Root 0: Cable Power Status NG B.Rst 0x00 ­ ­ ­ 0 0 0 0 0 0 ­ ­ ­ ­ ­ ­ 0x00 ­ ­ 0x00 0x00 0x00 R/W S.Rst 0x00 R/W Description H.Rst 0: Non PassSelfID 1: Self­ID to DMA FIFO 0: Non Pass PHY Packet 1: PHY Pkt to DMA FIFO 0: Non Pass BusRst Packet 1: BusRst Pkt to DMA FIFO 0: Disable Posted WB 1: Enable Posted WB 0x00 0: Disable Poosted WQ 1: Enable Posted WQ 0: PHY 1394.a uncorrespond 1: PHY 1394.a correspond 0: Ack Acceleration Disable 1: Ack Acceleration Enable 0: Cycle Master Not Capabl 1: Cycle Master Capable 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x3F ­ 0x3F 1: 1: R/W Maximum Number of certain Priority Arb Request R/W 0x00 Dual Phase Retry Limit Second Limit R/W Cycle Limit If (SecLimit = 0 and CycLimit=0) Dual Phase is ignore R/W R R(W) R 0: 1: 0: 1: 0: 1: 0: 1: Single Phase Retry Limit Max Retry Count Value If maxRty = 0, Single Phase Retry is ignore 0: Exist IRM Node 0: Other Node 1: None IRM Node 1: Self Node Physical ID of IRM Node No exist IRM Node then IRMID= 0x3F EPSON 29 S1R72801F00A S1R72801F00A Address 0x20 0x21 Register Name NODE_IDS_H NODE_IDS_L UltraDmaMode 0x22 (Reserved) Bit Symbol 7: BusID[9] 6: BusID[8] 5: BusID[7] 4: BusID[6] 3: BusID[5] 2: BusID[4] 1: BusID[3] 0: BusID[2] 7: BusID[1] 6: BusID[0] 5: PhyID[5] 4: PhyID[4] 3: PhyID[3] 2: PhyID[2] 1: PhyID[1] 0: PhyID[0] R/W Description R/W Serial Bus ID Number Single Bus, Bus ID = 0x3FF Multiple Bus, Bus ID is uniquely specifying 7: 6: 5: 4: 2: 1: 0: (Reserved) 7: 6: 5: 4: 3: 2: 1: 0: 0x24 0x25 0x26 0x27 30 PhyAccCtl_H PhyAccCtl_L PhyRdstat_H PhyRdstat_L 7: RdReq 6: WrReq 5: 4: 3: ReqAdd[3] 2: ReqAdd[2] 1: ReqAdd[1] 0: ReqAdd[0] 7: WrDat[7] 6: WrDAt[6] 5: WrDat[5] 4: WrDat[4] 3: WrDat[3] 2: WrDat[2] 1: WrDat[1] 0: WrDat[0] 7: 6: 5: 4: 3: RdAdd[3] 2: RdAdd[2] 1: RdAdd[1] 0: RdAdd[0] 7: RdDat[7] 6: RdDat[6] 5: RdDat[5] 4: RdDat[4] 3: RdDat[3] 2: RdDat[2] 1: RdDat[1] 0: RdDat[0] 0xFF ­ ­ ­ ­ 1 1 1 1 1 1 0xFF R 3: 0x23 H.Rst S.Rst B.Rst R/W R/W ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ Self Node's Physical ID Number 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 0: Normal 0: Normal 0: 0: 1: PHY Reg Rd Request 1: PHY Reg Wr Request 1: 1: R/W PHY Register Read/Write Request Address R/W PHY Register Write Data 0x00 0x00 ­ 0: 0: 0: 0: 0x00 0x00 ­ 0x00 0x00 ­ 1: 1: 1: 1: R PHY Register Read Address R PHY Register Read Data EPSON S1R72801F00A S1R72801F00A Address 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F Register Name ChnlIndex ChnlWindow CmprIndex CmprWindow CYCLE_TIME_H CYCLE_TIME_MH CYCLE_TIME_ML CYCLE_TIME_L Bit Symbol 7: 6: 5: 4: 3: Channel Index[3] 2: Channel Index[2] 1: Channel Index[1] 0: Channel Index[0] 7: Channel Window[7] 6: Channel Window[6] 5: Channel Window[5] 4: Channel Window[4] 3: Channel Window[3] 2: Channel Window[2] 1: Channel Window[1] 0: Channel Window[0] 7: 6: 5: 4: 3: Compare Index[3] 2: Compare Index[2] 1: Compare Index[1] 0: Compare Index[0] 7: Compare Window[7] 6: Compare Window[6] 5: Compare Window[5] 4: Compare Window[4] 3: Compare Window[3] 2: Compare Window[2] 1: Compare Window[1] 0: Compare Window[0] 7: Cycle Second[6] 6: Cycle Second[5] 5: Cycle Second[4] 4: Cycle Second[3] 3: Cycle Second[2] 2: Cycle Second[1] 1: Cycle Second[0] 0: Cycle Count[12] 7: Cycle Count[11] 6: Cycle Count[10] 5: Cycle Count[9] 4: Cycle Count[8] 3: Cycle Count[7] 2: Cycle Count[6] 1: Cycle Count[5] 0: Cycle Count[4] R/W Description 0: 0: 0: 0: 1: 1: 1: 1: R/W ISO (Async Stream) Cahnnel Window 0: 0: 0: 0: 1: 1: 1: 1: 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ R/W Compare Address Index R/W Compare Address Window 0x00 0x00 ­ R/W CYCLE_TIME.second_count 0x00 ­ ­ 0x00 ­ ­ 0x00 ­ ­ 0x00 ­ ­ R/W CYCLE_TIME.cycle_count 7: Cycle Count[3] 6: Cycle Count[2] 5: Cycle Count[1] 4: Cycle Count[0] 3: Cycle Offset[11] 2: Cycle Offset[10] 1: Cycle Offset[9] 0: Cycle Offset[8] 7: Cycle Offset[7] 6: Cycle Offset[6] 5: Cycle Offset[5] 4: Cycle Offset[4] 3: Cycle Offset[3] 2: Cycle Offset[2] 1: Cycle Offset[1] 0: Cycle Offset[0] 0x00 ISO (Async Stream) Channel Index R/W H.Rst S.Rst B.Rst R/W CYCLE_TIME.cycle_offset EPSON 31 S1R72801F00A S1R72801F00A Address 0x30 0x31 Register Name HwSBP2Ctl HwSBP2Stat UltraDmaMode 0x32 0x33 0x34 0x35 0x36 0x37 32 HwSBP2IntStat HwSBP2Index Bit Symbol R/W 7: PtNotPresent 6: HOSTtoDev 5: FromStream 4: 3: HwSBP2Rst 2: HwSBP2Rsum 1: HwSBP2Pause 0: HwSBP2Start R/W R/W R/W 7: FwPause 6: ErrPause 5: 4: WaitPLReady 3: HwSBP2Exec 2: PTaskExec 1: StTaskExec 0: TranExec 7: SplitTimeOut 6: TxAckedIllegal 5: TxAckMiss 4: BrAbort 3: 2: RxNotRespCmp 1: RxBroadCast 0: RxAckDataErr 7: 6: 5: 4: 3: HwSBP2 Index[3] 2: HwSBP2 Index[2] 1: HwSBP2 Index[1] 0: HwSBP2 Index[0] Description 1: Not Present 1: Host ­> Device 1: FromStream 1: 1: Reset 1: Resume 1: Pause 1: Start 0: Not Firmware Pause 0: Not Error Pause 0: 0: Not Ready 0: Stop 0: Stop 0: Stop 0: Stop 1: FirmWre Pause 1: Error Pause 1: 1: Ready 0x00 1: Execute 1: Execute 1: Execute 1: Execute 0: None 0: None 0: None 0: None 0: 0: None 0: None 0: None 1: SplitTimeOut 1: TxAckedIllegal 1: TxAsyMiss 1: BrAbort 0x00 1: 1: RxNotRespCmp 1: RxBroadCast 1: RxAckDataErr 0: 0: 0: 0: R(W) R(W) R(W) R(W) R(W) R(W) R(W) 1: 1: 1: 1: R/W PayloadSize_L 7: Payload Size[7] 6: Payload Size[6] 5: Payload Size[5] 4: Payload Size[4] 3: Payload Size[3] 2: Payload Size[2] 1: Payload Size[1] 0: Payload Size[0] R/W 0x00 ­ 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 ­ 0x00 ­ 0x00 ­ HwSBP2 Index HwSBP2 Window HwSBP2Window_L 7: HwSBP2 Window[7] 6: HwSBP2 Window[6] 5: HwSBP2 Window[5] 4: HwSBP2 Window[4] 3: HwSBP2 Window[3] 2: HwSBP2 Window[2] 1: HwSBP2 Window[1] 0: HwSBP2 Window[0] 7: Payload Size[15] 6: Payload Size[14] 5: Payload Size[13] 4: Payload Size[12] 3: Payload Size[11] 2: Payload Size[10] 1: Payload Size[9] 0: Payload Size[8] 0x00 0x00 R R R R R ­ 0x00 R R 0x00 0x00 W W W W HwSBP2Window_H 7: HwSBP2 Window[15] 6: HwSBP2 Window[14] 5: HwSBP2 Window[13] 4: HwSBP2 Window[12] 3: HwSBP2 Window[11] 2: HwSBP2 Window[10] 1: HwSBP2 Window[9] 0: HwSBP2 Window[8] R/W PayloadSize_H H.Rst S.Rst B.Rst 0: Present 0: Host IDE W 0: None 1: 1: 1: 1: CRC Clear 1: FIFO Clear 1: IDE Transfer Abort 1: IDE ­> SRAM 1: IDE DMA Start R Indicate IDE I/F Signals State R W 0: 0: 0: 0: 0: 0: 0: IDE DMA not Pause 0: Not DMA EPSON 1: 1: 1: 1: 1: 1: 1: IDE DMA Pause 1: IDE DMA Running S1R72801F00A S1R72801F00A Address Register Name Bit Symbol 0x68 IDE_ByteCount0 7: ByteCount[31] 6: ByteCount[30] 5: ByteCount[29] 4: ByteCount[28] 3: ByteCount[27] 2: ByteCount[26] 1: ByteCount[25] 0: ByteCount[24] 0x69 IDE_ByteCount1 7: ByteCount[23] 6: ByteCount[22] 5: ByteCount[21] 4: ByteCount[20] 3: ByteCount[19] 2: ByteCount[18] 1: ByteCount[17] 0: ByteCount[16] 0x6A IDE_ByteCount2 7: ByteCount[15] 6: ByteCount[14] 5: ByteCount[13] 4: ByteCount[12] 3: ByteCount[11] 2: ByteCount[10] 1: ByteCount[9] 0: ByteCount[8] 0x6B IDE_ByteCount3 7: ByteCount[7] 6: ByteCount[6] 5: ByteCount[5] 4: ByteCount[4] 3: ByteCount[3] 2: ByteCount[2] 1: ByteCount[1] 0: ByteCount[0] 0x6C IDE_CRC0 7: CRC[15] 6: CRC[14] 5: CRC[13] 4: CRC[12] 3: CRC[11] 2: CRC[10] 1: CRC[9] 0: CRC[8] 0x6D IDE_CRC1 7: CRC[7] 6: CRC[6] 5: CRC[5] 4: CRC[4] 3: CRC[3] 2: CRC[2] 1: CRC[1] 0: CRC[0] 0x6E IDE_TestIndex 7: 6: 5: 4: 3: 2: 1: 0: 0x6F IDE_TestWindow 7: 6: 5: 4: 3: 2: 1: 0: R/W Description H.Rst S.Rst B.Rst 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 R ­ 0x00 R/W 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ IDE Data Transfer Byte Count Register Read: Indicate Remain Byte Count Write: Set Total Transfer Byte Count IDE CRC Data Register 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: 0: 0: 0: 0: 0: 0: 0: 0: 1: 1: 1: 1: 1: 1: 1: 1: EPSON 39 S1R72801F00A S1R72801F00A Address Register Name Bit Symbol 0x70 IDE_CS00 7: 6: 5: 4: 3: 2: 1: 0: 0x71 IDE_CS01 7: 6: 5: 4: 3: 2: UltraDmaMode 1: 0: 0x72 IDE_CS02 7: 6: 5: 4: 3: 2: 1: 0: 0x73 IDE_CS03 7: 6: 5: 4: 3: 2: 1: 0: 0x74 IDE_CS04 7: 6: 5: 4: 3: 2: 1: 0: 0x75 IDE_CS05 7: 6: 5: 4: 3: 2: 1: 0: 0x76 IDE_CS06 7: 6: 5: 4: 3: 2: 1: 0: 0x77 IDE_CS07 7: 6: 5: 4: 3: 2: 1: 0: 40 R/W Description H.Rst S.Rst B.Rst Command Block Register R/W Data Register 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ Command Block Register R/W Read : Error Register Write: Features Register Command Block Register R/W Sector Count Register Command Block Register R/W Sector Number Register or Logical Block Address(LBA) bit 0 ­ 7 Command Block Register R/W Cylinder Low Register or Logical Block Address(LBA) bit 8 ­ 15 Command Block Register R/W Cylinder High Register or Logical Block Address(LBA) bit 16 ­ 23 Command Block Register R/W Device/Head Register 0x00 Logical Block Address(LBA) bit 24 ­ 27 Command Block Register R/W Read : Status Register 0x00 Write: Command Register EPSON S1R72801F00A S1R72801F00A Address Register Name Bit Symbol 0x78 IDE_CS10 7: 6: 5: 4: 3: 2: 1: 0: 0x79 IDE_CS11 7: 6: 5: 4: 3: 2: 1: 0: 0x7A IDE_CS12 7: 6: 5: 4: 3: 2: 1: 0: 0x7B IDE_CS13 7: 6: 5: 4: 3: 2: 1: 0: 0x7C IDE_CS14 7: 6: 5: 4: 3: 2: 1: 0: 0x7D IDE_CS15 7: 6: 5: 4: 3: 2: 1: 0: 0x7E IDE_CS16 7: 6: 5: 4: 3: 2: 1: 0: 0x7F IDE_CS17 7: 6: 5: 4: 3: 2: 1: 0: R/W Description H.Rst S.Rst B.Rst Control Block Register R/W Read : Data Bus Hi ­ Impedance Write: Not Used 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ 0x00 0x00 ­ Control Block Register R/W Read : Data Bus Hi ­ Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi ­ Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi ­ Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi ­ Impedance Write: Not Used Control Block Register R/W Read : Data Bus Hi ­ Impedance Write: Not Used Control Block Register R/W Read : Alternate Status Write: Device Control Control Block Register R/W Read : (obsolete) Write: Not Used EPSON 41 S1R72801F00A S1R72801F00A 8.1.4 Detail Description of Register (The base address of this register is 0x100000.) Address Register Name 0x00 MainIntStat Bit Symbol 7:SubIntStat 6: TxIsoCmp 5: RxDmaCmp 4: TxAsyCmp 3: HwSBP2Cmp 2: IDE_DmaCmp 1: IDE_INTRQ 0: BusReset R/W R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) Description 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Sub Interrupt Occurred 1: ISO Pkt Transmit Done 1: Packet Reception 1: AckCode Reception 1: HwSBP2 Process Complete 1: IDE DMA Transmit Complete 1: IDE Interface Interrupt 1: Bas Reset Detected H.Rst S.Rst B.Rst 0x00 0x00 ­ Main Interrupt Status Register When this IC interrupts the CPU, the CPU first reads this register to handle it, indicating which Interrupt Status Register is a factor of this interrupt. Subsequent to reading this register, the SubIntStat (Bit 7) reads an Interrupt Status Register associated with each bit to confirm which bit is an interrupt source and appropriately handle it. After that, it writes the read value to the Interrupt Status Register to clear the bit. In the case the interrupt factor still remains, however, the bit is not cleared. When one of 7 bits of the TxIsoCmp, RxDmaCmp, TxAsyCmp, HwSBP2Cmp, IDE_DmaCmp, IDE_INTRQ, and BusReset other than above is an interrupt source, this register clears the bit by writing the read value. Note) The bits of this register control the XInt of output pin. Writing to this register negates the XInt once even if the interrupt factor remains, asserting the XInt after a certain period. (Ready for a timer or edge interrupt). Bit7 Sub Interrupt Status When an interrupt factor exists at each bit shown at the SubIntStat Register, this bit becomes "1". Bit 6 Isochronous Packet Transmit Complete When an ISO Packet Transmit is complete, this bit becomes "1". Bit5 Receive Packet DMA Complete When a received packet is written to the Receive Buffer Area, this bit becomes "1". Bit4 Asynchronous Packet Transmit Complete When an Ack packet to an Async Transmit packet is received, this bit becomes "1". The Ack code is written to the footer area of the Transmit Packet Header. Bit 3 HwSBP2 Process Complete When a HwSBP2 processing is complete, this bit becomes "1". Bit2 IDE DMA Transmit Complete When an IDE I/F DMA Transmit is complete, this bit becomes "1". Bit1 IDE Interface Interrupt When the INTRQ signal is asserted to the IDE I/F, this bit becomes "1". Bit0 BusReset Detected When a BusReset signal is detected on the 1394 Serial Bus, this bit becomes "1". When it issues a BusReset, this bit becomes "1" as well. 42 EPSON S1R72801F00A S1R72801F00A Address Register Name 0x01 SubIntStat Bit Symbol 7: SelfIDdone 6: SelfIDerr 5: HwSBP2Err 4: HwSBP2BRst 3: LinkIntStat1 2: LinkIntStat0 1: PhyIntStat 0: DmaIntStat R/W R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) Description 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Self-ID Phase Done 1: Self-ID Packet Error 1: Hw SBP2 Error 1: BusReset in process HwSBP 1: Link1 Interrupt Occurred 1: Link0 Interrupt Occurred 1: PHY Interrupt Occurred 1: Dma Interrupt Occurred H.Rst S.Rst B.Rst 0x00 0x00 ­ Sub-Interrupt Status Register The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become "1" when the associated bit of the SubIntEnb Register is "1", this register asserts an interrupt signal to the CPU. The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read value again, it clears these bits. Subsequent to reading this register, the lower order 4 bits reads the Interrupt Status Register associated with each bit to confirm which bit is an interrupt source and appropriately handle it. After that, it writes the read value to the Interrupt Status Register to clear the bit. In the case that the interrupt factor still remains, however, the bit is not cleared. Bit7 Self Identify Period Complete When a Self ID period finishes, this bit becomes "1". Bit6 Self Identify Packet Error When a Self-ID packet with an error is received during the Self-ID period or when the Self-ID period finishes due to an error, this bit becomes "1". Bit5 HwSBP2Err When an interrupt factor from the HwSBP2 indicated on the HwSBP2IntStat Register exists, this bit becomes "1". Bit4 BusReset in process HwSBP2 When a BusReset occurs in the HwSBP2 processing, this bit becomes "1". Bit3 LINK Core Interrupt Status1 When an interrupt factor from the LINK core indicated on the LinkIntStat1 Register exists, this bit becomes "1". Bit2 LINK Core Interrupt Status0 When an interrupt factor from the LINK core indicated on the LinkIntStat0 Register exists, this bit becomes "1". Bit1 PHY/LINK Interrupt Status When an interrupt factor from the PHY status indicated on the PHYIntStat Register exists, this bit becomes "1". Bit0 LINK DMA Interrupt Status When an interrupt factor exists in the internal DMA operation indicated on the DmaIntStat Register, this bit becomes "1". Address Register Name 0x02 (Reserved) Bit Symbol 7: 6: 5: 4: 3: 2: 1: 0: R/W Description 0: 0: 0: 0: 0: 0: 0: 0: EPSON 1: 1: 1: 1: 1: 1: 1: 1: H.Rst S.Rst B.Rst 0x00 0x00 ­ 43 S1R72801F00A S1R72801F00A Address Register Name 0x03 DmaIntStat Bit Symbol 7: 6: TxAsyRtyGo 5: TxAsyBCSent 4: RxDmaFaild 3: TxAsyFaild 2: TxIsoFaild 1: TxAsyBRAbort 0: TxAsyMiss R/W R(W) R(W) R(W) R(W) R(W) R(W) R(W) Description 0: 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: 1: Async Tx Retry Go 1: AsyncTxBroadcast Sent 1: Rx DMA Failed 1: Async Tx Failed 1: ISO Tx Failed 1: Async Tx BusReset Abort 1: AsyncTxAckCodeMissing H.Rst S.Rst B.Rst 0x00 0x00 ­ DMA Interrupt Status Register The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become "H" when the associated bit of the DMAIntEnb Register is "1", this register asserts the interrupt signal to the CPU. The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read value again, it clears these bits. Bit7 Reserved When a Sub Action Gap is detected in PHY status of PHY/LINK interface, this bit becomes "1". Bit6 Transmit Async Packet Retry Go When an auto retry is performed after transmitting an Async packet and receiving an Ack_busy, this bit becomes "1". Bit5 Transmit Async Broadcast Packet Sent After a transmission of a Broadcast packet of Async or a PHY packet finishes, this bit becomes "1". Bit4 Receive Packet LINK DMA Failed When a received packet cannot be written to the buffer due to the following reasons, this bit becomes "1". 1) DMA was too late. 2) A packet was received when the ForceBusy bit is on. Bit3 Transmit Async Packet LINKDMA Failed When data cannot be transferred from the buffer to the LINK core at the time of Async packet transmission (DMA FIFO is Under Flow), this bit becomes "1". Bit2 Transmit ISO Packet LINKDMA Failed When data cannot be transferred from the buffer to the LINK core at the time of ISO packet transmission (DMA FIFO is Under Flow), this bit becomes "1". Bit 1 Transmit Async Packet BusReset Abort When a Transmit packet is disabled by a BusReset before an Ack packet is returned at the time of Async packet transmission, this bit becomes "1". Bit0 Transmit Async Packet Ack-code Missing When a Ack packet is not returned at the time of Async packet transmission, this bit becomes "1". 44 EPSON S1R72801F00A S1R72801F00A Address Register Name 0x04 LinkIntStat1 Bit Symbol 7: 6: 5: 4: 3: RxOnTardy 2: RxHcrcErr 1: RxUnkTcode 0: TxRtyExced R/W R(W) R(W) R(W) R(W) Description 0: 0: 0: 0: 0: None 0: None 0: None 0: None 1: 1: 1: 1: 1: Ack_tardy Sent 1: Rx Packet Header CRC Err 1: Rx Packet Tcode Unknown 1: Tx Retry Exceeded H.Rst S.Rst B.Rst 0x00 0x00 ­ LINK Core Interrupt Status Register 1 The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become "1" when the associated bit of the LINKIntEnb1 Register is "1", this register asserts the interrupt signal to the CPU. The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read value again, it clears these bits. Bit7 Reserved Bit6 Reserved Bit5 Reserved Bit4 Reserved Bit3 RxOnTardy When a packet is received when the ChipCtl. SendTardy bit is "1", an Ack_tardy is returned to the party of the other end and this bit becomes "1". Bit2 Receive Packet Header CRC Error When an error exists in the header CRC of a received packet, this bit becomes "1". Bit1 Receive Packet Tcode Unknown When the Tcode in a received packet is invalid, this bit becomes "1". Bit0 transmit Retry Exceeded If a transmit retry fails since the set value of the MaxRetry Register is exceeded when the RetryLimit Register is not zero or the MaxRetry Register is not 0 and this bit becomes "1". EPSON 45 S1R72801F00A S1R72801F00A Address Register Name 0x05 LinkIntStat0 Bit Symbol R/W 7: UnExpCh 6: DupliCh 5: IsoArbFaild 4: CycTooLong 3: CycOverFlw 2: CycEvent 1: CycLost 0: CycArbFail R(W) R(W) R(W) R(W) R(W) R(W) R(W) R(W) Description 0: None 0: None 0: None 0: None 0: None 0: None 0: None 0: None 1: Unknown Expected Channel 1: DuplicateChannelDetected 1: Iso Arbtration Failed 1: ISO Arbitration Failed 1: Cycle Timer Over Fullow 1: Local Cycle Event Occured 1: Cycle Start Packet Lost 1: CycleStartPkt Arbtration Fail H.Rst S.Rst B.Rst 0x00 0x00 ­ LINK Core Interrupt Status Register 0 The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become "1" when the associated bit of the LINKIntEnb0 Register is "1", this register asserts the interrupt signal to the CPU. The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read value again, it clears these bits. Bit7 Unknown Expected Channel When a packet of ISO channel not set in the CHANNEL_AVAILABLE Register is detected, this bit becomes "1". It is enabled when the WonIRM = "1" of IRM IDStat Register (the self node is IRM). Bit6 DuplicateChannelDetected When a packet of a same channel is detected in the ISO period of 1 cycle, this bit becomes "1". It is enabled when the WonIRM = "1" of IRM IDStat Register (the self node is IRM). Bit5 ISO Arbitration Failed When an ISO packet transmit request is received but a SubAction Gap is detected before it is transmitted, this bit becomes "1". Bit4 ISO Arbitration Failed When a Cycle_START packet is received but a SubAction Gap cannot be detected even after the ISOCHRONOUS_CYCLE_TIME has passed, this bit becomes "1". Bit3 Cycle Timer Over Flow When the CYCLE_TIMER overflows, this bit becomes "1". Bit2 Local Cycle Event Occurred When an local cycle event occurs, this bit becomes "1". Bit1 Cycle Start Packet Lost When the CYCLE_START_PACKET does not exist over two local cycle events, this bit becomes "1". Bit0 CycleStartPkt Arbitration Failed When a CYCLE_START_PACKET cannot be transmitted before the SubActionGap after a local cycle event occurs, this bit becomes "1". This bit is enabled when cmstr = "1". 46 EPSON S1R72801F00A S1R72801F00A Address Register Name 0x06 PhyIntStat Bit Symbol 7: SubGap 6: ArbGap 5: 4: 3: 2: Phy_int 1: PhyWrDone 0: PhyRdDone R/W Description R(W) 0: None R(W) 0: None 0: 0: 0: R(W) 0: None R(W) 0: None R(W) 0: None 1: Sub Action Gap Detected 1: ArbtrationResetGapDetected 1: 1: 1: 1: PHY Interrupt Detected 1: PHY Register Write Done 1: PHY Register Read Done H.Rst S.Rst B.Rst 0x00 0x00 ­ PHY Interrupt Status Register The value of each bit of this register indicates the status of a corresponding interrupt source. If these bits become "1" when the associated bit of the PHYIntEnb Register is "1", this register asserts the interrupt signal to the CPU. The CPU reads this register after receiving the interrupt signal to locate an interrupt source. By writing the read value again, it clears these bits. Bit 7 Sub Action Gap Detected When a Transmit Action Gap is detected in the PHY status of the PHY/LINK interface, this bit becomes "1". Bit6 Arbitration Reset Gap Detected When an Arbitration Reset Gap is detected in the PHY status of the PHY/LINK interface, this bit becomes "1". Bit5 Reserved Bit4 Reserved Bit3 Reserved Bit2 PHY/LINK Interface Interrupt Detected When a PHY_Interrupt is detected in the PHY status of the PHY/LINK interface, this bit becomes "1". This status indicates the PHY is put under one of the following. 1) In most instances, a loop is created in the cable topology. 2) Cable power is insufficient. 3) A bias change is detected. Bit1 PHY Register Write Done When the write access of the PHY Register is complete, this bit becomes