MF1323-06 S1D10605 SED1065 S1D10606 S1D10607 S1D10608 S1D10609 S1D10605D00B - Datasheet Archive

 

S1D10605 Series Rev.2.1 SED1065 Series Contents 1. DESCRIPTION

 

MF1323-06 MF1323-06 S1D10605 S1D10605 Series Rev.2.1 SED1065 SED1065 Series Contents 1. DESCRIPTION . 1 2. FEATURES . 1 3. BLOCK DIAGRAM . 3 4. PAD LAYOUT . 4 5. PAD CENTER COORDINATES . 5 6. PIN DESCRIPTIONS . 11 7. FUNCTION DESCRIPTION . 15 8. COMMAND DESCRIPTION . 37 9. COMMAND SETTING . 46 10. ABSOLUTE MAXIMUM RATINGS . 51 11. DC CHARACTERISTICS . 52 12. THE MPU INTERFACE (REFERENCE EXAMPLES) . 68 13. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLE) . 69 14. CONNECTIONS BETWEEN LCD DRIVERS (REFERENCE EXAMPLES) . 70 15. CAUTIONS . 71 ­i­ Rev.2.1 S1D10605 S1D10605 Series 1. DESCRIPTION The S1D10605 S1D10605 Series is a series of single-chip dot matrix liquid crystal display drivers that can be connected directly to a microprocessor bus. 8-bit parallel or serial display data sent from the microprocessor is stored in the internal display data RAM and the chip generates a liquid crystal drive signal independent of the microprocessor. Because the chips in the S1D10605 S1D10605 Series contain 65 × 132 bits of display data RAM and there is a 1-to-1 correspondence between the liquid crystal panel pixels and the internal RAM bits, these chips enable displays with a high degree of freedom. The S1D10606 S1D10606 Series chips contain 65 common output circuits and 132 segment output circuits, so that a single chip can drive a 65 × 132 dot display (capable of displaying 8 columns × 4 rows of a 16 × 16 dot kanji font). The S1D10607 S1D10607 Series chips contain 33 common output circuits and 132 segment output circuits, so that a single chip can drive 33 × 132 dot display (capable of displaying 8 columns × 2 rows of 16 × 16 dot kanji fonts). Thanks to the built-in 55 common output circuits and 132 segment output circuits, the S1D10608 S1D10608 Series is capable of displaying 55 × 132 dots (11 columns × 4 lines using 11 × 12 dots Kanji font) with a single chip. The S1D10609 S1D10609 Series chips contain 53 common output circuits and 132 segment output circuits, so that a single chip can drive 53 × 132 dot display (capable of displaying 11 columns × 4 rows of 11 × 12 dot kanji fonts). Moreover, the capacity of the display can be extended through the use of master/slave structures between chips. The chips are able to minimize power consumption because no external operating clock is necessary for the display data RAM read/write operation. Furthermore, because each chip is equipped internally with a lowpower liquid crystal driver power supply, resistors for liquid crystal driver power voltage adjustment and a display clock CR oscillator circuit, the S1D10605 S1D10605 Series chips can be used to create the lowest power display system with the fewest components for high-performance portable devices. 2. FEATURES · Direct display of RAM data through the display data RAM. RAM bit data: "1" Display on "0" Display off (during normal display) · RAM capacity 65 × 132 = 8580 bits · Display driver circuits S1D10605 S1D10605*: 65 common output and 132 segment outputs S1D10606 S1D10606*: 49 common output and 132 segment outputs S1D10607 S1D10607*: 33 common outputs and 132 segment outputs S1D10608 S1D10608*: 55 common outputs and 132 segment outputs S1D10609 S1D10609*: 53 common outputs and 132 segment outputs Rev.2.1 · High-speed 8-bit MPU interface (The chip can be connected directly to the both the 80x86 series MPUs and the 6800 series MPUs) /Serial interfaces are supported. · Abundant command functions Display data Read/Write, display ON/OFF, Normal/ Reverse display mode, page address set, display start line set, column address set, status read, display all points ON/OFF, LCD bias set, electronic volume, read/modify/write, segment driver direction select, power saver, static indicator, common output status select, V5 voltage regulation internal resistor ratio set. · Static drive circuit equipped internally for indicators. (1 system, with variable flashing speed.) · Low-power liquid crystal display power supply circuit equipped internally. Booster circuit (with Boost ratios of Double/Triple/ Quad, where the step-up voltage reference power supply can be input externally) High-accuracy voltage adjustment circuit (Thermal gradient ­0.05%/°C) V5 voltage regulator resistors equipped internally, V1 to V4 voltage divider resistors equipped internally, electronic volume function equipped internally, voltage follower. · CR oscillator circuit equipped internally (external clock can also be input) · Extremely low power consumption Operating power when the built-in power supply is used (an example) S1D10605D00B S1D10605D00B* 100 µA (V DD ­ V SS = VDD ­ VSS2 = 3.0 V, Quad voltage, V5 ­ VDD = ­ 11.0 V) S1D10606D00B S1D10606D00B* 59 µA (V DD ­ VSS = V DD ­ VSS2 = 3.0 V, Triple voltage, V5 ­ VDD = ­ 8.0 V) S1D10607D00B S1D10607D00B* 55 µA (V DD ­ VSS = V DD ­ VSS2 = 3.0 V, Triple voltage, V5 ­ VDD = ­ 8.0 V) S1D10608D00B S1D10608D00B* 58 µA (VDD ­ V SS = VDD ­ /S1D10609D00B /S1D10609D00B* VSS2 = 3.0 V, Triple voltage, V5 ­ VDD = ­ 8.0 V) Conditions: When all displays are in white and the normal mode is selected (see page 60 *12 for details of the conditions). · Power supply Operable on the low 1.8 voltage Logic power supply VDD ­ V SS = +1.8 V to ­3.6 V Boost reference voltage: VDD ­ VSS2 = 1.8 V to ­4.0 V Liquid crystal drive power supply: VDD ­ V5 = ­4.5 V to ­14.0 V · Wide range of operating temperatures: ­40 to +85°C · CMOS process · Shipping forms include bare chip and TCP. · These chips not designed for resistance to light or resistance to radiation. EPSON 1 S1D10605 S1D10605 Series Series Specifications Product name VREG temperature gradient ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C ­0.05%/°C Reset pin noise rejection Chip Thickness - - - - - 75ns 75ns 75ns 75ns 75ns 350ns 350ns 350ns 350ns 350ns 625µm 625µm 625µm 625µm 625µm 625µm 625µm 625µm 625µm 625µm 625µm 625µm 625µm 625µm 625µm Duty Bias SED COM 1/65 1/49 1/33 1/55 1/53 1/65 1/49 1/33 1/55 1/53 1/65 1/49 1/33 1/55 1/53 1/9, 1/7 1/8, 1/6 1/6, 1/5 1/8, 1/6 1/8, 1/6 1/9, 1/7 1/8, 1/6 1/6, 1/5 1/8, 1/6 1/8, 1/6 1/9, 1/7 1/8, 1/6 1/6, 1/5 1/8, 1/6 1/8, 1/6 132 132 132 132 132 132 132 132 132 132 132 132 132 132 132 65 49 33 55 53 65 49 33 55 53 65 49 33 55 53 Product name Duty Bias SED COM VREG temperature gradient S1D10605T00 S1D10605T00* 1/65 1/9, 1/7 132 65 ­0.05%/°C S1D10605D00B000 S1D10605D00B000 S1D10606D00B000 S1D10606D00B000 S1D10607D00B000 S1D10607D00B000 S1D10608D00B000 S1D10608D00B000 S1D10609D00B000 S1D10609D00B000 S1D10605D03B000 S1D10605D03B000 S1D10606D03B000 S1D10606D03B000 S1D10607D03B000 S1D10607D03B000 S1D10608D03B000 S1D10608D03B000 S1D10609D03B000 S1D10609D03B000 S1D10605D04B000 S1D10605D04B000 S1D10606D04B000 S1D10606D04B000 S1D10607D04B000 S1D10607D04B000 S1D10608D04B000 S1D10608D04B000 S1D10609D04B000 S1D10609D04B000 Standard TCP 2 EPSON Rev.2.1 S1D10605 S1D10605 Series 3. BLOCK DIAGRAM COMS · · · · · · · · · · COM63 COM63 COM0 · · · · · · · · · · · · · · · · · · · · · · · · · SEG131 SEG131 SEG0 Example: S1D10605 S1D10605 * VSS VDD V2 V3 SEG Drivers COMS V1 COM Drivers V4 V5 COM output status select circuit CAP1+ Display data latch circuit VSS2 VR Display timing generation circuit Power supply circuit Line address circuit VOUT Page address circuit CAP2+ CAP2­ CAP3+ I/O buffer CAP1­ Display data RAM 132 x 65 VRS IRS HPM FRS FR CL DOF M/S Oscillator circuit Column address circuit Bus holder Command decoder CLS Status Rev.2.1 EPSON D0 D1 D2 D3 D4 D5 D6 (SCL) D7 (SI) RES P/S WR (R/W) RD (E) A0 CS2 CS1 MPU interface 3 S1D10605 S1D10605 Series 4. PAD LAYOUT 99 1 100 309 S1D10605 S1D10605 Series (0, 0) Die No. D1065D0B D1065D0B 275 134 135 274 Item Chip Size Chip Thickness Bump Pitch Bump Size Bump Height Alignment Mark Left Upper Alignment Mark Left Lower Alignment Mark Right Upper Alignment Mark Right Lower 4 PAD No. 1 to 24 PAD No. 25 to 82 PAD No. 83 to 99 PAD No. 100 to 134 PAD No. 135 to 274 PAD No. 275 to 309 Alignment Coordinates Outside Diameter · Inside Diameter Alignment Coordinates Outside Diameter · Inside Diameter Alignment Coordinates Outside Diameter Alignment Coordinates Outside Diameter EPSON Size X Y 7.93 × 2.25 0.625 50 (Min.) 55 × 76 45 × 76 55 × 76 136 × 33 33 × 126 136 × 33 17 (Typ.) ­3590 × 980 78 · 33 Unit mm µm ­3690 × ­940 78 · 33 3635 × 980 78 3585 × ­940 78 Rev.2.1 S1D10605 S1D10605 Series 5. PAD CENTER COORDINATES Units: µm PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 Rev.2.1 PIN Name S1D10605 S1D10605 S1D10606 S1D10606 S1D10607 S1D10607 S1D10608 S1D10608 S1D10609 S1D10609 DUMMY1 DUMMY1 DUMMY1 DUMMY1 DUMMY1 FRS FRS FRS FRS FRS FR FR FR FR FR CL CL CL CL CL DOF DOF DOF DOF DOF TEST0 TEST0 TEST0 TEST0 TEST0 V SS VSS VSS V SS VSS CS1 CS1 CS1 CS1 CS1 CS2 CS2 CS2 CS2 CS2 VDD VDD V DD VDD VDD RES RES RES RES RES A0 A0 A0 A0 A0 V SS VSS VSS V SS VSS WR,R/W WR,R/W WR,R/W WR,R/W WR,R/W RD,E RD,E RD,E RD,E RD,E VDD VDD V DD VDD VDD D0 D0 D0 D0 D0 D1 D1 D1 D1 D1 D2 D2 D2 D2 D2 D3 D3 D3 D3 D3 D4 D4 D4 D4 D4 D5 D5 D5 D5 D5 D6,SCL D6,SCL D6,SCL D6,SCL D6,SCL D7,SI D7,SI D7,SI D7,SI D7,SI DUMMY2 DUMMY2 DUMMY2 DUMMY2 DUMMY2 VDD VDD V DD VDD VDD VDD VDD V DD VDD VDD VDD VDD V DD VDD VDD VDD VDD V DD VDD VDD V SS VSS VSS V SS VSS V SS VSS VSS V SS VSS V SS VSS VSS V SS VSS VSS2 VSS2 V SS2 VSS2 VSS2 VSS2 VSS2 V SS2 VSS2 VSS2 VSS2 VSS2 V SS2 VSS2 VSS2 VSS2 VSS2 V SS2 VSS2 VSS2 DUMMY3 DUMMY3 DUMMY3 DUMMY3 DUMMY3 VOUT V OUT VOUT VOUT V OUT VOUT V OUT VOUT VOUT V OUT CAP3­ CAP3­ CAP3­ CAP3­ CAP3­ CAP3­ CAP3­ CAP3­ CAP3­ CAP3­ DUMMY4 DUMMY4 DUMMY4 DUMMY4 DUMMY4 CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP1­ CAP1­ CAP1­ CAP1­ CAP1­ CAP1­ CAP1­ CAP1­ CAP1­ CAP1­ CAP2­ CAP2­ CAP2­ CAP2­ CAP2­ CAP2­ CAP2­ CAP2­ CAP2­ CAP2­ CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ V SS VSS VSS V SS VSS V SS VSS VSS V SS VSS VRS V RS VRS VRS V RS V RS VRS VRS V RS VRS EPSON X Y 3443 3360 3277 3194 3111 3029 2946 2863 2780 2697 2615 2532 2449 2366 2283 2201 2118 2035 1952 1869 1787 1704 1621 1538 1469 1408 1346 1284 1223 1161 1099 1038 976 914 853 791 729 668 606 544 483 421 359 298 236 175 113 51 ­10 ­72 ­134 ­195 ­257 ­319 983 X BUMP Y BUMP Size Size 55 76 45 5 S1D10605 S1D10605 Series Unit : µm PAD No. 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 6 S1D10605 S1D10605 V DD V DD V1 V1 V2 V2 DUMMY5 V3 V3 V4 V4 V5 V5 DUMMY6 VR VR V DD V DD TEST1 TEST1 TEST2 TEST2 DUMMY7 TEST3 TEST3 TEST4 TEST4 DUMMY8 V DD M/S CLS VSS C86 P/S V DD HPM VSS IRS V DD TEST5 TEST6 TEST7 TEST8 TEST9 TESTA DUMMY9 COM31 COM31 COM30 COM30 COM29 COM29 COM28 COM28 COM27 COM27 COM26 COM26 COM25 COM25 COM24 COM24 PIN Name S1D10606 S1D10606 S1D10607 S1D10607 S1D10608 S1D10608 S1D10609 S1D10609 VDD VDD V DD VDD VDD VDD V DD VDD V1 V1 V1 V1 V1 V1 V1 V1 V2 V2 V2 V2 V2 V2 V2 V2 DUMMY5 DUMMY5 DUMMY5 DUMMY5 V3 V3 V3 V3 V3 V3 V3 V3 V4 V4 V4 V4 V4 V4 V4 V4 V5 V5 V5 V5 V5 V5 V5 V5 DUMMY6 DUMMY6 DUMMY6 DUMMY6 VR VR VR VR VR VR VR VR VDD VDD V DD VDD VDD VDD V DD VDD TEST1 TEST1 TEST1 TEST1 TEST1 TEST1 TEST1 TEST1 TEST2 TEST2 TEST2 TEST2 TEST2 TEST2 TEST2 TEST2 DUMMY7 DUMMY7 DUMMY7 DUMMY7 TEST3 TEST3 TEST3 TEST3 TEST3 TEST3 TEST3 TEST3 TEST4 TEST4 TEST4 TEST4 TEST4 TEST4 TEST4 TEST4 DUMMY8 DUMMY8 DUMMY8 DUMMY8 VDD VDD V DD VDD M/S M/S M/S M/S CLS CLS CLS CLS VSS VSS VSS V SS C86 C86 C86 C86 P/S P/S P/S P/S VDD VDD V DD VDD HPM HPM HPM HPM VSS VSS VSS V SS IRS IRS IRS IRS VDD VDD V DD VDD TEST5 TEST5 TEST5 TEST5 TEST6 TEST6 TEST6 TEST6 TEST7 TEST7 TEST7 TEST7 TEST8 TEST8 TEST8 TEST8 TEST9 TEST9 TEST9 TEST9 TESTA TESTA TESTA TESTA DUMMY9 DUMMY9 DUMMY9 DUMMY9 DUMMY10 DUMMY10 COM15 COM15 DUMMY10 DUMMY10 DUMMY10 DUMMY10 DUMMY11 DUMMY11 COM15 COM15 COM26 COM26 COM25 COM25 COM23 COM23 COM14 COM14 DUMMY11 DUMMY11 DUMMY11 DUMMY11 DUMY12 DUMY12 COM14 COM14 COM25 COM25 COM24 COM24 COM22 COM22 COM13 COM13 COM24 COM24 DUMMY12 DUMMY12 DUMMY13 DUMMY13 COM13 COM13 COM23 COM23 COM23 COM23 COM21 COM21 COM12 COM12 COM22 COM22 COM22 COM22 COM20 COM20 COM12 COM12 COM21 COM21 COM21 COM21 EPSON X Y ­380 ­442 ­504 ­565 ­627 ­689 ­750 ­812 ­874 ­935 ­997 ­1058 ­1120 ­1182 ­1243 ­1305 ­1367 ­1428 ­1490 ­1552 ­1613 ­1675 ­1737 ­1798 ­1860 ­1922 ­1983 ­2045 ­2118 ­2201 ­2283 ­2366 ­2449 ­2532 ­2615 ­2697 ­2780 ­2863 ­2946 ­3029 ­3111 ­3194 ­3277 ­3360 ­3443 ­3794 983 X BUMP Y BUMP Size Size 45 76 55 865 815 765 715 665 615 565 515 465 136 33 Rev.2.1 S1D10605 S1D10605 Series Units : µm PAD No. 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 Rev.2.1 S1D10605 S1D10605 COM23 COM23 COM22 COM22 COM21 COM21 COM20 COM20 COM19 COM19 COM18 COM18 COM17 COM17 COM16 COM16 COM15 COM15 COM14 COM14 COM13 COM13 COM12 COM12 COM11 COM11 COM10 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMS DUMMY10 DUMMY10 DUMMY11 DUMMY11 DUMMY12 DUMMY12 DUMMY13 DUMMY13 DUMMY14 DUMMY14 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 SEG13 SEG13 SEG14 SEG14 SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 S1D10606 S1D10606 COM19 COM19 COM18 COM18 COM17 COM17 COM16 COM16 COM15 COM15 COM14 COM14 COM13 COM13 COM12 COM12 COM11 COM11 COM10 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DUMMY14 DUMMY14 COM0 DUMMY15 DUMMY15 COMS DUMMY16 DUMMY16 DUMMY17 DUMMY17 DUMMY18 DUMMY18 DUMMY19 DUMMY19 DUMMY20 DUMMY20 DUMMY21 DUMMY21 DUMMY22 DUMMY22 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 SEG13 SEG13 SEG14 SEG14 SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 PIN Name S1D10607 S1D10607 COM11 COM11 COM11 COM11 COM10 COM10 COM10 COM10 COM9 COM9 COM8 COM8 COM7 COM7 COM6 COM6 COM5 COM5 COM4 COM4 COM3 COM3 COM2 COM2 COM1 COM1 COM0 COM0 COMS DUMMY10 DUMMY10 DUMMY11 DUMMY11 DUMMY12 DUMMY12 DUMMY13 DUMMY13 DUMMY14 DUMMY14 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 SEG13 SEG13 SEG14 SEG14 SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 X S1D10608 S1D10608 COM20 COM20 COM19 COM19 COM18 COM18 COM17 COM17 COM16 COM16 COM15 COM15 COM14 COM14 COM13 COM13 COM12 COM12 COM11 COM11 COM10 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DUMMY12 DUMMY12 COM0 DUMMY13 DUMMY13 COMS DUMMY14 DUMMY14 DUMMY15 DUMMY15 DUMMY16 DUMMY16 DUMMY17 DUMMY17 DUMMY18 DUMMY18 DUMMY19 DUMMY19 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 SEG13 SEG13 SEG14 SEG14 SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 S1D10609 S1D10609 COM20 COM20 COM19 COM19 COM18 COM18 COM17 COM17 COM16 COM16 COM15 COM15 COM14 COM14 COM13 COM13 COM12 COM12 COM11 COM11 COM10 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 DUMMY13 DUMMY13 COM0 DUMMY14 DUMMY14 COMS DUMMY15 DUMMY15 DUMMY16 DUMMY16 DUMMY17 DUMMY17 DUMMY18 DUMMY18 DUMMY19 DUMMY19 DUMMY20 DUMMY20 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG10 SEG11 SEG11 SEG12 SEG12 SEG13 SEG13 SEG14 SEG14 SEG15 SEG15 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG23 SEG23 EPSON Y ­3794 415 365 314 264 214 164 114 64 14 ­36 ­86 ­136 ­186 ­236 ­286 ­336 ­386 ­436 ­486 ­536 ­586 ­636 ­686 ­736 ­786 ­836 ­958 ­3478 ­3428 ­3378 ­3328 ­3278 ­3228 ­3178 ­3128 ­3077 ­3027 ­2977 ­2927 ­2877 ­2827 ­2777 ­2727 ­2677 ­2627 ­2577 ­2527 ­2477 ­2427 ­2377 ­2327 ­2277 ­2227 ­2177 ­2127 X BUMP Y BUMP Size Size 136 33 33 126 7 S1D10605 S1D10605 Series Units : µm PAD No. 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 8 PIN Name S1D10605 S1D10605 S1D10606 S1D10606 S1D10607 S1D10607 S1D10608 S1D10608 S1D10609 S1D10609 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG24 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG25 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG26 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG27 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG28 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG29 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG30 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG31 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG32 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG33 SEG34 SEG34 SEG34 SEG34 SEG34 SEG34 SEG34 SEG34 SEG34 SEG34 SEG35 SEG35 SEG35 SEG35 SEG35 SEG35 SEG35 SEG35 SEG35 SEG35 SEG36 SEG36 SEG36 SEG36 SEG36 SEG36 SEG36 SEG36 SEG36 SEG36 SEG37 SEG37 SEG37 SEG37 SEG37 SEG37 SEG37 SEG37 SEG37 SEG37 SEG38 SEG38 SEG38 SEG38 SEG38 SEG38 SEG38 SEG38 SEG38 SEG38 SEG39 SEG39 SEG39 SEG39 SEG39 SEG39 SEG39 SEG39 SEG39 SEG39 SEG40 SEG40 SEG40 SEG40 SEG40 SEG40 SEG40 SEG40 SEG40 SEG40 SEG41 SEG41 SEG41 SEG41 SEG41 SEG41 SEG41 SEG41 SEG41 SEG41 SEG42 SEG42 SEG42 SEG42 SEG42 SEG42 SEG42 SEG42 SEG42 SEG42 SEG43 SEG43 SEG43 SEG43 SEG43 SEG43 SEG43 SEG43 SEG43 SEG43 SEG44 SEG44 SEG44 SEG44 SEG44 SEG44 SEG44 SEG44 SEG44 SEG44 SEG45 SEG45 SEG45 SEG45 SEG45 SEG45 SEG45 SEG45 SEG45 SEG45 SEG46 SEG46 SEG46 SEG46 SEG46 SEG46 SEG46 SEG46 SEG46 SEG46 SEG47 SEG47 SEG47 SEG47 SEG47 SEG47 SEG47 SEG47 SEG47 SEG47 SEG48 SEG48 SEG48 SEG48 SEG48 SEG48 SEG48 SEG48 SEG48 SEG48 SEG49 SEG49 SEG49 SEG49 SEG49 SEG49 SEG49 SEG49 SEG49 SEG49 SEG50 SEG50 SEG50 SEG50 SEG50 SEG50 SEG50 SEG50 SEG50 SEG50 SEG51 SEG51 SEG51 SEG51 SEG51 SEG51 SEG51 SEG51 SEG51 SEG51 SEG52 SEG52 SEG52 SEG52 SEG52 SEG52 SEG52 SEG52 SEG52 SEG52 SEG53 SEG53 SEG53 SEG53 SEG53 SEG53 SEG53 SEG53 SEG53 SEG53 SEG54 SEG54 SEG54 SEG54 SEG54 SEG54 SEG54 SEG54 SEG54 SEG54 SEG55 SEG55 SEG55 SEG55 SEG55 SEG55 SEG55 SEG55 SEG55 SEG55 SEG56 SEG56 SEG56 SEG56 SEG56 SEG56 SEG56 SEG56 SEG56 SEG56 SEG57 SEG57 SEG57 SEG57 SEG57 SEG57 SEG57 SEG57 SEG57 SEG57 SEG58 SEG58 SEG58 SEG58 SEG58 SEG58 SEG58 SEG58 SEG58 SEG58 SEG59 SEG59 SEG59 SEG59 SEG59 SEG59 SEG59 SEG59 SEG59 SEG59 SEG60 SEG60 SEG60 SEG60 SEG60 SEG60 SEG60 SEG60 SEG60 SEG60 SEG61 SEG61 SEG61 SEG61 SEG61 SEG61 SEG61 SEG61 SEG61 SEG61 SEG62 SEG62 SEG62 SEG62 SEG62 SEG62 SEG62 SEG62 SEG62 SEG62 SEG63 SEG63 SEG63 SEG63 SEG63 SEG63 SEG63 SEG63 SEG63 SEG63 SEG64 SEG64 SEG64 SEG64 SEG64 SEG64 SEG64 SEG64 SEG64 SEG64 SEG65 SEG65 SEG65 SEG65 SEG65 SEG65 SEG65 SEG65 SEG65 SEG65 SEG66 SEG66 SEG66 SEG66 SEG66 SEG66 SEG66 SEG66 SEG66 SEG66 SEG67 SEG67 SEG67 SEG67 SEG67 SEG67 SEG67 SEG67 SEG67 SEG67 SEG68 SEG68 SEG68 SEG68 SEG68 SEG68 SEG68 SEG68 SEG68 SEG68 SEG69 SEG69 SEG69 SEG69 SEG69 SEG69 SEG69 SEG69 SEG69 SEG69 SEG70 SEG70 SEG70 SEG70 SEG70 SEG70 SEG70 SEG70 SEG70 SEG70 SEG71 SEG71 SEG71 SEG71 SEG71 SEG71 SEG71 SEG71 SEG71 SEG71 SEG72 SEG72 SEG72 SEG72 SEG72 SEG72 SEG72 SEG72 SEG72 SEG72 SEG73 SEG73 SEG73 SEG73 SEG73 SEG73 SEG73 SEG73 SEG73 SEG73 SEG74 SEG74 SEG74 SEG74 SEG74 SEG74 SEG74 SEG74 SEG74 SEG74 SEG75 SEG75 SEG75 SEG75 SEG75 SEG75 SEG75 SEG75 SEG75 SEG75 SEG76 SEG76 SEG76 SEG76 SEG76 SEG76 SEG76 SEG76 SEG76 SEG76 SEG77 SEG77 SEG77 SEG77 SEG77 SEG77 SEG77 SEG77 SEG77 SEG77 EPSON X Y ­2077 ­2027 ­1977 ­1927 ­1877 ­1826 ­1776 ­1726 ­1676 ­1626 ­1576 ­1526 ­1476 ­1426 ­1376 ­1326 ­1276 ­1226 ­1176 ­1126 ­1076 ­1026 ­976 ­926 ­876 ­826 ­776 ­726 ­676 ­626 ­575 ­525 ­475 ­425 ­375 ­325 ­275 ­225 ­175 ­125 ­75 ­25 25 75 125 175 225 275 325 375 425 475 525 575 ­958 X BUMP Y BUMP Size Size 33 126 Rev.2.1 S1D10605 S1D10605 Series Units : µm PAD No. 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 Rev.2.1 PIN Name S1D10605 S1D10605 S1D10606 S1D10606 S1D10607 S1D10607 S1D10608 S1D10608 S1D10609 S1D10609 SEG78 SEG78 SEG78 SEG78 SEG78 SEG78 SEG78 SEG78 SEG78 SEG78 SEG79 SEG79 SEG79 SEG79 SEG79 SEG79 SEG79 SEG79 SEG79 SEG79 SEG80 SEG80 SEG80 SEG80 SEG80 SEG80 SEG80 SEG80 SEG80 SEG80 SEG81 SEG81 SEG81 SEG81 SEG81 SEG81 SEG81 SEG81 SEG81 SEG81 SEG82 SEG82 SEG82 SEG82 SEG82 SEG82 SEG82 SEG82 SEG82 SEG82 SEG83 SEG83 SEG83 SEG83 SEG83 SEG83 SEG83 SEG83 SEG83 SEG83 SEG84 SEG84 SEG84 SEG84 SEG84 SEG84 SEG84 SEG84 SEG84 SEG84 SEG85 SEG85 SEG85 SEG85 SEG85 SEG85 SEG85 SEG85 SEG85 SEG85 SEG86 SEG86 SEG86 SEG86 SEG86 SEG86 SEG86 SEG86 SEG86 SEG86 SEG87 SEG87 SEG87 SEG87 SEG87 SEG87 SEG87 SEG87 SEG87 SEG87 SEG88 SEG88 SEG88 SEG88 SEG88 SEG88 SEG88 SEG88 SEG88 SEG88 SEG89 SEG89 SEG89 SEG89 SEG89 SEG89 SEG89 SEG89 SEG89 SEG89 SEG90 SEG90 SEG90 SEG90 SEG90 SEG90 SEG90 SEG90 SEG90 SEG90 SEG91 SEG91 SEG91 SEG91 SEG91 SEG91 SEG91 SEG91 SEG91 SEG91 SEG92 SEG92 SEG92 SEG92 SEG92 SEG92 SEG92 SEG92 SEG92 SEG92 SEG93 SEG93 SEG93 SEG93 SEG93 SEG93 SEG93 SEG93 SEG93 SEG93 SEG94 SEG94 SEG94 SEG94 SEG94 SEG94 SEG94 SEG94 SEG94 SEG94 SEG95 SEG95 SEG95 SEG95 SEG95 SEG95 SEG95 SEG95 SEG95 SEG95 SEG96 SEG96 SEG96 SEG96 SEG96 SEG96 SEG96 SEG96 SEG96 SEG96 SEG97 SEG97 SEG97 SEG97 SEG97 SEG97 SEG97 SEG97 SEG97 SEG97 SEG98 SEG98 SEG98 SEG98 SEG98 SEG98 SEG98 SEG98 SEG98 SEG98 SEG99 SEG99 SEG99 SEG99 SEG99 SEG99 SEG99 SEG99 SEG99 SEG99 SEG100 SEG100 SEG100 SEG100 SEG100 SEG100 SEG100 SEG100 SEG100 SEG100 SEG101 SEG101 SEG101 SEG101 SEG101 SEG101 SEG101 SEG101 SEG101 SEG101 SEG102 SEG102 SEG102 SEG102 SEG102 SEG102 SEG102 SEG102 SEG102 SEG102 SEG103 SEG103 SEG103 SEG103 SEG103 SEG103 SEG103 SEG103 SEG103 SEG103 SEG104 SEG104 SEG104 SEG104 SEG104 SEG104 SEG104 SEG104 SEG104 SEG104 SEG105 SEG105 SEG105 SEG105 SEG105 SEG105 SEG105 SEG105 SEG105 SEG105 SEG106 SEG106 SEG106 SEG106 SEG106 SEG106 SEG106 SEG106 SEG106 SEG106 SEG107 SEG107 SEG107 SEG107 SEG107 SEG107 SEG107 SEG107 SEG107 SEG107 SEG108 SEG108 SEG108 SEG108 SEG108 SEG108 SEG108 SEG108 SEG108 SEG108 SEG109 SEG109 SEG109 SEG109 SEG109 SEG109 SEG109 SEG109 SEG109 SEG109 SEG110 SEG110 SEG110 SEG110 SEG110 SEG110 SEG110 SEG110 SEG110 SEG110 SEG111 SEG111 SEG111 SEG111 SEG111 SEG111 SEG111 SEG111 SEG111 SEG111 SEG112 SEG112 SEG112 SEG112 SEG112 SEG112 SEG112 SEG112 SEG112 SEG112 SEG113 SEG113 SEG113 SEG113 SEG113 SEG113 SEG113 SEG113 SEG113 SEG113 SEG114 SEG114 SEG114 SEG114 SEG114 SEG114 SEG114 SEG114 SEG114 SEG114 SEG115 SEG115 SEG115 SEG115 SEG115 SEG115 SEG115 SEG115 SEG115 SEG115 SEG116 SEG116 SEG116 SEG116 SEG116 SEG116 SEG116 SEG116 SEG116 SEG116 SEG117 SEG117 SEG117 SEG117 SEG117 SEG117 SEG117 SEG117 SEG117 SEG117 SEG118 SEG118 SEG118 SEG118 SEG118 SEG118 SEG118 SEG118 SEG118 SEG118 SEG119 SEG119 SEG119 SEG119 SEG119 SEG119 SEG119 SEG119 SEG119 SEG119 SEG120 SEG120 SEG120 SEG120 SEG120 SEG120 SEG120 SEG120 SEG120 SEG120 SEG121 SEG121 SEG121 SEG121 SEG121 SEG121 SEG121 SEG121 SEG121 SEG121 SEG122 SEG122 SEG122 SEG122 SEG122 SEG122 SEG122 SEG122 SEG122 SEG122 SEG123 SEG123 SEG123 SEG123 SEG123 SEG123 SEG123 SEG123 SEG123 SEG123 SEG124 SEG124 SEG124 SEG124 SEG124 SEG124 SEG124 SEG124 SEG124 SEG124 SEG125 SEG125 SEG125 SEG125 SEG125 SEG125 SEG125 SEG125 SEG125 SEG125 SEG126 SEG126 SEG126 SEG126 SEG126 SEG126 SEG126 SEG126 SEG126 SEG126 SEG127 SEG127 SEG127 SEG127 SEG127 SEG127 SEG127 SEG127 SEG127 SEG127 SEG128 SEG128 SEG128 SEG128 SEG128 SEG128 SEG128 SEG128 SEG128 SEG128 SEG129 SEG129 SEG129 SEG129 SEG129 SEG129 SEG129 SEG129 SEG129 SEG129 SEG130 SEG130 SEG130 SEG130 SEG130 SEG130 SEG130 SEG130 SEG130 SEG130 SEG131 SEG131 SEG131 SEG131 SEG131 SEG131 SEG131 SEG131 SEG131 SEG131 EPSON X Y 626 676 726 776 826 876 926 976 1026 1076 1126 1176 1226 1276 1326 1376 1426 1476 1526 1576 1626 1676 1726 1776 1826 1877 1927 1977 2027 2077 2127 2177 2227 2277 2327 2377 2427 2477 2527 2577 2627 2677 2727 2777 2827 2877 2927 2977 3027 3077 3128 3178 3228 3278 ­958 X BUMP Y BUMP Size Size 33 126 9 S1D10605 S1D10605 Series Units : µm PAD No. 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 10 S1D10605 S1D10605 DUMMY15 DUMMY15 DUMMY16 DUMMY16 DUMMY17 DUMMY17 DUMMY18 DUMMY18 DUMMY19 DUMMY19 COM32 COM32 COM33 COM33 COM34 COM34 COM35 COM35 COM36 COM36 COM37 COM37 COM38 COM38 COM39 COM39 COM40 COM40 COM41 COM41 COM42 COM42 COM43 COM43 COM44 COM44 COM45 COM45 COM46 COM46 COM47 COM47 COM48 COM48 COM49 COM49 COM50 COM50 COM51 COM51 COM52 COM52 COM53 COM53 COM54 COM54 COM55 COM55 COM56 COM56 COM57 COM57 COM58 COM58 COM59 COM59 COM60 COM60 COM61 COM61 COM62 COM62 COM63 COM63 COMS DUMMY20 DUMMY20 S1D10606 S1D10606 DUMMY23 DUMMY23 DUMMY24 DUMMY24 DUMMY25 DUMMY25 DUMMY26 DUMMY26 DUMMY27 DUMMY27 DUMMY28 DUMMY28 DUMMY29 DUMMY29 COM24 COM24 DUMMY30 DUMMY30 COM25 COM25 DUMMY31 DUMMY31 COM26 COM26 COM27 COM27 COM28 COM28 COM29 COM29 COM30 COM30 COM31 COM31 COM32 COM32 COM33 COM33 COM34 COM34 COM35 COM35 COM36 COM36 COM37 COM37 COM38 COM38 COM39 COM39 COM40 COM40 COM41 COM41 COM42 COM42 COM43 COM43 COM44 COM44 COM45 COM45 COM46 COM46 DUMMY32 DUMMY32 COM47 COM47 DUMMY33 DUMMY33 COMS DUMMY34 DUMMY34 DUMMY35 DUMMY35 DUMMY36 DUMMY36 PIN Name S1D10607 S1D10607 DUMMY15 DUMMY15 DUMMY16 DUMMY16 DUMMY17 DUMMY17 DUMMY18 DUMMY18 DUMMY19 DUMMY19 COM16 COM16 COM16 COM16 COM17 COM17 COM17 COM17 COM18 COM18 COM18 COM18 COM19 COM19 COM19 COM19 COM20 COM20 COM20 COM20 COM21 COM21 COM21 COM21 COM22 COM22 COM22 COM22 COM23 COM23 COM23 COM23 COM24 COM24 COM24 COM24 COM25 COM25 COM25 COM25 COM26 COM26 COM26 COM26 COM27 COM27 COM27 COM27 COM28 COM28 COM28 COM28 COM29 COM29 COM29 COM29 COM30 COM30 COM30 COM30 COM31 COM31 COM31 COM31 COMS DUMMY20 DUMMY20 X S1D10608 S1D10608 DUMMY20 DUMMY20 DUMMY21 DUMMY21 DUMMY22 DUMMY22 DUMMY23 DUMMY23 DUMMY24 DUMMY24 DUMMY25 DUMMY25 COM27 COM27 DUMMY26 DUMMY26 COM28 COM28 DUMMY27 DUMMY27 COM29 COM29 COM30 COM30 COM31 COM31 COM32 COM32 COM33 COM33 COM34 COM34 COM35 COM35 COM36 COM36 COM37 COM37 COM38 COM38 COM39 COM39 COM40 COM40 COM41 COM41 COM42 COM42 COM43 COM43 COM44 COM44 COM45 COM45 COM46 COM46 COM47 COM47 COM48 COM48 COM49 COM49 COM50 COM50 COM51 COM51 COM52 COM52 COM53 COM53 DUMMY28 DUMMY28 COMS DUMMY29 DUMMY29 DUMMY30 DUMMY30 S1D10609 S1D10609 DUMMY21 DUMMY21 DUMMY22 DUMMY22 DUMMY23 DUMMY23 DUMMY24 DUMMY24 DUMMY25 DUMMY25 DUMMY26 DUMMY26 COM26 COM26 DUMMY27 DUMMY27 COM27 COM27 DUMMY28 DUMMY28 COM28 COM28 COM29 COM29 COM30 COM30 COM31 COM31 COM32 COM32 COM33 COM33 COM34 COM34 COM35 COM35 COM36 COM36 COM37 COM37 COM38 COM38 COM39 COM39 COM40 COM40 COM41 COM41 COM42 COM42 COM43 COM43 COM44 COM44 COM45 COM45 COM46 COM46 COM47 COM47 COM48 COM48 COM49 COM49 COM50 COM50 DUMMY29 DUMMY29 COM51 COM51 DUMMY30 DUMMY30 COMS DUMMY31 DUMMY31 DUMMY32 DUMMY32 EPSON Y 3328 3378 3428 3478 3794 ­958 ­836 ­786 ­736 ­686 ­636 ­586 ­536 ­486 ­436 ­386 ­336 ­286 ­236 ­186 ­136 ­86 ­36 14 64 114 164 214 264 314 365 415 465 515 565 615 665 715 765 815 865 X BUMP Y BUMP Size Size 33 126 136 33 Rev.2.1 S1D10605 S1D10605 Series 6. PIN DESCRIPTIONS Power Supply Pins Pin Name VDD VSS VSS2 VRS V1, V2, V3, V4, V5 I/O Power Supply Power Supply Power Supply Power Supply Power Supply Function Shared with the MPU power supply terminal VCC. No. of Pins 13 This is a 0V terminal connected to the system GND. 9 This is the reference power supply for the step-up voltage circuit for the liquid crystal drive. This is the externally-input VREG power supply for the LCD power supply voltage regulator. These are only enabled for the models with the VREG external input option. This is a multi-level power supply for the liquid crystal drive. The voltage applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VDD, and must maintain the relative magnitudes shown below. 4 2 10 VDD (= V0) V1 V2 V3 V4 V5 Master operation: When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command. V1 V2 V3 V4 S1D10605 S1D10605* 1/9·V5 1/7·V5 2/9·V5 2/7·V5 7/9·V5 5/7·V5 8/9·V5 6/7·V5 S1D10606 S1D10606* S1D10607 S1D10607* S1D10608 S1D10608 * S1D10609 S1D10609* 1/8·V5 1/6·V5 1/6·V5 1/5·V5 1/8·V5 1/6·V5 1/8·V5 1/6·V5 2/8·V5 2/6·V5 2/6·V5 2/5·V5 2/8·V5 2/6·V5 2/8·V5 2/6·V5 6/8·V5 4/6·V5 4/6·V5 3/5·V5 6/8·V5 4/6·V5 6/8·V5 4/6·V5 7/8·V5 5/6·V5 5/6·V5 4/5·V5 7/8·V5 5/6·V5 7/6·V5 5/6·V5 LCD Power Supply Circuit Terminals Pin Name I/O Function CAP1+ O CAP1­ O CAP2+ O CAP2­ O CAP3­ O VOUT O VR I DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1­ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2­ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1+ terminal. DC/DC voltage converter. Connect a capacitor between this terminal and VSS. Output voltage regulator terminal. Provides the voltage between VDD and V5 through a resistive voltage divider. These are only enabled when the V5 voltage regulator internal resistors are not used (IRS = LOW). These cannot be used when the V5 voltage regulator internal resistors are used (IRS = HIGH). Rev.2.1 EPSON No. of Pins 2 2 2 2 2 2 2 11 S1D10605 S1D10605 Series System Bus Connection Terminals Pin Name I/O D7 to D0 I/O (SI) (SCL) A0 I RES I CS1 CS2 RD (E) I I WR (R/W) I C86 I P/S I Function This is an 8-bit bi-directional data bus that connects to an 8-bit or 16-bit standard MPU data bus. When the serial interface is selected (P/S = LOW), then D7 serves as the serial data input terminal (SI) and D6 serves as the serial clock input terminal (SCL). At this time, D0 to D5 are set to high impedance. When the chip select is inactive, D0 to D7 are set to high impedance. This is connect to the least significant bit of the normal MPU address bus, and it determines whether the data bits are data or a command. A0 = HIGH: Indicates that D0 to D7 are display data. A0 = LOW: Indicates that D0 to D7 are control data. When RES is set to LOW, the settings are initialized. The reset operation is performed by the RES signal level. This is the chip select signal. When CS1 = LOW and CS2 = HIGH, then the chip select becomes active, and data/command I/O is enabled. · When connected to an 8080 MPU, this is active LOW. This pin is connected to the RD signal of the 8080 MPU, and the S1D10605 S1D10605 series data bus is in an output status when this signal is LOW. · When connected to a 6800 Series MPU, this is active HIGH. This is the 6800 Series MPU enable clock input terminal. · When connected to an 8080 MPU, this is active LOW. This terminal connects to the 8080 MPU WR signal. The signals on the data bus are latched at the rising edge of the WR signal. · When connected to a 6800 Series MPU: This is the read/write control signal input terminal. When R/W = HIGH: Read. When R/W = LOW: Write. This is the MPU interface switch terminal. C86 = HIGH: 6800 Series MPU interface. C86 = LOW: 8080 MPU interface. This is the parallel data input/serial data input switch terminal. P/S = HIGH: Parallel data input. P/S = LOW: Serial data input. The following applies depending on the P/S status: No. of Pins 8 1 1 2 1 1 1 1 P/S Data/Command Data Read/Write Serial Clock HIGH A0 D0 to D7 RD, WR LOW A0 SI (D7) Write only SCL (D6) CLS I When P/S = LOW, D0 to D5 are HZ. D0 to D5 may be HIGH, LOW or Open. RD (E) and WR (P/W) are fixed to either HIGH or LOW. With serial data input, RAM display data reading is not supported. Terminal to select whether or enable or disable the display clock internal oscillator circuit. CLS = HIGH: Internal oscillator circuit is enabled CLS = LOW: Internal oscillator circuit is disabled (requires external input) When CLS = LOW, input the display clock through the CL terminal. When using the S1D10605 S1D10605 Series as a master or slave, set respective CLS pins at the same level. Display clock Built-in oscillator circuit used External input 12 Master HIGH LOW EPSON 1 Slave HIGH LOW Rev.2.1 S1D10605 S1D10605 Series Pin Name M/S I/O I Function This terminal selects the master/slave operation for the S1D10605 S1D10605 Series chips. Master operation outputs the timing signals that are required for the LCD display, while slave operation inputs the timing signals required for the liquid crystal display, synchronizing the liquid crystal display system. M/S = HIGH: Master operation M/S = LOW: Slave operation The following is true depending on the M/S and CLS status: M/S CLS Oscillator Circuit HIGH HIGH LOW LOW HIGH LOW CL I/O Enabled Disabled Disabled Disabled I/O DOF I/O FRS O IRS I HPM I Rev.2.1 CL FR FRS DOF Output Input Input Input Output Output Input Input Output Output Output Output Output Output Input Input This is the display clock input terminal The following is true depending on the M/S and CLS status. M/S CLS HIGH HIGH LOW LOW HIGH LOW FR Power Supply Circuit Enabled Enabled Disabled Disabled No. of Pins 1 1 CL Output Input Input Input When the S1D10605 S1D10605 Series chips are used in master/slave mode, the various CL terminals must be connected. This is the liquid crystal alternating current signal I/O terminal. M/S = HIGH: Output M/S = LOW: Input When the S1D10605 S1D10605 Series chip is used in master/slave mode, the various FR terminals must be connected. This is the liquid crystal display blanking control terminal. M/S = HIGH: Output M/S = LOW: Input When the S1D10605 S1D10605 Series chip is used in master/slave mode, the various DOF terminals must be connected. This is the output terminal for the static drive. This terminal is only enabled when the static indicator display is ON when in master operation mode, and is used in conjunction with the FR terminal. This terminal selects the resistors for the V5 voltage level adjustment. IRS = HIGH: Use the internal resistors IRS = LOW: Do not use the internal resistors. The V5 voltage level is regulated by an external resistive voltage divider attached to the VR terminal. This pin is enabled only when the master operation mode is selected. It is fixed to either HIGH or LOW when the slave operation mode is selected. This is the power control terminal for the power supply circuit for liquid crystal drive. HPM = HIGH: Normal mode HPM = LOW: High power mode This pin is enabled only when the master operation mode is selected. It is fixed to either HIGH or LOW when the slave operation mode is selected. EPSON 1 1 1 1 1 13 S1D10605 S1D10605 Series Liquid Crystal Drive Terminals Pin Name I/O Function SEG0 to SEG131 SEG131 O These are the liquid crystal segment drive outputs. Through a combination of the contents of the display RAM and with the FR signal, a single level is selected from VDD, V 2, V3, and V5. RAM DATA FR HIGH HIGH HIGH LOW LOW HIGH LOW LOW Power save - COM0 to COMn O No. of Pins 132 Output Voltage Normal Display Reverse Display VDD V2 V5 V3 V2 VDD V3 V5 VDD These are the liquid crystal common drive outputs. Part No. S1D10605 S1D10605* S1D10606 S1D10606* S1D10607 S1D10607* S1D10608 S1D10608* S1D10609 S1D10609* COM COM 0 to COM 63 COM 0 to COM 47 COM 0 to COM 31 COM 0 to COM 53 COM 0 to COM 51 Part No. S1D10605 S1D10605* S1D10606 S1D10606* S1D10607 S1D10607* S1D10608 S1D10608* S1D10609 S1D10609* 64 48 32 54 52 Through a combination of the contents of the scan data and with the FR signal, a single level is selected from VDD, V 1, V4, and V5. Scan Data HIGH HIGH LOW LOW Power Save COMS O FR Output Voltage HIGH V5 LOW VDD HIGH V1 LOW V4 - VDD These are the COM output terminals for the indicator. Both terminals output the same signal. Leave these open if they are not used. When in master/slave mode, the same signal is output by both master and slave. 2 Test Terminals Pin Name I/O TEST0 to 4 TEST7 to A TEST5, 6 I/O I Function These are terminals for IC chip testing. They are set to OPEN. These are terminals for IC chip testing. They are set to VDD or OPEN. No. of Pins 12 2 Total: 289 pins for the S1D10605 S1D10605*. 273 pins for the S1D10606 S1D10606*. 257 pins for the S1D10607 S1D10607*. 279 pins for the S1D10608 S1D10608*. 277 pins for the S1D10609 S1D10609*. 14 EPSON Rev.2.1 S1D10605 S1D10605 Series 7. FUNCTION DESCRIPTION The MPU Interface Selecting the Interface Type With the S1D10605 S1D10605 Series chips, data transfers are done through an 8-bit bi-directional data bus (D7 to D0) or through a serial data input (SI). Through selecting the P/S terminal polarity to the HIGH or LOW it is possible to select either parallel data input or serial data input as shown in Table 1. P/S HIGH: Parallel Input LOW: Serial Input CS1 CS1 CS1 CS2 CS2 CS2 Table 1 A0 RD A0 RD A0 - WR WR - C86 C86 - D7 D7 SI D6 D5 to D0 D6 D5 to D0 SCL (HZ) "-" indicates fixed to either HIGH or to LOW "(HZ)" means high-impedance state. The Parallel Interface When the parallel interface has been selected (P/S = HIGH), then it is possible to connect directly to either an 8080system MPU or a 6800 Series MPU (as shown in Table 2) by selecting the C86 terminal to either HIGH or to LOW. P/S HIGH: 6800 Series MPU Bus LOW: 8080 MPU Bus Table 2 CS1 CS2 CS1 CS2 CS1 CS2 A0 A0 A0 RD E RD WR D7 to D0 R/W D7 to D0 WR D7 to D0 Moreover, data bus signals are recognized by a combination of A0, RD (E), WR (R/W) signals, as shown in Table 3. Shared A0 1 1 0 0 Rev.2.1 6800 Series R/W 1 0 1 0 Table 3 8080 Series RD WR 0 1 1 0 0 1 1 0 EPSON Function Reads the display data Writes the display data Status read Write control data (command) 15 S1D10605 S1D10605 Series The Serial Interface When the serial interface has been selected (P/S = LOW) then when the chip is in active state (CS1 = LOW and CS2 = HIGH) the serial data input (SI) and the serial clock input (SCL) can be received. The serial data is read from the serial data input pin in the rising edge of the serial clocks D7, D6 through D0, in this order. This data is converted to 8 bits parallel data in the rising edge of the eighth serial clock for the processing. The A0 input is used to determine whether or the serial data input is display data or command data; when A0 = HIGH, the data is display data, and when A0 = LOW then the data is command data. The A0 input is read and used for detection every 8th rising edge of the serial clock after the chip becomes active. Figure 1 is a serial interface signal chart. CS1 CS2 SI D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 1 2 3 4 5 6 7 8 9 10 D5 D4 D3 D2 13 14 SCL 11 12 A0 Figure 1 * When the chip is not active, the shift registers and the counter are reset to their initial states. * Reading is not possible while in serial interface mode. * Caution is required on the SCL signal when it comes to line-end reflections and external noise. We recommend that operation be rechecked on the actual equipment. The Chip Select The S1D10605 S1D10605 Series chips have two chip select terminals: CS1 and CS2. The MPU interface or the serial interface is enabled only when CS1 = LOW and CS2 = HIGH. When the chip select is inactive, D0 to D7 enter a high impedance state, and the A0, RD, and WR inputs are inactive. When the serial interface is selected, the shift register and the counter are reset. Accessing the Display Data RAM and the Internal Registers Data transfer at a higher speed is ensured since the MPU is required to satisfy the cycle time (tCYC) requirement alone in accessing the S1D10605 S1D10605 Series. Wait time may not be considered. And, in the S1D10605 S1D10605 Series chips, each time data is sent from the MPU, a type of pipeline process between LSIs is performed through the bus holder attached to the internal data bus. For example, when the MPU writes data to the display data RAM, once the data is stored in the bus holder, then it is written to the display data RAM before the next data write cycle. Moreover, when the MPU reads the display data RAM, the first data read cycle (dummy) stores the read data in the bus holder, and then the data is read from the bus holder to the system bus at the next data read cycle. There is a certain restriction in the read sequence of the display data RAM. Please be advised that data of the specified address is not generated by the read instruction issued immediately after the address setup. This data is generated in data read of the second time. Thus, a dummy read is required whenever the address setup or write cycle operation is conducted. This relationship is shown in Figure 2. 16 EPSON Rev.2.1 S1D10605 S1D10605 Series The Busy Flag When the busy flag is "1" it indicates that the S1D10605 S1D10605 Series chip is running internal processes, and at this time no command aside from a status read will be received. The busy flag is outputted to D7 pin with the read instruction. If the cycle time (tCYC) is maintained, it is not necessary to check for this flag before each command. This makes vast improvements in MPU processing capabilities possible. Internal Timing MPU Writing WR DATA N N+1 N+2 N+3 Latch N+1 N BUS Holder N+2 N+3 Write Signal Reading MPU WR RD Internal Timing DATA N N n n+1 Address Preset Read Signal Column Address Preset N Bus Holder Increment N+1 N Address Set #n n Dummy Read N+2 n+1 Data Read #n n+2 Data Read #n+1 Figure 2 Rev.2.1 EPSON 17 S1D10605 S1D10605 Series Display Data RAM Display Data RAM The display data RAM is a RAM that stores the dot data for the display. It has a 65 (8 page × 8 bit +1) × 132 bit structure. It is possible to access the desired bit by specifying the page address and the column address. Because, as is shown in Figure 3, the D7 to D0 display data from the MPU corresponds to the liquid crystal display common direction, there are few constraints at the time of display data transfer when multiple S1D10605 S1D10605 series chips are used, thus and display structures can be created easily and with a high degree of freedom. Moreover, reading from and writing to the display RAM from the MPU side is performed through the I/O buffer, which is an independent operation from signal reading for the liquid crystal driver. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, it will not cause adverse effects on the display (such as flickering). D0 0 1 1 1 0 COM0 D1 1 0 0 0 0 COM1 D2 0 0 0 0 0 COM2 D3 0 1 1 1 0 COM3 D4 1 0 0 0 0 COM4 - - Display data RAM Liquid crystal display Figure 3 The Page Address Circuit As shown in Figure 4, page address of the display data RAM is specified through the Page Address Set Command. The page address must be specified again when changing pages to perform access. Page address 8 (D3, D2, D1, D0 = 1, 0, 0, 0) is the page for the RAM region used only by the indicators, and only display data D0 is used. The Column Addresses As is shown in Figure 4, the display data RAM column address is specified by the Column Address Set command. The specified column address is incremented (+1) with each display data read/write command. This allows the MPU display data to be accessed continuously. Moreover, the incrementation of column addresses stops with 83H. Because the column address is independent of the page address, when moving, for example, from page 0 column 83H to page 1 column 00H, it is necessary to respecify both the page address and the column address. Furthermore, as is shown in Table 4, the ADC command (segment driver direction select command) can be used to reverse the relationship between the display data RAM column address and the segment output. Because of this, the constraints on the IC layout when the LCD module is assembled can be minimized. Table 4 SEG SEG 131 Output SEG0 ADC "0" 0 (H) Column Address 83 (H) (D0) "1" 83 (H) Column Address 0 (H) The Line Address Circuit The line address circuit, as shown in Table 4, specifies the line address relating to the COM output when the contents of the display data RAM are displayed. Using the display start line address set command, what is normally the top line of the display can be specified (this is the COM0 output when the common output mode is normal, and the COM63 COM63 output for S1D10605 S1D10605 Series, COM47 COM47 output for S1D10606 S1D10606 Series, COM31 COM31 output for the S1D10607 S1D10607, COM53 COM53 output for the S1D10608 S1D10608 and COM51 COM51 output for the S1D10609 S1D10609 Series when the common output mode is reversed. The display area is a 65 line area for the S1D10605 S1D10605 Series, a 49 line area for the S1D10606 S1D10606, a 33 line area for the S1D10607 S1D10607, a 55 line area for the S1D10608 S1D10608 and a 53 line area for the S1D10609 S1D10609 from the display start line address. If the line addresses are changed dynamically using the display start line address set command, screen scrolling, page swapping, etc. can be performed. 18 EPSON Rev.2.1 S1D10605 S1D10605 Series 0 1 0 0 0 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 Page 3 Page 4 Page 5 Page 6 Page 7 Page 8 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 83 82 81 80 7F 7E 7D 7C 00 01 02 03 04 05 06 07 0 Page 2 54 lines 0 Page 1 Start 32 lines 1 48 lines 0 52 lines 0 63 lines 0 Page 0 1 0 D0 D0 ADC Column Address 0 LCD Out 0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 11H 12H 13H 14H 15H 16H 17H 18H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 7C 7D 7E 7F 80 81 82 83 0 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 07 06 05 04 03 02 01 00 0 When the Line common output Address mode is normal Data SEG127 SEG127 SEG125 SEG125 SEG126 SEG126 SEG127 SEG127 SEG128 SEG128 SEG129 SEG129 SEG130 SEG130 SEG131 SEG131 Page Address D3 D2 D1 D0 COM Output COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM10 COM11 COM11 COM12 COM12 COM13 COM13 COM14 COM14 COM15 COM15 COM16 COM16 COM17 COM17 COM18 COM18 COM19 COM19 COM20 COM20 COM21 COM21 COM22 COM22 COM23 COM23 COM24 COM24 COM25 COM25 COM26 COM26 COM27 COM27 COM28 COM28 COM29 COM29 COM30 COM30 COM31 COM31 COM32 COM32 COM33 COM33 COM34 COM34 COM35 COM35 COM36 COM36 COM37 COM37 COM38 COM38 COM39 COM39 COM40 COM40 COM41 COM41 COM42 COM42 COM43 COM43 COM44 COM44 COM45 COM45 COM46 COM46 COM47 COM47 COM48 COM48 COM49 COM49 COM50 COM50 COM51 COM51 COM52 COM52 COM53 COM53 COM54 COM54 COM55 COM55 COM56 COM56 COM57 COM57 COM58 COM58 COM59 COM59 COM60 COM60 COM61 COM61 COM62 COM62 COM63 COM63 COMS Regardless of the display start line address, the S1D10605 S1D10605 Series accesses 65th line, the S1D10606 S1D10606 Series accesses 49th line and the S1D10607 S1D10607 Series accesses 33th line and the S1D10608 S1D10608 Series accesses 55th line, the S1D10609 S1D10609 Series accesses 53 lines. Figure 4 Rev.2.1 EPSON 19 S1D10605 S1D10605 Series The Display Data Latch Circuit The display data latch circuit is a latch that temporarily stores the display data that is output to the liquid crystal driver circuit from the display data RAM. Because the display normal/reverse status, display ON/OFF status, and display all points ON/OFF commands control only the data within the latch, they do not change the data within the display data RAM itself. The Oscillator Circuit This is a CR-type oscillator that produces the display clock. The oscillator circuit is only enabled when M/S = HIGH and CLS = HIGH. When CLS = LOW the oscillation stops, and the display clock is input through the CL terminal. Display Timing Generator Circuit The display timing generator circuit generates the timing signal to the line address circuit and the display data latch circuit using the display clock. The display data is latched into the display data latch circuit synchronized with the display clock, and is output to the data driver output terminal. Reading to the display data liquid crystal driver circuits is completely independent of accesses to the display data RAM by the MPU. Consequently, even if the display data RAM is accessed asynchronously during liquid crystal display, there is absolutely no adverse effect (such as flickering) on the display. Moreover, the display timing generator circuit generates the common timing and the liquid crystal alternating current signal (FR) from the display clock. It generates a drive wave form using a 2 frame alternating current drive method, as is shown in Figure 5, for the liquid crystal drive circuit. Two-frame alternating current drive wave form (S1D10605 S1D10605*) 64 65 1 2 3 4 5 6 60 61 62 63 64 65 1 2 3 4 5 6 CL FR VDD V1 COM0 V4 V5 VDD V1 COM1 V4 V5 RAM DATA VDD V2 SEGn V3 V5 Figure 5 20 EPSON Rev.2.1 S1D10605 S1D10605 Series When multiple S1D10605 S1D10605 Series chips are used, the slave chips must be supplied the display timing signals (FR, CL, DOF) from the master chip[s]. Table 5 shows the status of the FR, CL, and DOF signals. Table 5 Operating Mode Master (M/S = HIGH) The internal oscillator circuit is enabled (CLS = HIGH) The internal oscillator circuit is disabled (CLS = LOW) Slave (M/S = LOW) Set the CLS pin to the same level as with the master. FR Output Output Input Input CL Output Input Input Input DOF Output Output Input Input The Common Output Status Select Circuit In the S1D10605 S1D10605 Series chips, the COM output scan direction can be selected by the common output status select command. (See Table 6.) Consequently, the constraints in IC layout at the time of LCD module assembly can be minimized. Table 6 Status COM Scan Direction S1D10605 S1D10605* S1D10606 S1D10606* S1D10607 S1D10607* S1D10608 S1D10608* S1D10609 S1D10609* Normal COM0 COM63 COM63 COM0 COM47 COM47 COM0 COM31 COM31 COM0 COM53 COM53 COM0 COM51 COM51 Reverse COM63 COM63 COM0 COM47 COM47 COM0 COM31 COM31 COM0 COM53 COM53 COM0 COM51 COM51 COM0 The Liquid Crystal Driver Circuits These are a 197-channel (S1D10605 S1D10605 Series), a 181-channel (S1D10606 S1D10606 Series) multiplexers 165-channel (S1D10607 S1D10607 Series), a 187-channel (S1D10608 S1D10608 Series). and a 185-channel (S1D10609 S1D10609 Series) that generate four voltage levels for driving the liquid crystal. The combination of the display data, the COM scan signal, and the FR signal produces the liquid crystal drive voltage output. Figure 6 shows examples of the SEG and COM output wave form. Rev.2.1 EPSON 21 S1D10605 S1D10605 Series COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM10 COM11 COM11 COM12 COM12 COM13 COM13 COM14 COM14 COM15 COM15 FR VDD VSS COM0 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 COM1 COM2 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 VDD V1 V2 V3 V4 V5 SEG0 SEG1 SEG2 COM0­SEG0 V5 V4 V3 V2 V1 V ­V1 ­V2 ­V3 ­V4 ­V5 COM0­SEG1 V5 V4 V3 V2 V1 V ­V1 ­V2 ­V3 ­V4 ­V5 COM0­SEG0 V5 V4 V3 V2 V1 V ­V1 ­V2 ­V3 ­V4 ­V5 COM0­SEG1 V5 V4 V3 V2 V1 V ­V1 ­V2 ­V3 ­V4 ­V5 Figure 6 22 EPSON Rev.2.1 S1D10605 S1D10605 Series The Power Supply Circuits The power supply circuits are low-power consumption power supply circuits that generate the voltage levels required for the liquid crystal drivers. They comprise Booster circuits, voltage regulator circuits, and voltage follower circuits. They are only enabled in master operation. The power supply circuits can turn the Booster circuits, the voltage regulator circuits, and the voltage follower circuits ON of OFF independently through the use of the Power Control Set command. Consequently, it is possible to make an external power supply and the internal power supply function somewhat in parallel. Table 7 shows the Power Control Set Command 3-bit data control function, and Table 8 shows reference combinations. Table 7 The Control Details of Each Bit of the Power Control Set Command Status Item "1" "0" D2 Booster circuit control bit ON OFF D1 Voltage regulator circuit (V regulator circuit) control bit ON OFF D0 Voltage follower circuit (V/F circuit) control bit ON OFF Table 8 Reference Combinations Use Settings Step-up D2 D1 D0 circuit V V/F regulator circuit circuit Step-up External voltage voltage system input terminal VSS2 Used Only the internal power supply is 1 1 1 O O O used 2 Only the V regulator circuit and 0 1 1 X O O VOUT, VSS2 Open the V/F circuit are used 3 Only the V/F circuit is used 0 0 1 X X O V5, V SS2 Open 4 Only the external power supply is 0 0 0 X X X V1 to V5 Open used * The "step-up system terminals" refer CAP1+, CAP1­, CAP2+, CAP2­, and CAP3­. * While other combinations, not shown above, are also possible, these combinations are not recommended because they have no practical use. 1 The Step-up Voltage Circuits Using the step-up voltage circuits equipped within the S1D10605 S1D10605 Series chips it is possible to product a Quad step-up, a Triple step-up, and a Double step-up of the VDD ­ VSS2 voltage levels. Quad step-up: Connect capacitor C1 between CAP1+ and CAP1­, between CAP2+ and CAP2­, between CAP1+ and CAP3­, and between VSS2 and VOUT, to produce a voltage level in the negative direction at the V OUT terminal that is 4 times the voltage level between VDD and VSS2 . Triple step-up: Connect capacitor C1 between CAP1+ and CAP1­, between CAP2+ and CAP2­ and between VSS2 and VOUT, and short between CAP3­ and VOUT to produce a voltage level in the negative direction at the VOUT terminal that is 3 times the voltage difference between VDD and V SS2. Double step-up: Connect capacitor C1 between CAP1+ and CAP1­, and between VSS2 and VOUT, leave CAP2+ open, and short between CAP2­, CAP3­ and VOUT to produce a voltage in the negative direction at the VOUT terminal that is twice the voltage between VDD and VSS2. The step-up voltage relationships are shown in Figure 7. Rev.2.1 EPSON 23 S1D10605 S1D10605 Series VSS2 + + CAP1+ C1 CAP1­ C1 VOUT CAP3­ CAP1+ + C1 CAP1­ CAP2­ C1 VOUT S1D10605 S1D10605 Series CAP3­ C1 S1D10605 S1D10605 Series VOUT VSS2 + C1 CAP3­ CAP1+ + C1 CAP1­ CAP2­ CAP2­ CAP2+ S1D10605 S1D10605 Series VSS2 + C1 OPEN CAP2+ C1 + CAP2+ 4 x step-up voltage circuit + 3 x step-up voltage circuit VDD = 0V VDD = 0V VSS2 = ­3V 2 x step-up voltage circuit VSS2 = ­3V VDD = 0V VSS2 = ­4V VOUT = 3 x VSS2 = ­9V VOUT = 2 x VSS2 = ­8V VOUT = 4 x VSS2 = ­12V 4x step-up voltage relationships 3x step-up voltage relationships 2x step-up voltage relationships Figure 7 * The V SS2 voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value. * Low VDD - VSS voltage causes decrease in efficiency of step-up. Usage above 2.4V for VDD - VSS is recommended. The Voltage Regulator Circuit The step-up voltage generated at VOUT outputs the liquid crystal driver voltage V5 through the voltage regulator circuit. Because the S1D10605 S1D10605 Series chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V5 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components. Moreover, in the S1D10605 S1D10605 Series, thermal gradients have been prepared as VREG options: approximately ­0.05%/°C. (A) When the V5 Voltage Regulator Internal Resistors Are Used Through the use of the V5 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V5 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V5 voltage can be calculated using equation A-1 over the range where | V5 | < | VOUT |. 24 EPSON Rev.2.1 S1D10605 S1D10605 Series Rb V5 = 1 + VEV Ra Rb = 1+ 1­ VREG Ra 162 [Q V = (1 - 162) V ] EV (Equation A-1) REG VDD VEV (constant voltage supply + electronic volume) Internal Ra + V5 ­ Internal Rb Figure 8 VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 9. Equipment Type Internal Power Supply Table 9 Thermal Gradient ­0.05 Units [%/°C ] VREG ­2.1 Units [V] is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronic volume register. Table 10 shows the value for depending on the electronic volume register settings. Rb/Ra is the V5 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V 5 voltage regulator internal resistor ratio set command. The (1 + Rb/Ra) ratio assumes the values shown in Table 11 depending on the 3-bit data settings in the V5 voltage regulator internal resistor ratio register. Table 10 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 . . . 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 Rev.2.1 63 62 61 . . . 2 1 0 EPSON 25 S1D10605 S1D10605 Series V5 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value) Table 11 S1D10605 S1D10605* S1D10606 S1D10606* Register Equipment Type by Thermal Gradient [Units: %/°C ] Equipment Type by Thermal Gradient [Units: %/°C ] D2 D1 D0 ­0.05 ­0.05 0 0 0 3.0 3.0 0 0 1 3.5 3.5 0 1 0 4.0 4.0 0 1 1 4.5 4.5 1 0 0 5.0 5.0 1 0 1 5.5 5.4 1 1 0 6.0 5.9 1 1 1 6.4 6.4 S1D10607 S1D10607* S1D10608 S1D10608*/S1D10609 /S1D10609* Register Equipment Type by Thermal Gradient [Units: %/°C ] Equipment Type by Thermal Gradient [Units: %/°C ] D2 D1 D0 ­0.05 ­0.05 0 0 0 3.0 3.0 0 0 1 3.5 3.5 0 1 0 4.0 4.0 0 1 1 4.5 4.5 1 0 0 5.0 5.0 1 0 1 5.4 5.4 1 1 0 5.9 5.9 1 1 1 6.4 6.4 For the internal resistance ratio, a manufacturing dispersion of up to ±7% should be taken into account. When not within the tolerance, adjust the V5 voltage by externally mounting Ra and Rb. Figs. 9 (for S1D10605 S1D10605 Series), Figs. 10 (for S1D10606 S1D10606 Series) Figs. 11 (for S1D10607 S1D10607 Series), Figs.12 (for S1D 10608*) and Figs. 13 (for S1D10609 S1D10609 Series). show V5 voltage measured by values of the internal resistance ratio resistor for V5 voltage adjustment and electric volume resister for each temperature grade model, when Ta = 25 °C. 26 EPSON Rev.2.1 S1D10605 S1D10605 Series S1D10605D00B S1D10605D00B * ­16 ­15 ­14 111 ­13 110 ­11 101 ­10 100 ­9 011 ­8 010 ­7 001 ­6 V5 [v] ­12 000 ­5 ­4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) ­3 ­2 ­1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 9: S1D10605D00B S1D10605D00B* For Models Where the Thermal Gradient = ­0.05%/°C The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic volume register. S1D10606D00B S1D10606D00B * ­16 ­15 ­14 111 ­13 110 ­12 101 ­11 100 ­10 011 V5 [v] ­9 010 ­8 001 ­7 000 ­6 ­5 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) ­4 ­3 ­2 ­1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 10: S1D10606D00B S1D10606D00B* For Models Where the Thermal Gradient = ­0.05%/°C The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic volume register. Rev.2.1 EPSON 27 S1D10605 S1D10605 Series ­16 S1D10607D00B S1D10607D00B* ­15 ­14 111 ­13 110 ­12 101 ­11 100 ­10 011 V5 [v] ­9 010 ­8 001 ­7 000 ­6 ­5 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) ­4 ­3 ­2 ­1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 11: S1D10607D00B S1D10607D00B* For Models Where the Thermal Gradient = ­0.05%/°C The V5 voltage as a function of the V5 voltage regulator internal resistor ratio register and the electronic volume register. S1D10608D00B S1D10608D00B* ­16 111 ­15 110 ­14 ­13 101 ­12 ­11 100 ­10 011 V5 [v] ­9 ­8 010 ­7 001 ­6 ­5 000 ­4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) ­3 ­2 ­1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 12: S1D10608D00B S1D10608D00B* For Models Where the Thermal Gradient = ­0.05%/°C The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic volume register. 28 EPSON Rev.2.1 S1D10605 S1D10605 Series ­16 S1D10609D00B S1D10609D00B * 111 ­15 110 ­14 ­13 101 ­12 ­11 100 ­10 011 V5 [v] ­9 ­8 010 ­7 001 ­6 ­5 000 ­4 The V5 voltage regulator internal resistance ratio registers (D2, D1, D0) ­3 ­2 ­1 Electric Volume Resister 3FH 30H 18H 00H 0 Figure 13: S1D10609D00B S1D10609D00B* Temperature Gradient = ­0.05%/°C Model The V5 voltage as a function of the V 5 voltage regulator internal resistor ratio register and the electronic volume register. Setup example: When selecting Ta = 25°C and V5 = 7 V for an S1D10607 S1D10607 model on which Temperature gradient = ­0.05%/°C. Using Figure 15 and the equation A-1, the following setup is enabled. At this time, the variable range and the notch width of the V 5 voltage is, as shown Table 13, as dependent on the electronic volume. Table 12 Contents For V5 voltage regulator Electronic Volume V5 Variable Range Notch width Rev.2.1 Min. ­8.4 (63 levels) Register D5 D4 D3 D2 D1 D0 - - - 0 1 0 1 0 0 1 0 1 Table 13 Typ. Max. ­6.8 (central value) ­5.1 (0 level) 51 EPSON Units [V] [mV] 29 S1D10605 S1D10605 Series (B) When an External Resistance is Used (i.e., The V5 Voltage Regulator Internal Resistors Are Not Used) (1) The liquid crystal power supply voltage V5 can also be set without using the V5 voltage regulator internal resistors (IRS terminal = LOW) by adding resistors Ra' and Rb' between VDD and VR, and between VR and V 5, respectively. When this is done, the use of the electronic volume function makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal power supply voltage V5 through commands. In the range where | V5 | < | VOUT |, the V5 voltage can be calculated using equation B-1 based on the external resistances Ra' and Rb'. Rb' VEV V5 = 1 + Ra' Rb' = 1+ 1­ VREG Ra' 162 [Q V = (1 - 162) V ] EV (Equation B-1) REG VDD VEV (fixed voltage power supply + electronic volume) External resistor Ra' + V5 ­ External resistor Rb' Figure 14 Setup example: When selecting Ta = 25°C and V5 = ­7 V for an S1D10607 S1D10607 Series model where the temperature gradient = ­0.05%/°C. When the central value of the electron volume register is (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), then = 31 and VREG = ­2.1 V so, according to equation B-1, Rb' V5 = 1 + 1- VREG Ra' 162 31 Rb' -11V = 1 + 1- ( -2.1) (Equation B-2) Ra' 162 Moreover, when the value of the current running through Ra' and Rb' is set to 5 µA, (Equation B-3) Ra' + Rb' = 1.4 M Consequently, by equations B-2 and B-3, Rb' = 3.12 Ra' Ra' = 340 k Rb' = 1060 k At this time, the V5 voltage variable range and notch width, based on the electron volume function, is as given in Table 14. V5 Variable Range Notch width 30 Min. ­8.6 (63 levels) Table 14 Typ. Max. ­7.0 (central value) ­5.3 (0 level) 52 EPSON Units [V] [mV] Rev.2.1 S1D10605 S1D10605 Series (C) When External Resistors are Used (i.e. The V5 Voltage Regulator Internal Resistors Are Not Used). (2) When the external resistor described above are used, adding a variable resistor as well makes it possible to perform fine adjustments on Ra' and Rb', to set the liquid crystal drive voltage V5 . In this case, the use of the electronic volume function makes it possible to control the liquid crystal power supply voltage V5 by commands to adjust the liquid crystal display brightness. In the range where | V 5 | < | VOUT | the V5 voltage can be calculated by equation C-1 below based on the R 1 and R2 (variable resistor) and R3 settings, where R 2 can be subjected to fine adjustments ( R2). R + R2 - R2 V5 = 1 + 3 VEV R1 + R2 R + R2 - R2 = 1 + 3 1­ VREG R1 + R2 162 [ ( ) Q VEV = 1 - 162 VREG ] (Equation C-1) VDD VEV (fixed voltage supply + electronic volume) Ra' External resistor R1 + V5 R2 External resistor R2 ­ VR Rb' External resistor R3 Figure 15 Setup example: When selecting Ta = 25°C and V5 = ­5 to ­9 V (using R2) for an S1D10607 S1D10607 model where the temperature gradient = ­0.05%/°C. When the central value for the electronic volume register is set at (D5, D4, D3, D2, D1, D0) = (1, 0, 0, 0, 0, 0), = 31 VREG = -2.1V so, according to equation C-1, when R2 = 0 , in order to make V5 = ­9 V, R + R2 31 -9V = 1 + 3 1 - 162 ( -2.1) R1 (Equation C-2) When R2 = R 2, in order to make V = ­5 V, R3 31 1- ( -2.1) -5V = 1 + R1 + R2 162 (Equation C-3) Moreover, when the current flowing VDD and V5 is set to 5 µA, R1 + R2 + R3 = 1.4 M (Equation C-4) With this, according to equation C-2, C-3 and C-4, R1 = 264 k R2 = 211k R3 = 925k At this time, the V5 voltage variable range and notch width based on the electron volume function is as shown in Table 15. Rev.2.1 EPSON 31 S1D10605 S1D10605 Series V5 Variable Range Notch width Table 15 Typ. Max. ­7.0 (central value) ­5.3 (0 level) 53 Min. ­8.7 (63 levels) Units [V] [mV] * When the V 5 voltage regulator internal resistors or the electronic volume function is used, it is necessary to at least set the voltage regulator circuit and the voltage follower circuit to an operating mode using the power control set commands. Moreover, it is necessary to provide a voltage from V OUT when the Booster circuit is OFF. * The VR terminal is enabled only when the V5 voltage regulator internal resistors are not used (i.e. the IRS terminal = LOW). When the V5 voltage regulator internal resistors are used (i.e. when the IRS terminal = HIGH), then the V R terminal is left open. * Because the input impedance of the VR terminal is high, it is necessary to take into consideration short leads, shield cables, etc. to handle noise. The Liquid Crystal Voltage Generator Circuit The V5 voltage is produced by a resistive voltage divider within the IC, and can be produced at the V1, V2, V 3, and V4 voltage levels required for liquid crystal driving. Moreover, when the voltage follower changes the impedance, it provides V1, V2, V3 and V4 to the liquid crystal drive circuit. 1/9 bias or 1/7 bias for S1D10605 S1D10605 Series, 1/8 bias or 1/ 6 bias for S1D10606 S1D10606 Series, 1/6 bias or 1/5 bias for the S1D10607 S1D10607 Series 1/8 bias or 1/6 bias for S1D10608 S1D10608 Series and 1/8 bias or 1/6 bias for S1D10609 S1D10609 Series can be selected. High Power Mode The power supply circuit equipped in the S1D10605 S1D10605 Series chips has very low power consumption (normal mode: HPM = HIGH). However, for LCDs or panels with large loads, this low-power power supply may cause display quality to degrade. When this occurs, setting the HPM terminal to LOW (high power mode) can improve the quality of the display. We recommend that the display be checked on actual equipment to determine whether or not to use this mode. Moreover, if the improvement to the display is inadequate even after high power mode has been set, then it is necessary to add a liquid crystal drive power supply externally. The Internal Power Supply Shutdown Command Sequence The sequence shown in Figure 16 is recommended for shutting down the internal power supply, first placing the power supply in power saver mode and then turning the power supply OFF. Sequence Details (Command, status) Command address D7 D6 D5 D4 D3 D2 D1 D0 Step1 Display OFF 1 0 1 0 1 1 1 0 Step2 Display all points ON 1 0 1 0 0 1 0 1 End Power saver commands (compound) Internal power supply OFF Figure 16 32 EPSON Rev.2.1 S1D10605 S1D10605 Series Reference Circuit Examples Figure 17 shows reference circuit examples. 1 When used all of the step-up circuit, voltage regulating circuit and V/F circuit (1) When the voltage regulator internal resistor is used. (Example where VSS2 = VSS, with 4x step-up) (2) When the voltage regulator internal resistor is not used. (Example where VSS2 = VSS, with 4x step-up) VDD C1 C1 C1 VDD VSS2 VOUT CAP3­ CAP1+ CAP1­ CAP2+ CAP2­ V5 VR VDD C2 C2 C2 C2 C2 V1 IRS C1 VSS C1 C1 C1 R3 R2 VDD VDD C2 V2 V3 V4 C2 V4 V5 C2 V5 (2) When the V5 voltage regulator internal resistor is used. VSS2 VOUT CAP3­ CAP1+ CAP1­ CAP2+ CAP2­ V5 VR R1 VDD C2 C2 C2 C2 C2 Rev.2.1 V1 VDD M/S IRS VSS External power supply S1D10605 S1D10605 Series R2 VDD V2 V3 IRS R3 V1 C2 VDD External power supply R1 C2 2 When the voltage regulator circuit and V/F circuit alone are used (1) When the V5 voltage regulator internal resistor is not used. VSS VSS2 VOUT CAP3­ CAP1+ CAP1­ CAP2+ CAP2­ V5 VR M/S VDD VSS2 VOUT CAP3­ CAP1+ CAP1­ CAP2+ CAP2­ V5 VR VDD C2 C2 V2 V1 M/S S1D10605 S1D10605 Series C1 VSS M/S S1D10605 S1D10605 Series IRS S1D10605 S1D10605 Series VDD V2 V3 C2 V3 V4 C2 V4 V5 C2 V5 EPSON 33 S1D10605 S1D10605 Series 3 When the V/F circuit alone is used 4 When the built-in power is not used VSS VSS2 VOUT CAP3­ CAP1+ CAP1­ CAP2+ CAP2­ V5 VR VSS External power supply VDD VDD C2 V1 C2 IRS M/S VSS2 VOUT CAP3­ CAP1+ CAP1­ CAP2+ CAP2­ V5 VR S1D10605 S1D10605 Series IRS VDD VDD V1 V2 C2 V4 C2 External power supply V3 C2 VDD V5 M/S S1D10605 S1D10605 Series VDD V2 V3 V4 V5 5 When the built-in power circuit is used to drive a liquid crystal panel heavily loaded with AC or DC, it is recommended to connect an external resistor to stabilize potentials of V1, V2, V3 and V 4 which are output from the built-in voltage follower. Examples of shared reference settings When V5 can vary between ­8 and 12 V Item Set value Units C1 C2 1.0 to 4.7 0.01 to 1.0 µF µF VDD, V0 R4 C2 V1 V2 V3 S1D10605 S1D10605 Series R4 V4 R4 R4 V5 Reference set value R4: 100k to 1M It is recommended to set an optimum resistance value R4 taking the liquid crystal display and the drive waveform. Figure 17 * 1 Because the VR terminal input impedance is high, use short leads and shielded lines. * 2 C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage. * 3 When using external power supply, large current flows during RES = LOW. Please be careful. Example of the Process by which to Determine the Settings: · Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to V OUT from the outside. · Determine C 2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that stabilizes the liquid crystal drive voltages (V 1 to V5 ). Note that all C2 capacitors must have the same capacitance value. · Next turn all the power supplies ON and determine C 1. 34 EPSON Rev.2.1 S1D10605 S1D10605 Series * Precautions when installing the COG When installing the COG, it is necessary to duly consider the fact that there exists a resistance of the ITO wiring occurring between the driver chip and the externally connected parts (such as capacitors and resistors). By the influence of this resistance, non-conformity may occur with the indications on the liquid crystal display. Therefore, when installing the COG design the module paying sufficient considerations to the following three points. 1. Suppress the resistance occurring between the driver chip pin to the externally connected parts as much as possible. 2. Suppress the resistance connecting to the power supply pin of the driver chip. 3. Make various COG module samples with different ITO sheet resistance to select the module with the sheet resistance with sufficient operation margin. Also, as for this driver IC, pay sufficient attention to the following points when connecting to external parts for the characteristics of the circuit. 1. Connection to the boosting capacitors The boosting capacitors (the capacitors connecting to respective CAP pins and capacitor being inserted between VOUT and VSS2) of this IC are being switched over by use of the transistor with very low ON-resistance of about 10. However, when installing the COG, the resistance of ITO wiring is being inserted in series with the switching transistor, thus dominating the boosting ability. Consequently, the boosting ability will be hindered as a result and pay sufficient attention to the wiring to respective boosting capacitors. 2. Connection of the smoothing capacitors for the liquid crystal drive The smoothing capacitors for the liquid crystal driving potentials (V1. V 2, V3 and V4) are indispensable for liquid crystal drives not only for the purpose of mere stabilization of the voltage levels. If the ITO wiring resistance which occurs pursuant to installation of the COG is supplemented to these smoothing capacitors, the liquid crystal driving potentials become unstable to cause non-conformity with the indications of the liquid crystal display. Therefore, when using the COG module, we definitely recommend to connect reinforcing resistors externally. Reference value of the resistance is 100k to 1M. Meanwhile, because of the existence of these reinforcing resistors, current consumption will increase. Indicated below is an exemplary connection diagram of external resistors. Please make sufficient evaluation work for the display statuses with any connection tests. Exemplary connection diagram 1. Exemplary connection diagram 2. VDD VDD VDD R4 V1 V2 C2 V3 C2 V1 C2 R4 S1D10605 S1D10605 Series C2 V2 C2 V3 C2 S1D10605 S1D10605 Series R4 VDD R4 V4 C2 C2 V4 R4 R4 C2 Rev.2.1 V5 C2 EPSON V5 35 S1D10605 S1D10605 Series The Reset Circuit When the RES input comes to the LOW level, these LSIs return to the default state. Their default states are as follows: 1. Display OFF 2. Normal display 3. ADC select: Normal (ADC command D0 = LOW) 4. Power control register: (D2, D1, D0) = (0, 0, 0) 5. Serial interface internal register data clear 6. LCD power supply bias rate: S1D10605 S1D10605* . 1/9 bias S1D10606 S1D10606*, 10608*, 10609* . 1/8 bias S1D10607 S1D10607* . 1/6 bias 7. All-indicator lamps-on OFF (All-indicator lamps ON/OFF command D0 = LOW) 8. Power saving clear 9. V5 voltage regulator internal resistors Ra and Rb separation (Internal resistors are connected while RES is LOW.) 10. Output conditions of SEG and COM terminals SEG : V2/V3 , COM : V1/V4 (Both the SEG terminal and the COM terminal output the VDA level while RES is LOW.) 11. Read modify write OFF 12. Static indicator OFF Static indicator register : (D1, D2) = (0, 0) 13. Display start line set to first line 14. Column address set to Address 0 15. Page address set to Page 0 16. Common output status normal 17. V5 voltage regulator internal resistor ratio set mode clear 18. Electronic volume register set mode clear Electronic volume register : (D5, D4, D3, D2, D1, D0) = (1, 0. 0, 0, 0, 0) 19. Test mode clear On the other hand, when the reset command is used, the above default settings from 11 to 19 are only executed. When the power is turned on, the IC internal state becomes unstable, and it is necessary to initialize it using the RES terminal. After the initialization, each input terminal should be controlled normally. Moreover, when the control signal from the MPU is in the high impedance, an overcurrent may flow to the IC. After applying a current, it is necessary to take proper measures to prevent the input terminal from getting into the high impedance state. If the internal liquid crystal power supply circuit is not used, it is necessary that RES is HIGH when the external liquid crystal power supply is turned on. This IC has the function to discharge V5 when RES is LOW, and the external power supply short-circuits to VDD when RES is LOW. While RES is LOW, the oscillator and the display timing generator stop, and the CL, FR, FRS and DOF terminals are fixed to HIGH. The terminals D0 to D7 are not affected. The VDD level is output from the SEG and COM output terminals. This means that an internal resistor is connected between VDD and V5. 36 EPSON Rev.2.1 S1D10605 S1D10605 Series 8. COMMAND DESCRIPTION The S1D10605 S1D10605 Series chips identify the data bus signals by a combination of A0, RD (E), WR (R/W) signals. Command interpretation and execution does not depend on the external clock, but rather is performed through internal timing only, and thus the processing is fast enough that normally a busy check is not required. In the 8080 MPU interface, commands are launched by inputting a low pulse to the RD terminal for reading, and inputting a low pulse to the WR terminal for writing. In the 6800 Series MPU interface, the interface is placed in a read mode when an HIGH signal is input to the R/W terminal and placed in a write mode when a LOW signal is input to the R/W terminal and then the command is launched by inputting a high pulse to the E terminal. (See "11. Timing Characteristics" regarding the timing.) Consequently, the 6800 Series MPU interface is different than the 80x86 Series MPU interface in that in the explanation of commands and the display commands the status read and display data read RD (E) becomes "1(H)". In the explanations below the commands are explained using the 8080 Series MPU interface as the example. When the serial interface is selected, the data is input in sequence starting with D7. (1) Display ON/OFF This command turns the display ON and OFF. A0 0 E R/W RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 0 1 1 1 1 0 Setting Display ON Display OFF When the display OFF command is executed when in the display all points ON mode, power saver mode is entered. See the section on the (20) "power saver" for details. (2) Display Start Line Set This command is used to specify the display start line address of the display data RAM shown in Figure 4. For further details see the 7. FUNCTION DESCRIPTION in "The Line Address Circuit". A0 0 E R/W RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 1 1 Line address 0 1 2 62 63 (3) Page Address Set This command specifies the page address corresponding to the low address when the MPU accesses the display data RAM (see Figure 4). Specifying the page address and column address enables to access a desired bit of the display data RAM. Changing the page address does not accompany a change in the status display. See the "page address" circuit in the 7. Function Description for the detail. A0 0 E R/W RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 0 0 Rev.2.1 EPSON Page address 0 1 2 7 8 37 S1D10605 S1D10605 Series (4) Column Address Set This command specifies the column address of the display data RAM shown in Figure 4. The column address is split into two sections (the higher 4 bits and the lower 4 bits) when it is set (fundamentally, set continuously). Each time the display data RAM is accessed, the column address automatically increments (+1), making it possible for the MPU to continuously read from/write to the display data. The column address increment is topped at 83H. This does not change the page address continuously. See the 7. Function Description in "The Column Address Circuit," for details. A0 High bits 0 Low bits E R/W RD WR D7 D6 D5 D4 D3 D2 D1 D0 A7 1 0 0 0 0 1 A7 A6 A5 A4 0 0 A3 A2 A1 A0 0 0 1 1 A6 0 0 0 A5 0 0 0 0 0 0 0 A4 0 0 0 A3 0 0 0 0 0 0 0 A2 0 0 0 0 0 Column A0 address 0 0 1 1 0 2 1 0 130 1 1 131 A1 0 0 1 (5) Status Read A0 0 E R/W RD WR 0 1 BUSY ADC ON/OFF RESET D7 BUSY D6 ADC D5 D4 ON/OFF RESET D3 D2 D1 D0 0 0 0 0 When BUSY = 1, it indicates that either processing is occurring internally or a reset condition is in process. While the chip does not accept commands until BUSY = 0, if the cycle time can be satisfied, there is no need to check for BUSY conditions. This shows the relationship between the column address and the segment driver. 0: Reverse (column address 131-n SEG n) 1: Normal (column address n SEG n) (The ADC command switches the polarity.) ON/OFF: indicates the display ON/OFF state. 0: Display ON 1: Display OFF (This display ON/OFF command switches the polarity.) This indicates that the chip is in the process of initialization either because of a RES signal or because of a reset command. 0: Operating state 1: Reset in progress (6) Display Data Write This command writes 8-bit data to the specified display data RAM address. Since the column address is automatically incremented by "1" after the write, the MPU can write the display data. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 Write data (7) Display Data Read This command reads 8-bit data from the specified display data RAM address. Since the column address is automatically incremented by "1" after the read, the CPU can continuously read multiple-word data. One dummy read is required immediately after the column address has been set. See the 7. Function Description in "Display Data RAM" for the explanation of accessing the internal registers. When the serial interface is used, reading of the display data becomes unavailable. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 1 0 1 Read Data 38 EPSON Rev.2.1 S1D10605 S1D10605 Series (8) ADC Select (Segment Driver Direction Select) This command can reverse the correspondence between the display RAM data column address and the segment driver output. Thus, sequence of the segment driver output pins may be reversed by the command. See the 7. Function Description "column address circuit" for the detail. Increment of the column address (by "1") accompanying the reading or writing the display data is done according to the column address indicated in Figure 4. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 0 0 0 1 Setting Normal Reverse (9) Display Normal/Reverse This command can reverse the lit and unlit display without overwriting the contents of the display data RAM. When this is done the display data RAM contents are maintained. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 1 1 0 1 Setting RAM Data HIGH LCD ON voltage (normal) RAM Data LOW LCD ON voltage (reverse) (10) Display All Points ON/OFF This command makes it possible to force all display points ON regardless of the content of the display data RAM. The contents of the display data RAM are maintained when this is done. This command takes priority over the display normal/reverse command. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 0 1 0 0 1 Setting Normal display mode Display all points ON When the display is in an OFF mode, executing the display all points ON command will place the display in power save mode. For details, see the (20) "Power Save section". (11) LCD Bias Set This command selects the voltage bias ratio required for the liquid crystal display. E R/W Select Status A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 S1D10605 S1D10605* S1D10606 S1D10606* S1D10607 S1D10607* S1D10608 S1D10608* S1D10609 S1D10609* 0 1 0 1 0 1 0 0 0 1 0 1/9 bias 1/8 bias 1/6 bias 1/8 bias 1/8 bias 1 1/7 bias 1/6 bias 1/5 bias 1/6 bias 1/6 bias (12) Read/Modify/Write This command is used paired with the "END" command. Once this command has been input, the display data read command does not change the column address, but only the display data write command increments (+1) the column address. This mode is maintained until the END command is input. When the END command is input, the column address returns to the address it was at when the read/modify/write command was entered. This function makes it possible to reduce the load on the MPU when there are repeating data changes in a specified display region, such as when there is a blanking cursor. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 0 0 * Even in read/modify/write mode, other commands aside from display data read/write commands can also be used. However, the column address set command cannot be used. Rev.2.1 EPSON 39 S1D10605 S1D10605 Series · The sequence for cursor display Page address set Column address set Read/modify/write Dummy read Data read Data process Data write No Change complete? Yes End Figure 18 (13) End This command releases the read/modify/write mode, and returns the column address to the address it was at when the mode was entered. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 1 1 1 0 Return Column address N N+1 N+2 N+3 Read/modify/write mode set ··· N+m N End Figure 19 (14) Reset This command initializes the display start line, the column address, the page address, the common output mode, the V5 voltage regulator internal resistor ratio, the electronic volume, and the static indicator are reset, and the read/modify/ write mode and test mode are released. There is no impact on the display data RAM. See the 7. Function Description in "Reset" for details. The reset operation is performed after the reset command is entered. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 0 The initialization when the power supply is applied must be done through applying a reset signal to the RES terminal. The reset command must not be used instead. 40 EPSON Rev.2.1 S1D10605 S1D10605 Series (15) Common Output Mode Select This command can select the scan direction of the COM output terminal. For details, see the 7. Function Description in "Common Output Mode Select Circuit." E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 Selected Mode S1D10605 S1D10605* S1D10606 S1D10606* S1D10607 S1D10607* S1D10608 S1D10608* S1D10609 S1D10609* 1 1 0 0 0 * * * Normal COM0COM63 COM0COM63 COM0COM47 COM0COM47 COM0COM31 COM0COM31 COM0COM53 COM0COM53 COM0COM51 COM0COM51 1 Reverse COM63COM0 COM63COM0 COM47COM0 COM47COM0 COM31COM0 COM31COM0 COM53COM0 COM53COM0 COM51COM0 COM51COM0 * Disabled bit (16) Power Controller Set This command sets the power supply circuit functions. See the 7. Function Description in "The Power Supply Circuit," for details E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 Selected Mode 0 1 0 0 0 1 0 1 0 Booster circuit: OFF 1 Booster circuit: ON 0 Voltage regulator circuit: OFF 1 Voltage regulator circuit: ON 0 Voltage follower circuit: OFF 1 Voltage follower circuit: ON [Translator's Note: the abbreviations explained within these parentheses for V and V/F have been written out in the English translation and are therefore no longer necessary.] (17) V 5 Voltage Regulator Internal Resistor Ratio Set This command sets the V5 voltage regulator internal resistor ratio. For details, see the 7. Function Description is "The Power Supply Circuits." E R/W A0 RD WR D7 D6 D5 D4 D3 D2 0 1 0 0 0 1 0 0 0 0 0 D1 0 0 1 1 1 1 1 D0 0 1 0 Rb/Ra Ratio Small 0 1 Large (18) The Electronic Volume (Double Byte Command) This command makes it possible to adjust the brightness of the liquid crystal display by controlling the liquid crystal drive voltage V 5 through the output from the voltage regulator circuits of the internal liquid crystal power supply. This command is a two byte command used as a pair with the electronic volume mode set command and the electronic volume register set command, and both commands must be issued one after the other. · The Electronic Volume Mode Set When this command is input, the electronic volume register set command becomes enabled. Once the electronic volume mode has been set, no other command except for the electronic volume register command can be used. Once the electronic volume register set command has been used to set data into the register, then the electronic volume mode is released. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 0 0 0 0 0 1 Rev.2.1 EPSON 41 S1D10605 S1D10605 Series · Electronic Volume Register Set By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the electronic volume register has been set. E R/W A0 RD WR D7 D6 0 1 0 * * 0 1 0 * * 0 1 0 * * 0 0 1 1 0 0 * * * * D5 0 0 0 D4 D3 0 0 0 0 0 0 1 1 1 1 1 1 D2 0 0 0 D1 0 1 1 D0 1 0 1 1 1 1 1 | V5 | Small 0 1 Large * Inactive bit When the electronic volume function is not used, set this to (1, 0, 0, 0, 0, 0) · The Electronic Volume Register Set Sequence Electronic volume mode set Electronic volume register set No Electronic volume mode clear Changes complete? Yes Figure 20 (19) Static Indicator (Double Byte Command) This command controls the static drive system indicator display. The static indicator display is controlled by this command only, and is independent of other display control commands. This is used when one of the static indicator liquid crystal drive electrodes is connected to the FR terminal, and the other is connected to the FRS terminal. A different pattern is recommended for the static indicator electrodes than for the dynamic drive electrodes. If the pattern is too close, it can result in deterioration of the liquid crystal and of the electrodes. The static indicator ON command is a double byte command paired with the static indicator register set command, and thus one must execute one after the other. (The static indicator OFF command is a single byte command.) · Static Indicator ON/OFF When the static indicator ON command is entered, the static indicator register set command is enabled. Once the static indicator ON command has been entered, no other command aside from the static indicator register set command can be used. This mode is cleared when data is set in the register by the static indicator register set command. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 0 1 0 1 1 0 0 1 42 Static Indicator OFF ON EPSON Rev.2.1 S1D10605 S1D10605 Series · Static Indicator Register Set This command sets two bits of data into the static indicator register, and is used to set the static indicator into a blinking mode. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 * * * * * * 0 0 0 1 1 0 1 1 Indicator Display State OFF ON (blinking at approximately one second intervals) ON (blinking at approximately 0.5 second intervals) ON (constantly on) * Disabled bit · Static Indicator Register Set Sequence Static indicator mode set Static indicator register set Static indicator mode clear No Changes complete? Yes Figure 21 (20) Power Save (Compound Command) When the display all points ON is performed while the display is in the OFF mode, the power saver mode is entered, thus greatly reducing power consumption. The power saver mode has two different modes: the sleep mode and the standby mode. When the static indicator is OFF, it is the sleep mode that is entered. When the static indicator is ON, it is the standby mode that is entered. In the sleep mode and in the standby mode, the display data is saved as is the operating mode that was in effect before the power saver mode was initiated, and the MPU is still able to access the display data RAM. Refer to figure 22 for power save off sequence. Static indicator OFF Static indicator ON Power saver (compound command) Sleep mode Standby mode Power save OFF (compound command) Display all points OFF command Static indicator ON (2 bytes command) Power save OFF (Display all points OFF command) Sleep mode cancel Standby mode cancel Figure 22 Rev.2.1 EPSON 43 S1D10605 S1D10605 Series · Sleep Mode This stops all operations in the LCD display system, and as long as there are no accesses from the MPU, the consumption current is reduced to a value near the static current. The internal modes during sleep mode are as follows: 1 The oscillator circuit and the LCD power supply circuit are halted. 2 All liquid crystal drive circuits are halted, and the segment in common drive outputs output a VDD level. · Standby Mode The duty LCD display system operations are halted and only the static drive system for the indicator continues to operate, providing the minimum required consumption current for the static drive. The internal modes are in the following states during standby mode. 1 The LCD power supply circuits are halted. The oscillator circuit continues to operate. 2 The duty drive system liquid crystal drive circuits are halted and the segment and common driver outputs output a VDD level. The static drive system does not operate. When a reset command is performed while in standby mode, the system enters sleep mode. * When an external power supply is used, it is recommended that the functions of the external power supply circuit be stopped when the power saver mode is started. For example, when the various levels of liquid crystal drive voltage are provided by external resistive voltage dividers, it is recommended that a circuit be added in order to cut the electrical current flowing through the resistive voltage divider circuit when the power saver mode is in effect. The S1D10605 S1D10605 series chips have a liquid crystal display blanking control terminal DOF. This terminal enters an LOW state when the power saver mode is launched. Using the output of DOF, it is possible to stop the function of an external power supply circuit. * When the master is turned on, the oscillator circuit is operable immediately after the powering on. (21) NOP Non-OPeration Command E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 0 0 0 1 1 (22) Test This is a command for IC chip testing. Please do not use it. If the test command is used by accident, it can be cleared by applying a LOW signal to the RES input by the reset command or by using an NOP. E R/W A0 RD WR D7 D6 D5 D4 D3 D2 D1 D0 0 1 0 1 1 1 1 * * * * * Inactive bit Note: The S1D10605 S1D10605 Series chips maintain their operating modes until something happens to change them. Consequently, excessive external noise, etc., can change the internal modes of the S1D10605 S1D10605 Series chip. Thus in the packaging and system design it is necessary to suppress the noise or take measure to prevent the noise from influencing the chip. Moreover, it is recommended that the operating modes be refreshed periodically to prevent the effects of unanticipated noise. 44 EPSON Rev.2.1 S1D10605 S1D10605 Series Table 16 Table of S1D10605 S1D10605 Series Commands (1) (2) Display start line set 0 1 0 0 1 (3) Page address set 0 1 0 1 0 1 1 Page address (4) Column address set upper bit 0 1 0 0 0 0 1 Most significant column address 0 1 0 0 0 0 0 (5) (6) (7) Column address set lower bit Status read Display data write Display data read 0 1 1 0 1 0 1 0 1 (8) ADC select 0 1 0 1 0 1 0 0 0 0 0 1 (9) Display normal/ reverse 0 1 0 1 0 1 0 0 1 1 0 1 (10) Display all points ON/OFF 0 1 0 1 0 1 0 0 1 0 0 1 (11) LCD bias set 0 1 0 1 0 1 0 0 0 1 0 1 (12) Read/modify/write 0 1 0 1 1 1 0 0 0 0 0 (13) End (14) Reset (15) Common output mode select 0 0 0 1 1 1 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 * 1 1 * 0 0 * (16) Power control set 0 1 0 0 0 1 0 1 (17) V5 voltage regulator internal resistor ratio set (18) Electronic volume mode set Electronic volume register set 0 1 0 0 0 1 0 0 Operating mode Resistor ratio 0 1 0 1 0 0 0 0 0 0 1 0 * * (19) Static indicator ON/OFF Static indicator register set (20) Power saver 0 1 0 1 0 1 0 1 1 0 1 0 * * * * * * (21) NOP (22) Test 0 0 Rev.2.1 A0 0 RD 1 WR 0 D7 1 Command Code D6 D5 D4 D3 0 1 0 1 Command Display ON/OFF 1 1 0 0 1 1 D1 1 D0 0 1 Display start address Status 1 1 D2 1 Least significant column address 0 0 0 0 Write data Read data 0 0 1 EPSON 0 * 0 * Sets the LCD drive voltage bias ratio S1D10605 S1D10605* . 0: 1/9, 1: 1/7 S1D10606 S1D10606* /S1D10608 /S1D10608* /S1D10609 /S1D10609* . 0: 1/8, 1: 1/6 S1D10607 S1D10607* . 0: 1/6, 1: 1/5 Column address increment At write: +1 At read: 0 Clear read/modify/write Internal reset Select COM output scan direction 0: normal direction, 1: reverse direction Select internal power supply operating mode Select internal resistor ratio (Rb/Ra) mode Set the V5 output voltage electronic volume register 0 0 1 Mode 1 * Sets the display RAM address SEG output correspondence 0: normal, 1: reverse Sets the LCD display normal/ reverse 0: normal, 1: reverse Display all points 0: normal display 1: all points ON 1 Electronic volume value 1 1 Function LCD display ON/OFF 0: OFF, 1: ON Sets the display RAM display start line address Sets the display RAM page address Sets the most significant 4 bits of the display RAM column address. Sets the least significant 4 bits of the display RAM column address. Reads the status data Writes to the display RAM Reads from the display RAM 1 * 0: OFF, 1: ON Set the flashing mode Display OFF and display all points ON compound command Command for non-operation Command for IC test. Do not use this command (Note) *: disabled data 45 S1D10605 S1D10605 Series 9. COMMAND DESCRIPTION Instruction Setup: Reference (reference) (1) Initialization Note: With this IC, when the power is applied, LCD driving non-selective potentials V2 and V3 (SEG pin) and V1 and V4 (COM pin) are output through the LCD driving output pins SEG and COM. When electric charge is remaining in the smoothing capacitor connecting between the LCD driving voltage output pins (V1 to V5) and the VDD pin, the picture on the display may become totally dark instantaneously when the power is turned on. To avoid occurrence of such a failure, we recommend the following flow when turning on the power. 1 When the built-in power is being used immediately after turning on the power: Turn ON the VDD-VSS power keeping the RES pin = LOW. When the power is stabilized Release the reset state. (RES pin = HIGH) Initialized state (Default) *1 Function setup by command input (User setup) (11) LCD bias setting *2 (8) ADC selection *3 (15) Common output state selection *4 Arrange to execute all the procedures from releasing the reset state through setting the power control within 5ms. Function setup by command input (User setup) (17) Setting the built-in resistance radio for regulation of the V5 voltage *5 (18) Electronic volume control *6 Function setup by command input (User setup) (16) Power control setting *7 This concludes the initialization * The target time of 5ms will result to vary depending on the panel characteristics and the capacitance of the smoothing capacitor. Therefore, we suggest you to conduct an operation ch