MF1282-02 S1C60N08 60R08 S1C60N08/S1C60R08 S1C60R08 60N01 S1C60 E0C6001 E0C6002 - Datasheet Archive

 

CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C60N08 / 60R08 Technical Manual S1C60N08 Technical Hardware/S1C60R08 Technical Hardware

 

MF1282-02 MF1282-02 CMOS 4-BIT SINGLE CHIP MICROCOMPUTER S1C60N08 S1C60N08 / 60R08 60R08 Technical Manual S1C60N08 S1C60N08 Technical Hardware/S1C60R08 Technical Hardware NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. © SEIKO EPSON CORPORATION 2001 All rights reserved. S1C60N08/S1C60R08 S1C60N08/S1C60R08 Technical Manual This publication consists of two manuals that explain the hardware specifications of the S1C60N08 S1C60N08 and S1C60R08 S1C60R08 (ROM emulator model for S1C60N08 S1C60N08) CMOS 4-bit single chip microcomputers. I. S1C60N08 S1C60N08 Technical Hardware This manual describes the functions, circuit configuration and control method of the S1C60N08 S1C60N08. II. S1C60R08 S1C60R08 Technical Hardware This manual describes the hardware specifications of the S1C60R08 S1C60R08 except where the functions are the same as the S1C60N08 S1C60N08. The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative. Configuration of product number Devices S1 C 60N01 60N01 F 0A01 00 Packing specification Specification Package (D: die form; F: QFP) Model number Model name (C: microcomputer, digital products) Product classification (S1: semiconductor) Development tools C 60R08 60R08 S5U1 D1 1 00 Packing specification Version (1: Version 1 2) Tool type (D1: Development Tool 1) Corresponding model number (60R08 60R08: for S1C60R08 S1C60R08) Tool classification (C: microcomputer use) Product classification (S5U1: development tool for semiconductor products) 1: For details about tool types, see the tables below. (In some manuals, tool types are represented by one digit.) 2: Actual versions are not written in the manuals. Comparison table between new and previous number S1C60 S1C60 Family processors Previous No. E0C6001 E0C6001 E0C6002 E0C6002 E0C6003 E0C6003 E0C6004 E0C6004 E0C6005 E0C6005 E0C6006 E0C6006 E0C6007 E0C6007 E0C6008 E0C6008 E0C6009 E0C6009 E0C6011 E0C6011 E0C6013 E0C6013 E0C6014 E0C6014 E0C60R08 E0C60R08 New No. S1C60N01 S1C60N01 S1C60N02 S1C60N02 S1C60N03 S1C60N03 S1C60N04 S1C60N04 S1C60N05 S1C60N05 S1C60N06 S1C60N06 S1C60N07 S1C60N07 S1C60N08 S1C60N08 S1C60N09 S1C60N09 S1C60N11 S1C60N11 S1C60N13 S1C60N13 S1C60140 S1C60140 S1C60R08 S1C60R08 S1C62 S1C62 Family processors Previous No. E0C621A E0C621A E0C6215 E0C6215 E0C621C E0C621C E0C6S27 E0C6S27 E0C6S37 E0C6S37 E0C623A E0C623A E0C623E E0C623E E0C6S32 E0C6S32 E0C6233 E0C6233 E0C6235 E0C6235 E0C623B E0C623B E0C6244 E0C6244 E0C624A E0C624A E0C6S46 E0C6S46 New No. S1C621A0 S1C621A0 S1C62150 S1C62150 S1C621C0 S1C621C0 S1C6S2N7 S1C6S3N7 S1C6N3A0 S1C6N3E0 S1C6S3N2 S1C62N33 S1C62N33 S1C62N35 S1C62N35 S1C6N3B0 S1C62440 S1C62440 S1C624A0 S1C624A0 S1C6S460 S1C6S460 Previous No. E0C6247 E0C6247 E0C6248 E0C6248 E0C6S48 E0C6S48 E0C624C E0C624C E0C6251 E0C6251 E0C6256 E0C6256 E0C6292 E0C6292 E0C6262 E0C6262 E0C6266 E0C6266 E0C6274 E0C6274 E0C6281 E0C6281 E0C6282 E0C6282 E0C62M2 E0C62M2 E0C62T3 E0C62T3 New No. S1C62470 S1C62470 S1C62480 S1C62480 S1C6S480 S1C6S480 S1C624C0 S1C624C0 S1C62N51 S1C62N51 S1C62560 S1C62560 S1C62920 S1C62920 S1C62N62 S1C62N62 S1C62660 S1C62660 S1C62740 S1C62740 S1C62N81 S1C62N81 S1C62N82 S1C62N82 S1C62M20 S1C62M20 S1C62T30 S1C62T30 Comparison table between new and previous number of development tools Development tools for the S1C60/62 S1C60/62 Family Previous No. ASM62 ASM62 DEV6001 DEV6001 DEV6002 DEV6002 DEV6003 DEV6003 DEV6004 DEV6004 DEV6005 DEV6005 DEV6006 DEV6006 DEV6007 DEV6007 DEV6008 DEV6008 DEV6009 DEV6009 DEV6011 DEV6011 DEV60R08 DEV60R08 DEV621A DEV621A DEV621C DEV621C DEV623B DEV623B DEV6244 DEV6244 DEV624A DEV624A DEV624C DEV624C DEV6248 DEV6248 DEV6247 DEV6247 New No. S5U1C62000A S5U1C62000A S5U1C60N01D S5U1C60N01D S5U1C60N02D S5U1C60N02D S5U1C60N03D S5U1C60N03D S5U1C60N04D S5U1C60N04D S5U1C60N05D S5U1C60N05D S5U1C60N06D S5U1C60N06D S5U1C60N07D S5U1C60N07D S5U1C60N08D S5U1C60N08D S5U1C60N09D S5U1C60N09D S5U1C60N11D S5U1C60N11D S5U1C60R08D S5U1C60R08D S5U1C621A0D S5U1C621A0D S5U1C621C0D S5U1C621C0D S5U1C623B0D S5U1C623B0D S5U1C62440D S5U1C62440D S5U1C624A0D S5U1C624A0D S5U1C624C0D S5U1C624C0D S5U1C62480D S5U1C62480D S5U1C62470D S5U1C62470D Previous No. DEV6262 DEV6262 DEV6266 DEV6266 DEV6274 DEV6274 DEV6292 DEV6292 DEV62M2 DEV62M2 DEV6233 DEV6233 DEV6235 DEV6235 DEV6251 DEV6251 DEV6256 DEV6256 DEV6281 DEV6281 DEV6282 DEV6282 DEV6S27 DEV6S27 DEV6S32 DEV6S32 DEV6S37 DEV6S37 EVA6008 EVA6008 EVA6011 EVA6011 EVA621AR EVA621AR EVA621C EVA621C EVA6237 EVA6237 EVA623A EVA623A New No. S5U1C62620D S5U1C62620D S5U1C62660D S5U1C62660D S5U1C62740D S5U1C62740D S5U1C62920D S5U1C62920D S5U1C62M20D S5U1C62M20D S5U1C62N33D S5U1C62N33D S5U1C62N35D S5U1C62N35D S5U1C62N51D S5U1C62N51D S5U1C62560D S5U1C62560D S5U1C62N81D S5U1C62N81D S5U1C62N82D S5U1C62N82D S5U1C6S2N7D S5U1C6S3N2D S5U1C6S3N7D S5U1C60N08E S5U1C60N08E S5U1C60N11E S5U1C60N11E S5U1C621A0E2 S5U1C621A0E2 S5U1C621C0E S5U1C621C0E S5U1C62N37E S5U1C62N37E S5U1C623A0E S5U1C623A0E Previous No. EVA623B EVA623B EVA623E EVA623E EVA6247 EVA6247 EVA6248 EVA6248 EVA6251R EVA6251R EVA6256 EVA6256 EVA6262 EVA6262 EVA6266 EVA6266 EVA6274 EVA6274 EVA6281 EVA6281 EVA6282 EVA6282 EVA62M1 EVA62M1 EVA62T3 EVA62T3 EVA6S27 EVA6S27 EVA6S32R EVA6S32R ICE62R ICE62R KIT6003 KIT6003 KIT6004 KIT6004 KIT6007 KIT6007 New No. S5U1C623B0E S5U1C623B0E S5U1C623E0E S5U1C623E0E S5U1C62470E S5U1C62470E S5U1C62480E S5U1C62480E S5U1C62N51E1 S5U1C62N51E1 S5U1C62N56E S5U1C62N56E S5U1C62620E S5U1C62620E S5U1C62660E S5U1C62660E S5U1C62740E S5U1C62740E S5U1C62N81E S5U1C62N81E S5U1C62N82E S5U1C62N82E S5U1C62M10E S5U1C62M10E S5U1C62T30E S5U1C62T30E S5U1C6S2N7E S5U1C6S3N2E2 S5U1C62000H S5U1C62000H S5U1C60N03K S5U1C60N03K S5U1C60N04K S5U1C60N04K S5U1C60N07K S5U1C60N07K I. S1C60N08 S1C60N08 Technical Hardware CONTENTS CONTENTS CHAPTER 1 OVERVIEW _ I-1 1.1 1.2 1.3 1.4 1.5 1.6 CHAPTER Configuration . Features . Block Diagram . Pin Layout Diagram . Pin Description . S1C60N08 S1C60N08 Option List . I-1 I-1 I-2 I-3 I-4 I-4 2 POWER SUPPLY AND INITIAL RESET _ I-7 2.1 2.2 Power Supply . I-7 Initial Reset . I-9 2.2.1 Power-on reset circuit . I-9 2.2.2 RESET terminal . I-9 2.2.3 Simultaneous high input to input ports (K00­K03) . I-9 2.2.4 Watchdog timer . I-10 2.2.5 Internal register at initial reset . I-10 2.3 CHAPTER 3 CPU, ROM, RAM _ I-11 3.1 3.2 3.3 CHAPTER Test Terminal (TEST) . I-10 CPU . I-11 ROM . I-11 RAM . I-11 4 PERIPHERAL CIRCUITS AND OPERATION _ I-12 4.1 4.2 Memory Map . I-12 Resetting Watchdog Timer . I-16 4.2.1 Configuration of watchdog timer . I-16 4.2.2 Mask option . I-16 4.2.3 Control of watchdog timer . I-16 4.2.4 Programming note . I-16 4.3 Oscillation Circuit and Prescaler . I-17 4.3.1 Configuration of oscillation circuit and prescaler . I-17 4.3.2 OSC1 oscillation circuit . I-17 4.3.3 OSC3 oscillation circuit . I-18 4.3.4 Control of oscillation circuit and prescaler . I-19 4.3.5 Programming notes . I-20 4.4 Input Ports (K00­K03, K10, K20­K23) . I-21 4.4.1 Configuration of input ports . I-21 4.4.2 Input comparison registers and interrupt function . I-21 4.4.3 Mask option . I-24 4.4.4 Control of input ports . I-24 4.4.5 Programming notes . I-26 4.5 Output Ports (R00­R03, R10­R13) . I-27 4.5.1 Configuration of output ports . I-27 4.5.2 Mask option . I-27 4.5.3 Control of output ports . I-29 4.5.4 Programming note . I-30 S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-i CONTENTS 4.6 I/O Ports (P00­P03, P10­P13) . I-31 4.6.1 Configuration of I/O ports . I-31 4.6.2 I/O control register and I/O mode . I-31 4.6.3 Mask option . I-31 4.6.4 Control of I/O ports . I-32 4.6.5 Programming notes . I-33 4.7 Serial Interface (SIN, SOUT, SCLK) . I-34 4.7.1 Configuration of serial interface . I-34 4.7.2 Master mode and slave mode of serial interface . I-34 4.7.3 Data input/output and interrupt function . I-35 4.7.4 Mask option . I-37 4.7.5 Control of serial interface . I-38 4.7.6 Programming notes . I-40 4.8 LCD Driver (COM0­COM3, SEG0­SEG47 SEG47) . I-41 4.8.1 Configuration of LCD driver . I-41 4.8.2 Cadence adjustment of oscillation frequency . I-46 4.8.3 Mask option (segment allocation) . I-47 4.8.4 Control of LCD driver . I-48 4.8.5 Programming notes . I-49 4.9 Clock Timer . I-50 4.9.1 Configuration of clock timer . I-50 4.9.2 Interrupt function . I-50 4.9.3 Control of clock timer . I-51 4.9.4 Programming notes . I-52 4.10 Stopwatch Timer . I-53 4.10.1 Configuration of stopwatch timer . I-53 4.10.2 Count-up pattern . I-53 4.10.3 Interrupt function . I-54 4.10.4 Control of stopwatch timer . I-55 4.10.5 Programming notes . I-56 4.11 Sound Generator . I-57 4.11.1 Configuration of sound generator . I-57 4.11.2 Frequency setting . I-58 4.11.3 Digital envelope . I-58 4.11.4 Mask option . I-59 4.11.5 Control of sound generator . I-60 4.11.6 Programming note . I-61 4.12 Event Counter . I-62 4.12.1 Configuration of event counter . I-62 4.12.2 Switching count mode . I-62 4.12.3 Mask option . I-63 4.12.4 Control of event counter . I-64 4.12.5 Programming notes . I-65 4.13 Analog Comparator . I-66 4.13.1 Configuration of analog comparator . I-66 4.13.2 Operation of analog comparator . I-66 4.13.3 Control of analog comparator . I-67 4.13.4 Programming notes . I-67 4.14 Battery Life Detection (BLD) Circuit . I-68 4.14.1 Configuration of BLD circuit . I-68 4.14.2 Programmable selection of evaluation voltage . I-68 4.14.3 Detection timing of BLD circuit . I-69 4.14.4 Control of BLD circuit . I-70 4.14.5 Programming notes . I-71 I-ii EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CONTENTS 4.15 Heavy Load Protection Function and Sub-BLD Circuit . I-72 4.15.1 Heavy load protection function . I-72 4.15.2 Operation of sub-BLD circuit . I-73 4.15.3 Control of heavy load protection function and sub-BLD circuit . I-74 4.15.4 Programming notes . I-76 4.16 Interrupt and HALT . I-77 4.16.1 Interrupt factors . I-79 4.16.2 Specific masks and factor flags for interrupt . I-79 4.16.3 Interrupt vectors . I-80 4.16.4 Control of interrupt and HALT . I-81 4.16.5 Programming notes . I-82 CHAPTER 5 SUMMARY OF NOTES _ I-83 5.1 5.2 5.3 Notes for Low Current Consumption . I-83 Summary of Notes by Function . I-84 Precautions on Mounting . I-89 CHAPTER 6 BASIC EXTERNAL WIRING DIAGRAM _ I-91 CHAPTER 7 ELECTRICAL CHARACTERISTICS _ I-93 7.1 7.2 7.3 7.4 7.5 CHAPTER I-93 I-93 I-94 I-95 I-98 8 PACKAGE _ I-99 8.1 8.2 CHAPTER Absolute Maximum Rating . Recommended Operating Conditions . DC Characteristics . Analog Circuit Characteristics and Current Consumption . Oscillation Characteristics . Plastic Package . I-99 Ceramic Package for Test Samples . I-100 I-100 9 PAD LAYOUT _ I-101 I-101 9.1 9.2 Diagram of Pad Layout . I-101 I-101 Pad Coordinates . I-102 I-102 S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-iii CHAPTER 1: OVERVIEW CHAPTER 1 OVERVIEW The S1C60N08 S1C60N08 Series is a single-chip microcomputer made up of the 4-bit core CPU S1C6200C S1C6200C, ROM (4,096 words × 12 bits), RAM (832 words × 4 bits), LCD driver, serial interface, event counter with dial input function, watchdog timer, and two types of time base counter. Because of its low-voltage operation and low power consumption, this series is ideal for a wide range of applications, and is especially suitable for battery-driven systems. 1.1 Configuration The S1C60N08 S1C60N08 Series is configured as follows, depending on supply voltage and oscillation circuits. Table 1.1.1 Model configuration Model Supply voltage Oscillation circuit Evaluation tool S1C60N08 S1C60N08 S1C60A08 S1C60A08 3.0 V 3.0 V OSC1 only OSC1 and OSC3 (Single clock) (Twin clock) S1C60R08 S1C60R08 S1C60L08 S1C60L08 1.5 V OSC1 only (Single clock) ­ 1.2 Features Table 1.2.1 Features Model OSC1 oscillation circuit OSC3 oscillation circuit Instruction set Instruction execution time (differs depending on instruction) (CLK: CPU operation frequency) ROM capacity RAM capacity Input ports Output ports I/O ports Serial interface LCD driver Time base counter Watchdog timer Event counter Sound generator Analog comparator Battery low detection circuit (BLD) External interrupt Internal interrupt Supply voltage Current CLK= 32.768 kHz consumption (when halted) (Typ. value) CLK= 32.768 kHz (when executed) CLK= 500 kHz (when executed) Form when shipped S1C60N08 S1C60N08 TECHNICAL HARDWARE S1C60N08/S1C60R08 S1C60N08/S1C60R08 S1C60L08 S1C60L08 S1C60A08/S1C60R08 S1C60A08/S1C60R08 Crystal oscillation circuit 32.768 kHz (Typ.)/38.400 kHz (Typ.) ­ CR or ceramic oscillation circuit (selected by mask option) 500 kHz (Typ.) 108 types 153 µsec, 214 µsec, 366 µsec (CLK = 32.768 kHz) 130 µsec, 182 µsec, 313 µsec (CLK = 38.400 kHz) ­ 10 µsec, 14 µsec, 24 µsec (CLK = 500 kHz) 4,096 words × 12 bits 832 words × 4 bits 9 bits (pull-down resistor can be added by mask option) 8 bits (BZ, BZ, FOUT and SIOF outputs are available by mask option) 8 bits (pull-down resistor is added during input data read-out) 1 port (8-bit clock synchronous system) 48 segments × 4, 3, or 2 commons (selected by mask option) V-3 V 1/4, 1/3 or 1/2 duty (voltage regulator and booster circuits built-in) Two types (timer and stopwatch) Built-in (can be disabled by mask option) Two 8-bit inputs (dial input evaluation or independent) Programmable in 8 sounds (8 frequencies) Digital envelope built-in (can be disabled by mask option) Inverted input × 1, non-inverted input × 1 Dual system (programmable in 8 values and a fixed value) 2.4 V, 2.2­2.55 V 1.2 V, 1.05­1.4 V 2.4 V, 2.2­2.55 V Input interrupt: 3 systems Time base counter interrupt: 2 systems Serial interface interrupt: 1 system 3.0 V (1.8­3.5 V) 1.5 V (0.9­1.7 V) 3.0 V (2.2­3.5 V) 1.0 µA 1.0 µA 1.1 µA 2.2 µA 2.2 µA 3.0 µA ­ ­ 50 µA QFP5-100pin, QFP15-100pin or chip EPSON I-1 CHAPTER 1: OVERVIEW 1.3 Block Diagram ROM System Reset Control 4,096 words × 12 bits RESET Core CPU S1C6200C S1C6200C OSC1 OSC2 OSC3 OSC4 OSC Interrupt Generator RAM Input Port 832 words × 4 bits COM0­3 SEG0­47 VDD VL1 VL2 VL3 CA CB VS1 VSS I/O Port P00­P03 P10­P13 Output Port LCD Driver 48 SEG × 4 COM R00­R03 R10­R13 Power Controller Sound Generator SVD Serial I/F Event Counter AMPP AMPM K00­K03, K10 K20­K23 TEST Timer Comparator SIN SOUT SCLK Stopwatch Fig. 1.3.1 Block diagram I-2 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 1: OVERVIEW 1.4 Pin Layout Diagram QFP5-100pin 80 81 50 INDEX 31 100 1 30 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin name COM1 COM0 SEG47 SEG47 SEG46 SEG46 SEG45 SEG45 SEG44 SEG44 SEG43 SEG43 SEG42 SEG42 SEG41 SEG41 SEG40 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37 SEG36 SEG36 SEG35 SEG35 SEG34 SEG34 SEG33 SEG33 SEG32 SEG32 SEG31 SEG31 SEG30 SEG30 SEG29 SEG29 SEG28 SEG28 SEG27 SEG27 SEG26 SEG26 SEG25 SEG25 No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin name SEG24 SEG24 TEST SEG23 SEG23 SEG22 SEG22 SEG21 SEG21 SEG20 SEG20 SEG19 SEG19 SEG18 SEG18 SEG17 SEG17 SEG16 SEG16 SEG15 SEG15 SEG14 SEG14 SEG13 SEG13 SEG12 SEG12 SEG11 SEG11 SEG10 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin name No. Pin name SEG0 76 P10 AMPP 77 R03 AMPM 78 R02 K23 79 R01 K22 80 R00 K21 81 R12 K20 82 R11 K10 83 R10 K03 84 R13 K02 85 VSS K01 86 RESET K00 87 OSC4 SIN 88 OSC3 SOUT 89 VS1 N.C. 90 OSC2 SCLK 91 OSC1 P03 92 VDD P02 93 VL3 P01 94 VL2 P00 95 VL1 N.C. 96 CA N.C. 97 CB P13 98 N.C. P12 99 COM3 P11 100 COM2 N.C. = No connection No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 51 Pin name SEG47 SEG47 SEG46 SEG46 SEG45 SEG45 SEG44 SEG44 SEG43 SEG43 SEG42 SEG42 SEG41 SEG41 SEG40 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37 SEG36 SEG36 SEG35 SEG35 SEG34 SEG34 SEG33 SEG33 SEG32 SEG32 SEG31 SEG31 SEG30 SEG30 SEG29 SEG29 SEG28 SEG28 SEG27 SEG27 SEG26 SEG26 SEG25 SEG25 SEG24 SEG24 TEST No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin name SEG23 SEG23 SEG22 SEG22 SEG21 SEG21 SEG20 SEG20 SEG19 SEG19 SEG18 SEG18 SEG17 SEG17 SEG16 SEG16 SEG15 SEG15 SEG14 SEG14 SEG13 SEG13 SEG12 SEG12 N.C. SEG11 SEG11 SEG10 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin name No. Pin name AMPP 76 R02 AMPM 77 R01 K23 78 R00 K22 79 R12 K21 80 R11 K20 81 R10 K10 82 R13 K03 83 VSS K02 84 RESET K01 85 OSC4 K00 86 OSC3 SIN 87 VS1 SOUT 88 OSC2 N.C. 89 OSC1 SCLK 90 VDD N.C. 91 VL3 P03 92 VL2 P02 93 VL1 P01 94 CA P00 95 CB P13 96 N.C. P12 97 COM3 P11 98 COM2 P10 99 COM1 R03 100 COM0 N.C. = No connection QFP15-100pin 75 51 50 76 INDEX 26 100 1 25 Fig. 1.4.1 Pin layout S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-3 CHAPTER 1: OVERVIEW 1.5 Pin Description Table 1.5.1 Pin description Pin No. Pin name QFP5-100 QFP5-100 QFP15-100 QFP15-100 92 90 VDD VSS VS1 VL1 VL2 VL3 CA, CB OSC1 OSC2 OSC3 OSC4 K00­K03 K10 K20­K23 P00­P03 P10­P13 R00­R03 R10 R13 R11 R12 SIN SOUT SCLK AMPP AMPM SEG0­47 COM0­3 RESET TEST 85 89 95 94 93 96, 97 91 90 88 87 62­59 58 57­54 70­67 76­73 80­77 83 84 82 81 63 64 66 52 53 51­28, 26­3 I/O Function 83 (I) (I) Power supply pin (+) Power supply pin (-) 87 93 92 ­ ­ ­ Oscillation and internal logic system voltage output pin LCD drive voltage output pin (approx. -1.05 V or 1/2·VL2) LCD drive voltage output pin (2·VL1 or approx. -2.10 V) 91 94, 95 ­ ­ LCD drive voltage output pin (3·VL1 or 3/2·VL2) 89 88 86 I O Crystal oscillation input pin Crystal oscillation output pin I CR or ceramic oscillation input pin * (N.C. for S1C60N08 S1C60N08 and S1C60L08 S1C60L08) 85 O I I I I/O I/O O O O O O I O I/O I I O CR or ceramic oscillation output pin * (N.C. for S1C60N08 S1C60N08 and S1C60L08 S1C60L08) Input port pin Input port pin Input port pin I/O port pin I/O port pin Output port pin Output port pin or BZ output pin * 61­58 57 56­53 70­67 74­71 78­75 81 82 80 79 62 63 65 51 52 50­39, 37­26, 24­1 2, 1, 100, 99 100­97 86 84 27 25 O I I Boost capacitor connecting pin Output port pin or BZ output pin * Output port pin or SIOF output pin * Output port pin or FOUT output pin * Serial interface data input pin Serial interface data output pin Serial interface clock input/output pin Analog comparator non-inverted input pin Analog comparator inverted input pin LCD segment output pin or DC output pin * LCD common output pin (1/2, 1/3 or 1/4 duty are selectable *) Initial reset input pin Input pin for test Can be selected by mask option 1.6 S1C60N08 S1C60N08 Option List Multiple specifications are available in each option item as indicated in the Option List. Select the specifications that meet the target system. Be sure to record the specifications for unused ports too, according to the instructions provided. 1. DEVICE TYPE · DEVICE TYPE . s s s · CLOCK TYPE (for Evaluation board) . s 1. S1C60N08 S1C60N08 (Normal Type) 2. S1C60L08 S1C60L08 (Low Power Type) 3. S1C60A08 S1C60A08 (Twin Clock Type) 1. 32 kHz s 2. 38 kHz 2. OSC3 SYSTEM CLOCK (only for S1C60A08 S1C60A08) s 1. CR I-4 EPSON s 2. Ceramic S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 1: OVERVIEW 3. MULTIPLE KEY ENTRY RESET · COMBINATION . s s s s · TIME AUTHORIZE . s 1. Not Use 2. Use K00, K01 3. Use K00, K01, K02 4. Use K00, K01, K02, K03 1. Use s 2. Not Use 4. WATCHDOG TIMER s 1. Use s 2. Not Use 5. INPUT INTERRUPT NOISE REJECTOR · K00­K03 . s 1. Use · K10 . s 1. Use · K20­K23 . s 1. Use s 2. Not Use s 2. Not Use s 2. Not Use 6. INPUT PORT PULL DOWN RESISTOR · K00 · K01 · K02 · K03 · K10 · K20 · K21 · K22 · K23 . . . . . . . . . s s s s s s s s s 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor 1. With Resistor s s s s s s s s s 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct 2. Gate Direct s s s s 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 7. OUTPUT PORT SPECIFICATION (R00­R03) · R00 . · R01 . · R02 . · R03 . s s s s 1. Complementary 1. Complementary 1. Complementary 1. Complementary 8. R10 SPECIFICATION · OUTPUT SPECIFICATION . s 1. Complementary · OUTPUT TYPE . s 1. DC Output s 2. Pch-OpenDrain s 2. Buzzer Output 9. R11 SPECIFICATION · OUTPUT SPECIFICATION . s 1. Complementary · OUTPUT TYPE . s 1. DC Output s 2. Pch-OpenDrain s 2. SIO Flag 10.R12 SPECIFICATION · OUTPUT SPECIFICATION . s 1. Complementary s 2. Pch-OpenDrain · OUTPUT TYPE . s 1. DC Output s 2. FOUT 32768 or 38400 [Hz] s 3. FOUT 16384 or 19200 [Hz] s 4. FOUT 8192 or 9600 [Hz] s 5. FOUT 4096 or 4800 [Hz] s 6. FOUT 2048 or 2400 [Hz] s 7. FOUT 1024 or 1200 [Hz] s 8. FOUT 512 or 600 [Hz] s 9. FOUT 256 or 300 [Hz] S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-5 CHAPTER 1: OVERVIEW 11.R13 SPECIFICATION · OUTPUT SPECIFICATION . s 1. Complementary s 2. Pch-OpenDrain · OUTPUT TYPE . s 1. DC Output s 2. Buzzer Inverted Output (R13 Control) s 3. Buzzer Inverted Output (R10 Control) 12. I/O PORT SPECIFICATION · P00 . · P01 . · P02 . · P03 . · P10 . · P11 . · P12 . · P13 . s s s s s s s s 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary 1. Complementary s s s s s s s s 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 2. Pch-OpenDrain 13. SIN PULL DOWN RESISTOR s 1. With Resistor s 2. Gate Direct s 1. Complementary s 2. Pch-OpenDrain · PULL DOWN RESISTOR . s 1. With Resistor · OUTPUT SPECIFICATION . s 1. Complementary · LOGIC . s 1. Positive s 2. Gate Direct s 2. Pch-OpenDrain s 2. Negative 14. SOUT SPECIFICATION 15. SCLK SPECIFICATION 16. SIO DATA PERMUTATION s 1. MSB First s 2. LSB First 17. EVENT COUNTER NOISE REJECTOR s 1. 2048 or 2400 [Hz] s 2. 256 or 300 [Hz] 18. LCD SPECIFICATION · BIAS SELECTION S1C60N08 S1C60N08 . s s s s S1C60L08 S1C60L08 . s s s S1C60A08 S1C60A08 . s s s s 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/3 Bias, Regulator Not Used, LCD 3 V 3. 1/2 Bias, Regulator Not Used, LCD 3 V 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/2 Bias, Regulator Not Used, LCD 3 V 3. 1/3 Bias, Regulator Not Used, LCD 4.5 V 1. 1/3 Bias, Regulator Used, LCD 3 V 2. 1/3 Bias, Regulator Not Used, LCD 3 V 3. 1/2 Bias, Regulator Not Used, LCD 3 V 4. 1/3 Bias, Regulator Not Used, LCD 4.5 V · DUTY SELECTION . s 1. 1/4 Duty s 2. 1/3 Duty s 3. 1/2 Duty 19. SEGMENT MEMORY ADDRESS s 1. 0 Page (040­06F) s 2. 2 Page (240­26F) I-6 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 2: POWER SUPPLY AND INITIAL RESET CHAPTER 2 POWER SUPPLY AND INITIAL RESET 2.1 Power Supply With a single external power supply (1) supplied to VDD through VSS, the S1C60N08 S1C60N08 Series generates the necessary internal voltage with the regulated voltage circuit ( for oscillators, for LCD) and the voltage booster/reducer circuit ( for LCD). 1 Supply voltage: S1C60N08/60A08 S1C60N08/60A08 . 3 V, S1C60L08 S1C60L08 . 1.5 V Figure 2.1.1 shows the power supply configuration of the S1C60N08 S1C60N08. Figure 2.1.2 shows the power supply configuration of the S1C60A08 S1C60A08 and S1C60L08 S1C60L08. The voltage for the internal circuit that is generated by the internal system voltage regulator. The S1C60N08 S1C60N08 generates with the LCD system voltage regulator and with the voltage booster/reducer. The S1C60A08 S1C60A08 and the S1C60L08 S1C60L08 generate with the voltage regulator and with the voltage booster/reducer. Notes: · External loads cannot be driven by the output voltage of the voltage regulator and voltage booster/reducer. · See Chapter 7, "Electrical Characteristics", for voltage values. Internal circuit VDD C5 VS1 Internal system voltage regurator VS1 C3 VL2 LCD system voltage regurator VL2 C2 C4 VL1 VL3 CA CB Oscillation circuit OSC1, 2 LCD driver COM0­3 SEG0­47 VL2 External power supply C1 VL1 LCD system voltage booster/reducer VL3 VSS Fig. 2.1.1 Power supply configuration of S1C60N08 S1C60N08 Internal circuit VDD C5 VS1 Internal system voltage regurator VS1 C3 VL1 LCD system voltage regurator C2 VL2 C4 VL3 OSC1, 2 OSC3, 4 (S1C60A08 S1C60A08) VL1 Oscillation circuit VL1 External power supply CA C1 VL2 LCD system voltage booster/reducer VL3 LCD driver COM0­3 SEG0­47 CB VSS Fig. 2.1.2 Power supply configuration of S1C60A08 S1C60A08 and S1C60L08 S1C60L08 S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-7 CHAPTER 2: POWER SUPPLY AND INITIAL RESET The LCD system voltage regulator can be disabled by mask option. In this case, external elements can be minimized because the external capacitors for the LCD system voltage regulator are not necessary. However when the LCD system voltage regulator is not used, the display quality of the LCD panel, when the supply voltage fluctuates (drops), is inferior to when the LCD system voltage regulator is used. Figure 2.1.3 shows the external element configuration when the LCD system voltage regulator is not used. 4.5 V LCD panel 1/4, 1/3 or 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA CB VSS C5 C2 C4 C1 3.0 V Note: VL2 is shorded to VSS inside the IC 3 V LCD panel 1/4, 1/3 or 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA CB VSS 3 V LCD panel 1/4, 1/3 or 1/2 duty, 1/2 bias VDD VS1 VL1 VL2 VL3 CA CB VSS C5 C2 C3 C1 3.0 V C5 C2 C1 3.0 V Note: VL3 is shorded to VSS inside the IC 4.5 V LCD panel 1/4, 1/3 or 1/2 duty, 1/3 bias VDD VS1 VL1 VL2 VL3 CA CB VSS 3 V LCD panel 1/4, 1/3 or 1/2 duty, 1/2 bias VDD VS1 VL1 VL2 VL3 CA CB VSS C5 C3 C4 C1 1.5 V C5 C4 C1 1.5 V Note: VL1 is shorded to VSS inside the IC Fig. 2.1.3 External elements when LCD system voltage regulator is not used Note: If there is any segment pad that is set to be DC type, the internal LCD voltage regulator cannot be chosen in all models. Or, if the internal LCD voltage regulator is chosen in any model, the segment pad cannot be set to be DC type. Table 2.1.1 LCD voltage regulator and DC output from SEG terminals LCD system voltage regulator DC output from SEG terminals Use Not available Not use Available I-8 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 2: POWER SUPPLY AND INITIAL RESET 2.2 Initial Reset To initialize the S1C60N08 S1C60N08 Series circuits, initial reset must be executed. There are four ways of doing this. (1) Initial reset by the power on reset circuit (2) External initial reset by the RESET terminal (3) External initial reset by simultaneous high input to terminals K00­K03 (4) Initial reset by the watchdog timer Figure 2.2.1 shows the configuration of the initial reset circuit. OSC1 OSC1 oscillation circuit OSC2 Watchdog timer Power-on reset circuit K00 VSS K01 Time authorize circuit K02 Noise rejector Initial reset K03 RESET VSS Mask option Fig. 2.2.1 Configuration of initial reset circuit 2.2.1 Power-on reset circuit The power-on reset circuit outputs the initial reset signal at power-on until the oscillation circuit starts oscillating. Note: The power-on reset circuit may not work properly due to unstable or lower voltage input. The following two initial reset method are recommended to generate the initial reset signal. 2.2.2 RESET terminal Initial reset can be executed externally by setting the reset terminal to the high level. This high level must be maintained for at least 5 msec (when oscillating frequency is fOSC1 = 32 kHz), because the initial reset circuit contains a noise rejector. When the reset terminal goes low the CPU begins to operate. 2.2.3 Simultaneous high input to input ports (K00­K03) Another way of executing initial reset externally is to input a high signal simultaneously to the input ports (K00­K03) selected with the mask option. The specified input port terminals must be kept high for at least 5 msec (when oscillating frequency is fOSC1 = 32 kHz), because the initial reset circuit contains a noise rejector. Table 2.2.3.1 shows the combinations of input ports (K00­K03) that can be selected with the mask option. Table 2.2.3.1 Input port combination Selection Combination A Not used B C D K00K01 K00K01 K00K01K02 K00K01K02 K00K01K02K03 K00K01K02K03 When, for instance, mask option D (K00*K01*K02*K03) is selected, initial reset is executed when the signals input to the four ports K00­K03 are all high at the same time. S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-9 CHAPTER 2: POWER SUPPLY AND INITIAL RESET Further, the time authorize circuit can be selected with the mask option. The time authorize circuit performs initial reset, when the input time of the simultaneous high input is authorized and found to be the same or more than the defined time (1 to 2 sec). If you use this function, make sure that the specified ports do not go high at the same time during ordinary operation. 2.2.4 Watchdog timer If the CPU runs away for some reason, the watchdog timer will detect this situation and output an initial reset signal. See Section 4.2, "Resetting Watchdog Timer", for details. 2.2.5 Internal register at initial reset Initial reset initializes the CPU as shown in the table below. Table 2.2.5.1 Initial values CPU Core Name Symbol Bit size Program counter step PCS 8 Program counter page PCP 4 New page pointer NPP 4 Stack pointer SP 8 Index register X X 10 Index register Y Y 10 Register pointer RP 4 General-purpose register A A 4 General-purpose register B B 4 Interrupt flag I 1 Decimal flag D 1 Zero flag Z 1 Carry flag C 1 Initial value 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Peripheral Circuits Bit size Initial value RAM 4 Undefined Display memory 4 Undefined Other peripheral circuits 4 See Section 4.1, "Memory Map". Name 2.3 Test Terminal (TEST) This terminal is used when the IC load is being detected. During ordinary operation be certain to connect this terminal to VSS. I-10 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 3: CPU, ROM, RAM CHAPTER 3 CPU, ROM, RAM 3.1 CPU The S1C60N08 S1C60N08 Series employs the core CPU S1C6200C S1C6200C for the CPU, so that register configuration, instructions and so forth are virtually identical to those in other family processors using the S1C6200/ S1C6200/ 6200A/6200B/6200C. Refer to the "S1C6200/6200A S1C6200/6200A Core CPU Manual" for details about the core CPU. Note the following points with regard to the S1C60N08 S1C60N08 Series: (1) The SLEEP operation is not assumed, so the SLP instruction cannot be used. (2) Because the ROM capacity is 4,096 words, bank bits are unnecessary and PCB and NBP are not used. (3) RAM is set up to four pages, so only the two low-order bits are valid for the page portion (XP, YP) of the index register that specifies addresses. (The two high-order bits are ignored.) 3.2 ROM The built-in ROM, a mask ROM for loading the program, has a capacity of 4,096 steps, 12 bits each. The program area is 16 pages (0­15), each of 256 steps (00H­FFH). After initial reset, the program start address is page 1, step 00H. The interrupt vector is allocated to page 1, steps 01H­0FH. Bank 0 Step 00H Page 0 Step 01H Program start address Page 1 Interrupt vector area Page 2 Page 3 Step 0FH Step 10H Program area Page 15 Step FFH 12 bits Fig. 3.2.1 ROM configuration 3.3 RAM The RAM, a data memory for storing a variety of data, has a capacity of 832 words, 4-bit words. When programming, keep the following points in mind: (1) Part of the data memory is used as stack area when saving subroutine return addresses and registers, so be careful not to overlap the data area and stack area. (2) Subroutine calls and interrupts take up three words on the stack. (3) Data memory 000H­00FH is the memory area pointed by the register pointer (RP). S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-11 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION Peripheral circuits (timer, I/O, and so on) of the S1C60N08 S1C60N08 Series are memory mapped. Thus, all the peripheral circuits can be controlled by using memory operations to access the I/O memory. The following sections describe how the peripheral circuits operate. 4.1 Memory Map The data memory of the S1C60N08 S1C60N08 Series has an address space of 865 words (913 words when display memory is laid out in Page 2), of which 48 words are allocated to display memory and 33 words, to I/O memory. Figure 4.1.1 shows the overall memory map for the S1C60N08 S1C60N08 Series, and Tables 4.1.1(a)­(c), the memory maps for the peripheral circuits (I/O space). Address Low 0 1 2 3 4 5 6 7 8 9 A B C D E F Page High 0 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 1 2 3 4 5 6 7 RAM (256 words × 4 bits) 0 8 R/W 9 A B C D E F 0 1 2 3 4 5 6 7 RAM (256 words × 4 bits) 1 8 R/W 9 A B C D E F Address Low 0 Page High 0 1 2 3 4 5 6 2 7 8 9 A B C D E F 0 1 2 3 4 5 6 3 7 8 9 A B C D E F 1 2 3 4 5 6 7 8 9 A B C D E F RAM (64 words × 4 bits) R/W Unused area I/O mamory (see Table 4.1.1) RAM (256 words × 4 bits) R/W Fig. 4.1.1 Memory map Address Low 0 Page High 4 5 0 or 2 6 1 2 3 4 5 6 7 8 9 A B C D E F Display memory (48 words × 4 bits) Page 0: R/W, Page 2: W only Fig. 4.1.2 Display memory map Notes: · The display memory area can be selected from between Page 0 (040H­06FH) and Page 2 (240H­26FH) by mask option. When Page 0 (040H­06FH) is selected, the display memory is assigned in the RAM area. So read/write operation is allowed. When Page 2 (240H­26FH) is selected, the display memory is assigned as a write-only memory. · Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter. For this reason, normal operation cannot be assured for programs that have been prepared with access to these areas. I-12 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(a) I/O memory map (2D0H, 2E0H­2ECH) Address Register Comment Name Init 1 1 0 Unused 0 3 ­ 2 ­ ­ 0 0 0 LOF 0 3 ­ 2 Unused ­ ­ 2D0H 0 3 ­ 2 Unused ­ ­ R R/W LOF 1 Normal All off LCD all off control Clock timer data (2 Hz) TM3 0 TM3 TM2 TM1 TM0 Clock timer data (4 Hz) TM2 0 2E0H Clock timer data (8 Hz) TM1 0 R Clock timer data (16 Hz) TM0 0 SWL3 MSB 0 SWL3 SWL2 SWL1 SWL0 SWL2 0 2E1H Stopwatch timer 1/100 sec data (BCD) SWL1 0 R SWL0 LSB 0 SWH3 MSB 0 SWH3 SWH2 SWH1 SWH0 SWH2 0 2E2H Stopwatch timer 1/10 sec data (BCD) SWH1 0 R SWH0 LSB 0 K03 ­ 2 High Low K03 K02 K01 K00 ­ 2 High K02 Low 2E3H Input port data (K00­K03) ­ 2 High K01 Low R ­ 2 High K00 Low KCP03 KCP03 0 KCP03 KCP03 KCP02 KCP02 KCP01 KCP01 KCP00 KCP00 KCP02 KCP02 0 2E4H Input comparison register (K00­K03) KCP01 KCP01 0 R/W KCP00 KCP00 0 EIK03 EIK03 0 Enable Mask EIK03 EIK03 EIK02 EIK02 EIK01 EIK01 EIK00 EIK00 EIK02 EIK02 0 Enable Mask 2E5H Interrupt mask register (K00­K03) EIK01 EIK01 0 Enable Mask R/W EIK00 EIK00 0 Enable Mask HLMOD Heavy load Normal Heavy load protection mode register 0 HLMOD BLD0 EISWIT1 EISWIT0 Low Normal Sub-BLD evaluation data BLD0 0 2E6H Enable Mask Interrupt mask register (stopwatch 1 Hz) EISWIT1 0 R/W R R/W Enable Mask Interrupt mask register (stopwatch 10 Hz) EISWIT0 0 SCTRG3 Trigger ­ Serial I/F clock trigger ­ SCTRG EIK10 EIK10 KCP10 KCP10 K10 EIK10 EIK10 Enable Mask Interrupt mask register (K10) 0 2E7H KCP10 KCP10 Input comparison register (K10) 0 W R/W R Low Input port data (K10) K10 ­ 2 High CSDC 0 Static Dynamic LCD drive switch CSDC ETI2 ETI8 ETI32 ETI32 ETI2 0 Enable Mask Interrupt mask register (clock timer 2 Hz) 2E8H ETI8 0 Enable Mask Interrupt mask register (clock timer 8 Hz) R/W ETI32 ETI32 0 Enable Mask Interrupt mask register (clock timer 32 Hz) 0 3 ­ 2 Unused ­ ­ 0 TI2 TI8 TI32 TI2 4 0 Interrupt factor flag (clock timer 2 Hz) Yes No 2E9H TI8 4 0 Interrupt factor flag (clock timer 8 Hz) Yes No R TI32 4 0 Interrupt factor flag (clock timer 32 Hz) Yes No IK1 4 0 Interrupt factor flag (K10) Yes No IK1 IK0 SWIT1 SWIT0 IK0 4 0 Interrupt factor flag (K00­K03) Yes No 2EAH SWIT1 4 0 Interrupt factor flag (stopwatch 1 Hz) Yes No R SWIT0 4 0 Interrupt factor flag (stopwatch 10 Hz) Yes No R03 0 High Low Output port (R03) R03 R02 R01 R00 R02 0 High Low Output port (R02) 2EBH R01 0 High Low Output port (R01) R/W R00 0 High Low Output port (R00) R13 0 High/On Low/Off Output port (R13)/BZ output control R11 R13 R12 R10 R12 0 High/On Low/Off Output port (R12)/FOUT output control SIOF 2ECH R11 0 High Low Output port (R11, LAMP) R/W SIOF 0 Run Stop Output port (SIOF) R/W R/W R R10 0 High/On Low/Off Output port (R10)/BZ output control 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-13 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(b) I/O memory map (2EDH­2FAH) Address Register D3 D2 D1 P03 P02 P01 2EDH R/W TMRST SWRUN SWRST 2EEH W R/W W WDRST WD2 WD1 2EFH W R SD3 SD2 SD1 2F0H R/W SD7 SD6 SD5 2F1H R/W SCS1 SCS0 SE2 2F2H R/W 0 0 IK2 2F3H R K23 K22 K21 2F4H R EIK23 EIK23 EIK22 EIK22 EIK21 EIK21 2F5H R/W BZFQ2 BZFQ1 BZFQ0 2F6H R/W ENVON ENVRT AMPDT 2F7H R/W EV03 R EV02 EV01 2F8H R EV07 EV06 EV05 2F9H R EV13 EV12 EV11 2FAH R 1 Initial value at initial reset 2 Not set in the circuit I-14 Comment 1 0 Name Init 1 P03 ­ 2 High Low P00 ­ 2 High I/O port data (P00­P03) P02 Low ­ 2 High Output latch is reset at initial reset P01 Low ­ 2 High P00 Low TMRST3 Reset Reset Clock timer reset ­ IOC0 SWRUN 0 Run Stop Stopwatch timer Run/Stop SWRST3 Reset Reset Stopwatch timer reset ­ R/W IOC0 0 Output Input I/O control register 0 (P00­P03) WDRST3 Reset Reset Watchdog timer reset ­ WD0 WD2 Timer data (watchdog timer) 1/4 Hz 0 WD1 Timer data (watchdog timer) 1/2 Hz 0 WD0 Timer data (watchdog timer) 1 Hz 0 SD3 × 5 SD0 × 5 SD2 Serial I/F data register (low-order 4 bits) × 5 SD1 × 5 SD0 SD7 × 5 SD4 × 5 SD6 Serial I/F data register (high-order 4 bits) × 5 SD5 × 5 SD4 [SCS1, 0] 0 1 2 3 SCS1 Serial I/F clock 1 EISIO Clock CLK CLK/2 CLK/4 Slave SCS0 mode selection 1 SE2 Serial I/F clock edge selection 0 EISIO 0 Enable Mask Interrupt mask register (serial I/F) 0 3 ­ 2 Unused ­ ­ ISIO 0 3 ­ 2 Unused ­ ­ IK2 4 0 Interrupt factor flag (K20­K23) Yes No ISIO 4 0 Interrupt factor flag (serial I/F) Yes No K23 ­ 2 High Low K20 ­ 2 High K22 Low Input port data (K20­K23) ­ 2 High K21 Low ­ 2 High K20 Low EIK23 EIK23 0 Enable Mask EIK20 EIK20 EIK22 EIK22 0 Enable Mask Interrupt mask register (K20­K23) EIK21 EIK21 0 Enable Mask EIK20 EIK20 0 Enable Mask 1 2 3 [BZFQ2­0] 0 BZFQ2 0 Buzzer ENVRST Frequency fOSC1/8 fOSC1/10 fOSC1/12 fOSC1/14 BZFQ1 0 frequency 5 6 7 [BZFQ2­0] 4 BZFQ0 0 selection Frequency fOSC1/16 fOSC1/20 fOSC1/24 fOSC1/28 W ENVRST3 Reset Reset ­ Envelope reset ENVON Envelope On/Off 0 On Off AMPON ENVRT 0 1.0 sec 0.5 sec Envelope cycle selection register AMPDT 1 +>+ < - Analog comparator data R/W AMPON Analog comparator On/Off 0 On Off EV03 0 EV00 EV02 0 Event counter 0 (low-order 4 bits) EV01 0 EV00 0 EV07 0 EV04 EV06 0 Event counter 0 (high-order 4 bits) EV05 0 EV04 0 EV13 0 EV10 EV12 0 Event counter 1 (low-order 4 bits) EV11 0 EV10 0 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Memory Map) Table 4.1.1(c) I/O memory map (2FBH­2FFH) Address Register Comment Name Init 1 1 0 EV17 0 EV17 EV16 EV15 EV14 EV16 0 2FBH Event counter 1 (high-order 4 bits) EV15 0 R EV14 0 EVSEL 0 Separate Phase Event counter mode selection EVSEL ENRUN EV1RST EV0RST EVRUN 0 Run Stop Event counter Run/Stop 2FCH EV1RST3 Reset Reset Event counter 1 reset ­ R/W W EV0RST3 Reset Reset Event counter 0 reset ­ P13 ­ 2 High Low P13 P12 P11 P10 ­ 2 High I/O port data (P10­P13) P12 Low 2FDH ­ 2 High Output latch is reset at initial reset P11 Low R/W ­ 2 High P10 Low PRSM 0 38 kHz 32 kHz OSC1 prescaler selection PRSM CLKCHG OSCC IOC1 CLKCHG 0 OSC3 OSC1 CPU clock switch 2FEH OSCC OSC3 oscillation On/Off 0 On Off R/W IOC1 0 Output Input I/O control register (P10­P13) BLS 0 On Off BLD On/Off BLS BLC2 BLC1 BLC0 BLD1 0 Low Normal BLD evaluation data BLD1 Evaluation voltage setting register 2FFH BLC2 × 5 [BLC2­0] 0 1 2 3 4 5 6 7 W BLC1 × 5 R/W S1C60N08/60A08 S1C60N08/60A08 2.20 2.25 2.30 2.35 2.40 2.45 2.50 2.55 (V) R S1C60L08 S1C60L08 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 (V) × 5 BLC0 1 Initial value at initial reset 3 Always "0" being read 5 Undefined 2 Not set in the circuit 4 Reset (0) immediately after being read D3 D2 D1 D0 S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-15 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Resetting Watchdog Timer) 4.2 Resetting Watchdog Timer 4.2.1 Configuration of watchdog timer The S1C60N08 S1C60N08 Series incorporates a watchdog timer as the source oscillator for OSC1 (clock timer 2 Hz signal). The watchdog timer must be reset cyclically by the software. If reset is not executed in at least 3 or 4 seconds, the initial reset signal is output automatically for the CPU. Figure 4.2.1.1 is the block diagram of the watchdog timer. Clock timer TM0­TM3 OSC1 demultiplier (256 Hz) 2 Hz Watchdog timer WD0­WD2 Initial reset signal Watchdog timer reset signal Fig. 4.2.1.1 Watchdog timer block diagram The watchdog timer, configured of a three-bit binary counter (WD0­WD2), generates the initial reset signal internally by overflow of the MSB. Watchdog timer reset processing in the program's main routine enables detection of program overrun, such as when the main routine's watchdog timer processing is bypassed. Ordinarily this routine is incorporated where periodic processing takes place, just as for the timer interrupt routine. The watchdog timer operates in the halt mode. If the halt status continues for 3 or 4 seconds, the initial reset signal restarts operation. 4.2.2 Mask option You can select whether or not to use the watchdog timer with the mask option. When "Not use" is chosen, there is no need to reset the watchdog timer. 4.2.3 Control of watchdog timer Table 4.2.3.1 lists the watchdog timer's control bits and their addresses. Table 4.2.3.1 Control bits of watchdog timer Address Register D3 D2 D1 WDRST WD2 WD1 2EFH W 1 Initial value at initial reset 2 Not set in the circuit R Comment 1 0 Name Init 1 3 Reset WDRST Watchdog timer reset Reset ­ WD0 WD2 Timer data (watchdog timer) 1/4 Hz 0 WD1 Timer data (watchdog timer) 1/2 Hz 0 WD0 Timer data (watchdog timer) 1 Hz 0 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 WDRST: Watchdog timer reset (2EFH·D3) This is the bit for resetting the watchdog timer. When "1" is written : Watchdog timer is reset When "0" is written : No operation Read-out : Always "0" When "1" is written to WDRST, the watchdog timer is reset, and the operation restarts immediately after this. When "0" is written to WDRST, no operation results. This bit is dedicated for writing, and is always "0" for read-out. 4.2.4 Programming note When the watchdog timer is being used, the software must reset it within 3-second cycles, and timer data (WD0­WD2) cannot be used for timer applications. I-16 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler) 4.3 Oscillation Circuit and Prescaler 4.3.1 Configuration of oscillation circuit and prescaler The S1C60N08 S1C60N08 and S1C60L08 S1C60L08 have one oscillation circuit (OSC1), and the S1C60A08 S1C60A08 has two oscillation circuits (OSC1 and OSC3). OSC1 is a crystal oscillation circuit that supplies the operating clock the CPU and peripheral circuits. OSC3 is either a CR or ceramic oscillation circuit. When processing with the S1C60A08 S1C60A08 requires high-speed operation, the CPU operating clock can be switched from OSC1 to OSC3. Figure 4.3.1.1 is the block diagram of this oscillation system. Prescaler selection signal OSC1 oscillation circuit Prescaler 2 Selector To peripheral circuits (256 Hz) Prescaler 1 To peripheral circuits Clock switch OSC3 oscillation circuit To CPU (and serial interface) CPU clock selection signal Oscillation circuit control signal Fig. 4.3.1.1 Oscillation system As Figure 4.3.1.1 indicates, two prescalers (demultiplier stage) are connected to the oscillation circuit. Prescaler 1 is for 32.768 kHz and prescaler 2 is for 38.4 kHz. These can be selected through the software to suit the crystal oscillator. This selection invokes the basic signal (256 Hz) for running the clock timer, stopwatch timer, and so forth. Also for S1C60A08 S1C60A08, selection of either OSC1 or OSC3 for the CPU's operating clock can be made through the software. 4.3.2 OSC1 oscillation circuit The S1C60N08 S1C60N08 Series has a built-in crystal oscillation circuit (OSC1 oscillation circuit). As an external element, the OSC1 oscillation circuit generates the operating clock for the CPU and peripheral circuits by connecting the crystal oscillator (Typ. 32.768 kHz) and trimmer capacitor (5­25 pF). Figure 4.3.2.1 is the block diagram of the OSC1 oscillation circuit. VDD RFX CGX RDX OSC1 X'tal OSC2 To CPU and peripheral circuits CDX VDD S1C60N08 S1C60N08 Series Fig. 4.3.2.1 OSC1 oscillation circuit As Figure 4.3.2.1 indicates, the crystal oscillation circuit can be configured simply by connecting the crystal oscillator (X'tal) between terminals OSC1 and OSC2 to the trimmer capacitor (CGX) between terminals OSC1 and VDD. Also, the crystal oscillator can be connected to the 38.4 kHz oscillator in addition to the 32.768 kHz oscillator. S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-17 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler) 4.3.3 OSC3 oscillation circuit In the S1C60N08 S1C60N08 Series, the S1C60A08 S1C60A08 has twin clock specification. The mask option enables selection of either the CR or ceramic oscillation circuit (OSC3 oscillation circuit) as the CPU's subclock source. Because the oscillation circuit itself is built-in, it provides the resistance as an external element when CR oscillation is selected, but when ceramic oscillation is selected both the ceramic oscillator and two capacitors (gate and drain capacitance) are required. Figure 4.3.3.1 is the block diagram of the OSC3 oscillation circuit. CCR OSC3 RCR To CPU (and serial interface) OSC4 Oscillation circuit control signal S1C60A08 S1C60A08 CR oscillation circuit Ceramic CDC OSC4 RDC OSC3 RFC VDD CGC To CPU (and serial interface) Oscillation circuit control signal S1C60A08 S1C60A08 Ceramic oscillation circuit Fig. 4.3.3.1 OSC3 oscillation circuit As indicated in Figure 4.3.3.1, the CR oscillation circuit can be configured simply by connecting the resistor (RCR) between terminals OSC3 and OSC4 when CR oscillation is selected. When 82 k is used for RCR, the oscillation frequency is about 410 kHz. When ceramic oscillation is selected, the ceramic oscillation circuit can be configured by connecting the ceramic oscillator (Typ. 500 kHz) between terminals OSC3 and OSC4 to the two capacitors (CGC and CDC) located between terminals OSC3 and OSC4 and VDD. For both CGC and CDC, connect capacitors that are about 100 pF. To lower current consumption of the OSC3 oscillation circuit, oscillation can be stopped through the software. For the S1C60N08 S1C60N08 and S1C60L08 S1C60L08 (single clock specification), do not connect anything to terminals OSC3 and OSC4. I-18 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler) 4.3.4 Control of oscillation circuit and prescaler Table 4.3.4.1 lists the control bits and their addresses for the oscillation circuit. Table 4.3.4.1 Control bits of oscillation circuit and prescaler Address Register D3 D2 D1 PRSM CLKCHG OSCC 2FEH R/W 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 PRSM 0 38 kHz 32 kHz OSC1 prescaler selection IOC1 CLKCHG 0 OSC3 OSC1 CPU clock switch OSCC OSC3 oscillation On/Off 0 On Off IOC1 0 Output Input I/O control register (P10­P13) 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 OSCC: OSC3 oscillation control (2FEH·D1) Controls oscillation ON/OFF for the OSC3 oscillation circuit. (S1C60A08 S1C60A08 only.) When "1" is written : The OSC3 oscillation ON When "0" is written : The OSC3 oscillation OFF Read-out : Valid When it is necessary to operate the CPU of the S1C60A08 S1C60A08 at high speed, set OSCC to "1". At other times, set it to "0" to reduce current consumption. For S1C60N08 S1C60N08 and S1C60L08 S1C60L08, keep OSCC set to "0". At initial reset, OSCC is set to "0". CLKCHG: CPU clock switch (2FEH·D2) The CPU's operation clock is selected with this register. (S1C60A08 S1C60A08 only.) When "1" is written : OSC3 clock is selected When "0" is written : OSC1 clock is selected Read-out : Valid When the S1C60A08 S1C60A08's CPU clock is to be OSC3, set CLKCHG to "1"; for OSC1, set CLKCHG to "0". This register cannot be controlled for S1C60N08 S1C60N08 and S1C60L08 S1C60L08, so that OSC1 is selected no matter what the set value. At initial reset, CLKCHG is set to "0". PRSM: OSC1 prescaler selection (2FEH·D3) Selects the prescaler for the crystal oscillator of the OSC1 oscillation circuit. When "1" is written : 38.4 kHz When "0" is written : 32.768 kHz Read-out : Valid Operation of the clock timer and stopwatch timer can be mode accurate by selecting this register. When the set value for this register does not suit the crystal oscillator used, the operation cycles of the previously mentioned peripheral circuitry is multiplied as shown below. fOSC1 = 32.768 kHz and PRSM = "1": T' 1.172T fOSC1 = 38.4 kHz and PRSM = "0": T' 0.853T At initial reset, PRSM is set to "0". S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-19 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Oscillation Circuit and Prescaler) 4.3.5 Programming notes (1) It takes at least 5 msec from the time the OSC3 oscillation circuit goes ON until the oscillation stabilizes. Consequently, when switching the CPU operation clock from OSC1 to OSC3, do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went ON. Further, the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use, so allow ample margin when setting the wait time. (2) When switching the clock form OSC3 to OSC1, use a separate instruction for switching the OSC3 oscillation OFF. An error in the CPU operation can result if this processing is performed at the same time by the one instruction. (3) To operate the clock timer and stopwatch timer accurately, select the prescaler of the OSC1 to match the crystal oscillator used. I-20 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4 Input Ports (K00­K03, K10, K20­K23) 4.4.1 Configuration of input ports The S1C60N08 S1C60N08 Series has nine bits (4 bits × 2 + 1 bit) of general-purpose input ports. Each of the input port terminals (K00­K03, K10, K20­K23) provides internal pull-down resistor. Pull-down resistor can be selected for each bit with the mask option. Figure 4.4.1.1 shows the configuration of input port. VDD Data bus Interrupt request K Mask option Address VSS Fig. 4.4.1.1 Configuration of input port Selection of "With pull-down resistor" with the mask option suits input from the push switch, key matrix, and so forth. When "Gate direct" is selected, the port can be used for slide switch input and interfacing with other LSIs. Further, The input port terminal K02 and K03 are used as the input terminals for the event counter. (See Section 4.12, "Event Counter", for details.) 4.4.2 Input comparison registers and interrupt function All nine bits of the input ports (K00­K03, K10, K20­K23) provide the interrupt function for the five bits, K00­K03 and K10. The conditions for issuing an interrupt can be set by the software for the five bits, K00­ K03 and K10. Further, whether to mask the interrupt function can be selected individually for all nine bits by the software. Figure 4.4.2.1 shows the configuration of K00­K03 and K10. Figure 4.4.2.3 shows the configuration of K20­K23. K Data bus Address Input comparison register (KCP) Address Interrupt mask register (EIK) One for each terminal series Noise rejector Interrupt factor flag (IK) Mask option (K00­K03, K10) Interrupt request Address Address Fig. 4.4.2.1 Input interrupt circuit configuration (K00­K03, K10) S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-21 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) The input interrupt timing for K00­K03 and K10 depends on the value set for the input comparison registers (KCP00 KCP00­KCP03 KCP03 and KCP10 KCP10). Interrupt can be selected to occur at the rising or falling edge of the input. The interrupt mask registers (EIK00 EIK00­EIK03 EIK03, EIK10 EIK10) enables the interrupt mask to be selected individually for K00­K03 and K10. However, whereas the interrupt function is enabled inside K00­K03, the interrupt occurs when the contents change from matching those of the input comparison register to non-matching contents. Interrupt for K10 can be generated by setting the same conditions individually. When the interrupt is generated, the interrupt factor flag (IK0 and IK1) is set to "1". Figure 4.4.2.2 shows an example of an interrupt for K00­K03. Interrupt mask register EIK03 EIK03 1 EIK02 EIK02 1 EIK01 EIK01 1 EIK00 EIK00 0 Input comparison register KCP03 KCP03 KCP02 KCP02 KCP01 KCP01 KCP00 KCP00 1 0 1 0 With the above setting, the interrupt of K00­K03 is generated under the following condition: Input port (1) K03 1 K02 0 K01 1 K00 0 (2) K03 1 K02 0 K01 1 K00 1 (3) K03 0 K02 0 K01 1 K00 1 (4) K03 0 K02 1 K01 1 K00 1 (Initial value) Interrupt generation Because K00 interrupt is masked, interrupt will be generated when no matching occurs between the contents of the 3 bits K01­K03 and the 3 bits input comparison register KCP01 KCP01­KCP03 KCP03. Fig. 4.4.2.2 Example of interrupt of K00­K03 K00 is masked by the interrupt mask register (EIK00 EIK00), so that an interrupt does not occur at (2). At (3), K03 changes to "0"; the data of the terminal that is interrupt enabled no longer matches the data of the input comparison register, so that interrupt occurs. As already explained, the condition for the interrupt to occur is the change in the port data and contents of the input comparison register from matching to nonmatching. Hence, in (4), when the nonmatching status changes to another nonmatching status, an interrupt does not occur. Further, terminals that have been masked for interrupt do not affect the conditions for interrupt generation. I-22 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) K Noise rejector Data bus Address Interrupt mask register (EIK) Interrupt factor flag (IK2) Mask option (K20­K23) Address Interrupt request Address Fig. 4.4.2.3 Input interrupt circuit configuration (K20­K23) There is no input comparison register for K20­K23, and interrupt is fixed to occur at th rising edge of input. The interrupt mask can be selected for each of the four terminals with the interrupt mask register (EIK20 EIK20­EIK23 EIK23). When all the enabled terminals are "0", interrupt occurs when one or more of the ports changed to "1". When an interrupt occurs, the interrupt factor flag (IK2) is set to "1". Figure 4.4.2.4 shows an example of an interrupt being generated for K20­K23. Interrupt mask register EIK23 EIK23 0 EIK22 EIK22 1 EIK21 EIK21 1 EIK20 EIK20 1 With the above setting, the interrupt of K20­K23 is generated under the following condition: Input port (1) K23 0 K22 0 K21 0 K20 0 (2) K23 1 K22 0 K21 0 K20 0 (3) K23 1 K22 0 K21 1 K20 0 (4) K23 1 K22 0 K21 1 K20 1 (Initial value) Interrupt generation Because K23 interrupt is masked, interrupt will be generated when one or more terminals among the 3 bits K20­K22 become "1" from a state where all terminals were "0". Fig. 4.4.2.4 Example of interrupt of K20­K23 The mask register (EIK23 EIK23) masks the interrupt of K23, so an interrupt does not occur at (2). At (3), K21 becomes "1", so that an interrupt occurs if the interrupt enabled terminals were all "0" and at least one terminal then changes to "1". At (4), the conditions for interrupt are not established, so an interrupt does not occur. Futher, terminals that have been masked for interrupt do not affect the conditions for interrupt generation. S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-23 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4.3 Mask option The contents that can be selected with the input port mask option are as follows: (1) Internal pull-down resistor can be selected for each of the nine bits of the input ports (K00­K03, K10, K20­K23). When you have selected "Gate direct", take care that the floating status does not occur for the input. Select "With pull-down resistor" for input ports that are not being used. (2) The input interrupt circuit contains a noise rejector for preventing interrupt occurring through noise. The mask option enables selection of whether to use the noise rejector for each separate terminal series. When "Use" is selected, a maximum delay of 1 msec occurs from the time interrupt condition is established until the interrupt factor flag (IK) is set to "1". 4.4.4 Control of input ports Table 4.4.4.1 lists the input ports control bits and their addresses. Table 4.4.4.1 Input port control bits Address Register D3 D2 D1 D0 K03 K02 K01 K00 2E3H R KCP03 KCP03 KCP02 KCP02 KCP01 KCP01 KCP00 KCP00 2E4H R/W EIK03 EIK03 EIK02 EIK02 EIK01 EIK01 EIK00 EIK00 2E5H R/W SCTRG EIK10 EIK10 KCP10 KCP10 K10 2E7H W IK1 R/W IK0 R SWIT1 SWIT0 IK2 ISIO K21 K20 EIK21 EIK21 EIK20 EIK20 2EAH R 0 0 2F3H R K23 K22 2F4H R EIK23 EIK23 EIK22 EIK22 2F5H R/W 1 Initial value at initial reset 2 Not set in the circuit I-24 Comment 1 0 Name Init 1 K03 ­ 2 High Low ­ 2 High K02 Low Input port data (K00­K03) ­ 2 High K01 Low ­ 2 High K00 Low KCP03 KCP03 0 KCP02 KCP02 0 Input comparison register (K00­K03) KCP01 KCP01 0 KCP00 KCP00 0 EIK03 EIK03 0 Enable Mask EIK02 EIK02 0 Enable Mask Interrupt mask register (K00­K03) EIK01 EIK01 0 Enable Mask EIK00 EIK00 0 Enable Mask SCTRG3 Trigger ­ Serial I/F clock trigger ­ EIK10 EIK10 Enable Mask Interrupt mask register (K10) 0 KCP10 KCP10 Input comparison register (K10) 0 Low Input port data (K10) K10 ­ 2 High IK1 4 0 Interrupt factor flag (K10) Yes No IK0 4 0 Interrupt factor flag (K00­K03) Yes No SWIT1 4 0 Interrupt factor flag (stopwatch 1 Hz) Yes No SWIT0 4 0 Interrupt factor flag (stopwatch 10 Hz) Yes No 0 3 ­ 2 Unused ­ ­ 0 3 ­ 2 Unused ­ ­ IK2 4 0 Interrupt factor flag (K20­K23) Yes No ISIO 4 0 Interrupt factor flag (serial I/F) Yes No K23 ­ 2 High Low ­ 2 High K22 Low Input port data (K20­K23) ­ 2 High K21 Low ­ 2 High K20 Low EIK23 EIK23 0 Enable Mask EIK22 EIK22 0 Enable Mask Interrupt mask register (K20­K23) EIK21 EIK21 0 Enable Mask EIK20 EIK20 0 Enable Mask 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) K00­K03, K10, K20­K23: Input port data (2E3H, 2E7H·D0, 2F4H) Input data of the input port terminals can be read out with these registers. When "1" is read out : High level When "0" is read out : Low level Writing : Invalid The read-out is "1" when the terminal voltage of the nine bits of the input ports (K00­K03, K10, K20­K23) goes high (VDD), and "0" when the voltage goes low (VSS). These bits are dedicated for read-out, so writing cannot be done. KCP00 KCP00­KCP03 KCP03, KCP10 KCP10: Input comparison registers (2E4H, 2E7H·D1) Interrupt conditions for terminals K00­K03 and K10 can be set with these registers. When "1" is written : Falling edge When "0" is written : Rising edge Read-out : Valid Of the nine bits of the input ports, the interrupt conditions can be set for the rising or falling edge of input for each of the five bits (K00­K03 and K10), through the input comparison registers (KCP00 KCP00­KCP03 KCP03 and KCP10 KCP10). At initial reset, these registers are set to "0". EIK00 EIK00­EIK03 EIK03, EIK10 EIK10, EIK20 EIK20­EIK23 EIK23: Interrupt mask registers (2E5H, 2E7H·D2, 2F5H) Masking the interrupt of the input port terminals can be selected with these registers. When "1" is written : Enable When "0" is written : Mask Read-out : Valid With these registers, masking of the input port bits can be selected for each of the nine bits. Writing to the interrupt mask registers can be done only in the DI status (interrupt flag = "0"). At initial reset, these registers are all set to "0". IK0, IK1, IK2: Interrupt factor flags (2EAH·D2 and D3, 2F3H·D1) These flags indicate the occurrence of input interrupt. When "1" is read out : Interrupt has occurred When "0" is read out : Interrupt has not occurred Writing : Invalid The interrupt factor flags IK0, IK1 and IK2 are associated with K00­K03, K10 and K20­K23, respectively. From the status of these flags, the software can decide whether an input interrupt has occurred. These flags are reset when the software reads them. Read-out can be done only in the DI status (interrupt flag = "0"). At initial reset, these flags are set to "0". S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-25 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Input Ports) 4.4.5 Programming notes (1) When input ports are changed from high to low by pull-down resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Hence, when fetching input ports, set an appropriate wait time. Particular care needs to be taken of the key scan during key matrix configuration. Aim for a wait time of about 1 msec. (2) When "Use" is selected with the noise rejector mask option, a maximum delay of 1 msec occurs from time the interrupt conditions are established until the interrupt factor flag (IK) is set to "1" (until the interrupt is actually generated). Hence, pay attention to the timing when reading out (resetting) the interrupt factor flag. For example, when performing a key scan with the key matrix, the key scan changes the input status to set the interrupt factor flag, so it has to be read out to reset it. However, if the interrupt factor flag is read out immediately after key scanning, the delay will cause the flag to be set after read-out, so that it will not be reset. (3) Input interrupt programing related precautions Port K input Active status Active status Input comparison register Falling edge interrupt Rising edge interrupt Mask register Factor flag set Not set Factor flag set When the content of the mask register is rewritten while the port K input is in the active status, the input interrupt factor flags are set at and , being the interrupt due to the falling edge and the interrupt due to the rising edge. Fig. 4.4.5.1 Input interrupt timing When using an input interrupt, if you rewrite the content of the mask register, when the value of the input terminal which becomes the interrupt input is in the active status, the factor flag for input interrupt may be set. Therefore, when using the input interrupt, the active status of the input terminal implies input terminal = low status, when the falling edge interrupt is effected and input terminal = high status, when the rising edge interrupt is effected. When an interrupt is triggered at the falling edge of an input terminal, a factor flag is set with the timing of shown in Figure 4.4.5.1. However, when clearing the content of the mask register with the input terminal kept in the low status and then setting it, the factor flag of the input interrupt is again set at the timing that has been set. Consequently, when the input terminal is in the active status (low status), do not rewrite the mask register (clearing, then setting the mask register), so that a factor flag will only set at the falling edge in this case. When clearing, then setting the mask register, set the mask register, when the input terminal is not in the active status (high status). When an interrupt is triggered at the rising edge of the input terminal, a factor flag will be set at the timing of shown in Figure 4.4.5.1. In this case, when the mask registers cleared, then set, you should set the mask register, when the input terminal is in the low status. In addition, when the mask register = "1" and the content of the input comparison register is rewritten in the input terminal active status, an input interrupt factor flag may be set. Thus, you should rewrite the content of the input comparison register in the mask register = "0" status. (4) Read out the interrupt factor flag (IK) only in the DI status (interrupt flag = "0"). Read-out during EI status (interrupt flag = "1") will cause malfunction. (5) Write the interrupt mask register (EIK) only in the DI status (interrupt flag = "0"). Writing during EI status (interrupt flag = "1") will cause malfunction. I-26 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5 Output Ports (R00­R03, R10­R13) 4.5.1 Configuration of output ports The S1C60N08 S1C60N08 Series has eight bits (4 bits × 2) of general output ports. Output specifications of the output ports can be selected individually with the mask option. Two kinds of output specifications are available: complementary output and Pch open drain output. Further, the mask option enables the output ports R10­R13 to be used as special output ports. Figure 4.5.1.1 shows the configuration of the output ports. Data bus VDD Register Rxx Complementary Pch open drain Address VSS Mask option Fig. 4.5.1.1 Configuration of output ports 4.5.2 Mask option The mask option enables the following output port selection. (1) Output specifications of output ports Output specifications for the output ports (R00­R03, R10­R13) enable selection of either complementary output or Pch open drain output for each of the eight bits. However, even when Pch open drain output is selected, voltage exceeding source voltage must not be applied to the output port. (2) Special output In addition to the regular DC output, special output can be selected for the output ports R10­R13 as shown in Table 4.5.2.1. Figure 4.5.2.1 shows the structure of the output ports R10­R13. Table 4.5.2.1 Special output Output port Special output R10 R13 R11 R12 BZ output BZ output (selectable only when R10 is used as BZ output) SIOF output FOUT output S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-27 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) BZ R10 Register R10 R13 Data bus Register R13 SIOF R11 Register R11 FOUT R12 Register R12 Address 2ECH Mask option Fig. 4.5.2.1 Structure of output port R10­R13 BZ, BZ (R10, R13) BZ and BZ are the buzzer signal output for driving the piezoelectric buzzer. The buzzer signal is generated by demultiplicaion of fOSC1. Also, a digital envelope can be added to the buzzer signal. See Section 4.11, "Sound Generator", for details. Notes: · When the BZ and BZ output signals are turned ON or OFF, a hazard can result. · When DC output is set for the output port R10, the output port R13 cannot be set for BZ output. Figure 4.5.2.2 shows the output waveform for BZ and BZ. R00(R03) register "0" "1" "0" BZ output (R10 terminal) BZ output (R13 terminal) Fig. 4.5.2.2 Output waveform of BZ and BZ SIOF (R11) When the output port R11 is set for SIOF output, it outputs the signal indicating the running status (RUN/STOP) of the serial interface. See Section 4.7, "Serial Interface", for details. FOUT (R12) When the output port R12 is set for FOUT output, it outputs the clock of fOSC1 or the demultiplied fOSC1. The clock frequency is selectable with the mask options, from the frequencies listed in Table 4.5.2.2. Table 4.5.2.2 FOUT clock frequency Setting value fOSC1 / 1 fOSC1 / 2 fOSC1 / 4 fOSC1 / 8 fOSC1 / 16 fOSC1 / 32 fOSC1 / 64 fOSC1 / 128 Clock frequency (Hz) fOSC1 = 32.768 kHz fOSC1 = 38.400 kHz 32,768 38,400 16,384 19,200 8,192 9,600 4,096 4,800 2,048 2,400 1,024 1,200 512 600 256 300 Note: A hazard may occur when the FOUT signal is turned ON or OFF. I-28 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) 4.5.3 Control of output ports Table 4.5.3.1 lists the output ports' control bits and their addresses. Table 4.5.3.1 Control bits of output ports Address Register D3 D2 D1 D0 R03 R02 R01 R00 2EBH R/W R11 R13 R12 2ECH SIOF R10 R/W R/W R R/W Name R03 R02 R01 R00 R13 R12 R11 SIOF R10 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Init 1 0 High Low Output port (R03) 0 High Low Output port (R02) 0 High Low Output port (R01) 0 High Low Output port (R00) 0 High/On Low/Off Output port (R13)/BZ output control 0 High/On Low/Off Output port (R12)/FOUT output control 0 High Low Output port (R11, LAMP) 0 Run Stop Output port (SIOF) 0 High/On Low/Off Output port (R10)/BZ output control 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read R00­R03, R10­R13 (when DC output): Output port data (2EBH, 2ECH) Sets the output data for the output ports. When "1" is written : High output When "0" is written : Low output Read-out : Valid The output port terminals output the data written in the corresponding registers (R00­R03, R10­R13) without changing it. When "1" is written in the register, the output port terminal goes high (VDD), and when "0" is written, the output port terminal goes low (VSS). At initial reset, all registers are set to "0". R10, R13 (when BZ and BZ output is selected): Buzzer output control (2ECH·D0 and D3) These bits control the output of the buzzer signals (BZ, BZ). When "1" is written : Buzzer signal is output When "0" is written : Low level (DC) is output Read-out : Valid BZ is output from terminal R13. With the mask option, selection can be made perform this output control by R13, or to perform output control simultaneously with BZ by R10. · When R13 controls BZ output BZ output and BZ output can be controlled independently. BZ output is controlled by writing data to R10, and BZ output is controlled by writing data to R13. · When R10 controls BZ output BZ output and BZ output can be controlled simultaneously by writing data to R10 only. For this case, R13 can be used as a one-bit general register having both read and write functions, and data of this register exerts no affect on BZ output (output from the R13 pin). At initial reset, registers R10 and R13 are set to "0". R11 (when SIOF output is selected): Serial interface status (2ECH·D1) Indicates the running status of the serial interface. When "1" is read out : RUN When "0" is read out : STOP Writing : Valid See Section 4.7, "Serial Interface", for details of SIOF. This bit is exclusively for reading out, so data cannot be written to it. S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-29 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Ports) R12 (when FOUT is selected): FOUT output control (2ECH·D2) Controls the FOUT (clock) output. When "1" is written : Clock output When "0" is written : Low level (DC) output Read-out : Valid FOUT output can be controlled by writing data to R12. At initial reset, this register is set to "0". 4.5.4 Programming note When BZ, BZ and FOUT are selected with the mask option, a hazard may be observed in the output waveform when the data of the output register changes. I-30 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6 I/O Ports (P00­P03, P10­P13) 4.6.1 Configuration of I/O ports Data bus The S1C60N08 S1C60N08 Series has eight bits (4 bits × 2) of general-purpose I/O ports. Figure 4.6.1.1 shows the configuration of the I/O ports. The four bits of each of the I/O ports P00­P03 and P10­P13 can be set to either input mode or output mode. Modes can be set by writing data to the I/O control register. Input control Register P Address Address I/O control register VSS Fig. 4.6.1.1 Configuration of I/O port 4.6.2 I/O control register and I/O mode Input or output mode can be set for the four bits of I/O port P00­P03 and I/O port P10­P13 by writing data into the corresponding I/O control register IOC0 and IOC1. To set the input mode, "0" is written to the I/O control register. When an I/O port is set to input mode, it becomes high impedance status and works as an input port. However, the input line is pulled down when input data is read. The output mode is set when "1" is written to the I/O control register. When an I/O port set to output mode works as an output port, it outputs a high signal (VDD) when the port output data is "1", and a low signal (VSS) when the port output data is "0". At initial reset, the I/O control registers are set to "0", and the I/O port enters the input mode. 4.6.3 Mask option The output specification during output mode (IOC = "1") of these I/O ports can be set with the mask option for either complementary output or Pch open drain output. This setting can be performed for each bit of each port. However, when Pch open drain output has been selected, voltage in excess of the power voltage must not be applied to the port. S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-31 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) 4.6.4 Control of I/O ports Table 4.6.4.1 lists the I/O ports' control bits and their addresses. Table 4.6.4.1 I/O port control bits Address Register D3 D2 D1 P03 P02 P01 2EDH R/W TMRST SWRUN SWRST 2EEH W R/W W P13 P12 P11 2FDH R/W PRSM CLKCHG OSCC 2FEH R/W 1 Initial value at initial reset 2 Not set in the circuit Comment 1 0 Name Init 1 P03 Low ­ 2 High P00 ­ 2 High I/O port data (P00­P03) P02 Low ­ 2 High Output latch is reset at initial reset P01 Low ­ 2 High P00 Low TMRST3 Reset Reset Clock timer reset ­ IOC0 SWRUN 0 Run Stop Stopwatch timer Run/Stop SWRST3 Reset Reset Stopwatch timer reset ­ R/W IOC0 0 Output Input I/O control register 0 (P00­P03) P13 ­ 2 High Low P10 ­ 2 High I/O port data (P10­P13) P12 Low ­ 2 High Output latch is reset at initial reset P11 Low ­ 2 High P10 Low PRSM 0 38 kHz 32 kHz OSC1 prescaler selection IOC1 CLKCHG 0 OSC3 OSC1 CPU clock switch OSCC OSC3 oscillation On/Off 0 On Off IOC1 0 Output Input I/O control register (P10­P13) 3 Always "0" being read 5 Undefined 4 Reset (0) immediately after being read D0 P00­P03, P10­P13: I/O port data (2EDH, 2FDH) I/O port data can be read and output data can be set through these ports. When writing data When "1" is written : High level When "0" is written : Low level When an I/O port is set to the output mode, the written data is output unchanged from the I/O port terminal. When "1" is written as the port data, the port terminal goes high (VDD), and when "0" is written, the level goes low (VSS). Port data can be written also in the input mode. When reading data out When "1" is read out : High level When "0" is read out : Low level The terminal voltage level of the I/O port is read out. When the I/O port is in the input mode the voltage level being input to the port terminal can be read out; in the output mode the output voltage level can be read. When the terminal voltage is high (VDD) the port data that can be read is "1", and when the terminal voltage is low (VSS) the data is "0". Further, the built-in pull-down resistance goes ON during read-out, so that the I/O port terminal is pulled down. Notes: · When the I/O port is set to the output mode and a low-impedance load is connected to the port terminal, the data written to the register may differ from the data read out. · When the I/O port is set to the input mode and a low-level voltage (VSS) is input, erroneous input results if the time constant of the capacitive load of the input line and the built-in pull-down resistance load is greater than the read-out time. When the input data is being read out, the time that the input line is pulled down is equivalent to 1.5 cycles of the CPU system clock. However, the electric potential of the terminals must be settled within 0.5 cycles. If this condition cannot be fulfilled, some measure must be devised such as arranging pull-down resistance externally, or performing multiple read-outs. I-32 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (I/O Ports) IOC0, IOC1: I/O control registers (2EEH·D0, 2FEH·D0) The input and output modes of the I/O ports can be set with these registers. When "1" is written : Output mode When "0" is written : Input mode Read-out : Valid The input and output modes of the I/O ports are set in units of four bits. IOC0 sets the mode for P00­P03, and IOC1 sets the mode for P10­P13. Writing "1" to the I/O control register makes the corresponding I/O port enter the output mode, and writing "0" induces the input mode. At initial reset, these two registers are set to "0", so the I/O ports are in the input mode. 4.6.5 Programming notes (1) When input data are changed from high to low by built-in pull-down resistance, the fall of the waveform is delayed on account of the time constant of the pull-down resistance and input gate capacitance. Consequently, if data is read out while the CPU is running in the OSC3 oscillation circuit, data must be read out continuously for about 500 µsec. (2) When the I/O port is set to the output mode and the data register has been read, the terminal data instead of the register data can be read out. Because of this, if a low-impedance load is connected and read-out performed, the value of the register and the read-out result may differ. S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-33 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.7 Serial Interface (SIN, SOUT, SCLK) 4.7.1 Configuration of serial interface The S1C60N08 S1C60N08 Series has a synchronous clock type 8 bits serial interface built-in. The configuration of the serial interface is shown in Figure 4.7.1.1. The CPU, via the 8 bits shift register, can read the serial input data from the SIN terminal. Moreover, via the same 8 bits shift register, it can convert parallel data to serial data and output it to the SOUT terminal. The synchronous clock for serial data input/output may be set by selecting by software any one of 3 types of master mode (internal clock mode: when the S1C60N08 S1C60N08 Series is to be the master for serial input/output) and a type of slave mode (external clock mode: when the S1C60N08 S1C60N08 Series is to be the slave for serial input/output). Also, when the serial interface is used at slave mode, SIOF signal which indicates whether or not the serial interface is available to transmit or receive can be output to output port R11 by mask option. SD0­SD7 Shift register (8 bits) SIN SCS0 Output latch SOUT SE2 SCS1 Serial clock counter Serial clock selector SCLK Serial clock generator Serial I/F interrupt control circuit System clock EISIO Serial I/F activating circuit SCTRG ISIO SIOF Fig. 4.7.1.1 Configuration of serial interface 4.7.2 Master mode and slave mode of serial interface The serial interface of the S1C60N08 S1C60N08 Series has two types of operation mode: master mode and slave mode. In the master mode, it uses an internal clock as synchronous clock of the built-in shift register, generates this internal clock at the SCLK terminal and controls the external (slave side) serial device. In the slave mode, the synchronous clock output from the external (master side) serial device is input from the SCLK terminal and uses it as the synchronous clock to the built-in shift register. The master mode and slave mode are selected by writing data to registers SCS1 and SCS0 (address 2F2H·D2, D3). When the master mode is selected, a synchronous clock may be selected from among 3 types as shown in Table 4.7.2.1. Table 4.7.2.1 Synchronous clock selection SCS1 0 0 1 1 SCS0 0 1 0 1 Mode Master mode Slave mode Synchronous clock CLK CLK/2 CLK/4 External clock CLK: CPU system clock At initial reset, the slave mode (external clock mode) is selected. Moreover, the synchronous clock, along with the input/output of the 8 bits serial data, is controlled as follows: · At master mode, after output of 8 clocks from the SCLK terminal, clock output is automatically suspended and SCLK terminal is fixed at low level. · At slave mode, after input of 8 clocks to the SCLK terminal, subsequent clock inputs are masked. I-34 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) Note: When using the serial interface in the master mode, CPU system clock is used as the synchronous clock. Accordingly, when the serial interface is operating, system clock switching (fOSC1 fOSC3) should not be performed. A sample basic serial input/output portion connection is shown in Figure 4.7.2.1. SCLK External serial device CLK SOUT SOUT S1C60N08 S1C60N08 SIN SCLK SOUT SOUT SIN SIN Input terminal External serial device CLK S1C60N08 S1C60N08 SIN R11(SIOF) READY Master mode Input terminal Slave mode Fig. 4.7.2.1 Sample basic connection 4.7.3 Data input/output and interrupt function The serial interface can input/output data via the internal 8 bits shift register. The shift register operates by synchronizing with either the synchronous clock output from SCLK terminal (master mode), or the synchronous clock input to SCLK (slave mode). The serial interface generates interrupt on completion of the 8 bits serial data input/output. Detection of serial data input/output is done by the counting of the synchronous clock (SCLK); the clock completes input/output operation when 8 counts (equivalent to 8 cycles) have been made and then generates interrupt. The serial data input/output procedure data is explained below: (1) Serial data output procedure and interrupt The serial interface is capable of outputting parallel data as serial data, in units of 8 bits. By setting the parallel data to 4 bits registers SD0­SD3 (address 2F0H) and SD4­SD7 (address 2F1H) individually and writing "1" to SCTRG bit (address 2E7H·D3), it synchronizes with the synchronous clock and serial data is output at the SOUT terminal. The synchronous clock used here is as follows: in the master mode, internal clock which is output to the SCLK terminal while in the slave mode, external clock which is input from the SCLK terminal. The serial output of the SOUT termina changes with the rising edge of the clock that is input or output from the SCLK terminal. The serial data to the built-in shift register is shifted with the rising edge of the SCLK signal when SE2 bit (address 2F2H·D1) is "1" and is shifted with the falling edge of the SCLK signal when SE2 bit (address 2F2H·D1) is "0". When the output of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO (address 2F3H·D0) is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIO (address 2F2H·D0). (2) Serial data input procedure and interrupt The serial interface is capable of inputting serial data as parallel data, in units of 8 bits. The serial data is input from the SIN terminal, synchronizes with the synchronous clock, and is sequentially read in the 8 bits shift register. As in the above item (1), the synchronous clock used here is as follows: in the master mode, internal clock which is output to the SCLK terminal while in the slave mode, external clock which is input from the SCLK terminal. The serial data to the built-in shift register is read with the rising edge of the SCLK signal when SE2 bit is "1" and is read with the falling edge of the SCLK signal when SE2 bit is "0". Moreover, the shift register is sequentially shifted as the data is fetched. When the input of the 8 bits data from SD0 to SD7 is completed, the interrupt factor flag ISIO is set to "1" and interrupt is generated. Moreover, the interrupt can be masked by the interrupt mask register EISIO. Note, however, that regardless of the setting of the interrupt mask register, the interrupt factor flag is set to "1" after input of the 8 bits data. The data input in the shift register can be read from data registers SD0­SD7 by software. S1C60N08 S1C60N08 TECHNICAL HARDWARE EPSON I-35 CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) (3) Serial data input/output permutation The S1C60N08 S1C60N08 Series allows the input/output permutation of serial data to be selected by mask option as to either LSB first or MSB first. The block diagram showing input/output permutation in case of LSB first and MSB first is provided in Figure 4.7.3.1. SIN Address [2F1H] SD7 SD6 SD5 SD4 Address [2F0H] SD3 SD2 SD1 SD0 Output latch SOUT Output latch SOUT In case of LSB first SIN Address [2F0H] SD0 SD1 SD2 SD3 Address [2F1H] SD4 SD5 SD6 SD7 In case of MSB first Fig. 4.7.3.1 Serial data input/output permutation (4) SIOF signal When the serial interface is used in the slave mode (external clock mode), SIOF is used to indicate whether the internal serial interface is available to transmit or receive data for the master side (external) serial device. SIOF signal is generated from output port R11 by mask option. SIOF signal becomes "1" (high) when the S1C60N08 S1C60N08 serial interface becomes available to transmit or receive data; normally, it is at "0" (low). SIOF signal changes from "0" to "1" immediately after "1" is written to SCTRG and returns from "1" to "0" when eight synchronous clock has been counted. (5) Timing chart The serial interface timing chart is shown in Figure 4.7.3.2. SCTRG SCLK SIN 8-bit shift register SOUT ISIO SIOF (a) SE2 = "1" SCTRG SCLK SIN 8-bit shift register SOUT ISIO SIOF (b) SE2 = "0" Fig. 4.7.3.2 Serial interface timing chart I-36 EPSON S1C60N08 S1C60N08 TECHNICAL HARDWARE CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface) 4.7.4 Mask option The serial interface may be selected for the following by mask option. (1) Whether or not the SIN terminal will use built-in pull down resistor may be selected. If the use of no pull down resistor is selected, take care that floating state does not occur at the SIN terminal. When the SIN terminal is not used, the use of pull down resistor should be selected. (2) Either complementary output or P channel (Pch) open drain as output specification for the SOUT terminal may be selected. However, even if Pch open drain has been selected, application of voltage exceeding power source voltage to the SOUT terminal will be prohibited. (3) Whether or not the SCLK terminal will use pull down resistor which is turned ON during input mode (external clock) may be selected. If the use of no pull down resistor is selected, take care that floating state does not occur at the SCLK terminal duri