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MSP430-3P-TOTAL-TP320120-PRGA Texas Instruments Beagle I2C/SPI/MDIO Protocol Analyzer visit Texas Instruments

MDIO clause 45

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MDIO clause 45

Abstract: BCM8705 industry standard · IEEE 802.3TMae serial Ethernet transceiver (LAN/WAN PHY), MDIO Clause 45 management , ) BCM8705 Block Diagram XAUI BCM8705 MAC MDC MDIO Management Interface 9.953/10.3125/10.5188 , internally biased differential LVPECL SYSRSTB RSTB MDC MDIO PRTAD[4:0] Control and Status
Broadcom
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MDIO clause 45 regulator 8705 Broadcom BCM8705 BCM8704 10G cdr StrataXGS 10-GBE/FIBRE 5188-G OC-192 64B/66B 38-MH 8705-PB02-R
Abstract: standard â'¢ IEEE 802.3ae Serial Ethernet Transceiver (LAN/WAN PHY), MDIO Clause 45 management interface , BCM8705 MAC MDC MDIO Management Interface 9.953/10.3125/10.5188 Gbps WIS XGXS PCS/PMA , RSTB MDC MDIO PRTAD[4:0] Control and Status PLOSB/A1 PMD Analog XAUI CMOS LASI Broadcom
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10-GIGABIT BCM870 8B/10B 8705-PB01-D2
Abstract: from the MDIO (Clause 45) interface. The resultant word is returned in the variable nData , to the MDIO (Clause 22) interface. Parameters: nPhyAddr â'" This value is the address of the slave , to the MDIO (Clause 24) interface. Parameters: nPortAddr â'" This value is the address of the slave , PC-I2C-DEV with MDIO and SPI support Software Developer User Manual FDI Future Designs , .12 7. MDIO Routines Future Designs
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Abstract: Jumbo Packet Support JTAG; IEEE 1149.1 /1149.6 Test Interface Industry Standard MDIO Clause 45 and 22 , CHANNEL C BACKPLANE XAUI CHANNEL B 10GBASE-KR CHANNEL D XGXS XAUI CHANNEL D MDC MDIO , TLK10034 provides a management data input/output (MDIO) interface as well as a JTAG interface for device , ] LO SA MDIO LS_OK_OUT_A MDC MDIO LS_OK_IN_A CONTROL, STATUS, TEST ST MODE_SEL Texas Instruments
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XAUI/10GBASE-KR 3125G 10G-KR ISO/TS16949
Abstract: Packet Support JTAG; IEEE 1149.1 /1149.6 Test Interface Industry Standard MDIO Clause 45 and 22 Control , CHANNEL C 10GBASE-KR CHANNEL C XGXS 10GBASE-KR CHANNEL D XAUI CHANNEL D MDC MDIO 1 , input/output (MDIO) interface as well as a JTAG interface for device configuration, control, and , HST X0_ CLK OUTP/N HST X1_ CLK OUTP/N PRTAD[ 4:0] LO SA LS_OK_IN_A LS_OK_OUT_A MDIO MDC MDIO Texas Instruments
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MDIO clause 45

Abstract: 78 los per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL ADDR pins compatible, not 1.2V , 0.1 0.3 ns 0 2.5 MHz 40 MDC/MDIO TIMING SPECIFICATIONS (Clause 45) fMDC MDC , though an MDIO interface as well as through pins, featuring configurable transmitter deemphasis , Internal Pulling both pins low enables MDIO control, default is no de-emphasis. pull down PE1 PE0 0 , . LVCMOS Internal Pulling both pins low enables MDIO control, default is no receive equalization. pull
National Semiconductor
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SCAN12100 SCAN25100 78 los remote control transmiter AVDD33 SCAN12100TYA

MDIO clause 45

Abstract: AVDD33 per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL ADDR pins compatible, not 1.2V , /MDIO TIMING SPECIFICATIONS (Clause 45) fMDC MDC Frequency 9 www.national.com SCAN25100 , SCAN25100 is programmable though an MDIO interface as well as through pins, featuring configurable , Transmitter de-emphasis configuration. LVCMOS Internal Pulling both pins low enables MDIO control, default is , Receive input equalization configuration. LVCMOS Internal Pulling both pins low enables MDIO control
National Semiconductor
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SCAN25100TYA TQFP-100 MDIO clause 45 specification

MDIO clause 45

Abstract: technical information for MDIO Clause 22 and MDIO Clause 45. Technical Support for most MDIO peripherals , device that adheres to IEEE 802.3 Clause 22 (old MDIO) â'¢ MDIO_45 â'" This token defines an MDIO device that adheres to IEEE 802.3ae Clause 45 (10G MDIO) â'¢ SPI â'" This token defines a SPI device , Configuring the PC-I2C Board 4 4.5 MDIO Operation , 4.5 MDIO Operation 4.5.1 MDIO Support PC-I2C supports and has been tested for IEEE 802.3 serial
Future Designs
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MDIO clause 45

Abstract: MDIO clause 22 (XAUI) Management data input/output (MDIO) master interface for PHY device management 64 , -Gbps Ethernet MAC XGMII Interface 10-Gbps Ethernet MAC 10-Gbps Ethernet PHY Device MDIO , Application Avalon-ST Interface Altera FPGA MDIO Master Verification Altera verified the 10 , reference design: Register access Management data input and output (MDIO) access Frame , and Resource Utilization-Stratix II GX Device XAUI FIFO (eightbyte words) MDIO
Altera
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AN-516-2 MDIO clause 22 verilog code for 10 gb ethernet fpga vhdl code for crc-32 verilog code CRC generated ethernet packet 10 Gbps ethernet phy avalon mm vhdl IP-10GETHERNET

IBM thinkpad r51

Abstract: lcx125 implemented to conform with IEEE 802.2ae-2002 MDC/MDIO Clause 45. On the evaluation board the MDIO address , Configuration and Control Jumpers MDIO Interface JTAG Interface DDR Parallel Interface Onboard Oscillator , synchronize remote base station RE modules to the REC. The SCAN25100 is programmable though an MDIO , Flexible pin and MDIO configurability Advanced testability features IEEE 1149.1 and 1149.6 At-speed BIST , 1.8V Supply regulation Buffered Parallel Port interface to internal MDIO registers Access to all
National Semiconductor
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IBM thinkpad r51 lcx125 ibm thinkpad board diagram x31 thinkpad r51 ibm thinkpad board diagram ibm thinkpad board x31
Abstract: 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL compatible, not 1.2V signal compatible. LOOP [0] 0 1 , TIMING SPECIFICATIONS (Clause 45) fMDC tS-MDIO tH-MDIO tD-MDIO tX-MDIO MDC Frequency Setup Time Hold Time , networks. The SCAN25100 is programmable though an MDIO interface as well as through pins, featuring , Diagram Rate Select etc. Pin Control Pattern Generator Input FIFO REFCLK (30.72 MHz) MDIO Link , 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 Texas Instruments
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SNLS223C

mimo antenna

Abstract: configuration bus. Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL compatible, not , ns Between 20% and 80% levels 0.1 0 MDC/MDIO TIMING SPECIFICATIONS (Clause 45) MDIO (input , disabled. LOOP [1] 0 0 1 1 MDC/MDIO 30 31 37 36 35 34 33 45 41 44 43 46 83 84 POWER 9, 15, 20, AVDD18 32 , complexity of external clock networks. The SCAN12100 is programmable though an MDIO interface as well as , ) MDIO Link Status (Lock, LOS, LOF, etc.) Configuration (Loopback, Rate, BIST, etc.) Delay Calibration
Texas Instruments
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mimo antenna SNLS245E
Abstract: IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL compatible, not 1.2V signal compatible , (Clause 45) fMDC MDC Frequency tS-MDIO Setup Time MDIO (input) valid to MDC rising clock , SCAN25100 is programmable though an MDIO interface as well as through pins, featuring configurable , etc. MDIO Link Status (Lock, LOS, LOF, etc.) Configuration (Loopback, Rate, BIST, etc.) Delay , 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 Texas Instruments
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Abstract: bus. Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL compatible, not , ps p-p 0.3 ns MDC/MDIO TIMING SPECIFICATIONS (Clause 45) (8) (9) (10) (11) 10 , though an MDIO interface as well as through pins, featuring configurable transmitter de-emphasis , '" REVISED MAY 2008 www.ti.com Block Diagram Rate Select etc. MDIO RXCLK CDR Clock Line , 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 38 PIN 101 88 37 89 DAP Texas Instruments
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SNLS245D
Abstract: on Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL ADDR pins , ps p-p 0.1 0.3 ns 0 2.5 MHz 40 MDC/MDIO TIMING SPECIFICATIONS (Clause 45) f , programmable though an MDIO interface as well as through pins, featuring configurable transmitter de , GND 47 AVDD18 80 46 TRSTB 81 45 TDI 82 44 TMS 43 TCK RES2 , 32 AVDD18 RESETB 95 31 MDIO SPMODE[0] 96 97 30 MDC 29 PVDD33 28 -
OCR Scan

BTS 5010

Abstract: MDIO clause 45 on Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL ADDR pins , ns 0 2.5 MHz 40 MDC/MDIO TIMING SPECIFICATIONS (Clause 45) fMDC MDC Frequency , SCAN25100 is programmable though an MDIO interface as well as through pins, featuring configurable , Internal Pulling both pins low enables MDIO control, default is no de-emphasis. pull down PE1 PE0 0 , . LVCMOS Internal Pulling both pins low enables MDIO control, default is no receive equalization. pull
National Semiconductor
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BTS 5010 ask transmiter remote transmiter 802.3ae MDIO

HF RFID loop antenna design

Abstract: MDIO clause 45 MDC/MDIO configuration bus. Internal pull up on Protocol per IEEE 802.2ae-2002 MDC/MDIO Clause 45 , 40 60 65 0.3 % ps p-p ns MDC/MDIO TIMING SPECIFICATIONS (Clause 45) fMDC tS-MDIO tH-MDIO tD-MDIO , back mode 99 100 LOOP [0] LOOP [1] MDC/MDIO 30 31 37 36 35 34 33 45 41 44 43 46 83 84 POWER 9 , networks. The SCAN25100 is programmable though an MDIO interface as well as through pins, featuring , both pins low enables MDIO control, default is no de-emphasis. pull down PE1 PE0 0 0 1 1 0 1 0 1 No
National Semiconductor
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HF RFID loop antenna design SNLS223B SCAN251002457

MDIO clause 45

Abstract: 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL compatible, not 1.2V signal compatible. LOOP [0] 0 1 , TIMING SPECIFICATIONS (Clause 45) fMDC tS-MDIO tH-MDIO tD-MDIO tX-MDIO MDC Frequency Setup Time Hold Time , networks. The SCAN25100 is programmable though an MDIO interface as well as through pins, featuring , Diagram Rate Select etc. Pin Control Pattern Generator Input FIFO REFCLK (30.72 MHz) MDIO Link , 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83
Texas Instruments
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Abstract: IEEE 802.2ae-2002 MDC/MDIO Clause 45. These pins are 3.3V LVTTL compatible, not 1.2V signal compatible , (Clause 45) fMDC MDC Frequency tS-MDIO Setup Time MDIO (input) valid to MDC rising clock , SCAN25100 is programmable though an MDIO interface as well as through pins, featuring configurable , etc. MDIO Link Status (Lock, LOS, LOF, etc.) Configuration (Loopback, Rate, BIST, etc.) Delay , 51 50 76 49 77 48 78 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 Texas Instruments
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MDIO clause 45

Abstract: SCAN25100 2.5 MHz 40 MDC/MDIO TIMING SPECIFICATIONS (Clause 45) fMDC MDC Frequency tS-MDIO , Clause 45. These pins are 3.3V LVTTL ADDR pins compatible, not 1.2V signal compatible. IEEE 1149.1 , though an MDIO interface as well as through pins, featuring configurable transmitter deemphasis , low enables MDIO control, default is no de-emphasis. pull down PE1 PE0 0 1 Low de-emphasis , both pins low enables MDIO control, default is no receive equalization. pull down EQ1 EQ0 0 0
National Semiconductor
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K28-1 NSC crystal 30.72MHz remote control rx tx MDIO MDC
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