MCF5282UMAD MCF5282 MCF5282UM E6-E11 F7-F10 L7-L10 M6-M11 G7-G10 H7-H10 J7-J10 - Datasheet Archive

 

Errata MCF5282UMAD Rev. 5, 3/2004 Freescale Semiconductor, Inc. Errata to the MCF5282 ColdFire Microcontroller User's Manual This

 

Freescale Semiconductor, Inc. Errata MCF5282UMAD MCF5282UMAD Rev. 5, 3/2004 Freescale Semiconductor, Inc. Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual This errata describes corrections to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual, Motorola document order number MCF5282UM MCF5282UM. For convenience, the addenda items are grouped by revision. Please check the world wide web at http://motorola.com/semiconductors for the latest updates. 1 Errata for Next Revision 10.3.2/10-8 Add the following note: `If an interrupt source is being masked in the interrupt controller mask register (IMR) or a module's interrupt mask register while the interrupt mask in the status register (SR[I]) is set to a value lower than the interrupt's level, a spurious interrupt may occur. This is because by the time the status register acknowledges this interrupt, the interrupt has been masked. A spurious interrupt is generated because the CPU cannot determine the interrupt source. To avoid this situation for interrupts sources with levels 1-6, first write a higher level interrupt mask to the status register, before setting the mask in the IMR or the module's interrupt mask register. After the mask is set, return the interrupt mask in the status register to its previous value. Since level seven interrupts cannot be disabled in the status register prior to masking, use of the IMR or module interrupt mask registers to disable level seven interrupts is not recommended.' 25.4.10/25-16 Change CANICR to ICRn. Table 25-17/25-29 Add the following information to BITERR and ACKERR descriptions: "To clear this bit, first read it as a one, then write it as a one. Writing zero has no effect." Table 25-17/25-30 Change bit ordering: ERRINT should be bit 2 and BOFFINT should be bit 1. Table 25-19/25-32 Change BUFnI field description from "To clear an interrupt flag, first read the flag as a one, then write it as a zero" to "To clear an interrupt flag, first read the flag as a one, then write it as a one." For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Errata to Revision 2.0 2 Errata to Revision 2.0 Table 33-8/33-9 3 Reference to `TA = TL to TH' was not deleted. Delete. Errata to Revision 1.0 Change `Real time debug support, with two user-visible hardware breakpoint registers' To `Real time debug support, with one user-visible hardware breakpoint register' Table 2-2/2-7 Freescale Semiconductor, Inc. 1.1/1-1 Change the I field description to read: "Interrupt level mask. Defines the current interrupt level. Interrupt requests are inhibited for all priority levels less than or equal to the current level, except the edge-sensitive level 7 request, which cannot be masked." Table 5-1/5-2 Replace the description of PRI1 and PRI2 with the following: Description Priority bit. PRI1 determines if DMA or CPU has priority in upper 32K bank of memory. PRI2 determines if DMA or CPU has priority in lower 32K bank of memory. If bit is set, DMA has priority. If bit is reset, CPU has priority. Priority is determined according to the following table. PRI[1:2] Upper Bank Priority Lower Bank Priority 00 DMA Accesses DMA Accesses 01 10 DMA Accesses CPU Accesses CPU Accesses DMA Accesses 11 CPU Accesses CPU Accesses NOTE: The Motorola-recommended setting for the priority bits is 00. Table 5-1/5-3 2 Add the following note to the SPV bit description: "The BDE bit in the second RAMBAR register must also be set to allow dual port access to the SRAM. For more information, see Section 8.4.2, `Memory Base Address Register (RAMBAR).'" Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Errata to Revision 1.0 Figure 6-2/6-4 Replace Figure 6-2, "CFM 512K Array Memory Map," with the figure below. Logical Block 1 (256 Kbytes) 0x0007 FFFF Flash Physical Block 2 Flash Physical Block 3 2H[31] 2H[1] 3H[0] 3L[0] 0x0004 0000 2H[0] Memory Array 2L Memory Array 3H Memory Array 3L 2H[0] 2L[0] 3H[0] 3L[0] 2L[1] 0x0004 0004 3L[31] 3L[1] 0x0004 0008 Freescale Semiconductor, Inc. 3H[1] 3H[31] Memory Array 2H 0x0004 000C 2L[31] 2L[0] 0x0003 FFFF Logical Block 0 (256 Kbytes) Flash Physical Block 0 Flash Physical Block 1 0H[31] Configuration Field (0x0000_0400­ 0x0000_0417) 0x0000 000C 1H[1] 1L[1] 0x0000 0008 0H[1] 1H[1] 1L[1] 0x0000 0000 0H[0] 1H[31] 1L[31] Memory Array 0H Memory Array 0L Memory Array 1H Memory Array 1L 0H[0] 0L[0] 1H[0] 1L[0] 0L[1] 0x0000 0004 0L[31] 0L[0] Each memory array = 64 Kbytes (16 bits wide × 32K) Each physical block = 128 Kbytes (32 bits wide × 32K) Figure 6-2. CFM 512K Array Memory Map Table 6-12/6-16 Change value for page erase verify command to 0x06. Table 6-13/6-20 Change value for page erase verify command to 0x06. Table 8-3/8-5 Add the following note the BDE bit description: "The SPV bit in the CPU's RAMBAR must also be set to allow dual port access to the SRAM. For more information, see Section 5.3.1, `SRAM Base Address Register (RAMBAR).'" Figure 9-1/9-3 Remove ÷ 2 from CLKGEN block. 10.3.6/10-11 Add this text to the end of the first paragraph: "If a specific interrupt request is completely unused, the ICRnx value can remain in its reset (and disabled) state." 10.5/10-17 Add the following note: "The wakeup mask level taken from LPICR[6:4] is adjusted by hardware to allow a level 7 IRQ to generate a wakeup. That is, the wakeup mask value used by the interrupt controller must be in the range of 0­6." MOTOROLA Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com 3 Freescale Semiconductor, Inc. Errata to Revision 1.0 Figure 12-4/12-8 Change CSCRn to reflect that AA is set at reset, as in the figure below. 15 14 13 10 9 Field - WS - Reset: CSCR0 - 11_11 8 - Reset: Other CSCRs 7 6 5 4 3 2 AA PS1 PS0 BEM BSTR BSTW 1 D19 D18 - 0 - - Uninitialized R/W R/W Address 0x08A (CSCR0); 0x096 (CSCR1); 0x0A2 (CSCR2); 0x0AE (CSCR3); 0x0BA (CSCR4); 0x0C6 (CSCR5); 0x0D2 (CSCR6) Figure 12-4. Chip Select Control Registers (CSCRn) Freescale Semiconductor, Inc. 13.5/13-15 Remove final paragraph. The paragraph incorrectly states that the MCF5282 MCF5282 does not have a bus monitor. Table 14-3/14-11 Change `Internal Pull-Up' column to pull-up indications in the table below. Table 14-3. MCF5282 MCF5282 Signals and Pin Numbers Sorted by Function Pin Functions MAPBGA Pin Description Primary 2 Secondary Tertiary Internal Primary Pull-up I/O 1 Reset R11 RSTI - - Reset in I Yes P11 RSTO - - Reset out O - Clock T8 EXTAL - - External clock/crystal in I - R8 XTAL - - Crystal drive O - N7 CLKOUT - - Clock out O - Chip Configuration/Mode Selection R14 CLKMOD0 - - Clock mode select I Yes T14 CLKMOD1 - - Clock mode select I Yes T11 RCON - - Reset configuration enable I Yes H1 D26 PA2 - Chip mode I/O - K2 D17 PB1 - Chip mode I/O - K3 D16 PB0 - Chip mode I/O - J4 D19 PB3 - Boot device/data port size I/O - K1 D18 PB2 - Boot device/data port size I/O - J2 D21 PB5 - Output pad drive strength I/O - O Yes External Memory Interface and Ports C6:B6:A5 4 A[23:21] PF[7:5] CS[6:4] Address bus Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Errata to Revision 1.0 Table 14-3. MCF5282 MCF5282 Signals and Pin Numbers Sorted by Function (continued) Pin Functions MAPBGA Pin Description Internal Primary Pull-up I/O 1 Secondary Tertiary C4:B4:A4:B3:A3 A[20:16] PF[4:0] - Address bus O Yes A2:B1:B2:C1: C2:C3:D1:D2 A[15:8] PG[7:0] - Address bus O Yes D3:D4:E1:E2: E3:E4:F1:F2 A[7:0] PH[7:0] - Address bus O Yes F3:G1:G2:G3: G4:H1:H2:H3 Freescale Semiconductor, Inc. Primary 2 D[31:24] PA[7:0] - Data bus I/O - H4:J1:J2:J3: J4:K1:K2:K3 D[23:16] PB[7:0] - Data bus I/O - L1:L2:L3:L4: M1:M2:M3:M4 D[15:8] PC[7:0] - Data bus I/O - N1:N2:N3:P1: N5:T6:R6:P6 D[7:0] PD[7:0] - Data bus I/O - P14:T15:R15:R16 BS[3:0] PJ[7:4] - Byte strobe I/O Yes N16 OE PE7 - Output enable I/O - P16 TA PE6 - Transfer acknowledge I/O Yes P15 TEA PE5 - Transfer error acknowledge I/O Yes N15 R/W PE4 - Read/write I/O Yes N14 SIZ1 PE3 SYNCA Transfer size I/O Yes 3 M16 SIZ0 PE2 SYNCB Transfer size I/O Yes 4 M15 TS PE1 SYNCA Transfer start I/O Yes M14 TIP PE0 SYNCB Transfer in progress I/O Yes Chip Selects L16:L15:L14:L13 CS[3:0] PJ[3:0] - Chip selects 3-0 I/O Yes C6:B6:A5 A[23:21] PF[7:5] CS[6:4] Chip selects 6-4 O Yes SDRAM Controller H15 SRAS PSD5 - SDRAM row address strobe I/O - H16 SCAS PSD4 - SDRAM column address strobe I/O - G15 DRAMW PSD3 - SDRAM write enable I/O - H13:G16 SDRAM_CS[1:0] PSD[2:1] - SDRAM chip selects I/O - H14 SCKE PSD0 - SDRAM clock enable I/O - I/O - External Interrupts Port B15:B16:C14:C15: C16: D14:D15 MOTOROLA IRQ[7:1] PNQ[7:1] - External interrupt request Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com 5 Freescale Semiconductor, Inc. Errata to Revision 1.0 Table 14-3. MCF5282 MCF5282 Signals and Pin Numbers Sorted by Function (continued) Pin Functions MAPBGA Pin Description Primary 2 Secondary Tertiary Internal Primary Pull-up I/O 1 Ethernet EMDIO PAS5 URXD2 Management channel serial data I/O - B10 EMDC PAS4 UTXD2 Management channel clock I/O - A8 ETXCLK PEH7 - MAC Transmit clock I/O - D6 ETXEN PEH6 - MAC Transmit enable I/O - D7 ETXD0 PEH5 - MAC Transmit data I/O - B11 ECOL PEH4 - MAC Collision I/O - A10 ERXCLK PEH3 - MAC Receive clock I/O - C8 ERXDV PEH2 - MAC Receive enable I/O - D9 ERXD0 PEH1 - MAC Receive data I/O - A11 ECRS PEH0 - MAC Carrier sense I/O - A7:B7:C7 ETXD[3:1] PEL[7:5] - MAC Transmit data I/O - D10 ETXER PEL4 - MAC Transmit error I/O - A9:B9:C9 ERXD[3:1] PEL[3:1] - MAC Receive data I/O - B8 Freescale Semiconductor, Inc. C10 ERXER PEL0 - MAC Receive error I/O - FlexCAN D16 CANRX PAS3 URXD2 FlexCAN Receive data I/O - E13 CANTX PAS2 UTXD2 FlexCAN Transmit data I/O - I2C E14 SDA PAS1 URXD2 I2C Serial data I/O Yes 5 E15 SCL PAS0 UTXD2 I2C Serial clock I/O Yes 6 QSPI F13 PQS0 - QSPI data out I/O - E16 QSPI_DIN PQS1 - QSPI data in I/O - F14 QSPI_CLK PQS2 - QSPI clock I/O - G14:G13:F16:F15 6 QSPI_DOUT QSPI_CS[3:0] PQS[6:3] - QSPI chip select I/O - Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Errata to Revision 1.0 Table 14-3. MCF5282 MCF5282 Signals and Pin Numbers Sorted by Function (continued) Pin Functions MAPBGA Pin Description Primary 2 Secondary Tertiary Internal Primary Pull-up I/O 1 UARTs URXD1 PUA3 - U1 receive data I/O - P7 UTXD1 PUA2 - U1 transmit data I/O - N6 URXD0 PUA1 - U0 receive data I/O - T7 UTXD0 PUA0 - U0 transmit data I/O - C10 Freescale Semiconductor, Inc. R7 EMDIO PAS5 URXD2 U2 receive data I/O - B10 EMDC PAS4 UTXD2 U2 transmit data I/O - D16 CANRX PAS3 URXD2 U2 receive data I/O - E13 CANTX PAS2 UTXD2 U2 transmit data I/O - E14 SDA PAS1 URXD2 U2 receive data I/O Yes5 E15 SCL PAS0 UTXD2 U2 transmit data I/O Yes6 K16 DTIN3 PTC3 URTS1/ URTS0 U1/U0 Request to Send I/O - K15 DTOUT3 PTC2 URTS1/ URTS0 U1/U0 Request to Send I/O - K14 DTIN2 PTC1 UCTS1/ UCTS0 U1/U0 Clear to Send I/O - K13 DTOUT2 PTC0 UCTS1/ UCTS0 U1/U0 Clear to Send I/O - J16 DTIN1 PTD3 URTS1/ URTS0 U1/U0 Request to Send I/O - J15 DTOUT1 PTD2 URTS1/ URTS0 U1/U0 Request to Send I/O - J14 DTIN0 PTD1 UCTS1/ UCTS0 U1/U0 Clear to Send I/O - J13 DTOUT0 PTD0 UCTS1/ UCTS0 U1/U0 Clear to Send I/O - General Purpose Timers T13:R13:P13:N13 GPTA[3:0] PTA[3:0] - Timer A IC/OC/PAI I/O Yes T12:R12:P12:N12 GPTB[3:0] PTB[3:0] - Timer B IC/OC/PAI I/O Yes N14 SIZ1 PE3 SYNCA Timer A synchronization input I/O Yes3 M16 SIZ0 PE2 SYNCB Timer B synchronization input I/O Yes4 M15 TS PE1 SYNCA Timer A synchronization input I/O Yes M14 TIP PE0 SYNCB Timer B synchronization input I/O Yes MOTOROLA Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com 7 Freescale Semiconductor, Inc. Errata to Revision 1.0 Table 14-3. MCF5282 MCF5282 Signals and Pin Numbers Sorted by Function (continued) Pin Functions MAPBGA Pin Description Primary 2 Secondary Tertiary Internal Primary Pull-up I/O 1 DMA Timers DTIN3 PTC3 URTS1/ URTS0 Timer 3 in I/O - K15 DTOUT3 PTC2 URTS1/ URTS0 Timer 3 out I/O - K14 DTIN2 PTC1 UCTS1/ UCTS0 Timer 2 in I/O - K13 DTOUT2 PTC0 UCTS1/ UCTS0 Timer 2 out I/O - J16 DTIN1 PTD3 URTS1/ URTS0 Timer 1 in I/O - J15 DTOUT1 PTD2 URTS1/ URTS0 Timer 1 out I/O - J14 DTIN0 PTD1 UCTS1/ UCTS0 Timer 0 in I/O - J13 Freescale Semiconductor, Inc. K16 DTOUT0 PTD0 UCTS1/ UCTS0 Timer 0 out I/O - Queued Analog-to-Digital Converter (QADC) T3 AN0 PQB0 ANW Analog channel 0 I/O - R2 AN1 PQB1 ANX Analog channel 1 I/O - T2 AN2 PQB2 ANY Analog channel 2 I/O - R1 AN3 PQB3 ANZ Analog channel 3 I/O - R4 AN52 PQA0 MA0 Analog channel 52 I/O - T4 AN53 PQA1 MA1 Analog channel 53 I/O - P3 AN55 PQA3 ETRIG1 Analog channel 55 I/O - R3 AN56 PQA4 ETRIG2 Analog channel 56 I/O - P4 VRH - - High analog reference I - T5 VRL - - Low analog reference I - Debug and JTAG Test Port Control R9 - - JTAG Enable I - P9 DSCLK TRST - Debug clock / TAP reset I Yes 7 T9 TCLK - - TAP clock I Yes7 P10 BKPT TMS - Breakpoint/TAP test mode select I Yes7 R10 8 JTAG_EN DSI TDI - Debug data in / TAP data in I Yes7 Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Errata to Revision 1.0 Table 14-3. MCF5282 MCF5282 Signals and Pin Numbers Sorted by Function (continued) Pin Functions MAPBGA Pin Description Internal Primary Pull-up I/O 1 Primary 2 Secondary Tertiary T10 DSO TDO - Debug data out / TAP data out O - C12:D12:A13:B13 DDATA[3:0] PDD[7:4] - Debug data I/O - C13:A14:B14:A15 PST[3:0] PDD[3:0] - Processor status data I/O - Test mode pin I - Test N10 TEST - Freescale Semiconductor, Inc. Power Supplies R5 VDDA - - Analog positive supply I - P5:T1 VSSA - - Analog ground I - P2 VDDH - - ESD positive supply I - N8 VDDPLL - - PLL positive supply I - P8 VSSPLL - - PLL ground I - A6:C11 VPP - - Flash (stress) programming voltage I - A12:C5:D5:D11 VDDF - - Flash positive supply I - B5:B12: VSSF - - Flash module ground I - N11 VSTBY - - Standby power I - E6-E11 E6-E11:F5:F7-F10 F7-F10: F12:G5:G6:G11: G12:H5:H6:H11: H12:J5:J6:J11:J12: K5:K6:K11:K12:L5: L7-L10 L7-L10:L12: M6-M11 M6-M11 VDD - - Positive supply I - A1:A16:E5:E12:F6: F11:G7-G10 G7-G10:H7-H10 H7-H10 :J7-J10 J7-J10:K7-K10 K7-K10:L6: L11:M5:M12:T16 VSS - - Ground I - 1 2 3 4 5 6 7 Pull-ups are not active when GPIO functions are selected for the pins. The primary functionality of a pin is not necessarily its default functionality. Pins that have GPIO functionality will default to GPIO inputs. Pull-up is active only with the SYNCA function. Pull-up is active only with the SYNCB function. Pull-up is active only with the SDA function. Pull-up is active only with SCL function. Pull-up is active when JTAG_EN is driven high. MOTOROLA Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com 9 Freescale Semiconductor, Inc. Errata to Revision 1.0 Table 17-13/17-26 Change encodings for bits 31­9 to: 0 1 The corresponding interrupt source is masked. The corresponding interrupt source is not masked. Chapter 19 Change PIT1­PIT4 to PIT0­PIT3 throughout chapter. When a timer is referenced individually, PIT1 should be PIT0, PIT2 should be PIT1, PIT3 should be PIT2, and PIT4 should be PIT3. Other chapters in the user's manual use the correct nomenclature: PIT0­PIT3. 19.6.3/19-7 Change timeout period equation to the equation below. Freescale Semiconductor, Inc. PRE[3:0] × (PM[15:0] + 1) × 2 Timeout period = -system clock Figure 23-11 Change UISR bits 5­3 to reserved bits, as in the figure below. 7 6 3 2 1 0 UIMR Field COS - DB FFULL/RxRDY TxRDY UISR Field COS - DB FFULL/RxRDY TxRDY Reset 0000_0000 R/W Read only for status, write only for mask Address IPSBAR + 0x214 (UISR0), 0x254 (UISR1), 0x294 (UISR2) Figure 23-11. UART Interrupt Status/Mask Registers (UISRn/UIMRn) 24.6.1/24-11 Change `I2CR = 0xA' to `I2CR = 0xA0.' 27.2.1/27-2 Change `When interfacing to 16-bit ports, the port C and D pins and PJ[7:6] (BS[3:2]) can be configured as general-purpose input/output (I/O)' To `When interfacing to 16-bit ports, the port C and D pins and PJ[5:4] (BS[1:0]) can be configured as general-purpose input/output (I/O)' 32.2/32-7 Added additional device number order information to Table 32-2. Table 32-2. Orderable Part Numbers Motorola Part Number Description Speed Temperature MCF5280CVF66 MCF5280CVF66 MCF5280 MCF5280 RISC Microprocessor, 256 MAPBGA 66.67 MHz -40° to +85° C MCF5280CVF80 MCF5280CVF80 MCF5280 MCF5280 RISC Microprocessor, 256 MAPBGA 80 MHz -40° to +85° C MCF5281CVF66 MCF5281CVF66 MCF5281 MCF5281 RISC Microprocessor, 256 MAPBGA 66.67 MHz -40° to +85° C MCF5281CVF80 MCF5281CVF80 MCF5281 MCF5281 RISC Microprocessor, 256 MAPBGA 80 MHz -40° to +85° C MCF5282CVF66 MCF5282CVF66 MCF5282 MCF5282 RISC Microprocessor, 256 MAPBGA 66.67 MHz -40° to +85° C MCF5282CVF80 MCF5282CVF80 MCF5282 MCF5282 RISC Microprocessor, 256 MAPBGA 80 MHz -40° to +85° C Chapter 33 10 Delete references to `TA = TL to TH'. Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Errata to Revision 1.0 Table 33-1/33-1 Replace Vin row with the row below, in which the maximum value has been changed to 6.0 V. Table 33-1Absolute Maximum Ratings Rating Symbol Table 33-6/33-8 Unit VIN Digital Input Voltage Value ­ 0.3 to + 6.0 V Replace IDDA row with the row below, in which the maximum value in normal operation has been changed to 5.0 mA. Table 33-6 Electrical Specifications (Operating) Freescale Semiconductor, Inc. Parameter Symbol Figure 33-5/33-16 Max Unit - - Analog Supply Current Normal Operation Low-Power Stop Min 5.0 10.0 mA µA IDDA Replace Figure 33-5, `SDRAM Read Cycle' with the figure below. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLKOUT D3 D1 A[23:0] Row Column D4 SRAS D2 SCAS 1 D4 DRAMW D5 D[31:0] D6 SDRAM_CS[1:0] D4 BS[3:0] ACTV 1 DACR[CASL] NOP READ NOP PRE =2 Figure 33-5. SDRAM Read Cycle MOTOROLA Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com 11 Freescale Semiconductor, Inc. Revision History 4 Revision History Table 1 provides a revision history for this document. Table 1. Revision History Table Rev. Number Substantive Changes Date of Release 7/2003 Added page erase verify errata for Chapter 6, "ColdFire Flash Module (CFM)." 9/2003 2 · · · · Added errata for UART interrupt status register. Added errata for PIT timer timeout equation. Added I2CR write errata. Added errata for `Internal Pull-Up' column in `MCF5282 MCF5282 Signals and Pin Numbers Sorted by Function' table. · Added errata for "SDRAM Read Cycle' figure. 11/2003 3 · Added errata for Chapter 19. PIT1­PIT4 should be PIT0­PIT3. 1/2004 4 · Added errata for spurious interrupt. · Added errata for Table 33-8. Single instance of TA = TL to TH was overlooked in revision 2.0 of the manual. This instance has now been removed. 3/2004 5 12 Initial release. 1 Freescale Semiconductor, Inc. 0 · · · · 3/2004 Added errata for Section 25.4.10: change CANICR to ICRn. Added errata for BITERR and ACKERR field descriptions. Added errata for BOFFINT and ERRINT bit sequence. Added errata for BUFnI field description. Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Revision History Freescale Semiconductor, Inc. THIS PAGE INTENTIONALLY LEFT BLANK MOTOROLA Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com 13 Freescale Semiconductor, Inc. Revision History Freescale Semiconductor, Inc. THIS PAGE INTENTIONALLY LEFT BLANK 14 Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. Revision History Freescale Semiconductor, Inc. THIS PAGE INTENTIONALLY LEFT BLANK 15 Errata to the MCF5282 MCF5282 ColdFire Microcontroller User's Manual For More Information On This Product, Go to: www.freescale.com MOTOROLA Freescale Semiconductor, Inc. HOW TO REACH US: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 1-800-521-6274 or 480-768-2130 JAPAN: Motorola Japan Ltd. SPS, Technical Information Center 3-20-1, Minami-Azabu Minato-ku Tokyo, 106-8573 Japan 81-3-3440-3569 Freescale Semiconductor, Inc. ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd. Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong 852-26668334 HOME PAGE: http://motorola.com/semiconductors Information in this document is provided solely to enable system and software implementers to use Motorola products. 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