MCF5275 MCF5274 MCF5274L MCF5275L MCF5275RM/D CH370 QCR15 - Datasheet Archive

 

Devices Supported: MCF5274 MCF5274L MCF5275 MCF5275L MCF5275RM/D Rev. 1 08/2004 How to Reach Us: Home Page: www.freescale.com

 

MCF5275 MCF5275 Reference Manual Devices Supported: MCF5274 MCF5274 MCF5274L MCF5274L MCF5275 MCF5275 MCF5275L MCF5275L MCF5275RM/D MCF5275RM/D Rev. 1 08/2004 How to Reach Us: Home Page: www.freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 CH370 1300 N. Alma School Road Chandler, Arizona 85224 1-800-521-6274 or 480-768-2130 Europe, Middle East, and Africa: +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Japan: Freescale Semiconductor Japan Ltd. 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MCF5275RM/D MCF5275RM/D Rev. 1 08/2004 Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) Clock Module Power Management Chip Configuration Module (CCM) Reset Controller Module System Control Module (SCM) General Purpose I/O Module Interrupt Controller Modules DMA Controller Module Edge Port Module (EPORT) Chip Select Module External Interface Module (EIM) Synchronous DRAM Controller Fast Ethernet Controller (FEC) Universal Serial Bus Device (USB) PWM Module Watchdog Timer Module Programmable Interrupt Timers (PITs) DMA Timers Queued Serial Peripheral Interface (QSPI) UART Modules I2C interface Message Digest Hardware Accelerator (MDHA) Random Number Generator (RNG) Symmetric Key Hardware Accelerator (SKHA) IEEE 1149.1 Test Access Port (JTAG) Debug Support Register Memory Map Quick Reference Index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A IND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A IND Overview Signal Descriptions ColdFire Core Enhanced Multiply-Accumulate Unit (EMAC) Cache Static RAM (SRAM) Clock Module Power Management Chip Configuration Module (CCM) Reset Controller Module System Control Module (SCM) General Purpose I/O Module Interrupt Controller Modules DMA Controller Module Edge Port Module (EPORT) Chip Select Module External Interface Module (EIM) Synchronous DRAM Controller Fast Ethernet Controllers (FEC0 & FEC1) Universal Serial Bus Device (USB) PWM Module Watchdog Timer Module Programmable Interrupt Timers (PITs) DMA Timers Queued Serial Peripheral Interface (QSPI) UART Modules I2C interface Message Digest Hardware Accelerator (MDHA) Random Number Generator (RNG) Symmetric Key Hardware Accelerator (SKHA) IEEE 1149.1 Test Access Port (JTAG) Debug Support Register Memory Map Quick Reference Index Contents Paragraph Number Title Page Number Chapter 1 Overview 1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.5.1 1.3.5.2 1.3.6 1.3.7 1.3.8 1.3.9 1.3.10 1.3.11 1.3.12 1.3.13 1.3.14 1.3.15 1.3.16 1.3.17 1.3.18 1.3.19 1.3.20 1.3.21 1.3.22 1.4 MCF5275 MCF5275 Family Configurations. 1-1 Block Diagram . 1-2 Features . 1-4 Feature Overview. 1-4 V2 Core Overview . 1-8 Integrated Debug Module . 1-8 JTAG. 1-9 On-chip Memories . 1-9 Cache . 1-9 SRAM . 1-10 Fast Ethernet Controller (FEC). 1-10 Universal Serial Bus (USB). 1-10 UARTs . 1-10 I2C Bus. 1-10 QSPI. 1-11 Cryptography . 1-11 DMA Timers (DTIM0-DTIM3) . 1-11 Pulse Width Modulation (PWM) Module . 1-11 Periodic Interrupt Timers (PIT0-PIT3). 1-11 Software Watchdog Timer. 1-12 Clock Module and Phase Locked Loop (PLL) . 1-12 Interrupt Controllers (INTC0, INTC1) . 1-12 DMA Controller. 1-12 External Interface Module (EIM) . 1-12 Double Data Rate (DDR) SDRAM Controller . 1-13 Reset. 1-13 GPIO . 1-13 Documentation. 1-14 Chapter 2 Signal Descriptions 2.1 2.1.1 2.2 Introduction. 2-1 Overview. 2-1 Signal Properties Summary . 2-3 MCF5275 MCF5275 Reference Manual, Rev. 1 Freescale Semiconductor v Contents Paragraph Number 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.3.11 2.3.12 2.3.13 2.3.14 2.3.15 2.3.16 2.4 Title Page Number External Signal Descriptions . 2-8 Reset Signals. 2-8 PLL and Clock Signals . 2-9 Mode Selection . 2-9 External Memory Interface Signals . 2-9 DDR SDRAM Controller Signals. 2-11 External Interrupt Signals . 2-12 Fast Ethernet Controller Signals . 2-12 Queued Serial Peripheral Interface (QSPI). 2-14 I2C I/O SIGNALS . 2-14 UART Module Signals . 2-15 USB Signals. 2-15 DMA Timer Signals. 2-17 Pulse Width Modulator Signals . 2-17 Debug Support Signals . 2-18 Test Signals. 2-19 Power and Ground Pins . 2-20 External Boot Mode. 2-20 Chapter 3 ColdFire Core 3.1 3.2 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.1.4 3.2.1.5 3.2.2 3.2.3 3.2.3.1 3.2.3.2 3.2.3.3 3.2.3.4 3.2.3.5 3.2.3.6 3.3 3.4 3.5 Processor Pipelines . Processor Register Description . User Programming Model . Data Registers (D0­D7) . Address Registers (A0­A6). Stack Pointer (A7) . Program Counter (PC) . Condition Code Register (CCR). EMAC Register Description. Supervisor Register Description . Status Register (SR). Supervisor/User Stack Pointers (A7 and OTHER_A7). Vector Base Register (VBR) . Cache Control Register (CACR) . Access Control Registers (ACR0, ACR1). SRAM Base Address Register (RAMBAR). Memory Map/Register Definition . Additions to the Instruction Set Architecture . Exception Processing Overview . 3-1 3-2 3-2 3-2 3-3 3-3 3-3 3-4 3-4 3-5 3-6 3-7 3-7 3-7 3-8 3-8 3-8 3-9 3-9 MCF5275 MCF5275 Reference Manual, Rev. 1 vi Freescale Semiconductor Contents Paragraph Number 3.6 3.7 3.7.1 3.7.2 3.7.3 3.7.4 3.7.5 3.7.6 3.7.7 3.7.8 3.7.9 3.7.10 3.7.11 3.7.12 3.7.13 3.7.14 3.8 3.8.1 3.8.2 3.9 3.10 3.11 3.12 3.13 3.14 Title Page Number Exception Stack Frame Definition. Processor Exceptions . Access Error Exception . Address Error Exception. Illegal Instruction Exception. Divide-By-Zero. Privilege Violation. Trace Exception . Unimplemented Line-A Opcode. Unimplemented Line-F Opcode . Debug Interrupt. RTE and Format Error Exception. TRAP Instruction Exception. Interrupt Exception . Fault-on-Fault Halt . Reset Exception . Instruction Execution Timing . Timing Assumptions. MOVE Instruction Execution Times . Standard One Operand Instruction Execution Times . Standard Two Operand Instruction Execution Times. Miscellaneous Instruction Execution Times. EMAC Instruction Execution Times . Branch Instruction Execution Times . ColdFire Instruction Set Architecture Enhancements . 3-11 3-13 3-13 3-13 3-13 3-14 3-14 3-14 3-15 3-15 3-15 3-15 3-15 3-15 3-16 3-16 3-19 3-19 3-20 3-21 3-22 3-24 3-24 3-26 3-26 Chapter 4 Enhanced Multiply-Accumulate Unit (EMAC) 4.1 4.2 4.3 4.4 4.4.1 4.4.1.1 4.4.2 4.5 4.5.1 4.5.2 4.5.3 Multiply-Accumulate Unit. 4-1 Introduction to the MAC. 4-2 General Operation. 4-3 Memory Map/Register Definition . 4-6 MAC Status Register (MACSR). 4-6 Fractional Operation Mode. 4-9 Mask Register (MASK) . 4-11 EMAC Instruction Set Summary . 4-12 EMAC Instruction Execution Times . 4-13 Data Representation. 4-14 MAC Opcodes . 4-14 MCF5275 MCF5275 Reference Manual, Rev. 1 Freescale Semiconductor vii Contents Paragraph Number Title Page Number Chapter 5 Cache 5.1 5.1.1 5.1.2 5.1.3 5.1.3.1 5.1.3.2 5.1.3.3 5.1.3.4 5.1.3.5 5.2 5.2.1 5.2.1.1 5.2.1.2 Introduction. 5-1 Features. 5-1 Physical Organization . 5-1 Operation . 5-3 Interaction with Other Modules. 5-3 Memory Reference Attributes . 5-4 Cache Coherency and Invalidation. 5-4 Reset . 5-5 Cache Miss Fetch Algorithm/Line Fills . 5-5 Memory Map/Register Definition . 5-6 Registers Description. 5-7 Cache Control Register (CACR) . 5-7 Access Control Registers (ACR0, ACR1). 5-10 Chapter 6 Static RAM (SRAM) 6.1 6.1.1 6.1.2 6.2 6.2.1 6.2.2 6.2.3 6.2.4 Introduction. Features. Operation . Register Description . SRAM Base Address Register (RAMBAR). SRAM Initialization. SRAM Initialization Code . Power Management . 6-1 6-1 6-1 6-1 6-2 6-4 6-4 6-5 Chapter 7 Clock Module 7.1 7.1.1 7.1.2 7.1.3 7.1.3.1 7.1.3.2 7.1.3.3 7.1.3.4 Introduction. Block Diagram. Features. Modes of Operation . Normal PLL Mode with Crystal Reference. Normal PLL Mode with External Reference. 1:1 PLL Mode. External Clock Mode (Bypass Mode) . 7-1 7-2 7-4 7-4 7-5 7-5 7-5 7-5 MCF5275 MCF5275 Reference Manual, Rev. 1 viii Freescale Semiconductor Contents Paragraph Number 7.1.3.5 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.3 7.3.1 7.3.1.1 7.3.1.2 7.4 7.4.1 7.4.2 7.4.2.1 7.4.2.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.6.1 7.4.6.2 7.4.6.3 7.4.6.4 7.4.6.5 7.4.6.6 7.4.6.7 7.4.6.8 7.4.6.9 7.4.6.10 7.4.6.11 7.4.6.12 7.4.6.13 7.5 Title Page Number Low-power Mode Operation . 7-6 External Signal Descriptions . 7-7 EXTAL . 7-7 XTAL. 7-7 CLKOUT . 7-7 CLKMOD[1:0] . 7-7 RSTOUT. 7-8 Memory Map/Register Definition . 7-8 Register Descriptions. 7-8 Synthesizer Control Register (SYNCR) . 7-8 Synthesizer Status Register (SYNSR) . 7-11 Functional Description. 7-13 System Clock Modes . 7-13 Clock Operation During Reset. 7-14 Power-On Reset (POR). 7-14 External Reset. 7-15 System Clock Generation . 7-15 Programming the Frequency Modulation . 7-16 Frequency Modulation Depth Calibration . 7-18 PLL Operation . 7-21 Phase and Frequency Detector (PFD). 7-22 Charge Pump/Loop Filter . 7-23 Current Controlled Oscillator (ICO). 7-23 Multiplication Factor Divider (MFD). 7-23 PLL Lock Detection . 7-23 PLL Loss-of-Lock Conditions. 7-24 PLL Loss-of-Lock Reset. 7-25 PLL Loss-of-Lock Interrupt Request. 7-25 Loss-of-Clock Detection. 7-25 Loss-of-Clock Reset . 7-25 Loss-of-Clock Interrupt Request . 7-26 Alternate Clock Selection . 7-26 Loss-of-Clock in Stop Mode . 7-26 Interrupts . 7-31 Chapter 8 Power Management 8.1 8.1.1 8.2 Introduction. 8-1 Features. 8-1 Memory Map/Register Definition . 8-1 MCF5275 MCF5275 Reference Manual, Rev. 1 Freescale Semiconductor ix Contents Paragraph Number 8.2.1 8.2.1.1 8.2.1.2 8.3 8.3.1 8.3.1.1 8.3.1.2 8.3.1.3 8.3.1.4 8.3.1.5 8.3.2 8.3.2.1 8.3.2.2 8.3.2.3 8.3.2.4 8.3.2.5 8.3.2.6 8.3.2.7 8.3.2.8 8.3.2.9 8.3.2.10 8.3.2.11 8.3.2.12 8.3.2.13 8.3.2.14 8.3.2.15 8.3.2.16 8.3.2.17 8.3.2.18 8.3.2.19 8.3.2.20 8.3.2.21 8.3.2.22 8.3.2.23 8.3.3 Title Page Number Register Descriptions. 8-1 Low-Power Interrupt Control Register (LPICR). 8-2 Low-Power Control Register (LPCR) . 8-3 Functional Description. 8-4 Low-Power Modes. 8-4 Run Mode . 8-5 Wait Mode . 8-5 Doze Mode. 8-5 Stop Mode. 8-5 Peripheral Shut Down. 8-6 Peripheral Behavior in Low-Power Modes . 8-6 ColdFire Core . 8-6 Static Random-Access Memory (SRAM) . 8-6 System Control Module (SCM). 8-6 DDR SDRAM Controller (SDRAMC). 8-6 Chip Select Module . 8-7 DMA Controller (DMAC0­DMA3). 8-7 UART Modules (UART0, UART1, and UART2) . 8-7 I2C Module. 8-8 Queued Serial Peripheral Interface (QSPI). 8-8 DMA Timers (DTIM0­DTIM3). 8-8 Interrupt Controllers (INTC0, INTC1) . 8-9 Fast Ethernet Controller (FEC). 8-9 I/O Ports. 8-9 Reset Controller . 8-9 Chip Configuration Module. 8-10 Clock Module . 8-10 Edge Port . 8-10 Watchdog Timer . 8-11 Programmable Interrupt Timers (PIT0, PIT1, PIT2 and PIT3) . 8-11 USB Module . 8-11 PWM Module . 8-11 BDM . 8-11 JTAG. 8-11 Summary of Peripheral State During Low-Power Modes . 8-12 Chapter 9 Chip Configuration Module (CCM) 9.1 9.1.1 Introduction. 9-1 Block Diagram. 9-1 MCF5275 MCF5275 Reference Manual, Rev. 1 x Freescale Semiconductor Contents Paragraph Number 9.1.2 9.1.3 9.2 9.2.1 9.2.2 9.2.3 9.3 9.3.1 9.3.2 9.3.3 9.3.3.1 9.3.3.2 9.3.3.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.5 Title Page Number Features. 9-1 Modes of Operation . 9-2 External Signal Descriptions . 9-2 RCON . 9-2 CLKMOD[1:0] . 9-2 D[26:24, 21, 19:16] (Reset Configuration Override) . 9-2 Memory Map/Register Definition . 9-3 Programming Model . 9-3 Memory Map . 9-3 Register Descriptions. 9-4 Chip Configuration Register (CCR) . 9-4 Reset Configuration Register (RCON). 9-5 Chip Identification Register (CIR) . 9-7 Functional Description. 9-7 Reset Configuration . 9-7 Chip Mode Selection . 9-9 Boot Device Selection . 9-10 Output Pad Strength Configuration . 9-10 Clock Mode Selection. 9-10 Chip Select Configuration . 9-11 Reset. 9-11 Chapter 10 Reset Controller Module 10.1 10.1.1 10.1.2 10.2 10.2.1 10.2.2 10.3 10.3.1 10.3.2 10.4 10.4.1 10.4.1.1 10.4.1.2 10.4.1.3 10.4.1.4 10.4.1.5 Introduction. Block Diagram. Features. External Signal Description . RESET . RSTOUT. Memory Map/Register Definition . Reset Control Register (RCR) . Reset Status Register (RSR) . Functional Description. Reset Sources. Power-On Reset . External Reset. Watchdog Timer Reset . Loss-of-Clock Reset . Loss-of-Lock Reset. 10-1 10-1 10-1 10-2 10-2 10-2 10-2 10-2 10-3 10-4 10-4 10-5 10-5 10-5 10-5 10-6 MCF5275 MCF5275 Reference Manual, Rev. 1 Freescale Semiconductor xi Contents Paragraph Number 10.4.1.6 10.4.2 10.4.2.1 10.4.2.2 10.4.2.3 10.4.3 10.4.3.1 10.4.3.2 Title Page Number Software Reset . Reset Control Flow . Synchronous Reset Requests . Internal Reset Request . Power-On Reset . Concurrent Resets . Reset Flow . Reset Status Flags . 10-6 10-6 10-8 10-8 10-8 10-8 10-8 10-9 Chapter 11 System Control Module (SCM) 11.1 11.1.1 11.1.2 11.2 11.2.1 11.2.1.1 11.2.1.2 11.2.1.3 11.2.1.4 11.2.1.5 11.3 11.3.1 11.3.2 11.3.2.1 11.3.2.2 11.3.3 11.4 11.4.1 11.4.2 11.4.3 11.4.3.1 11.4.3.2 11.4.3.3 Introduction. 11-1 Overview. 11-1 Features. 11-1 Memory Map/Register Definition . 11-2 Register Descriptions. 11-3 Internal Peripheral System Base Address Register (IPSBAR). 11-3 Memory Base Address Register (RAMBAR) . 11-4 Core Reset Status Register (CRSR). 11-6 Core Watchdog Control Register (CWCR) . 11-7 Core Watchdog Service Register (CWSR). 11-8 Internal Bus Arbitration . 11-9 Overview. 11-10 Arbitration Algorithms . 11-10 Round-Robin Mode . 11-10 Fixed Mode. 11-11 Bus Master Park Register (MPARK). 11-11 System Access Control Unit (SACU). 11-13 Overview. 11-13 Features. 11-13 Memory Map/Register Definition . 11-14 Master Privilege Register (MPR) . 11-15 Peripheral Access Control Registers (PACR0­PACR8). 11-15 Grouped Peripheral Access Control Register (GPACR) . 11-17 Chapter 12 General Purpose I/O Module 12.1 Introduction. 12-1 MCF5275 MCF5275 Reference Manual, Rev. 1 xii Freescale Semiconductor Contents Paragraph Number 12.1.1 12.1.2 12.2 12.3 12.3.1 12.3.1.1 12.3.1.2 12.3.1.3 12.3.1.4 12.3.1.5 12.3.1.6 12.3.1.7 12.3.1.8 12.4 12.4.1 12.4.2 12.5 Title Page Number Overview. 12-3 Features. 12-3 External Signal Description . 12-3 Memory Map/Register Definition . 12-10 Register Descriptions. 12-11 Port Output Data Registers (PODR_x). 12-11 Port Data Direction Registers (PDDR_x). 12-14 Port Pin Data/Set Data Registers (PPDSDR_x) . 12-16 Port Clear Output Data Registers (PCLRR_x) . 12-19 Pin Assignment Registers (PAR_x). 12-21 Timer Pin Assignment Registers (PAR_TIMERH & PAR_TIMERL). 12-30 USB Pin Assignment Register (PAR_USB). 12-32 FEC0 & FEC1 Pin Assignment Registers (PAR_FEC0 & PAR_FEC1) 12-33 Functional Description. 12-34 Overview. 12-34 Port Digital I/O Timing. 12-35 Initialization/Application Information . 12-35 Chapter 13 Interrupt Controller Modules 13.1 13.1.1 13.1.2 13.1.2.1 13.1.2.2 13.1.2.3 13.2 13.2.1 13.2.1.1 13.2.1.2 13.2.1.3 13.2.1.4 13.2.1.5 13.2.1.6 13.2.1.7 13.3 13.4 Introduction. 13-1 68K/ColdFire Interrupt Architecture Overview . 13-1 Interrupt Controller Theory of Operation . 13-2 Interrupt Recognition. 13-3 Interrupt Prioritization . 13-3 Interrupt Vector Determination . 13-4 Memory Map/Register Definition . 13-4 Register Descriptions. 13-6 Interrupt Pending Registers (IPRHn, IPRLn). 13-6 Interrupt Mask Register (IMRHn, IMRLn). 13-8 Interrupt Force Registers (INTFRCHn, INTFRCLn). 13-10 Interrupt Request Level Register (IRLRn) . 13-11 Interrupt Acknowledge Level and Priority Register (IACKLPRn). 13-12 Interrupt Control Register (ICRnx, (x = 1, 2,., 63) . 13-12 Software and Level n IACK Registers (SWIACKR, L1IACK­L7IACK). 13-15 Prioritization Between Interrupt Controllers . 13-17 Low-Power Wakeup Operation . 13-17 MCF5275 MCF5275 Reference Manual, Rev. 1 Freescale Semiconductor xiii Contents Paragraph Number Title Page Number Chapter 14 Edge Port Module (EPORT) 14.1 14.2 14.3 14.4 14.4.1 14.4.1.1 14.4.1.2 14.4.1.3 14.4.1.4 14.4.1.5 14.4.1.6 Introduction. Low-Power Mode Operation . Interrupt/General-Purpose I/O Pin Descriptions. Memory Map/Register Definition . Register Description . EPORT Pin Assignment Register (EPPAR). EPORT Data Direction Register (EPDDR). Edge Port Interrupt Enable Register (EPIER) . Edge Port Data Register (EPDR). Edge Port Pin Data Register (EPPDR) . Edge Port Flag Register (EPFR). 14-1 14-1 14-2 14-2 14-3 14-3 14-4 14-5 14-5 14-6 14-6 Chapter 15 Chip Select Module 15.1 15.1.1 15.2 15.2.1 15.2.2 15.2.3 15.3 15.3.1 15.3.1.1 15.3.2 15.3.2.1 15.4 15.4.1 15.4.1.1 15.4.1.2 15.4.1.3 15.5 Introduction. 15-1 Overview. 15-1 External Signal Description . 15-1 Chip Selects (CS[7:0]) . 15-1 Output Enable (OE) . 15-1 Byte Strobes (BS[3:2]). 15-2 Chip Select Operation . 15-3 General Chip Select Operation . 15-3 8- and 16-Bit Port Sizing . 15-4 Enhanced Wait State Operation. 15-4 External Boot Chip Select Operation . 15-5 Memory Map/Register Definition . 15-6 Chip Select Module Registers. 15-7 Chip Select Address Registers (CSAR0­CSAR7) . 15-7 Chip Select Mask Registers (CSMR0­CSMR7) . 15-8 Chip Select Control Registers (CSCR0­CSCR7). 15-9 Code Example. 15-11 Chapter 16 External Interface Module (EIM) 16.1 Introduction. 16-1 MCF5275 MCF5275 Reference Manual, Rev. 1 xiv Freescale Semiconductor Contents Paragraph Number 16.1.1 16.2 16.3 16.4 16.5 16.5.1 16.5.2 16.5.3 16.5.4 16.5.5 16.5.6 16.5.7 16.5.7.1 16.5.7.2 16.5.7.3 16.6 16.7 Title Page Number Features. 16-1 Bus and Control Signals . 16-1 Bus Characteristics . 16-2 Bus Errors . 16-3 Data Transfer Operation . 16-3 Bus Cycle Execution. 16-4 Data Transfer Cycle States . 16-5 Read Cycle. 16-7 Write Cycle . 16-8 Fast Termination Cycles . 16-9 Back-to-Back Bus Cycles . 16-10 Burst Cycles. 16-11 Line Transfers. 16-12 Line Read Bus Cycles. 16-12 Line Write Bus Cycles. 16-14 Secondary Wait State Operation. 16-17 Misaligned Operands . 16-17 Chapter 17 SDRAM Controller (SDRAMC) 17.1 17.1.1 17.1.2 17.1.3 17.2 17.3 17.3.1 17.3.2 17.3.3 17.3.3.1 17.4 17.4.1 17.4.1.1 17.4.1.2 17.4.1.3 17.4.1.4 17.4.1.5 17.4.1.6 17.4.1.7 17.4.2 Introduction. 17-1 Features. 17-1 Terminology. 17-2 Block Diagram. 17-3 External Signal Description . 17-4 Interface Recommendations . 17-4 Supported Memory Configurations . 17-4 SDRAM Connection Block Diagram . 17-7 DDR SDRAM Layout Considerations . 17-7 Termination Example . 17-8 SDRAM Overview . 17-8 SDRAM Commands . 17-8 Activate Command (ACTV). 17-9 Read Command (READ). 17-9 Write Command (WRITE) . 17-10 Precharge All Banks Command (PALL). 17-10 Load Mode/Extended Mode Register Command (LMR, LEMR). 17-10 Auto Refresh Command (REF) . 17-12 Self Refresh (SREF) and Power Down (PDWN) Commands. 17-12 Power-Up Initialization. 17-13 MCF5275 MCF5275 Reference Manual, Rev. 1 Freescale Semiconductor xv Contents Paragraph Number 17.5 17.5.1 17.5.2 17.5.3 17.5.4 17.5.5 17.5.6 17.6 17.6.1 17.6.2 17.7 17.7.1 17.7.2 17.7.3 17.7.4 17.7.5 17.7.6 17.7.7 17.8 17.8.1 17.8.2 17.8.3 Title Page Number Memory Map/Register Definition . SDRAM Mode/Extended Mode Register (SDMR) . SDRAM Control Register (SDCR). SDRAM Configuration Register 1 (SDCFG1). SDRAM Configuration Register 2 (SDCFG2). SDRAM Base Address Registers (SDBAR0 & SDBAR1) . SDRAM Address Mask Registers (SDMR0 & SDMR1). Functional Overview. Page Management. Transfer Size . DDR SDRAM Example. SDRAM Chip Select Settings. SDRAM Configuration 1 Register Settings. SDRAM Configuration 2 Register Settings. SDRAM Control Register Settings and PALL command . Set the Extended Mode Register. Set the Mode Register and Reset DLL . Issue a PALL command. Perform Two Refresh Cycles. Clear the Reset DLL Bit in the Mode Register. Enable Automatic Refresh and Lock Mode Register . Initialization Code. 17-14 17-14 17-15 17-17 17-19 17-20 17-20 17-21 17-21 17-22 17-23 17-24 17-26 17-27 17-27 17-28 17-29 17-30 17-31 17-32 17-33 17-34 Chapter 18 DMA Controller Module 18.1 18.1.1 18.1.2 18.2 18.3 18.3.1 18.3.2 18.3.3 18.3.4 18.3.4.1 18.3.5 18.4 18.4.1 18.4.2 18.4.3 Introduction. 18-1 Overview. 18-1 Features. 18-3 DMA Transfer Overview. 18-4 Memory Map/Register Definition . 18-5 DMA Request Control (DMAREQC) . 18-6 Source Address Registers (SAR0­SAR3) . 18-7 Destination Address Registers (DAR0­DAR3) . 18-8 Byte Count Registers (BCR0­BCR3) and DMA Status Registers (DSR0­DSR3) . 18-8 DMA Status Registers (DSR0­DSR3) . 18-9 DMA Control Registers (DCR0­DCR3). 18-10 Functional Description. 18-13 Transfer Requests (Cycle-Steal and Continuous Modes) . 18-14 Dual-Address Data Transfer Mode. 18-14 Channel Initialization and Startup . 18-15 MCF5275 MCF5275 Reference Manual, Rev. 1 xvi Freescale Semiconductor Contents Paragraph Number 18.4.3.1 18.4.3.2 18.4.4 18.4.4.1 18.4.4.2 18.4.4.3 18.4.5 Title Page Number Channel Prioritization. Programming the DMA Controller Module . Data Transfer . External Request and Acknowledge Operation. Auto-Alignment. Bandwidth Control. Termination. 18-15 18-15 18-16 18-16 18-17 18-18 18-18 Chapter 19 Fast Ethernet Controllers (FEC0 & FEC1) 19.1 19.1.1 19.1.2 19.1.3 19.1.4 19.1.4.1 19.1.5 19.1.5.1 19.1.5.2 19.1.6 19.1.7 19.2 19.2.1 19.2.2 19.2.3 19.2.4 19.2.4.1 19.2.4.2 19.2.4.3 19.2.4.4 19.2.4.5 19.2.4.6 19.2.4.7 19.2.4.8 19.2.4.9 19.2.4.10 19.2.4.11 19.2.4.12 19.2.4.13 19.2.4.14 Introduction. 19-1 Overview. 19-1 Block Diagram. 19-1 Features. 19-3 Modes of Operation . 19-4 Full and Half Duplex Operation . 19-4 Interface Options. 19-4 10 Mbps and 100 Mbps MII Interface. 19-4 10 Mpbs 7-Wire Interface Operation. 19-5 Address Recognition Options . 19-5 Internal Loopback . 19-5 Memory Map/Register Definition . 19-5 High-Level Module Memory Map . 19-5 Register Memory Map . 19-6 MIB Block Counters Memory Map. 19-6 Register Description . 19-8 Ethernet Interrupt Event Register (EIR) . 19-9 Interrupt Mask Registers (EIMR0 & EIMR1). 19-10 Receive Descriptor Active Registers (RDAR0 & RDAR1) . 19-11 Transmit Descriptor Active Registers (TDAR0 & TDAR1). 19-12 Ethernet Control Registers (ECR0 & ECR1) . 19-13 MII Management Frame Registers (MMFR0 & MMFR1) . 19-14 MII Speed Control Registers (MSCR0 & MSCR1) . 19-16 MIB Control Registers (MIBC0 & MIBC1) . 19-17 Receive Control Registers (RCR0 & RCR1). 19-17 Transmit Control Registers (TCR0 & TCR1) . 19-19 Physical Address Low Registers (PALR0 & PALR1) . 19-20 Physical Address High Registers (PAUR0 & PAUR1). 19-20 Opcode/Pause Duration Registers (OPD0 & OPD1). 19-21 Descriptor Individual Upper Address Registers (IAUR0 & IAUR1). 19-22 MCF5275 MCF5275 Reference Manual, Rev. 1 Freescale Semiconductor xvii Contents Paragraph Number 19.2.4.15 19.2.4.16 19.2.4.17 19.2.4.18 19.2.4.19 19.2.4.20 19.2.4.21 19.2.4.22 19.2.4.23 19.2.5 19.2.5.1 19.2.5.2 19.2.5.3 19.3 19.3.1 19.3.1.1 19.3.2 19.3.3 19.3.4 19.3.5 19.3.6 19.3.7 19.3.8 19.3.9 19.3.10 19.3.11 19.3.12 19.3.13 19.3.14 19.3.14.1 19.3.14.2 Title Page Number Descriptor Individual Lower Address Registers (IALR0 & IALR1) . Descriptor Group Upper Address Registers (GAUR0 & GAUR1). Descriptor Group Lower Address Registers (GALR0 & GALR1) . FIFO Transmit FIFO Watermark Registers (TFWR0 & TFWR1). FIFO Receive Bound Registers (FRBR0 & FRBR1) . FIFO Receive Start Registers (FRSR0 & FRSR1) . Receive Descriptor Ring Start Registers (ERDSR0 & ERDSR1). Transmit Buffer Descriptor Ring Start Registers (ETSDR0 & ETSDR1) . Receive Buffer Size Registers (EMRBR0 & EMRBR1) . Buffer Descriptors. Driver/DMA Operation with Buffer Descriptors . Ethernet Receive Buffer Descriptors (RxBD0 & RxBD1). Ethernet Transmit Buffer Descriptors (TxBD0 & TxBD1). Functional Description. Initialization Sequence. Hardware Controlled Initialization . User Initialization (Prior to Setting ECRn[ETHER_EN]). Microcontroller Initialization. User Initialization (After Asserting ECRn[ETHER_EN]) . Network Interface Options. FEC Frame Transmission . FEC Frame Reception. Ethernet Address Recognition . Hash Algorithm. Full Duplex Flow Control. Inter-Packet Gap (IPG) Time. Collision Handling. Internal and External Loopback. Ethernet Error-Handling Procedure . Transmission Errors. Reception Errors . 19-22 19-23 19-24 19-24 19-25 19-26 19-26 19-27 19-28 19-28 19-29 19-31 19-32 19-34 19-34 19-34 19-35 19-36 19-36 19-36 19-37 19-38 19-39 19-42 19-45 19-46 19-46 19-46 19-47 19-47 19-48 Chapter 20 Universal Serial Bus 20.1 20.1.1 20.1.2 20.1.3 20.1.4 20.2 Introduction. Block Diagram. Overview. Features. Modes of Operation . External Signal Description . 20-1 20-1 20-1 20-2 20-2 20-3 MCF5275 MCF5275 Reference Manual, Rev. 1 xviii Freescale Semiconductor Contents Paragraph Number 20.2.1 20.2.2 20.2.3 20.2.4 20.2.5 20.2.6 20.2.7 20.3 20.3.1 20.3.1.1 20.3.1.2 20.3.1.3 20.3.1.4 20.3.1.5 20.3.1.6 20.3.1.7 20.3.1.8 20.3.1.9 20.3.1.10 20.3.1.11 20.3.1.12 20.3.1.13 20.3.1.14 20.3.1.15 20.3.1.16 20.3.1.17 20.3.1.18 20.3.1.19 20.3.1.20 20.4 20.4.1 20.4.1.1 20.4.1.2 20.5 20.5.1 20.5.2 20.5.2.1 20.5.2.2 20.6 20.6.1 20.6.2 Title Page Number USB Clock (USB_CLK). 20-3 USB Speed (USB_SPEED) . 20-3 USB Negative/Positive Receive Signal Inputs (USB_RN & USB_RP) . 20-4 USB Receive Data (USB_RXD) . 20-4 USB Suspended (USB_SUSP) . 20-4 USB Negative/Positive Transmit Signal Output (USB_TN & USB_TP) . 20-4 USB Transmit Enable (USB_TXEN) . 20-4 Memory Map/Register Definition . 20-4 Register Descriptions. 20-5 USB Frame Number and Match Register (USB_FRAME). 20-6 USB Specification/Release Number Register (USB_SPEC) . 20-6 USB Status Register (USB_SR) . 20-7 USB Control Register (USB_CR) . 20-7 USB Descriptor RAM Address Register (USB_DAR) . 20-9 USB Descriptor RAM/Endpoint Buffer Data Register (USB_DDR). 20-10 USB Interrupt Status Register (USB_ISR). 20-10 USB Interrupt Mask Register (USB_IMR) . 20-12 USB FIFO Memory Control Register (USB_MCR) . 20-13 Endpoint n Status/Control Register (USB_EPnSR). 20-13 Endpoint n Interrupt Status Register (USB_EPnISR) . 20-15 Endpoint n Interrupt Mask Register (USB_EPnIMR) . 20-17 Endpoint n FIFO Data Register (USB_EPnFDR). 20-17 Endpoint n FIFO Status Register (USB_EPnFSR) . 20-18 Endpoint n FIFO Control Register (USB_EPnFCR) . 20-19 Endpoint n Last Read Frame Pointer (USB_EPnLRFP). 20-21 Endpoint n Last Write Frame Pointer (USB_EPnLWFP). 20-21 Endpoint n FIFO Alarm Register (USB_EPnFAR) . 20-22 Endpoint n FIFO Read Pointer (USB_EPnFRP). 20-23 Endpoint n FIFO Write Pointer (USB_EPnFWP). 20-24 Functional Description. 20-25 USB Components . 20-25 Descriptor RAM . 20-25 FIFO Controller . 20-25 Reset Strategy . 20-25 Description of Reset Operation. 20-26 Hard Reset. 20-26 USB Device Reset . 20-26 USB Bus Reset . 20-26 Interrupts . 20-27 Description of Interrupt Operation . 20-27 Detailed Interrupt Descriptions. 20-27 MCF5275 MCF5275 Reference Manual, Rev. 1 Freescale Semiconductor xix Contents Paragraph Number 20.6.2.1 20.6.2.2 20.6.2.3 20.7 20.7.1 20.7.1.1 20.7.1.2 20.7.1.3 20.7.1.4 20.7.1.5 20.7.1.6 20.7.1.7 20.7.2 20.7.2.1 20.7.2.2 20.7.2.3 20.7.2.4 20.7.3 20.7.3.1 20.7.3.2 20.7.3.3 20.7.3.4 20.7.3.5 20.7.3.6 Title Page Number USB Global Interrupt. Endpoint Interrupts . Interrupts, Missed Interrupts, and the USB Device. Software Interface. Device Initialization. Configuration Download . USB Endpoint to FIFO Mapping. USB Descriptor Download . USB Interrupt Register . Endpoint Registers. FIFO Sizes . Enable the Device . Exception Handling . Unable to Complete Device Request. Aborted Device Request . Unable to Fill or Empty FIFO Due to Temporary Problem . Catastrophic Error. Data Transfer Operations. USB Packets . USB Transfers . Control Transfers . Bulk Traffic . Interrupt Traffic . Isochronous Operations . 20-27 20-29 20-30 20-31 20-31 20-32 20-34 20-35 20-36 20-36 20-36 20-36 20-37 20-37 20-37 20-37 20-38 20-38 20-38 20-39 20-40 20-41 20-42 20-42 Chapter 21 Watchdog Timer Module 21.1 21.1.1 21.1.2 21.2 21.2.1 21.2.1.1 21.2.1.2 21.2.1.3 21.2.1.4 Introduction. Low-Power Mode Operation . Block Diagram. Memory Map/Register Definition . Register Description . Watchdog Control Register (WCR). Watchdog Modulus Register (WMR). Watchdog Count Register (WCNTR). Watchdog Service Register (WSR) . 21-1 21-1 21-2 21-2 21-2 21-3 21-4 21-4 21-4 MCF5275 MCF5275 Reference Manual, Rev. 1 xx Freescale Semiconductor Contents Paragraph Number Title Page Number Chapter 22 Pulse Width Modulation (PWM) Module 22.1 22.1.1 22.2 22.2.1 22.2.2 22.2.3 22.2.4 22.2.5 22.2.6 22.2.7 22.2.8 22.2.9 22.2.10 22.2.11 22.3 22.3.1 22.3.1.1 22.3.1.2 22.3.1.3 22.3.2 22.3.2.1 22.3.2.2 22.3.2.3 22.3.2.4 22.3.2.5 22.3.2.6 22.3.2.7 22.3.2.8 Introduction. 22-1 Overview. 22-1 Memory Map/Register Definition . 22-2 PWM Enable Register (PWME). 22-2 PWM Polarity Register (PWMPOL) . 22-3 PWM Clock Select Register (PWMCLK) . 22-4 PWM Prescale Clock Select Register (PWMPRCLK). 22-4 PWM Center Align Enable Register (PWMCAE) . 22-5 PWM Control Register (PWMCTL). 22-6 PWM Scale A Register (PWMSCLA). 22-7 PWM Scale B Register (PWMSCLB) . 22-7 PWM Channel Counter Registers (PWMCNTn). 22-8 PWM Channel Period Registers (PWMPERn). 22-9 PWM Channel Duty Registers (PWMDTYn) . 22-10 Functional Description. 22-10 PWM Clock Select. 22-10 Prescaled Clock (A or B). 22-11 Scaled Clock (SA or SB) . 22-11 Clock Select . 22-12 PWM Channel Timers . 22-12 PWM Enable. 22-13 PWM Polarity . 22-13 PWM Period and Duty. 22-13 PWM Timer Counters. 22-14 Left Aligned Outputs . 22-15 Center Aligned Outputs . 22-16 PWM 16-Bit Functions. 22-18 PWM Boundary Cases. 22-19 Chapter 23 Programmable Interrupt Timer Modules (PIT0­PIT3) 23.1 23.1.1 23.1.2 23.1.3 23.2 23.2.1 Introduction. Overview. Block Diagram. Low-Power Mode Operation . Memory Map/Register Definition . Register Description . 23-1 23-1 23-1 23-2 23-2 23-3 MCF5275 MCF5275 Reference Manual, Rev. 1 Freescale Semiconductor xxi Contents Paragraph Number 23.2.1.1 23.2.1.2 23.2.1.3 23.3 23.3.1 23.3.2 23.3.3 23.3.4 Title Page Number PIT Control and Status Register (PCSRn). PIT Modulus Register (PMRn). PIT Count Register (PCNTRn). Functional Description. Set-and-Forget Timer Operation. Free-Running Timer Operation . Timeout Specifications . Interrupt Operation . 23-3 23-5 23-5 23-6 23-6 23-6 23-7 23-7 Chapter 24 DMA Timers (DTIM0­DTIM3) 24.1 24.1.1 24.1.2 24.2 24.2.1 24.2.2 24.2.3 24.2.4 24.2.5 24.2.6 24.2.7 24.2.8 24.2.9 24.2.10 24.2.11 24.3 24.3.1 24.3.2 Introduction. 24-1 Overview. 24-1 Features. 24-2 Memory Map/Register Definition . 24-2 Prescaler. 24-2 Capture Mode . 24-3 Reference Compare. 24-3 Output Mode . 24-3 Memory Map . 24-3 DMA Timer Mode Registers (DTMRn). 24-4 DMA Timer Extended Mode Registers (DTXMRn). 24-5 DMA Timer Event Registers (DTERn) . 24-6 DMA Timer Reference Registers (DTRRn). 24-7 DMA Timer Capture Registers (DTCRn) . 24-8 DMA Timer Counters (DTCNn) . 24-8 Using the DMA Timer Modules . 24-9 Code Example. 24-10 Calculating Time-Out Values . 24-11 Chapter 25 Queued Serial Peripheral Interface (QSPI) Module 25.1 25.1.1 25.1.2 25.1.3 25.1.3.1 Introduction. Overview. Features. Module Description . Interface and Signals. 25-1 25-1 25-1 25-1 25-2 MCF5275 MCF5275 Reference Manual, Rev. 1 xxii Freescale Semiconductor Contents Paragraph Number 25.1.4 25.2 25.2.1 25.2.1.1 25.2.1.2 25.2.1.3 25.2.2 25.2.3 25.2.4 25.2.5 25.3 25.3.1 25.3.2 25.3.3 25.3.4 25.3.5 25.3.6 25.3.7 25.3.8 Title Page Number Internal Bus Interface. 25-3 Operation . 25-3 QSPI RAM. 25-4 Receive RAM . 25-5 Transmit RAM. 25-5 Command RAM. 25-6 Baud Rate Selection. 25-6 Transfer Delays. 25-7 Transfer Length. 25-8 Data Transfer . 25-8 Memory Map/Register Definition . 25-9 QSPI Mode Register (QMR) . 25-9 QSPI Delay Register (QDLYR) . 25-11 QSPI Wrap Register (QWR). 25-12 QSPI Interrupt Register (QIR). 25-12 QSPI Address Register (QAR) . 25-14 QSPI Data Register (QDR). 25-14 Command RAM Registers (QCR0­QCR15 QCR15). 25-14 Programming Example . 25-16 Chapter 26 UART Modules 26.1 26.1.1 26.1.2 26.2 26.3 26.3.1 26.3.2 26.3.3 26.3.4 26.3.5 26.3.6 26.3.7 26.3.8 26.3.9 26.3.10 26.3.11 26.3.12 26.3.13 Introduction. 26-1 Overview. 26-1 Features. 26-2 External Signal Description . 26-3 Memory Map/Register Definition . 26-4 UART Mode Registers 1 (UMR1n) . 26-5 UART Mode Register 2 (UMR2n). 26-7 UART Status Registers (USRn) . 26-8 UART Clock Select Registers (UCSRn) . 26-10 UART Command Registers (UCRn). 26-10 UART Receive Buffers (URBn). 26-12 UART Transmit Buffers (UTBn) . 26-12 UART Input Port Change Registers (UIPCRn). 26-13 UART Auxiliary Control Register (UACRn). 26-13 UART Interrupt Status/Mask Registers (UISRn/UIMRn) . 26-14 UART Baud Rate Generator Registers (UBG1n/UBG2n). 26-15 UART Input Port Register (UIPn). 26-16 UART Output Port Command Registers (UOP1n/UOP0n) . 26-16 MCF5275 MCF5275 Reference Manual, Rev. 1 Freescale Semiconductor xxiii Contents Paragraph Number 26.4 26.4.1 26.4.1.1 26.4.1.2 26.4.2 26.4.2.1 26.4.2.2 26.4.2.3 26.4.3 26.4.3.1 26.4.3.2 26.4.3.3 26.4.4 26.4.5 26.4.5.1 26.4.5.2 26.4.6 26.4.6.1 26.4.6.2 Title Page Number Functional Description. Transmitter/Receiver Clock Source. Programmable Divider. Calculating Baud Rates. Transmitter and Receiver Operating Modes. Transmitter. Receiver . FIFO. Looping Modes . Automatic Echo Mode. Local Loop-Back Mode. Remote Loop-Back Mode. Multidrop Mode. Bus Operation . Read Cycles . Write Cycles . Programming . Interrupt and DMA Request Initialization. UART Module Initialization Sequence . 26-17 26-17 26-17 26-18 26-19 26-19 26-21 26-23 26-24 26-24 26-24 26-25 26-25 26-27 26-27 26-27 26-27 26-28 26-30 Chapter 27 I C Interface 2 27.1 27.2 27.3 27.4 27.4.1 27.4.2 27.4.3 27.4.4 27.4.5 27.4.6 27.4.7 27.4.8 27.5 27.5.1 27.5.2 27.5.3 27.5.4 27.5.5 Introduction. 27-1 Overview. 27-1 Features . 27-1 I2C System Configuration. 27-3 START Signal. 27-3 Slave Address Transmission. 27-4 Data Transfer . 27-4 Acknowlege . 27-4 STOP Signal . 27-5 Repeated START. 27-5 Clock Synchronization and Arbitration . 27-6 Handshaking and Clock Stretching. 27-8 Memory Map/Register Definition . 27-8 I2C Address Register (I2ADR) . 27-8 I2C Frequency Divider Register (I2FDR). 27-9 I2C Control Register (I2CR). 27-10 I2C Status Register (I2SR). 27-11 I2C Data I/O Register (I2DR) . 27-12 MCF5275 MCF5275 Reference Manual, Rev. 1 xxiv Freescale Semiconductor Contents Paragraph Number 27.6 27.6.1 27.6.2 27.6.3 27.6.4 27.6.5 27.6.6 27.6.7 Title Page Number I2C Programming Examples . Initialization Sequence. Generation of START. Post-Transfer Software Response. Generation of STOP. Generation of Repeated START. Slave Mode . Arbitration Lost. 27-13 27-13 27-14 27-14 27-15 27-16 27-16 27-16 Chapter 28 Message Digest Hardware Accelerator (MDHA) 28.1 28.1.1 28.1.2 28.1.3 28.2 28.2.1 28.2.1.1 28.2.2 28.2.3 28.2.4 28.2.5 28.2.6 28.2.7 28.2.8 28.2.9 28.2.10 28.3 28.3.1 28.3.2 28.3.3 28.3.3.1 28.3.3.2 28.3.3.3 28.3.3.4 28.3.3.5 28.3.3.6 28.4 28.4.1 28.4.2 Introduction. 28-1 Overview. 28-1 Features. 28-1 Modes of Operation . 28-2 Memory Map/Register Definition . 28-3 MDHA Mode Register (MDMR) . 28-4 Invalid Modes . 28-6 MDHA Control Register (MDCR) . 28-7 MDHA Command Register (MDCMR) . 28-7 MDHA Status Register (MDSR) . 28-8 MDHA Interrupt Status & Mask Registers (MDISR and MDIMR) . 28-10 MDHA Data Size Register (MDDSR). 28-11 MDHA Input FIFO (MDIN). 28-12 MDHA Message Digest Registers 0 (MDx0). 28-12 MDHA Message Data Size Register (MDMDS). 28-12 MDHA Message Digest Registers 1 (MDx1). 28-13 Functional