9S12DP256BDGV2/D MC9S12DP256B MC9S12DT256B MC9S12DJ256B MC9S12DG256B 80QFP - Datasheet Archive

 

9S12DP256BDGV2/D MC9S12DP256B Device User Guide V02.11 Covers also MC9S12DT256B, MC9S12DJ256B, MC9S12DG256B Original Release

 

DOCUMENT NUMBER 9S12DP256BDGV2/D 9S12DP256BDGV2/D MC9S12DP256B MC9S12DP256B Device User Guide V02.11 Covers also MC9S12DT256B MC9S12DT256B, MC9S12DJ256B MC9S12DJ256B, MC9S12DG256B MC9S12DG256B Original Release Date: 29 Mar 2001 Revised: Mar 8, 2002 Motorola, Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. 1 DOCUMENT NUMBER 9S12DP256BDGV2/D 9S12DP256BDGV2/D Revision History Version Revision Effective Number Date Date Author Description of Changes V01.00 29 MAR 2001 29 MAR 2001 V01.01 8 MAY 2001 8 MAY 2001 VDD5 spec change 4.5V . . 5.25V Current Injection on single pin +- 2.5mA added DC bias level on EXTAL pin minor cosmetics and corrected typos V02.00 16 May 2001 16 May 2001 changed ATD Electrical Characteristics seperate coupling ratio for positive and negative bulk current injection added pinout for 80QFP 80QFP corrected SPI timing V02.01 5 June 2001 corrected Expanded Bus Timing Characteristics V02.02 14 June 2001 Some corrections on pin usage after review V02.03 18 June 2001 Minor corrections with respect to format and wording Added SRAM data retention disclaimer V02.04 26 June 2001 Changed Oscillator Characteristics tCQOUT max 2.5s and replaced Clock Monitor Time-out by Clock Monitor Failure Assert Frequency Changed Self Clock Mode Frequency min 1MHz and max 5.5MHz Changed IDDPS (RTI and COP disabled) to 400uA V02.05 11 July 2001 Corrected fref and REFDV/SYNR Settings for PLL Stabilization Delay Measurements, added tEXTR and tEXTF to Oscillator Characteristics, Corrected tEXTL and tEXTH values V02.06 17 July 2001 Added thermal resistance for LQFP 80, added PCB layout proposal for power and ground connections V02.07 24 July 2001 Added Document Names Variable definitions and Names have been hidden Added Maskset 1K79X 1K79X Modified description in chapter A.5.2 Oscillator Initial version. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. 2 MC9S12DP256B MC9S12DP256B Device User Guide - 9S12DP256BDGV2/D 9S12DP256BDGV2/D V02.11 Version Revision Effective Number Date Date V02.08 24 August 2001 Author Description of Changes Corrected local enable bits in interrupt vector table Corrected #33 - #36 in table A-20 A.4 Voltage Regulator characteristics was removed A.1 to A.7 major rework according to feedback from PE 12 Nov 2001 Changed document name and title to MC9. Added table containing other devices covered by this document Added NVM Blank check specificaiton Added external ADC trigger to pin description Updated A-7 Supply Current Characteristics Updated Table0-1 Derivative Differences Added Item8 to Table A-8 V02.10 28 Feb 2002 IOL/IOH reduced to 10mA/2mA for full/reduced drive Changed ATD characteristic Cins max to 22pF Changed VDD min VDDPLL min to 2.35V Removed Oscillator startup time from POR or STOP changed input capacitance for standard i/o pin to 6pF V02.11 26 Mar 2002 Corrected NVM reliability spec V02.09 3 MC9S12DP256B MC9S12DP256B Device User Guide - 9S12DP256BDGV2/D 9S12DP256BDGV2/D V02.11 4 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 Table of Contents Section 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.6 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Device Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Part ID Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Section 2 Signal Description 2.1 Device Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.2 Signal Properties Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 2.3 Detailed Signal Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.3.1 EXTAL, XTAL - Oscillator Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 2.3.2 RESET - External Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.3.3 TEST - Test Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.3.4 VREGEN - Voltage Regulator Enable Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.3.5 XFC - PLL Loop Filter Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 2.3.6 BKGD / TAGHI / MODC - Background Debug, Tag High, and Mode Pin . . . . . . . .32 2.3.7 PAD[15] / AN1[7] / ETRIG1 - Port AD Input Pin [15] . . . . . . . . . . . . . . . . . . . . . . . .32 2.3.8 PAD[14:8] / AN1[6:0] - Port AD Input Pins [14:8]. . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.3.9 PAD[7] / AN0[7] / ETRIG0 - Port AD Input Pin [7] . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.3.10 PAD[6:0] / AN0[6:0] - Port AD Input Pins [6:0]. . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.3.11 PA[7:0] / ADDR[15:8] / DATA[15:8] - Port A I/O Pins . . . . . . . . . . . . . . . . . . . . . . .33 2.3.12 PB[7:0] / ADDR[7:0] / DATA[7:0] - Port B I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . .33 2.3.13 PE7 / NOACC / XCLKS - Port E I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.3.14 PE6 / MODB / IPIPE1 - Port E I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.3.15 PE5 / MODA / IPIPE0 - Port E I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2.3.16 PE4 / ECLK - Port E I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.3.17 PE3 / LSTRB / TAGLO - Port E I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.3.18 PE2 / R/W - Port E I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.3.19 PE1 / IRQ - Port E Input Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.3.20 PE0 / XIRQ - Port E Input Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.3.21 PH7 / KWH7 / SS2 - Port H I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 5 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 2.3.22 2.3.23 2.3.24 2.3.25 2.3.26 2.3.27 2.3.28 2.3.29 2.3.30 2.3.31 2.3.32 2.3.33 2.3.34 2.3.35 2.3.36 2.3.37 2.3.38 2.3.39 2.3.40 2.3.41 2.3.42 2.3.43 2.3.44 2.3.45 2.3.46 2.3.47 2.3.48 2.3.49 2.3.50 2.3.51 2.3.52 2.3.53 2.3.54 2.3.55 2.3.56 2.3.57 6 PH6 / KWH6 / SCK2 - Port H I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 PH5 / KWH5 / MOSI2 - Port H I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 PH4 / KWH4 / MISO2 - Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 PH3 / KWH3 / SS1 - Port H I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 PH2 / KWH2 / SCK1 - Port H I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 PH1 / KWH1 / MOSI1 - Port H I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 PH0 / KWH0 / MISO1 - Port H I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 PJ7 / KWJ7 / TXCAN4 / SCL - PORT J I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . .35 PJ6 / KWJ6 / RXCAN4 / SDA - PORT J I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . .36 PJ[1:0] / KWJ[1:0] - Port J I/O Pins [1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PK7 / ECS / ROMONE - Port K I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PK[5:0] / XADDR[19:14] - Port K I/O Pins [5:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PM7 / TXCAN3 / TXCAN4 - Port M I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PM6 / RXCAN3 / RXCAN4 - Port M I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 PM5 / TXCAN2 / TXCAN0 / TXCAN4 / SCK0 - Port M I/O Pin 5. . . . . . . . . . . . . . .36 PM4 / RXCAN2 / RXCAN0 / RXCAN4/ MOSI0 - Port M I/O Pin 4. . . . . . . . . . . . . .36 PM3 / TXCAN1 / TXCAN0 / SS0 - Port M I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . .37 PM2 / RXCAN1 / RXCAN0 / MISO0 - Port M I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . .37 PM1 / TXCAN0 / TXB - Port M I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 PM0 / RXCAN0 / RXB - Port M I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 PP7 / KWP7 / PWM7 / SCK2 - Port P I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . .37 PP6 / KWP6 / PWM6 / SS2 - Port P I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 PP5 / KWP5 / PWM5 / MOSI2 - Port P I/O Pin 5. . . . . . . . . . . . . . . . . . . . . . . . . . .37 PP4 / KWP4 / PWM4 / MISO2 - Port P I/O Pin 4. . . . . . . . . . . . . . . . . . . . . . . . . . .38 PP3 / KWP3 / PWM3 / SS1 - Port P I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PP2 / KWP2 / PWM2 / SCK1 - Port P I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PP1 / KWP1 / PWM1 / MOSI1 - Port P I/O Pin 1. . . . . . . . . . . . . . . . . . . . . . . . . . .38 PP0 / KWP0 / PWM0 / MISO1 - Port P I/O Pin 0. . . . . . . . . . . . . . . . . . . . . . . . . . .38 PS7 / SS0 - Port S I/O Pin 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PS6 / SCK0 - Port S I/O Pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PS5 / MOSI0 - Port S I/O Pin 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PS4 / MISO0 - Port S I/O Pin 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PS3 / TXD1 - Port S I/O Pin 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PS2 / RXD1 - Port S I/O Pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PS1 / TXD0 - Port S I/O Pin 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 PS0 / RXD0 - Port S I/O Pin 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 2.3.58 PT[7:0] / IOC[7:0] - Port T I/O Pins [7:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.4 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.4.1 VDDX,VSSX - Power & Ground Pins for I/O Drivers . . . . . . . . . . . . . . . . . . . . . . . .40 2.4.2 VDDR, VSSR - Power & Ground Pins for I/O Drivers & for Internal Voltage Regulator 40 2.4.3 VDD1, VDD2, VSS1, VSS2 - Core Power Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 2.4.4 VDDA, VSSA - Power Supply Pins for ATD and VREG . . . . . . . . . . . . . . . . . . . . .40 2.4.5 VRH, VRL - ATD Reference Voltage Input Pins . . . . . . . . . . . . . . . . . . . . . . . . . . .40 2.4.6 VDDPLL, VSSPLL - Power Supply Pins for PLL . . . . . . . . . . . . . . . . . . . . . . . . . . .40 2.4.7 VREGEN - On Chip Voltage Regulator Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Section 3 System Clock Description 3.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Section 4 Modes of Operation 4.1 4.2 4.2.1 4.2.2 4.2.3 4.3 4.3.1 4.3.2 4.3.3 4.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Normal Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Special Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Test Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Securing the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Operation of the Secured Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Unsecuring the Microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Section 5 Resets and Interrupts 5.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.2 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.2.1 Vector Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 5.3 Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 5.3.1 I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 5.3.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Section 6 Star12 Core Block Description Section 7 Clock and Reset Generator (CRG) Block Description 7 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 7.1 Device-specific information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 7.1.1 XCLKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Section 8 Enhanced Capture Timer (ECT) Block Description Section 9 Analog to Digital Converter (ATD) Block Description Section 10 Inter-IC Bus (IIC) Block Description Section 11 Serial Communications Interface (SCI) Block Description Section 12 Serial Peripheral Interface (SPI) Block Description Section 13 J1850 J1850 (BDLC) Block Description Section 14 Pulse Width Modulator (PWM) Block Description Section 15 Flash EEPROM 256K Block Description Section 16 EEPROM 4K Block Description Section 17 RAM Block Description Section 18 MSCAN Block Description Section 19 Port Integration Module (PIM) Block Description Section 20 Voltage Regulator (VREG) Block Description Appendix A Electrical Characteristics A.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 A.1.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 A.1.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 A.1.3 Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 A.1.4 Current Injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 A.1.5 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 A.1.6 ESD Protection and Latch-up Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 A.1.7 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 8 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 A.1.8 Power Dissipation and Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 A.1.9 I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 A.1.10 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 A.2 ATD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 A.2.1 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 A.2.2 Factors influencing accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 A.2.3 ATD accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 A.3 NVM, Flash and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 A.3.1 NVM timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 A.3.2 NVM Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 A.4 Voltage Regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 A.5 Reset, Oscillator and PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 A.5.1 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 A.5.2 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 A.5.3 Phase Locked Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 A.6 MSCAN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 A.7 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 A.7.1 Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 A.7.2 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 A.8 External Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 A.8.1 General Muxed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Appendix B Package Information B.1 B.2 B.3 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 112-pin LQFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 80-pin QFP package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 9 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 10 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 List of Figures Figure 1-1 Figure 1-2 Figure 2-1 Figure 2-2 Figure 2-3 Figure 3-1 Figure 20-1 Figure 20-2 Figure A-1 Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7 Figure A-8 Figure A-9 Figure B-1 Figure B-2 MC9S12DP256 MC9S12DP256 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 MC9S12DP256 MC9S12DP256 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Pin Assignments in 112-pin LQFP for MC9S12DP256 MC9S12DP256 . . . . . . . . . . . . . . . . . . . .28 Pin Assignments in 80-pin QFP for MC9S12DP256 MC9S12DP256 . . . . . . . . . . . . . . . . . . . . . .29 PLL Loop Filter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Recommended PCB Layout 112 LQFP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Recommended PCB Layout for 80QFP 80QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 ATD Accuracy Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Basic PLL functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Jitter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Maximum bus clock jitter approximation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 SPI Master Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 SPI Slave Timing (CPHA =1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 General External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 112-pin LQFP mechanical dimensions (case no. 987) . . . . . . . . . . . . . . . . . . 100 80-pin QFP Mechanical Dimensions (case no. 841B) . . . . . . . . . . . . . . . . . . . 101 11 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 12 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 List of Tables Table 0-2 Table 0-1 Table 1-1 Table 1-2 Table 1-3 Table 2-1 Table 4-1 Table 5-1 Table A-1 Table A-2 Table A-3 Table A-4 Table A-5 Table A-6 Table A-7 Table A-8 Table A-9 Table A-10 Table A-11 Table A-12 Table A-13 Table A-14 Table A-15 Table A-16 Table A-17 Table A-18 Table A-19 Table A-20 Document References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Derivative Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Device Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Assigned Part ID Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Memory size registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Signal Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Interrupt Vector Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 ESD and Latch-Up Protection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Thermal Package Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 5V I/O Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Supply Current Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 ATD Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 ATD Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 ATD Conversion Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 NVM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 NVM Reliability Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Voltage Regulator Recommended Load Capacitances . . . . . . . . . . . . . . . . . . . .81 Startup Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 PLL Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 MSCAN Wake-up Pulse Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 SPI Master Mode Timing Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 SPI Slave Mode Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Expanded Bus Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 13 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 14 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 Preface The Device User Guide provides information about the MC9S12DP256B MC9S12DP256B device made up of standard HCS12 HCS12 blocks and the HCS12 HCS12 processor core. Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386 EB386. Table 0-1 Derivative Differences1 Generic device MC9S12DP256B MC9S12DP256B MC9S12DT256B MC9S12DT256B MC9S12DJ256B MC9S12DJ256B MC9S12DG256B MC9S12DG256B base part number SC511346 SC511346 SC511347 SC511347 SC511348 SC511348 SC511349 SC511349 CAN 5 3 2 2 J1850/BDLC J1850/BDLC 0 0 1 0 Package 112 LQFP 112 LQFP 112 LQFP/80 LQFP/80 QFP 112 LQFP Mask set K79X K79X K79X K79X Temp Options M, V, C M, V, C M, V, C M, V, C package Code PV PV PV/FU PV Notes An errata exists An errata exists An errata exists An errata exists conntact Sales office conntact Sales office conntact Sales office conntact Sales office NOTES: 1. e.g. part number SC511346MPV SC511346MPV, is 9S12DP256 9S12DP256 device in 112 QFP package with M temerature rating This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 HCS12 Core User Guide and all the individual Block User Guides of the implemented modules. In a effort to reduce redundancy all module specific information is located only in the respective Block User Guide. If applicable, special implementation details of the module are given in the block description sections of this document. See Table 0-2 for names and versions of the referenced documents throughout the Device User Guide. Table 0-2 Document References User Guide Version Document Order Number HCS12 HCS12 V1.5 Core User Guide 1.2 HCS12COREUG HCS12COREUG CRG Block User Guide V02 S12CRGV2/D S12CRGV2/D ECT_16B8C 16B8C Block User Guide V01 S12ECT16B8CV1/D S12ECT16B8CV1/D ATD_10B8C 10B8C Block User Guide V02 S12ATD10B8CV2/D S12ATD10B8CV2/D IIC Block User Guide V02 S12IICV2/D S12IICV2/D SCI Block User Guide V02 S12SCIV2/D S12SCIV2/D SPI Block User Guide V02 S12SPIV2/D S12SPIV2/D PWM_8B8C Block User Guide V01 S12PWM8B8CV1/D S12PWM8B8CV1/D FTS256K FTS256K Block User Guide V02 S12FTS256KV2/D S12FTS256KV2/D EETS4K Block User Guide V02 S12EETS4KV2/D S12EETS4KV2/D BDLC Block User Guide V01 S12BDLCV1/D S12BDLCV1/D MSCAN Block User Guide V02 S12MSCANV2/D S12MSCANV2/D 15 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 User Guide Document Order Number V01 S12VREGV1/D S12VREGV1/D PIM_9DP256 9DP256 Block User Guide 16 Version VREG Block User Guide V02 S12PIM9DP256V2/D S12PIM9DP256V2/D MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 Section 1 Introduction 1.1 Overview The MC9S12DP256 MC9S12DP256 microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (HCS12 HCS12 CPU), 256K bytes of Flash EEPROM, 12K bytes of RAM, 4K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), three serial peripheral interfaces (SPI), an 8-channel IC/OC enhanced capture timer, two 8-channel, 10-bit analog-to-digital converters (ADC), an 8-channel pulse-width modulator (PWM), a digital Byte Data Link Controller (BDLC), 29 discrete digital I/O channels (Port A, Port B, Port K and Port E), 20 discrete digital I/O lines with interrupt and wakeup capability, five CAN 2.0 A, B software compatible modules (MSCAN12 MSCAN12), and an Inter-IC Bus. The MC9S12DP256 MC9S12DP256 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. 1.2 Features · HCS12 HCS12 Core ­ 16-bit HCS12 HCS12 CPU i. Upward compatible with M68HC11 M68HC11 instruction set ii. Interrupt stacking and programmer's model identical to M68HC11 M68HC11 iii. Instruction queue iv. Enhanced indexed addressing ­ MEBI (Multiplexed External Bus Interface) ­ MMC (Module Mapping Control) ­ INT (Interrupt control) ­ BKP (Breakpoints) ­ BDM (Background Debug Mode) · CRG (low current oscillator, PLL, reset, clocks, COP watchdog, real time interrupt, clock monitor) · 8-bit and 4-bit ports with interrupt functionality ­ ­ · Digital filtering Programmable rising or falling edge trigger Memory ­ 256K Flash EEPROM ­ 4K byte EEPROM ­ 12K byte RAM 17 MC9S12DP256B MC9S12DP256B Device User Guide - V02.11 · Two 8-channel Analog-to-Digital Converters ­ ­ · 10-bit resolution External conversion trigger capability Five 1M bit per second, CAN 2.0 A, B software compatible modules ­ ­ Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit ­ Four separate interrupt channels for Rx, Tx, error and wake-up ­ Low-pass filter wake-up function ­ · Five receive and three transmit buffers Loop-back for self test operation Enhanced Capture Timer ­ ­ 8 programmable input capture or output compare channels ­ · 16-bit main counter with 7-bit prescaler Two 8-bit or one 16-bit pulse accumulators 8 PWM channels ­ ­ 8-bit 8-channel or 16-bit 4-channel ­ Separate control for each pulse width and duty cycle ­ Center-aligned or left-aligned outputs ­ Programmable clock select logic with a wide range of frequencies ­ Fast emergency shutdown input ­ · Programmable period and duty cycle Usable as interrupt inputs Serial interfaces ­ ­ · Two asynchronous Serial Communications Interfaces (SCI) Three Synchronous Serial Peripheral Interface (SPI) Byte Data Link Controller (BDLC) ­ · SAE J1850 J1850 Class B Data Communications Network Interface Compatible and ISO Compatible for Low-Speed (