MC74VHC50 MC74VHC50M MC74VHC50DT MC74VHC50D MC74VHC50/D VHC50 AND8004/D - Datasheet Archive

 

Product Preview Hex Buffer The MC74VHC50 is an advanced high speed CMOS buffer fabricated with silicon gate CMOS technology. It

 

MC74VHC50 MC74VHC50 Product Preview Hex Buffer The MC74VHC50 MC74VHC50 is an advanced high speed CMOS buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The internal circuit is composed of three stages, including a buffered output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems. · · · · · · · · · High Speed: tPD = 3.8ns (Typ) at VCC = 5V Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C High Noise Immunity: VNIH = VNIL = 28% VCC Power Down Protection Provided on Inputs Balanced Propagation Delays Designed for 2V to 5.5V Operating Range Low Noise: VOLP = 0.8V (Max) Latchup Performance Exceeds 300mA ESD Performance: HBM > 2000V; Machine Model > 200V LOGIC DIAGRAM A1 1 2 3 4 A3 5 6 14­LEAD SOIC D SUFFIX CASE 751A PIN CONNECTION AND MARKING DIAGRAM (Top View) VCC 14 Y1 A1 1 1 A3 1 9 8 A4 1 11 10 Y3 Y4 A5 A5 A6 13 Y6 12 A5 11 Y5 10 A4 9 Y4 8 1 2 3 4 5 6 7 A1 Y1 A2 Y2 A3 Y3 GND Y1 Y2 Y2 Y3 Y=A A4 14­LEAD TSSOP DT SUFFIX CASE 948G 14­LEAD SOIC EIAJ M SUFFIX CASE 965 LOGIC SYMBOL A2 A2 http://onsemi.com Y5 1 A6 Y4 1 For detailed package marking information, see the Marking Diagram section on page 4 of this data sheet. Y5 Y6 ORDERING INFORMATION 12 Device Y6 Shipping SOIC 55 Units/Rail TSSOP 96 Units/Rail MC74VHC50M MC74VHC50M 13 Package MC74VHC50DT MC74VHC50DT A6 SOIC EIAJ 50 Units/Rail MC74VHC50D MC74VHC50D FUNCTION TABLE A Input This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice. © Semiconductor Components Industries, LLC, 2000 April, 2000 ­ Rev. 1 1 Y Output L H L H Publication Order Number: MC74VHC50/D MC74VHC50/D MC74VHC50 MC74VHC50 MAXIMUM RATINGS* Symbol Value Unit DC Supply Voltage Characteristics VCC ­0.5 to +7.0 V DC Input Voltage VIN ­0.5 to +7.0 V VOUT ­0.5 to 7.0 ­0.5 to VCC + 0.5 V IIK ­20 mA IOK +20 mA IOUT +25 mA DC Supply Current, VCC and GND ICC +50 mA Power Dissipation in Still Air, SOIC Packages TSSOP Package PD 500 450 mW Lead temperature, 1 mm from case for 10 s TL 260 °C DC Output Voltage VCC = 0 High or Low State Input Diode Current Output Diode Current (VOUT < GND; VOUT > VCC) DC Output Current, per Pin Storage temperature Tstg ­65 to +150 °C * Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute­maximum­rated conditions is not implied. Functional operation should be restricted to the Recommended Operating Conditions. Derating - SOIC Packages: ­ 7 mW/_C from 65_ to 125_C TSSOP Package: ­ 6.1 mW/_C from 65_ to 125_C RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Max Unit DC Supply Voltage VCC 2.0 5.5 V DC Input Voltage VIN 0.0 5.5 V VOUT 0.0 VCC V TA ­55 +85 °C tr , tf 0 0 100 20 ns/V DC Output Voltage Operating Temperature Range Input Rise and Fall Time VCC = 3.3V ± 0.3V VCC = 5.0V ± 0.5V http://onsemi.com 2 MC74VHC50 MC74VHC50 DC ELECTRICAL CHARACTERISTICS VCC Symbol Parameter Test Conditions (V) Min 1.5 2.1 3.15 3.85 VIH Minimum High­Level Input Voltage 2.0 3.0 4.5 5.5 VIL Maximum Low­Level Input Voltage VOH Minimum High­Level Output Voltage VIN = VIH or VIL Typ 2.0 3.0 4.5 5.5 VIN = VIH or VIL IOH = ­50µA 2.0 3.0 4.5 Min 3.0 4.5 2.58 3.94 VIN = VIH or VIL IOL = 50µA Max 1.5 2.1 3.15 3.85 1.9 2.9 4.4 2.0 3.0 4.5 VIN = VIH or VIL IOL = 4mA IOL = 8mA Maximum Low­Level Output Voltage VIN = VIH or VIL Max 0.5 0.9 1.35 1.65 VIN = VIH or VIL IOH = ­4mA IOH = ­8mA VOL TA 85°C TA = 25°C 2.0 3.0 4.5 TA 125°C Min Max 1.5 2.1 3.15 3.85 V 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 1.9 2.9 4.4 1.9 2.9 4.4 2.48 3.80 Unit V V 2.34 3.66 V 0.0 0.0 0.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 3.0 4.5 0.36 0.36 0.44 0.44 V 0.52 0.52 V IIN Maximum Input Leakage Current VIN = 5.5V or GND 0 to 5.5 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current VIN = VCC or GND 5.5 2.0 20 40 µA ÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î Î Î ÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î ÎÎ Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î Î ÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î Î Î Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ AC ELECTRICAL CHARACTERISTICS (Cload = 50 pF, Input tr = tf = 3.0ns) TA 85°C TA = 25°C Symbol tPLH, tPHL CIN Parameter Maximum Propogation Delay, Input A to Y Test Conditions Min Typ Max Min Max TA 125°C Min Max Unit ns VCC = 3.0 ± 0.3V CL = 15 pF CL = 50 pF 5.0 7.5 7.1 10.6 8.5 12.0 10.0 14.5 VCC = 5.0 ± 0.5V CL = 15 pF CL = 50 pF 3.8 5.3 5.5 7.5 6.5 8.5 8.0 10.0 4 10 10 10 Maximum Input Capacitance pF Typical @ 25°C, VCC = 5.0V CPD Power Dissipation Capacitance (Note 1.) pF 18 1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC. CPD is used to determine the no­load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC. NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V) TA = 25°C Symbol Characteristic Typ Max Unit VOLP Quiet Output Maximum Dynamic VOL 0.8 1.0 V VOLV Quiet Output Minimum Dynamic VOL ­0.8 ­1.0 V VIHD Minimum High Level Dynamic Input Voltage 3.5 V VILD Maximum Low Level Dynamic Input Voltage 1.5 V http://onsemi.com 3 MC74VHC50 MC74VHC50 TEST POINT VCC OUTPUT 50% A DEVICE UNDER TEST GND tPHL tPLH CL* 50% VCC Y *Includes all probe and jig capacitance Figure 1. Switching Waveforms Figure 2. Test Circuit INPUT Figure 3. Input Equivalent Circuit MARKING DIAGRAMS (Top View) 14 13 12 11 10 9 14 13 12 11 10 8 3 4 6 7 50 AWLYWW* 2 8 VHC VHC50 VHC50 1 9 ALYW* 5 6 7 1 2 14­LEAD SOIC D SUFFIX CASE 751A 3 4 5 14­LEAD TSSOP DT SUFFIX CASE 948G 14 13 12 11 10 9 8 6 7 VHC50 VHC50 AWLYWW* 1 2 3 4 5 14­LEAD SOIC EIAJ M SUFFIX CASE 965 *See Applications Note #AND8004/D AND8004/D for date code and traceability information. http://onsemi.com 4 MC74VHC50 MC74VHC50 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A­03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. ­A­ 14 8 P 7 PL ­B­ 1 0.25 (0.010) 7 G 0.25 (0.010) M T F J M K D 14 PL M R X 45° C SEATING PLANE B M B S A S http://onsemi.com 5 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7° 0° 6.20 5.80 0.50 0.25 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7° 0° 0.228 0.244 0.010 0.019 MC74VHC50 MC74VHC50 PACKAGE DIMENSIONS DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G­01 ISSUE O 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE ­W­. S S N 2X 14 L/2 0.25 (0.010) 8 M B ­U­ L PIN 1 IDENT. F 7 1 S DETAIL E K A ­V­ K1 J J1 ÇÇÇ ÉÉ ÇÇÇ ÉÉ 0.15 (0.006) T U N SECTION N­N ­W­ C 0.10 (0.004) ­T­ SEATING PLANE D G H DETAIL E http://onsemi.com 6 DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 ­­­ 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 ­­­ 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74VHC50 MC74VHC50 PACKAGE DIMENSIONS M SUFFIX PLASTIC SOIC EIAJ PACKAGE CASE 965­01 ISSUE O 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE L 7 1 M_ DETAIL P Z D VIEW P A e c A1 b 0.13 (0.005) M 0.10 (0.004) http://onsemi.com 7 DIM A A1 b c D E e HE 0.50 LE M Q1 Z MILLIMETERS MIN MAX ­­­ 2.05 0.05 0.20 0.35 0.50 0.18 0.27 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 ­­­ 1.42 INCHES MIN MAX ­­­ 0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 ­­­ 0.056 MC74VHC50 MC74VHC50 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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