MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 M68HC05 MC68HC705KJ1/D MC68HC705JK1 - Datasheet Archive

 

MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet M68HC05 Microcontrollers MC68HC705KJ1/D Rev. 4 5/2003 MOTOROLA.COM/SEMICONDUCTORS

 

MC68HC705KJ1 MC68HC705KJ1 MC68HRC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 MC68HLC705KJ1 Data Sheet M68HC05 M68HC05 Microcontrollers MC68HC705KJ1/D MC68HC705KJ1/D Rev. 4 5/2003 MOTOROLA.COM/SEMICONDUCTORS MC68HC705JK1 MC68HC705JK1 MC68HRC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 MC68HLC705KJ1 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://motorola.com/semiconductors/ The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Data Sheet 3 Revision History Revision History Revision Level 17 17 Figure 1-6. Ceramic Resonator Connections with Oscillator Internal Resistor Mask Option - changed PA7 designator to OSC1 in two places 18 Figure 1-7. Ceramic Resonator Connections without Oscillator Internal Resistor Mask Option - changed PA7 designator to OSC1 in two places 18 Figure 1-8. External Clock Connections - changed PA7 designator to OSC1 in two places 19 Figure B-1. Crystal Connections - added OSC2 designation 107 Table B-3. MC68HLC705KJ1 MC68HLC705KJ1 (Low Frequency) Order Numbers - Corrected table title 3.0 Page Number(s) Figure 1-5. Crystal Connections without Oscillator Internal Resistor Mask Option - changed PA7 designator to OSC1 in two places April, 2002 Description Figure 1-4. Crystal Connections with Oscillator Internal Resistor Mask Option - changed PA7 designator to OSC1 in two places Date 108 Reformatted to new publications standards. May, 2003 Data Sheet 4 4.0 Figure A-2. Typical Internal Operating Frequency for Various VDD at 25°C - RC Oscillator Option Only - replaced graph Throughout 104 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Revision History MOTOROLA Data Sheet - MC68HC705KJ1 MC68HC705KJ1 List of Sections Section 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Section 3. Computer Operating Properly Module (COP). . . . . . . . . . . 31 Section 4. Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . . . 35 Section 5. External Interrupt Module (IRQ). . . . . . . . . . . . . . . . . . . . . . 53 Section 6. Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Section 7. Parallel I/O Ports (PORTS) . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Section 8. Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Section 9. Multifunction Timer Module . . . . . . . . . . . . . . . . . . . . . . . . . 81 Section 10. Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Section 11. Ordering Information and Mechanical Specifications . . . . . . . . . . . . . . . . . . . . 99 Appendix A. MC68HRC705KJ1 MC68HRC705KJ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 Appendix B. MC68HLC705KJ1 MC68HLC705KJ1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA List of Sections Data Sheet 5 List of Sections Data Sheet 6 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 List of Sections MOTOROLA Data Sheet - MC68HC705KJ1 MC68HC705KJ1 Table of Contents Section 1. Introduction 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.2 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.3 Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 1.4 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2.1 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2.2 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2.3 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2.4 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.5 PA0­PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.6 PB2 and PB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 16 16 18 19 19 19 19 20 20 Section 2. Memory 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2 Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3 Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.4 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.5 Input/Output Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.6 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.7 2.7.1 2.7.2 2.7.3 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPROM/OTPROM Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . EPROM Programming Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . EPROM Erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.9 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 29 25 25 26 27 Section 3. Computer Operating Properly Module (COP) 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Table of Contents Data Sheet 7 Table of Contents 3.3 3.3.1 3.3.2 3.3.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Watchdog Timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Watchdog Timeout Period . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 31 32 32 3.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.5 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.6 3.6.1 3.6.2 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Section 4. Central Processor Unit (CPU) 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.3 CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.4 Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.5 4.5.1 4.5.2 4.5.3 4.5.4 4.5.5 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 38 38 39 4.6 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.3 Direct. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.7 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.1.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.3 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 40 40 40 40 40 41 41 41 41 42 42 43 43 45 45 46 4.7 Data Sheet 8 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Table of Contents MOTOROLA Table of Contents Section 5. External Interrupt Module (IRQ) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 5.3.1 5.3.2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.4 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.5 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Section 6. Low-Power Modes 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.2 Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3 Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1.1 STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.1.2 WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2.1 STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2.2 WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 COP Watchdog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3.1 STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3.2 WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 Timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4.1 STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4.2 WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5.1 STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.5.2 WAIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 60 60 60 61 61 61 61 61 62 62 62 62 62 62 63 6.4 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.5 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Section 7. Parallel I/O Ports (PORTS) 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulldown Register A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port LED Drive Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A I/O Pin Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Table of Contents 66 66 66 68 68 68 Data Sheet 9 Table of Contents 7.3 7.3.1 7.3.2 7.3.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pulldown Register B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 69 69 71 7.4 I/O Port Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Section 8. Resets and Interrupts 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.2 8.2.1 8.2.2 8.2.3 8.2.4 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 73 74 75 75 8.3 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 Software Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.3.2 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.4 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 75 75 77 77 77 77 Section 9. Multifunction Timer Module 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 9.4 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 9.5 9.5.1 9.5.2 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Timer Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 9.6 9.6.1 9.6.2 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Section 10. Electrical Specifications 10.1 10.2 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.4 Power Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 10.5 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 10.6 3.3-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 10.7 10 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 10.3 Data Sheet Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Table of Contents MOTOROLA Table of Contents 10.8 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 10.9 EPROM Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 94 10.10 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Section 11. Ordering Information and Mechanical Specifications 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.2 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.3 16-Pin PDIP - Case #648 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.4 16-Pin SOIC - Case #751G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.5 16-Pin Cerdip - Case #620A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Appendix A. MC68HRC705KJ1 MC68HRC705KJ1 A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 A.2 RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 A.3 Typical Internal Operating Frequency for RC Oscillator Option . . . . . . 104 A.4 RC Oscillator Connections (No External Resistor) . . . . . . . . . . . . . . . . 105 A.5 Typical Internal Operating Frequency versus Temperature (No External Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 A.6 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Appendix B. MC68HLC705KJ1 MC68HLC705KJ1 B.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 B.2 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 B.3 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 108 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Table of Contents Data Sheet 11 Table of Contents Data Sheet 12 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Table of Contents MOTOROLA Data Sheet - MC68HC705KJ1 MC68HC705KJ1 Section 1. Introduction 1.1 Features Features on the MC68HC705KJ1 MC68HC705KJ1 include: · Robust noise immunity · 4.0-MHz internal operating frequency at 5.0 V · 1240 Bytes of EPROM/OTPROM (electrically programmable read-only memory/one-time programmable read-only memory), including eight bytes for user vectors · 64 bytes of user RAM · Peripheral modules: ­ 15-stage multifunction timer ­ Computer operating properly (COP) watchdog · 10 bidirectional input/output (I/O) lines, including: ­ 10-mA sink capability on all I/O pins ­ Software programmable pulldowns on all I/O pins ­ Keyboard scan with selectable interrupt on four I/O pins ­ 5.5-mA source capability on six I/O pins · Selectable sensitivity on external interrupt (edge- and level-sensitive or edge-sensitive only) · On-chip oscillator with connections for: ­ Crystal ­ Ceramic resonator ­ Resistor-capacitor (RC) oscillator (MC68HRC705KJ1 MC68HRC705KJ1) with or without external resistor ­ External clock ­ Low-speed (32-kHz) crystal (MC68HLC705KJ1 MC68HLC705KJ1) · Memory-mapped I/O registers · Fully static operation with no minimum clock speed · Power-saving stop, halt, wait, and data-retention modes · External interrupt mask bit and acknowledge bit · Illegal address reset MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Introduction Data Sheet 13 Introduction · Internal steering diode and pullup resistor from RESET pin to VDD · Selectable EPROM security(1) · Selectable oscillator bias resistor 1.2 Structure OSC1 OSC2 INTERNAL OSCILLATOR 15-STAGE 15-STAGE MULTIFUNCTION TIMER SYSTEM DIVIDE BY ³2 CPU CONTROL ALU 68HC05 68HC05 CPU IRQ/VPP ACCUMULATOR CPU REGISTERS INDEX REGISTER 0 0 0 0 0 0 0 0 1 1 STK PTR PB3(1) PORT B RESET DATA DIRECTION REGISTER B WATCHDOG AND ILLEGAL ADDRESS DETECT PB2(1) STATIC RAM (SRAM) ­ 64 BYTES USER EPROM ­ 1240 BYTES PA7 PA6 PA5 PORT A CONDITION CODE REGISTER 1 1 1 H I N Z C DATA DIRECTION REGISTER A PROGRAM COUNTER PA4 PA3(1) (2) PA2(1) (2) PA1(1) (2) PA0(1) (2) 10-mA sink capability on all I/O pins MASK OPTION REGISTER (MOR) Notes: 1. 5.5 mA source capability 2. External interrupt capability Figure 1-1. Block Diagram 1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the EPROM/OTPROM difficult for unauthorized users. Data Sheet 14 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Introduction MOTOROLA Introduction Programmable Options 1.3 Programmable Options The options in Table 1-1 are programmable in the mask option register. Table 1-1. Programmable Options Feature Option COP watchdog timer Enabled or disabled External interrupt triggering Edge-sensitive only or edge- and level-sensitive Port A IRQ pin interrupts Enabled or disabled Port pulldown resistors Enabled or disabled STOP instruction mode Stop mode or halt mode Crystal oscillator internal resistor Enabled or disabled EPROM security Enabled or disabled Short oscillator delay counter Enabled or disabled 1.4 Pin Functions Pin assignments are shown in Figure 1-2 with the functions described in the following subsections. RESET 1 16 IRQ/VPP OSC1 2 15 PA0 OSC2 3 14 PA1 PB3 4 13 PA2 PB2 5 12 PA3 VDD 6 11 PA4 VSS 7 10 PA5 PA7 8 9 PA6 Figure 1-2. Pin Assignments MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Introduction Data Sheet 15 Introduction 1.4.1 VDD and VSS VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Very fast signal transitions occur on the MCU pins, placing high, short-duration current demands on the power supply. To prevent noise problems, take special care, as Figure 1-3 shows, by placing the bypass capacitors as close as possible to the MCU. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. V+ VDD VDD MCU C1 0.1 µF C2 + C2 C1 VSS VSS Figure 1-3. Bypassing Layout Recommendation 1.4.2 OSC1 and OSC2 The OSC1 and OSC2 pins are the connections for the on-chip oscillator. The oscillator can be driven by any of the following: 1. Standard crystal (See Figure 1-4 and Figure 1-5.) 2. Ceramic resonator (See Figure 1-6 and Figure 1-7.) 3. Resistor/capacitor (RC) oscillator (Refer to Appendix A. MC68HRC705KJ1 MC68HRC705KJ1.) 4. External clock signal as shown in (See Figure 1-8.) 5. Low speed (32 kHz) crystal connections (Refer to Appendix B. MC68HLC705KJ1 MC68HLC705KJ1.) The frequency, fOSC, of the oscillator or external clock source is divided by two to produce the internal operating frequency, fOP. 1.4.2.1 Crystal Oscillator Figure 1-4 and Figure 1-5 show a typical crystal oscillator circuit for an AT-cut, parallel resonant crystal. Follow the crystal supplier's recommendations, as the crystal parameters determine the external component values required to provide reliable startup and maximum stability. The load capacitance values used in the oscillator circuit design should include all stray layout capacitances. Data Sheet 16 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Introduction MOTOROLA Introduction Pin Functions To minimize output distortion, mount the crystal and capacitors as close as possible to the pins. An internal startup resistor of approximately 2 M is provided between OSC1 and OSC2 for the crystal oscillator as a programmable mask option. NOTE: Use an AT-cut crystal and not an AT-strip crystal because the MCU can overdrive an AT-strip crystal. VSS MCU C3 XTAL OSC2 OSC1 OSC1 OSC2 C4 XTAL C3 27 pF C4 27 pF VDD C2 C1 VSS Figure 1-4. Crystal Connections with Oscillator Internal Resistor Mask Option VSS C3 MCU R 10 M OSC2 OSC1 OSC1 XTAL R OSC2 C4 VDD XTAL C3 27 pF C4 27 pF C2 C1 VSS Figure 1-5. Crystal Connections without Oscillator Internal Resistor Mask Option MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Introduction Data Sheet 17 Introduction 1.4.2.2 Ceramic Resonator Oscillator To reduce cost, use a ceramic resonator instead of the crystal. The circuits shown in Figure 1-6 and Figure 1-7 show ceramic resonator circuits. Follow the resonator manufacturer's recommendations, as the resonator parameters determine the external component values required for maximum stability and reliable starting. The load capacitance values used in the oscillator circuit design should include all stray capacitances. Mount the resonator and components as close as possible to the pins for startup stabilization and to minimize output distortion. An internal startup resistor of approximately 2 M is provided between OSC1 and OSC2 as a programmable mask option. VSS CERAMIC RESONATOR C3 27 pF C3 OSC1 CERAMIC RESONATOR OSC2 OSC1 MCU OSC2 C4 C4 27 pF VDD C2 C1 VSS Figure 1-6. Ceramic Resonator Connections with Oscillator Internal Resistor Mask Option VSS C3 CERAMIC RESONATOR R 10 M OSC2 OSC1 MCU OSC1 R OSC2 C4 C3 27 pF CERAMIC RESONATOR VDD C4 27 pF C2 C1 VSS Figure 1-7. Ceramic Resonator Connections without Oscillator Internal Resistor Mask Option Data Sheet 18 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Introduction MOTOROLA Introduction Pin Functions 1.4.2.3 RC Oscillator Refer to Appendix A. MC68HRC705KJ1 MC68HRC705KJ1. 1.4.2.4 External Clock An external clock from another CMOS-compatible device can be connected to the OSC1 input, with the OSC2 input not connected, as shown in Figure 1-8. This configuration is possible regardless of whether the crystal/ceramic resonator or the RC oscillator is enabled. OSC2 OSC1 MCU EXTERNAL CMOS CLOCK Figure 1-8. External Clock Connections 1.4.3 RESET Applying a logic 0 to the RESET pin forces the MCU to a known startup state. An internal reset also pulls the RESET pin low. An internal resistor to VDD pulls the RESET pin high. A steering diode between the RESET and VDD pins discharges any RESET pin voltage when power is removed from the MCU. The RESET pin contains an internal Schmitt trigger to improve its noise immunity as an input. Refer to Section 8. Resets and Interrupts for more information. 1.4.4 IRQ/VPP The external interrupt/programming voltage pin (IRQ/VPP) drives the asynchronous IRQ interrupt function of the CPU. Additionally, it is used to program the user EPROM and mask option register. (See Section 2. Memory and Section 5. External Interrupt Module (IRQ).) The LEVEL bit in the mask option register provides negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering for the interrupt function. If level-sensitive triggering is selected, the IRQ/VPP input requires an external resistor to VDD for wired-OR operation. If the IRQ/VPP pin is not used, it must be tied to the VDD supply. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Introduction Data Sheet 19 Introduction The IRQ/VPP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The voltage on this pin should not exceed VDD except when the pin is being used for programming the EPROM. NOTE: The mask option register can enable the PA0­PA3 pins to function as external interrupt pins. 1.4.5 PA0­PA7 These eight input/output (I/O) lines comprise port A, a general-purpose bidirectional I/O port. (See Section 5. External Interrupt Module (IRQ) for information on PA0­PA3 external interrupts.) 1.4.6 PB2 and PB3 These two I/O lines comprise port B, a general-purpose bidirectional I/O port. Data Sheet 20 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Introduction MOTOROLA Data Sheet - MC68HC705KJ1 MC68HC705KJ1 Section 2. Memory 2.1 Introduction This section provides: · Memory map (Figure 2-1) · Summary of the input/output registers (Figure 2-2) · Description of: ­ Random-access memory (RAM) ­ EPROM/OTPROM (electrically programmable read-only memory/one-time programmable read-only memory) ­ Mask option register Memory features include: · 1232 Bytes of User EPROM, Plus Eight Bytes for User Vectors · 64 Bytes of User RAM 2.2 Unimplemented Memory Locations Accessing an unimplemented location can have unpredictable effects on MCU operation. In Figure 2-2 and in register figures in this document, unimplemented locations are shaded. 2.3 Reserved Memory Locations Accessing a reserved location can have unpredictable effects on MCU operation. In Figure 2-2 and in register figures in this document, reserved locations are marked with the word Reserved or with the letter R. 2.4 Memory Map See Figure 2-1. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Memory Data Sheet 21 Memory PORT A DATA REGISTER (PORTA) $0000 PORT B DATA REGISTER (PORTB) $0001 $0002 UNIMPLEMENTED $0003 DATA DIRECTION REGISTER A (DDRA) $0004 DATA DIRECTION REGISTER B (DDRB) $0005 $0006 UNIMPLEMENTED $0007 TIMER STATUS AND CONTROL REGISTER (TSCR) TIMER CONTROL REGISTER (TCR) $0009 IRQ STATUS AND CONTROL REGISTER (ISCR) $0000 $0008 $000A I/O REGISTERS 32 BYTES $000B $001F UNIMPLEMENTED $0020 $000F UNIMPLEMENTED 160 BYTES PULLDOWN REGISTER PORT A (PDRA) $0010 PULLDOWN REGISTER PORT B (PDRB) $00BF $0011 $0012 $00C0 RAM 64 BYTES UNIMPLEMENTED EPROM PROGRAMMING REGISTER (EPROG) $0018 $00FF $0017 $0100 UNIMPLEMENTED 512 BYTES $0019 $02FF UNIMPLEMENTED $0300 $001E EPROM 1232 BYTES RESERVED $001F COP REGISTER (COPR)(1) $07F0 MASK OPTION REGISTER (MOR) $07F1 $07CF $07D0 UNIMPLEMENTED 30 BYTES $07ED $07EE $07EF $07F2 RESERVED TEST ROM 2 BYTES $07F7 $07F0 TIMER INTERRUPT VECTOR HIGH $07FA $07FB SOFTWARE INTERRUPT VECTOR HIGH $07FC SOFTWARE INTERRUPT VECTOR LOW $07FD RESET VECTOR HIGH $07FE RESET VECTOR LOW $07FF $07F9 EXTERNAL INTERRUPT VECTOR HIGH REGISTERS AND EPROM 16 BYTES $07F8 TIMER INTERRUPT VECTOR LOW EXTERNAL INTERRUPT VECTOR LOW $07FF Note 1. Writing to bit 0 of $07F0 clears the COP watchdog. Figure 2-1. Memory Map Data Sheet MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 22 Memory MOTOROLA Memory Input/Output Register Summary 2.5 Input/Output Register Summary Addr. Register Name Bit 7 Port A Data Register Read: (PORTA) Write: See page 66. Reset: $0000 Read: Port B Data Register (PORTB) Write: See page 69. Reset: $0001 $0002 5 4 3 2 1 Bit 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 0 0 Unaffected by reset Refer to Section 7. Parallel I/O Ports (PORTS) PB3 Refer to Section 7. Parallel I/O Ports (PORTS) PB2 Unaffected by reset Unimplemented $0003 6 Unimplemented $0004 Data Direction Register A Read: DDRA7 (DDRA) Write: See page 66. Reset: 0 Read: $0005 Data Direction Register B (DDRB) Write: See page 69. Reset: 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 0 0 0 0 0 0 0 0 RTIF Refer to Section 7. Parallel I/O Ports (PORTS) 0 0 TOIE RTIE DDRB3 0 0 TOFR 0 0 0 DDRA0 DDRB2 0 DDRA1 RTIFR Refer to Section 7. Parallel I/O Ports (PORTS) 0 0 RT1 RT0 $0006 Unimplemented $0007 Unimplemented TOF $0008 Timer Status and Control Read: Register (TSCR) Write: See page 83. Reset: 0 0 0 0 0 0 1 1 Timer Counter Register Read: (TCR) Write: See page 84. Reset: TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 0 0 0 0 0 0 0 0 0 0 0 IRQF 0 0 0 0 0 0 0 $0009 $000A IRQ Status and Control Read: Register (ISCR) Write: See page 57. Reset: IRQE 1 R = Unimplemented 0 IRQR R = Reserved 0 0 U = Unaffected Figure 2-2. I/O Register Summary (Sheet 1 of 2) MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Memory Data Sheet 23 Memory Addr. Register Name $000B Bit 7 6 5 4 3 2 1 Bit 0 PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0 0 0 0 0 0 0 0 0 PDIB3 PDIB2 0 0 0 ELAT MPGM EPGM Unimplemented $000F Unimplemented $0010 Pulldown Register Port A Read: (PDRA) Write: See page 68. Reset: Read: Pulldown Register Port B (PDRB) Write: See page 71. $0011 Refer to Section 7. Parallel I/O Ports (PORTS) Refer to Section 7. Parallel I/O Ports (PORTS) Reset: 0 0 0 0 0 $0017 Unimplemented 0 0 0 0 0 $0018 EPROM Programming Read: Register (EPROG) Write: See page 26. Reset: R R R R 0 0 0 0 0 0 0 0 R R R R R R R R $0012 Unimplemented $0019 Unimplemented $001E Unimplemented $001F Reserved Read: COP Register (COPR) Write: See page 32. Reset: $07F0 $07F1 Read: Mask Option Register (MOR) Write: See page 27. Reset: COPC U U U U U U U 0 SOSCD EPMSEC OSCRES SWAIT PDI PIRQ LEVEL COPEN Unaffected by reset = Unimplemented R = Reserved U = Unaffected Figure 2-2. I/O Register Summary (Sheet 2 of 2) Data Sheet MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 24 Memory MOTOROLA Memory RAM 2.6 RAM The 64 addresses from $00C0 to $00FF serve as both the user RAM and the stack RAM. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements when the CPU stores a byte on the stack and increments when the CPU retrieves a byte from the stack. NOTE: Be careful when using nested subroutines or multiple interrupt levels. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. 2.7 EPROM/OTPROM An MCU with a quartz window has 1240 bytes of erasable, programmable ROM (EPROM). The quartz window allows EPROM erasure with ultraviolet light. NOTE: Keep the quartz window covered with an opaque material except when erasing the MCU. Ambient light can affect MCU operation. In an MCU without the quartz window, the EPROM cannot be erased and serves as 1240 bytes of one-time programmable ROM (OTPROM). The following addresses are user EPROM/OTPROM locations: · $0300­$07CF · $07F8­$07FF, used for user-defined interrupt and reset vectors The COP register (COPR) is an EPROM/OTPROM location at address $07F0. The mask option register (MOR) is an EPROM/OTPROM location at address $07F1. 2.7.1 EPROM/OTPROM Programming The two ways to program the EPROM/OTPROM are: · Manipulating the control bits in the EPROM programming register to program the EPROM/OTPROM on a byte-by-byte basis · Programming the EPROM/OTPROM with the M68HC705J M68HC705J In-Circuit Simulator (M68HC705JICS M68HC705JICS) available from Motorola MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Memory Data Sheet 25 Memory 2.7.2 EPROM Programming Register The EPROM programming register (EPROG) contains the control bits for programming the EPROM/OTPROM. Address: $0018 Bit 7 Read: 6 5 4 3 0 0 0 0 0 R R R R 0 0 0 0 R = Reserved Write: Reset: 0 = Unimplemented 2 1 Bit 0 ELAT MPGM EPGM 0 0 0 Figure 2-3. EPROM Programming Register (EPROG) ELAT - EPROM Bus Latch Bit This read/write bit latches the address and data buses for EPROM/OTPROM programming. Clearing the ELAT bit automatically clears the EPGM bit. EPROM/OTPROM data cannot be read while the ELAT bit is set. Reset clears the ELAT bit. 1 = Address and data buses configured for EPROM/OTPROM programming the EPROM 0 = Address and data buses configured for normal operation MPGM - MOR Programming Bit This read/write bit applies programming power from the IRQ/VPP pin to the mask option register. Reset clears MPGM. 1 = Programming voltage applied to MOR 0 = Programming voltage not applied to MOR EPGM - EPROM Programming Bit This read/write bit applies the voltage from the IRQ/VPP pin to the EPROM. To write the EPGM bit, the ELAT bit must be set already. Reset clears EPGM. 1 = Programming voltage (IRQ/VPP pin) applied to EPROM 0 = Programming voltage (IRQ/VPP pin) not applied to EPROM NOTE: Writing logic 1s to both the ELAT and EPGM bits with a single instruction sets ELAT and clears EPGM. ELAT must be set first by a separate instruction. Bits [7:3] - Reserved Take the following steps to program a byte of EPROM/OTPROM: 1. Apply the programming voltage, VPP, to the IRQ/VPP pin. 2. Set the ELAT bit. 3. Write to any EPROM/OTPROM address. 4. Set the EPGM bit and wait for a time, tEPGM. 5. Clear the ELAT bit. Data Sheet MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 26 Memory MOTOROLA Memory Mask Option Register 2.7.3 EPROM Erasing The erased state of an EPROM bit is logic 0. Erase the EPROM by exposing it to 15 Ws/cm2 of ultraviolet light with a wavelength of 2537 angstroms. Position the ultraviolet light source one inch from the EPROM. Do not use a shortwave filter. 2.8 Mask Option Register The mask option register (MOR) is an EPROM/OTPROM byte that controls the following options: · COP watchdog (enable or disable) · External interrupt pin triggering (edge-sensitive only or edge- and level-sensitive) · Port A external interrupts (enable or disable) · Port pulldown resistors (enable or disable) · STOP instruction (stop mode or halt mode) · Crystal oscillator internal resistor (enable or disable) · EPROM security (enable or disable) · Short oscillator delay (enable or disable) Take the following steps to program the mask option register (MOR): 1. Apply the programming voltage, VPP, to the IRQ/VPP pin. 2. Write to the MOR. 3. Set the MPGM bit and wait for a time, tMPGM. 4. Clear the MPGM bit. 5. Reset the MCU. Address: $07F1 Bit 7 Read: Write: 6 5 4 3 2 1 Bit 0 SOSCD EPMSEC OSCRES SWAIT SWPDI PIRQ LEVEL COPEN Reset: Unaffected by reset Figure 2-4. Mask Option Register (MOR) SOSCD - Short Oscillator Delay Bit The SOSCD bit controls the oscillator stabilization counter. The normal stabilization delay following reset or exit from stop mode is 4064 tcyc. Setting SOSCD enables a 128 tcyc stabilization delay. 1 = Short oscillator delay enabled 0 = Short oscillator delay disabled MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Memory Data Sheet 27 Memory EPMSEC - EPROM Security Bit The EPMSEC bit controls access to the EPROM/OTPROM. 1 = External access to EPROM/OTPROM denied 0 = External access to EPROM/OTPROM not denied OSCRES - Oscillator Internal Resistor Bit The OSCRES bit enables a 2-M internal resistor in the oscillator circuit. 1 = Oscillator internal resistor enabled 0 = Oscillator internal resistor disabled NOTE: Program the OSCRES bit to logic 0 in devices using low-speed crystal or RC oscillators with external resistor. SWAIT - Stop-to-Wait Conversion Bit The SWAIT bit enables halt mode. When the SWAIT bit is set, the CPU interprets the STOP instruction as a WAIT instruction, and the MCU enters halt mode. Halt mode is the same as wait mode, except that an oscillator stabilization delay of 1 to 4064 tcyc occurs after exiting halt mode. 1 = Halt mode enabled 0 = Halt mode not enabled SWPDI - Software Pulldown Inhibit Bit The SWPDI bit inhibits software control of the I/O port pulldown devices. The SWPDI bit overrides the pulldown inhibit bits in the port pulldown inhibit registers. 1 = Software pulldown control inhibited 0 = Software pulldown control not inhibited PIRQ - Port A External Interrupt Bit The PIRQ bit enables the PA0­PA3 pins to function as external interrupt pins. 1 = PA0­PA3 enabled as external interrupt pins 0 = PA0­PA3 not enabled as external interrupt pins LEVEL -External Interrupt Sensitivity Bit The LEVEL bit controls external interrupt triggering sensitivity. 1 = External interrupts triggered by active edges and active levels 0 = External interrupts triggered only by active edges COPEN - COP Enable Bit The COPEN bit enables the COP watchdog. 1 = COP watchdog enabled 0 = COP watchdog disabled Data Sheet MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 28 Memory MOTOROLA Memory EPROM Programming Characteristics 2.9 EPROM Programming Characteristics Table 2-1. EPROM Programming Characteristics(1) Characteristic Symbol Min Typ Max Programming Voltage IRQ/VPP VPP 16.0 16.5 17.0 Programming Current IRQ/VPP IPP -¦ 3.0 10.0 4 4 - - - - Programming Time Per Array Byte MOR tEPGM tMPGM Unit V mA ms 1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = ­40°C to +85°C MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Memory Data Sheet 29 Memory Data Sheet MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 30 Memory MOTOROLA Data Sheet - MC68HC705KJ1 MC68HC705KJ1 Section 3. Computer Operating Properly Module (COP) 3.1 Introduction The computer operating properly (COP) watchdog resets the MCU in case of software failure. Software that is operating properly periodically services the COP watchdog and prevents COP reset. The COP watchdog function is programmable by the COPEN bit in the mask option register. 3.2 Features The computer operating properly module (COP) includes these features: · Protection from runaway software · Wait mode and halt mode operations 3.3 Operation Operation of the COP module is discussed here. 3.3.1 COP Watchdog Timeout Four counter stages at the end of the timer make up the COP watchdog. The COP resets the MCU if the timeout period occurs before the COP watchdog timer is cleared by application software and the IRQ/VPP pin voltage is between VSS and VDD. Periodically clearing the counter starts a new timeout period and prevents COP reset. A COP watchdog timeout indicates that the software is not executing instructions in the correct sequence. NOTE: The internal clock drives the COP watchdog. Therefore, the COP watchdog cannot generate a reset for errors that cause the internal clock to stop. The COP watchdog depends on a power supply voltage at or above a minimum specification and is not guaranteed to protect against brownout. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Computer Operating Properly Module (COP) Data Sheet 31 Computer Operating Properly Module (COP) 3.3.2 COP Watchdog Timeout Period The COP watchdog timer function is implemented by dividing the output of the real-time interrupt circuit (RTI) by eight. The RTI select bits in the timer status and control register control RTI output, and the selected output drives the COP watchdog. (See timer status and control register in Section 9. Multifunction Timer Module.) NOTE: The minimum COP timeout period is seven times the RTI period. The COP is cleared asynchronously with the value in the RTI divider; hence, the COP timeout period will vary between 7x and 8x the RTI period. 3.3.3 Clearing the COP Watchdog To clear the COP watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the COP register at location $07F0 (see Figure 3-1). Clearing the COP bit disables the COP watchdog timer regardless of the IRQ/VPP pin voltage. If the main program executes within the COP timeout period, the clearing routine should be executed only once. If the main program takes longer than the COP timeout period, the clearing routine must be executed more than once. NOTE: Place the clearing routine in the main program and not in an interrupt routine. Clearing the COP watchdog in an interrupt routine might prevent COP watchdog timeouts even though the main program is not operating properly. 3.4 Interrupts The COP watchdog does not generate interrupts. 3.5 COP Register The COP register (COPR) is a write-only register that returns the contents of EPROM location $07F0 when read. Address: $07F0 Bit 7 6 5 4 3 2 1 U U U U U U U Bit 0 Read: Write: Reset: COPC = Unimplemented 0 U = Unaffected Figure 3-1. COP Register (COPR) COPC - COP Clear Bit This write-only bit resets the COP watchdog. Reading address $07F0 returns undefined results. Data Sheet 32 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Computer Operating Properly Module (COP) MOTOROLA Computer Operating Properly Module (COP) Low-Power Modes 3.6 Low-Power Modes The STOP and WAIT instructions have the following effects on the COP watchdog. 3.6.1 Stop Mode The STOP instruction clears the COP watchdog counter and disables the clock to the COP watchdog. NOTE: To prevent the STOP instruction from disabling the COP watchdog, program the stop-to-wait conversion bit (SWAIT) in the mask option register to logic 1. Upon exit from stop mode by external reset: · The counter begins counting from $0000. · The counter is cleared again after the oscillator stabilization delay and begins counting from $0000 again. Upon exit from stop mode by external interrupt: · · NOTE: The counter begins counting from $0000. The counter is not cleared again after the oscillator stabilization delay and continues counting throughout the oscillator stabilization delay. Immediately after exiting stop mode by external interrupt, service the COP to ensure a full COP timeout period. 3.6.2 Wait Mode The WAIT instruction has no effect on the COP watchdog. NOTE: To prevent a COP timeout during wait mode, exit wait mode periodically to service the COP. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Computer Operating Properly Module (COP) Data Sheet 33 Computer Operating Properly Module (COP) Data Sheet 34 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Computer Operating Properly Module (COP) MOTOROLA Data Sheet - MC68HC705KJ1 MC68HC705KJ1 Section 4. Central Processor Unit (CPU) 4.1 Introduction The central processor unit (CPU) consists of a CPU control unit, an arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit fetches and decodes instructions. The ALU executes the instructions. The CPU registers contain data, addresses, and status bits that reflect the results of CPU operations. 4.2 Features Features of the CPU include: · 4.0-MHz bus frequency on standard part · 8-bit accumulator · 8-bit index register · 11-bit program counter · 6-bit stack pointer · Condition code register with five status flags · 62 instructions · 8 addressing modes · Power-saving stop, wait, halt, and data-retention modes The programming model is shown in Figure 4-1. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Central Processor Unit (CPU) Data Sheet 35 Central Processor Unit (CPU) ARITHMETIC/LOGIC UNIT CPU CONTROL UNIT 7 6 5 4 3 2 1 0 ACCUMULATOR (A) 7 6 5 4 3 2 1 0 INDEX REGISTER (X) 15 14 13 12 11 10 9 8 7 6 0 0 0 1 1 15 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 0 5 4 3 2 1 0 STACK POINTER (SP) 5 4 3 2 1 0 0 PROGRAM COUNTER (PC) 7 6 5 4 3 2 1 0 1 1 1 H I N Z C CONDITION CODE REGISTER (CCR) HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG Figure 4-1. Programming Model 4.3 CPU Control Unit The CPU control unit fetches and decodes instructions during program operation. The control unit selects the memory locations to read and write and coordinates the timing of all CPU operations. 4.4 Arithmetic/Logic Unit The arithmetic/logic unit (ALU) performs the arithmetic, logic, and manipulation operations decoded from the instruction set by the CPU control unit. The ALU produces the results called for by the program and sets or clears status and control bits in the condition code register (CCR). Data Sheet 36 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) CPU Registers 4.5 CPU Registers The M68HC05 M68HC05 CPU contains five registers that control and monitor MCU operation: · Accumulator · Index register · Stack pointer · Program counter · Condition code register CPU registers are not memory mapped. 4.5.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and results of ALU operations. Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Unaffected by reset Figure 4-2. Accumulator (A) 4.5.2 Index Register In the indexed addressing modes, the CPU uses the byte in the index register to determine the conditional address of the operand. The index register also can serve as a temporary storage location or a counter. Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Unaffected by reset Figure 4-3. Index Register (X) MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Central Processor Unit (CPU) Data Sheet 37 Central Processor Unit (CPU) 4.5.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset or after the reset stack pointer instruction (RSP), the stack pointer is preset to $00FF. The address in the stack pointer decrements after a byte is stacked and increments before a byte is unstacked. Bit 15 Read: 14 13 12 11 10 9 8 7 6 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 5 4 3 2 1 Bit 0 1 1 1 1 1 1 Write: Reset: = Unimplemented Figure 4-4. Stack Pointer (SP) The 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A subroutine uses two stack locations; an interrupt uses five locations. 4.5.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. The five most significant bits of the program counter are ignored and appear as 00000. Normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. Bit 15 Reset: 14 13 12 11 0 0 0 0 0 10 9 8 7 6 5 4 3 2 1 Bit 0 Loaded with vector from $07FE and $07FF Figure 4-5. Program Counter (PC) Data Sheet 38 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) CPU Registers 4.5.5 Condition Code Register The condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111. The condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. Bit 7 Read: 6 5 1 1 1 1 1 1 Write: Reset: 4 3 2 1 Bit 0 H I N Z C U 1 U U U = Unimplemented U = Unaffected Figure 4-6. Condition Code Register (CCR) H - Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an ADD or ADC operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. I - Interrupt Mask Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is logic 0, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. If an interrupt request occurs while the interrupt mask is logic 1, the interrupt request is latched. Normally, the CPU processes the latched interrupt request as soon as the interrupt mask is cleared again. A return from interrupt instruction (RTI) unstacks the CPU registers, restoring the interrupt mask to its cleared state. After any reset, the interrupt mask is set and can be cleared only by a software instruction. N - Negative Flag The CPU sets the negative flag when an ALU operation produces a negative result. Z - Zero Flag The CPU sets the zero flag when an ALU operation produces a result of $00. C - Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some logical operations and data manipulation instructions also clear or set the carry/borrow flag. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Central Processor Unit (CPU) Data Sheet 39 Central Processor Unit (CPU) 4.6 Instruction Set The MCU instruction set has 62 instructions and uses eight addressing modes. 4.6.1 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: · Inherent · Immediate · Direct · Extended · Indexed, no offset · Indexed, 8-bit offset · Indexed, 16-bit offset · Relative 4.6.1.1 Inherent Inherent instructions are those that have no operand, such as return-from-interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long. 4.6.1.2 Immediate Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. 4.6.1.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. 4.6.1.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. Data Sheet 40 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. 4.6.1.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000­$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or input/output (I/O) location. 4.6.1.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000­$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 4.6.1.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. 4.6.1.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Central Processor Unit (CPU) Data Sheet 41 Central Processor Unit (CPU) byte that gives a branching range of ­128 to +127 bytes from the address of the next location after the branch instruction. When using the Motorola assembler, the programmer does not need to calculate the offset because the assembler determines the proper offset and verifies that it is within the span of the branch. 4.6.2 Instruction Types The MCU instructions fall into the following five categories: · Register/memory instructions · Read-modify-write instructions · Jump/branch instructions · Bit manipulation instructions · Control instructions 4.6.2.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 4-1. Register/Memory Instructions Instruction Add Memory Byte and Carry Bit to Accumulator Mnemonic ADC Add Memory Byte to Accumulator ADD AND Memory Byte with Accumulator AND Bit Test Accumulator BIT Compare Accumulator CMP Compare Index Register with Memory Byte CPX EXCLUSIVE OR Accumulator with Memory Byte EOR Load Accumulator with Memory Byte LDA Load Index Register with Memory Byte LDX Multiply MUL OR Accumulator with Memory Byte ORA Subtract Memory Byte and Carry Bit from Accumulator SBC Store Accumulator in Memory STA Store Index Register in Memory Data Sheet 42 STX Subtract Memory Byte from Accumulator SUB MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set 4.6.2.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write instructions on registers with write-only bits. Table 4-2. Read-Modify-Write Instructions Instruction Mnemonic Arithmetic Shift Left (Same as LSL) ASL Arithmetic Shift Right ASR Bit Clear BCLR(1) Bit Set BSET(1) Clear Register CLR Complement (One's Complement) COM Decrement DEC Increment INC Logical Shift Left (Same as ASL) LSL Logical Shift Right LSR Negate (Two's Complement) NEG Rotate Left through Carry Bit ROL Rotate Right through Carry Bit ROR Test for Negative or Zero TST(2) 1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value. 4.6.2.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from ­128 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Central Processor Unit (CPU) Data Sheet 43 Central Processor Unit (CPU) to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. NOTE: Do not use BRCLR or BRSET instructions on registers with write-only bits. Table 4-3. Jump and Branch Instructions Instruction Mnemonic Branch if Carry Bit Clear BCC Branch if Carry Bit Set BCS Branch if Equal BEQ Branch if Half-Carry Bit Clear BHCC Branch if Half-Carry Bit Set BHCS Branch if Higher BHI Branch if Higher or Same BHS Branch if IRQ Pin High BIH Branch if IRQ Pin Low BIL Branch if Lower BLO Branch if Lower or Same BLS Branch if Interrupt Mask Clear BMC Branch if Minus BMI Branch if Interrupt Mask Set BMS Branch if Not Equal BNE Branch if Plus BPL Branch Always BRA Branch if Bit Clear Branch Never BRCLR BRN Branch if Bit Set BRSET Branch to Subroutine Unconditional Jump 44 JMP Jump to Subroutine Data Sheet BSR JSR MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set 4.6.2.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 4-4. Bit Manipulation Instructions Instruction Bit Clear Mnemonic BCLR Branch if Bit Clear BRCLR Branch if Bit Set BRSET Bit Set NOTE: BSET Do not use bit manipulation instructions on registers with write-only bits. 4.6.2.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 4-5. Control Instructions Instruction Mnemonic Clear Carry Bit CLC Clear Interrupt Mask CLI No Operation NOP Reset Stack Pointer RSP Return from Interrupt RTI Return from Subroutine RTS Set Carry Bit SEC Set Interrupt Mask Stop Oscillator and Enable IRQ Pin SEI STOP Software Interrupt SWI Transfer Accumulator to Index Register TAX Transfer Index Register to Accumulator TXA Stop CPU Clock and Enable Interrupts WAIT MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Central Processor Unit (CPU) Data Sheet 45 Central Processor Unit (CPU) 4.6.3 Instruction Set Summary ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X - IMM DIR EXT IX2 IX1 IX 2 A9 ii B9 dd 3 C9 hh ll 4 D9 ee ff 5 4 E9 ff 3 F9 - IMM DIR EXT IX2 IX1 IX 2 AB ii BB dd 3 CB hh ll 4 DB ee ff 5 4 EB ff 3 FB - - IMM DIR EXT IX2 IX1 IX 2 A4 ii B4 dd 3 C4 hh ll 4 D4 ee ff 5 4 E4 ff 3 F4 DIR INH INH IX1 IX 38 48 58 68 78 dd DIR INH INH IX1 IX 37 47 57 67 77 dd REL Effect on CCR Description H I N Z C A (A) + (M) + (C) Add with Carry A (A) + (M) Add without Carry A (A) (M) Logical AND Arithmetic Shift Left (Same as LSL) C 0 b7 ASR opr ASRA ASRX ASR opr,X ASR ,X Branch if Carry Bit Clear - - b0 Arithmetic Shift Right BCC rel - C b7 - - b0 PC (PC) + 2 + rel ? C = 0 ff 5 3 3 6 5 5 3 3 6 5 24 rr 3 DIR (b0) DIR (b1) DIR (b2) DIR (b3) - - - - - DIR (b4) DIR (b5) DIR (b6) DIR (b7) 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 PC (PC) + 2 + rel ? C = 1 - - - - - REL 25 rr 3 Mn 0 - - - - - ff Cycles Opcode ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X Operation Address Mode Source Form Operand Table 4-6. Instruction Set Summary (Sheet 1 of 6) BCLR n opr Clear Bit n BCS rel Branch if Carry Bit Set (Same as BLO) BEQ rel Branch if Equal PC (PC) + 2 + rel ? Z = 1 - - - - - REL 27 rr 3 BHCC rel Branch if Half-Carry Bit Clear PC (PC) + 2 + rel ? H = 0 - - - - - REL 28 rr 3 BHCS rel Branch if Half-Carry Bit Set PC (PC) + 2 + rel ? H = 1 - - - - - REL 29 rr 3 BHI rel Branch if Higher PC (PC) + 2 + rel ? C Z = 0 - - - - - REL 22 rr 3 BHS rel Branch if Higher or Same BIH rel Branch if IRQ Pin High Data Sheet 46 PC (PC) + 2 + rel ? C = 0 - - - - - REL 24 rr 3 PC (PC) + 2 + rel ? IRQ = 1 - - - - - REL 2F rr 3 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set H I N Z C Operand Cycles BIL rel Opcode Source Form Address Mode Table 4-6. Instruction Set Summary (Sheet 2 of 6) - - - - - REL 2E rr 3 - - - IMM DIR EXT IX2 IX1 IX 2 A5 ii B5 dd 3 C5 hh ll 4 D5 ee ff 5 4 E5 ff 3 F5 - - - - - REL 25 rr 3 PC (PC) + 2 + rel ? C Z = 1 - - - - - REL 23 rr 3 REL 2C rr 3 Operation Description PC (PC) + 2 + rel ? IRQ = 0 Branch if IRQ Pin Low Effect on CCR BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X Bit Test Accumulator with Memory Byte BLO rel Branch if Lower (Same as BCS) BLS rel Branch if Lower or Same BMC rel Branch if Interrupt Mask Clear PC (PC) + 2 + rel ? I = 0 BMI rel Branch if Minus PC (PC) + 2 + rel ? N = 1 - - - - - REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC (PC) + 2 + rel ? I = 1 - - - - - REL 2D rr 3 BNE rel Branch if Not Equal PC (PC) + 2 + rel ? Z = 0 - - - - - REL 26 rr 3 BPL rel Branch if Plus PC (PC) + 2 + rel ? N = 0 - - - - - REL 2A rr 3 BRA rel Branch Always PC (PC) + 2 + rel ? 1 = 1 - - - - - BRCLR n opr rel Branch if Bit n Clear BRN rel Branch Never BRSET n opr rel Branch if Bit n Set BSET n opr (A) (M) PC (PC) + 2 + rel ? C = 1 - - - - - REL 20 rr 3 DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 01 03 05 07 09 0B 0D 0F dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 REL 21 rr 3 DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 00 02 04 06 08 0A 0C 0E dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 DIR (b0) DIR (b1) DIR (b2) DIR (b3) - - - - - DIR (b4) DIR (b5) DIR (b6) DIR (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 PC (PC) + 2; push (PCL) SP (SP) ­ 1; push (PCH) SP (SP) ­ 1 PC (PC) + rel - - - - - REL AD rr 6 PC (PC) + 2 + rel ? Mn = 0 PC (PC) + 2 + rel ? 1 = 0 PC (PC) + 2 + rel ? Mn = 1 Mn 1 Set Bit n - - - - - - - - - - - - - BSR rel Branch to Subroutine CLC Clear Carry Bit C0 - - - - 0 INH 98 2 CLI Clear Interrupt Mask I0 - 0 - - - INH 9A 2 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Central Processor Unit (CPU) Data Sheet 47 Central Processor Unit (CPU) CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Data Sheet 48 DIR INH INH IX1 IX 3F 4F 5F 6F 7F dd - - IMM DIR EXT IX2 IX1 IX 2 A1 ii B1 dd 3 C1 hh ll 4 D1 ee ff 5 4 E1 ff 3 F1 - - DIR INH INH IX1 IX 33 43 53 63 73 - - IMM DIR EXT IX2 IX1 IX 2 A3 ii B3 dd 3 C3 hh ll 4 D3 ee ff 5 4 E3 ff 3 F3 - - DIR INH INH IX1 IX 3A 4A 5A 6A 7A - IMM DIR EXT IX2 IX1 IX 2 A8 ii B8 dd 3 C8 hh ll 4 D8 ee ff 5 4 E8 ff 3 F8 - DIR INH INH IX1 IX 3C 4C 5C 6C 7C DIR EXT IX2 IX1 IX BC dd 2 CC hh ll 3 DC ee ff 4 3 EC ff 2 FC Effect on CCR H I N Z C M $00 A $00 X $00 M $00 M $00 Clear Byte Compare Accumulator with Memory Byte Complement Byte (One's Complement) Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Unconditional Jump M (M) = $FF ­ (M) A (A) = $FF ­ (A) X (X) = $FF ­ (X) M (M) = $FF ­ (M) M (M) = $FF ­ (M) (X) ­ (M) M (M) ­ 1 A (A) ­ 1 X (X) ­ 1 M (M) ­ 1 M (M) ­ 1 Decrement Byte Increment Byte (A) ­ (M) A (A) (M) M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 PC Jump Address - - 0 1 - - - - - 1 - - - - - - ff dd ff dd ff dd ff Cycles Description Operand CLR opr CLRA CLRX CLR opr,X CLR ,X Operation Opcode Source Form Address Mode Table 4-6. Instruction Set Summary (Sheet 3 of 6) 5 3 3 6 5 5 3 3 6 5 5 3 3 6 5 5 3 3 6 5 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Instruction Set LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) ­ 1 Push (PCH); SP (SP) ­ 1 PC Effective Address Jump to Subroutine A (M) Load Accumulator with Memory Byte X (M) Load Index Register with Memory Byte 2 A6 ii B6 dd 3 C6 hh ll 4 D6 ee ff 5 4 E6 ff 3 F6 - IMM DIR EXT IX2 IX1 IX 2 AE ii BE dd 3 CE hh ll 4 DE ee ff 5 4 EE ff 3 FE DIR INH INH IX1 IX 38 48 58 68 78 dd 0 b7 DIR INH INH IX1 IX 34 44 54 64 74 dd Unsigned Multiply 0 C b7 0 - - - 0 INH 42 NEG opr NEGA NEGX NEG opr,X NEG ,X - - DIR INH INH IX1 IX 30 40 50 60 70 NOP INH 9D M ­(M) = $00 ­ (M) A ­(A) = $00 ­ (A) X ­(X) = $00 ­ (X) M ­(M) = $00 ­ (M) M ­(M) = $00 ­ (M) No Operation - - - - - A (A) (M) Logical OR Accumulator with Memory Rotate Byte Left through Carry Bit - - 0 b0 X : A (X) × (A) Negate Byte (Two's Complement) - - b0 - - C - - b7 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Central Processor Unit (CPU) b0 - ff ff Cycles - IMM DIR EXT IX2 IX1 IX - - C Logical Shift Left (Same as ASL) MUL MOTOROLA BD dd 5 CD hh ll 6 DD ee ff 7 6 ED ff 5 FD - - Description Logical Shift Right ROL opr ROLA ROLX ROL opr,X ROL ,X - - - - - DIR EXT IX2 IX1 IX Effect on CCR H I N Z C LSR opr LSRA LSRX LSR opr,X LSR ,X ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X Opcode JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X Operation Address Mode Source Form Operand Table 4-6. Instruction Set Summary (Sheet 4 of 6) 5 3 3 6 5 5 3 3 6 5 1 1 dd ff 5 3 3 6 5 2 IMM DIR EXT IX2 IX1 IX AA BA CA DA EA FA ii dd hh ll ee ff ff DIR INH INH IX1 IX 39 49 59 69 79 dd ff 2 3 4 5 4 3 5 3 3 6 5 Data Sheet 49 Central Processor Unit (CPU) DIR INH INH IX1 IX 36 46 56 66 76 dd INH 9C 2 INH 80 9 - - - - - INH 81 6 - - IMM DIR EXT IX2 IX1 IX 2 A2 ii B2 dd 3 C2 hh ll 4 D2 ee ff 5 4 E2 ff 3 F2 Effect on CCR Description H I N Z C ROR opr RORA RORX ROR opr,X ROR ,X Rotate Byte Right through Carry Bit RSP Reset Stack Pointer SP $00FF RTI Return from Interrupt SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) RTS Return from Subroutine SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) C b7 - - b0 - - - - - SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X Subtract Memory Byte and Carry Bit from Accumulator SEC Set Carry Bit C1 - - - - 1 INH 99 SEI Set Interrupt Mask I1 - 1 - - - INH ff 9B STA opr STA opr STA opr,X STA opr,X STA ,X Stop Oscillator and Enable IRQ Pin STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SWI Data Sheet 50 M (A) M (X) Store Index Register In Memory Subtract Memory Byte from Accumulator Software Interrupt A (A) ­ (M) - DIR EXT IX2 IX1 IX B7 C7 D7 E7 F7 - 0 - - - Store Accumulator in Memory STOP A (A) ­ (M) ­ (C) INH - - - - - PC (PC) + 1; Push (PCL) SP (SP) ­ 1; Push (PCH) SP (SP) ­ 1; Push (X) SP (SP) ­ 1; Push (A) - 1 - - - SP (SP) ­ 1; Push (CCR) SP (SP) ­ 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte 5 3 3 6 5 2 2 dd hh ll ee ff ff 8E - - Cycles Operand Operation Opcode Source Form Address Mode Table 4-6. Instruction Set Summary (Sheet 5 of 6) 4 5 6 5 4 2 dd hh ll ee ff ff 4 5 6 5 4 DIR EXT IX2 IX1 IX BF CF DF EF FF IMM DIR EXT IX2 IX1 IX 2 A0 ii B0 dd 3 C0 hh ll 4 D0 ee ff 5 4 E0 ff 3 F0 INH 83 1 0 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Central Processor Unit (CPU) MOTOROLA Central Processor Unit (CPU) Opcode Map Transfer Accumulator to Index Register TST opr TSTA TSTX TST opr,X TST ,X Test Memory Byte for Negative or Zero TXA Transfer Index Register to Accumulator WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n X (A) 97 2 dd 4 3 3 5 4 Stop CPU Clock and Enable Interrupts opr PC PCH PCL REL rel rr SP X Z # () ­( ) ? : - 3D 4D 5D 6D 7D INH 9F 2 - 0 - - - A (X) DIR INH INH IX1 IX - - - - - (M) ­ $00 Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit INH Effect on CCR Cycles - - - - - Description Opcode TAX Operation Operand H I N Z C Source Form Address Mode Table 4-6. Instruction Set Summary (Sheet 6 of 6) INH 8F 2 - - - ff Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected 4.7 Opcode Map See Table 4-7. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Central Processor Unit (CPU) Data Sheet 51 Bit Manipulation DIR DIR MSB LSB 0 1 2 3 4 6 MOTOROLA MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Central Processor Unit (CPU) 5 7 8 9 A B C D E F 0 1 Branch REL DIR 2 3 Read-Modify-Write INH INH IX1 4 5 6 IX 7 5 5 3 5 3 3 6 5 BRSET0 BSET0 BRA NEG NEGA NEGX NEG NEG 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 BRCLR0 BCLR0 BRN 3 DIR 2 DIR 2 REL 1 5 5 3 11 BRSET1 BSET1 BHI MUL 3 DIR 2 DIR 2 REL 1 INH 5 5 3 5 3 3 6 5 BRCLR1 BCLR1 BLS COM COMA COMX COM COM 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 5 3 3 6 5 BRSET2 BSET2 BCC LSR LSRA LSRX LSR LSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR2 BCLR2 BCS/BLO 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET3 BSET3 BNE ROR RORA RORX ROR ROR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR3 BCLR3 BEQ ASR ASRA ASRX ASR ASR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET4 BSET4 BHCC ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR4 BCLR4 BHCS ROL ROLA ROLX ROL ROL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET5 BSET5 BPL DEC DECA DECX DEC DEC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR5 BCLR5 BMI 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET6 BSET6 BMC INC INCA INCX INC INC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 4 3 3 5 4 BRCLR6 BCLR6 BMS TST TSTA TSTX TST TST 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 3 5 5 BIL BSET7 BRSET7 REL DIR 2 3 DIR 2 1 5 5 3 5 3 3 6 5 BRCLR7 BCLR7 BIH CLR CLRA CLRX CLR CLR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 INH = Inherent IMM = Immediate DIR = Direct EXT = Extended REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset Control INH INH 8 IMM A 9 9 RTI INH 6 RTS INH 2 2 2 10 SWI INH 2 2 2 2 1 1 1 1 1 1 1 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2 2 STOP INH 2 2 WAIT TXA INH 1 INH DIR B 2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 2 2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 2 6 BSR REL 2 2 LDX 2 IMM 2 2 MSB LSB LSB of Opcode in Hexadecimal Register/Memory EXT IX2 0 3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3 0 C 4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3 D 5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2 IX1 IX E F 4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1 MSB LSB 3 0 SUB IX 3 CMP IX 3 SBC 2 IX 3 3 CPX IX 3 AND 4 IX 3 5 BIT IX 3 6 LDA IX 4 STA 7 IX 3 8 EOR IX 3 9 ADC IX 3 ORA A IX 3 B ADD IX 2 JMP IX 5 JSR C D IX 3 E LDX IX 4 STX IX MSB of Opcode in Hexadecimal 5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode 1 F Central Processor Unit (CPU) Data Sheet 52 Table 4-7. Opcode Map Data Sheet - MC68HC705KJ1 MC68HC705KJ1 Section 5. External Interrupt Module (IRQ) 5.1 Introduction The external interrupt (IRQ) module provides asynchronous external interrupts to the CPU. The following sources can generate external interrupts: · IRQ/VPP pin · PA0­PA3 pins 5.2 Features The external interrupt module (IRQ) includes these features: · Dedicated external interrupt pin (IRQ/VPP) · Selectable interrupt on four input/output (I/O) pins (PA0­PA3) · Programmable edge-only or edge- and level-interrupt sensitivity 5.3 Operation The interrupt request/programming voltage pin (IRQ/VPP) and port A pins 0­3 (PA0­PA3) provide external interrupts. The PIRQ bit in the mask option register (MOR) enables PA0­PA3 as IRQ interrupt sources, which are combined into a single OR'ing function to be latched by the IRQ latch. Figure 5-1 shows the structure of the IRQ module. After completing its current instruction, the CPU tests the IRQ latch. If the IRQ latch is set, the CPU then tests the I bit in the condition code register and the IRQE bit in the IRQ status and control register. If the I bit is clear and the IRQE bit is set, the CPU then begins the interrupt sequence. This interrupt is serviced by the interrupt service routine located at $07FA and $07FB. The CPU clears the IRQ latch while it fetches the interrupt vector, so that another external interrupt request can be latched during the interrupt service routine. As soon as the I bit is cleared during the return from interrupt, the CPU can recognize the new interrupt request. Figure 5-3 shows the sequence of events caused by an interrupt. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA External Interrupt Module (IRQ) Data Sheet 53 External Interrupt Module (IRQ) TO BIH & BIL INSTRUCTION PROCESSING IRQ LEVEL-SENSITIVE TRIGGER (MOR LEVEL BIT) IRQF VDD EXTERNAL INTERRUPT REQUEST D IRQ Q LATCH CK PA3 PA2 PA1 PA0 IRQE CLR PIRQ (MOR) RESET IRQ VECTOR FETCH IRQR Figure 5-1. IRQ Module Block Diagram Addr. $000A Register Name Bit 7 IRQ Status and Control Read: Register (ISCR) Write: See page 57. Reset: IRQE 1 6 5 0 0 4 3 2 0 IRQF 0 R 0 0 0 = Unimplemented R 1 Bit 0 0 0 IRQR 0 0 0 0 = Reserved Figure 5-2. IRQ Module I/O Register Summary 5.3.1 IRQ/VPP Pin An interrupt signal on the IRQ/VPP pin latches an external interrupt request. The LEVEL bit in the mask option register provides negative edge-sensitive triggering or both negative edge-sensitive and low level-sensitive triggering for the interrupt function. If edge- and level-sensitive triggering is selected, a falling edge or a low level on the IRQ/VPP pin latches an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR external interrupt sources. An external interrupt request is latched as long as any source is holding the IRQ/VPP pin low. If level-sensitive triggering is selected, the IRQ/VPP input requires an external resistor to VDD for wired-OR operation. If the IRQ/VPP pin is not used, it must be tied to the VDD supply. Data Sheet 54 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 External Interrupt Module (IRQ) MOTOROLA External Interrupt Module (IRQ) Operation FROM RESET YES I BIT SET? NO EXTERNAL INTERRUPT? YES CLEAR IRQ LATCH. NO TIMER INTERRUPT? YES STACK PCL, PCH, X, A, CCR. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. NO FETCH NEXT INSTRUCTION. SWI INSTRUCTION? YES NO RTI INSTRUCTION? YES NO UNSTACK CCR, A, X, PCH, PCL. EXECUTE INSTRUCTION. Figure 5-3. Interrupt Flowchart If edge-sensitive-only triggering is selected, a falling edge on the IRQ/VPP pin latches an external interrupt request. A subsequent external interrupt request can be latched only after the voltage level on the IRQ/VPP pin returns to logic 1 and then falls again to logic 0. The IRQ/VPP pin contains an internal Schmitt trigger as part of its input to improve noise immunity. The voltage on this pin can affect the mode of operation and should not exceed VDD. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA External Interrupt Module (IRQ) Data Sheet 55 External Interrupt Module (IRQ) 5.3.2 Optional External Interrupts The inputs for the lower four bits of port A (PA0­PA3) can be connected to the IRQ pin input of the CPU if enabled by the PIRQ bit in the mask option register. This capability allows keyboard scan applications where the transitions or levels on the I/O pins will behave the same as the IRQ/VPP pin except for the inverted phase (logic 1, rising edge). The active state of the IRQ/VPP pin is a logic 0 (falling edge). The PA0­PA3 pins are selected as a group to function as IRQ interrupts and are enabled by the IRQE bit in the IRQ status and control register. The PA0­PA3 pins can be positive-edge triggered only or positive-edge and high-level triggered. If edge- and level-sensitive triggering is selected, a rising edge or a high level on a PA0­PA3 pin latches an external interrupt request. Edge- and level-sensitive triggering allows the use of multiple wired-OR external interrupt sources. As long as any source is holding a PA0­PA3 pin high, an external interrupt request is latched, and the CPU continues to execute the interrupt service routine. If edge-sensitive only triggering is selected, a rising edge on a PA0­PA3 pin latches an external interrupt request. A subsequent external interrupt request can be latched only after the voltage level of the previous interrupt signal returns to logic 0 and then rises again to logic 1. NOTE: The BIH and BIL instructions apply only to the level on the IRQ/VPP pin itself and not to the output of the logic OR function with the PA0­PA3 pins. The state of the individual port A pins can be checked by reading the appropriate port A pins as inputs. Enabled PA0­PA3 pins cause an IRQ interrupt regardless of whether these pins are configured as inputs or outputs. The IRQ pin has an internal Schmitt trigger. The optional external interrupts (PA0­PA3) do not have internal Schmitt triggers. The interrupt mask bit (I) in the condition code register (CCR) disables all maskable interrupt requests, including external interrupt requests. Data Sheet 56 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 External Interrupt Module (IRQ) MOTOROLA External Interrupt Module (IRQ) IRQ Status and Control Register 5.4 IRQ Status and Control Register The IRQ status and control register (ISCR) controls and monitors operation of the IRQ module. All unused bits in the ISCR read as logic 0s. The IRQF bit is cleared and the IRQE bit is set by reset. Address: $000A Bit 7 Read: Write: Reset: IRQE 1 6 5 4 3 2 1 Bit 0 0 0 0 IRQF 0 0 0 R 0 0 = Unimplemented IRQR 0 0 R = Reserved 0 0 0 Figure 5-4. IRQ Status and Control Register (ISCR) IRQR - Interrupt Request Reset Bit This write-only bit clears the external interrupt request flag. 1 = Clears external interrupt and IRQF bit 0 = No effect on external interrupt and IRQF bit IRQF - External Interrupt Request Flag The external interrupt request flag is a clearable, read-only bit that is set when an external interrupt request is pending. Reset clears the IRQF bit. 1 = External interrupt request pending 0 = No external interrupt request pending IRQE - External Interrupt Request Enable Bit This read/write bit enables external interrupts. Reset sets the IRQE bit. 1 = External interrupt requests enabled 0 = External interrupt requests disabled The STOP and WAIT instructions set the IRQE bit so that an external interrupt can bring the MCU out of these low-power modes. In addition, reset sets the I bit which masks all interrupt sources. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA External Interrupt Module (IRQ) Data Sheet 57 External Interrupt Module (IRQ) 5.5 Timing tILIL IRQ/VPP PIN tILIH tILIH IRQ1 . . . IRQn IRQ (INTERNAL) Figure 5-5. External Interrupt Timing Table 5-1. External Interrupt Timing (VDD = 5.0 Vdc)(1) Characteristic Symbol Min Max Unit IRQ Interrupt Pulse Width Low (Edge-Triggered) tILIH 1.5 - tcyc(2) IRQ Interrupt Pulse Width (Edge- and Level-Triggered) tILIH 1.5 Note(3) tcyc PA0­PA3 Interrupt Pulse Width High (Edge-Triggered) tILIL 1.5 - tcyc PA0­PA3 Interrupt Pulse Width High (Edgeand Level-Triggered) tILIH 1.5 Note(3) tcyc 1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = ­40°C to + 85°C, unless otherwise noted. 2. tcyc = 1/fOP; fOP = fOSC/2. 3. The minimum tILIL should not be less than the number of interrupt service routine cycles plus 19 tcyc. Table 5-2. External Interrupt Timing (VDD = 3.3 Vdc)(1) Characteristic Symbol Min Max Unit IRQ Interrupt Pulse Width Low (Edge-Triggered) tILIH 1.5 - tcyc(2) IRQ Interrupt Pulse Width (Edge- and Level-Triggered) tILIH 1.5 Note(3) tcyc PA0­PA3 Interrupt Pulse Width High (Edge-Triggered) tILIL 1.5 - tcyc PA0­PA3 Interrupt Pulse Width High (Edgeand Level-Triggered) tILIH 1.5 Note(3) tcyc 1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = ­40°C to + 85°C, unless otherwise noted. 2. tcyc = 1/fOP; fOP = fOSC/2. 3. The minimum tILIL should not be less than the number of interrupt service routine cycles plus 19 tcyc. Data Sheet 58 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 External Interrupt Module (IRQ) MOTOROLA Data Sheet - MC68HC705KJ1 MC68HC705KJ1 Section 6. Low-Power Modes 6.1 Introduction The MCU can enter the following low-power standby modes: · Stop mode - The STOP instruction puts the MCU in its lowest power-consumption mode. · Wait mode - The WAIT instruction puts the MCU in an intermediate power-consumption mode. · Halt mode - Halt mode is identical to wait mode, except that an oscillator stabilization delay of 1 to 4064 internal clock cycles occurs when the MCU exits halt mode. The stop-to-wait conversion bit, SWAIT, in the mask option register, enables halt mode. Enabling halt mode prevents the computer operating properly (COP) watchdog from being inadvertently turned off by a STOP instruction. · Data-retention mode - In data-retention mode, the MCU retains RAM contents and CPU register contents at VDD voltages as low as 2.0 Vdc. The data-retention feature allows the MCU to remain in a low power-consumption state during which it retains data, but the CPU cannot execute instructions. 6.2 Exiting Stop and Wait Modes The following events bring the MCU out of stop mode and load the program counter with the reset vector or with an interrupt vector: Exiting Stop Mode · External reset - A logic 0 on the RESET pin resets the MCU, starts the CPU clock, and loads the program counter with the contents of locations $07FE and $07FF. · External interrupt - A high-to-low transition on the IRQ/VPP pin or a low-to-high transition on an enabled port A external interrupt pin starts the CPU clock and loads the program counter with the contents of locations $07FA and $07FB. MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 MOTOROLA Low-Power Modes Data Sheet 59 Low-Power Modes Exiting Wait Mode · External reset - A logic 0 on the RESET pin resets the MCU, starts the CPU clock, and loads the program counter with the contents of locations $07FE and $07FF. · External interrupt - A high-to-low transition on the IRQ/VPP pin or a low-to-high transition on an enabled port A external interrupt pin starts the CPU clock and loads the program counter with the contents of locations $07FA and $07FB. · COP watchdog reset - A timeout of the COP watchdog resets the MCU, starts the CPU clock, and loads the program counter with the contents of locations $07FE and $07FF. Software can enable timer interrupts so that the MCU periodically can exit wait mode to reset the COP watchdog. · Timer interrupt - Real-time interrupt requests and timer overflow interrupt requests start the MCU clock and load the program counter with the contents of locations $07F8 and $07F9. 6.3 Effects of Stop and Wait Modes The STOP and WAIT instructions have the following effects on MCU modules. 6.3.1 Clock Generation Effects of STOP and WAIT on clock generation are discussed here. 6.3.1.1 STOP The STOP instruction disables the internal oscillator, stopping the CPU clock and all peripheral clocks. After exiting stop mode, the CPU clock and all enabled peripheral clocks begin running after the oscillator stabilization delay. NOTE: The oscillator stabilization delay holds the MCU in reset for the first 4064 internal clock cycles. 6.3.1.2 WAIT The WAIT instruction disables the CPU clock. After exiting wait mode, the CPU clock and all enabled peripheral clocks immediately begin running. Data Sheet 60 MC68HC705KJ1 MC68HC705KJ1·MC68HRC705KJ1 MC68HRC705KJ1·MC68HLC705KJ1 MC68HLC705KJ1 - Rev. 4.0 Low-Power Modes MOT