MC68HC912DT128A/D MC68HC912DT128A MC68HC912DG128A MC68HC912DT128 MC68HC912DG128 - Datasheet Archive

 

MC68HC912DT128A MC68HC912DG128A Technical Data Rev 2.0 June 12, 2001 Revision History Revision History This section lists the

 

MC68HC912DT128A/D MC68HC912DT128A/D MC68HC912DT128A MC68HC912DT128A MC68HC912DG128A MC68HC912DG128A Technical Data Rev 2.0 June 12, 2001 Revision History Revision History This section lists the revision history of the document since the first release. Data for previous internal drafts is unavailable. Changes from Rev 1.0 to Rev 2.0 Section Page (in Rev 2.0) 28, 29 Description of change Figures 4 and 5, pin 97 changed to TEST and note added. 31 33 Pinout and Signal Descriptions Text added about connection of power supplies. Note about non-standard oscillator circuit expanded. 33 DC bias capacitor added to Figure 8 and notes added to cover DC bias. 39, 45 Text added in Table 6 and Port CAN pin descriptions about non-connection of TxCAN pins when MSCAN modules are not used. Registers 53, 58 CD bit name corrected in ATD0CTL5 and ATD1CTL5. EEPROM 102 141 to 158 New section added `EEPROM Selective Write More Zeros' Major rewrite of Limp-Home and Fast STOP Recovery modes. 159 System Clock Frequency Formulae updated for clarification. 160 Figure 18 modified for clarification. 163 Figure 21 modified for clarification. 192 Figure 28 modified for clarification. 321 Shading removed from CC bit in Table 54. Clock Functions Enhanced Capture Timer Analog-To-Digital Converter 320, 321 CD bit name corrected. MC68HC912DT128A MC68HC912DT128A Rev 2.0 MOTOROLA Revision History 3 Revision History Section Page (in Rev 2.0) 351, 352 Description of change Preliminary notes removed. 359 EEPROM Programming Maximum Time to `AUTO' Bit Set and EEPROM Erasing Maximum Time to `AUTO' Bit Set added to Table 73. 367 Several values in Table 78 updated. Electrical Characteristics 359 Changed note after Table 73 and Table 74 to read `Based on the average life time operating temperature of 70°C.' Appendix A: MC68HC912DT128A MC68HC912DT128A 375 New section added `2d. EEPROM Selective Write More Zeros'. New section added `6. Port ADx'. New section added `7. ATD'. Appendix B: CGM Practical Aspects 378 New section added `DC Bias'. Changes from first version (internal release, no revision number) to Rev 1.0 Section Page (in Rev 1.0) Description of change General Description 21 Ordering Information updated. EEPROM 109 Addition of Caution regarding attempts to erase or program protected locations. MSI 236 Clarification of SP0DR register state on reset. MC68HC912DT128A MC68HC912DT128A Rev 2.0 4 Revision History MOTOROLA List of Sections List of Sections Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Central Processing Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pinout and Signal Descriptions . . . . . . . . . . . . . . . . . . . . 27 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Resource Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Bus Control and Input/Output . . . . . . . . . . . . . . . . . . . . 83 Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Resets and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 I/O Ports With Key Wake-Up . . . . . . . . . . . . . . . . . . . . . 127 Clock Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 © Motorola, Inc., 2000 MOTOROLA MC68HC912DT128A MC68HC912DT128A Rev 2.0 List of Sections 5 List of Sections Pulse-Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . 171 Enhanced Capture Timer . . . . . . . . . . . . . . . . . . . . . . . 187 Multiple Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . 223 Inter-IC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 MSCAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Analog-To-Digital Converter (ATD) . . . . . . . . . . . . . . . 311 Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . 327 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 351 Appendix A: MC68HC912DT128A MC68HC912DT128A . . . . . . . . . . . . . . . . 373 Appendix B: CGM Practical Aspects . . . . . . . . . . . . . 377 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 Literature Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 MC68HC912DT128A MC68HC912DT128A Rev 2.0 6 List of Sections MOTOROLA Table of Contents Table of Contents Revision History Changes from Rev 1.0 to Rev 2.0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Changes from first version to Rev 1.0 . . . . . . . . . . . . . . . . . . . . . . . . . 4 List of Sections Table of Contents General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MC68HC912DT128A MC68HC912DT128A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 17 MC68HC912DG128A MC68HC912DG128A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 18 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Central Processing Unit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Pinout and Signal Descriptions Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MC68HC912DT128A MC68HC912DT128A Pin Assignments in 112-pin QFP . . . . . . . . . . . 27 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Registers Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MC68HC912DT128A MC68HC912DT128A Rev 2.0 MOTOROLA Table of Contents 7 Table of Contents Operating Modes Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Resource Mapping Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Internal Resource Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 Flash EEPROM mapping through internal Memory Expansion . . . . .72 Miscellaneous System Control Register . . . . . . . . . . . . . . . . . . . . . . .77 Mapping test registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Bus Control and Input/Output Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . .83 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 Flash EEPROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . .97 Erasing the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 EEPROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 EEPROM Selective Write More Zeros . . . . . . . . . . . . . . . . . . . . . . .102 EEPROM Programmer's Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 Program/Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Shadow Word Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 Programming EEDIVH and EEDIVL Registers . . . . . . . . . . . . . . . . .112 MC68HC912DT128A MC68HC912DT128A Rev 2.0 8 Table of Contents MOTOROLA Table of Contents Resets and Interrupts Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . . . . . . . Interrupt test registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Register Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 115 116 116 117 119 120 121 123 124 I/O Ports With Key Wake-Up Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key Wake-up and port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . Key Wake-Up Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 127 128 132 Clock Functions Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . Limp-Home and Fast STOP Recovery modes . . . . . . . . . . . . . . . . System Clock Frequency Formulae . . . . . . . . . . . . . . . . . . . . . . . . Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 135 136 137 139 141 159 160 163 164 164 165 Pulse-Width Modulator Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Boundary Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 171 175 186 MC68HC912DT128A MC68HC912DT128A Rev 2.0 MOTOROLA Table of Contents 9 Table of Contents Enhanced Capture Timer Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . .194 Timer Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 Timer and Modulus Counter Operation in Different Modes . . . . . . .221 Multiple Serial Interface Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . .224 Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 Inter-IC Bus Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 IIC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .248 IIC System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 IIC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250 IIC Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 MSCAN Controller Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .276 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 Programmer's Model of Message Storage . . . . . . . . . . . . . . . . . . . .289 Programmer's Model of Control Registers . . . . . . . . . . . . . . . . . . . .294 MC68HC912DT128A MC68HC912DT128A Rev 2.0 10 Table of Contents MOTOROLA Table of Contents Analog-To-Digital Converter (ATD) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ATD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 311 312 313 325 Development Support Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 327 327 329 343 350 Electrical Characteristics Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 Appendix A: MC68HC912DT128 MC68HC912DT128 A Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 Significant changes from the MC68HC912DG128 MC68HC912DG128 (non-A suffix device) 373 Appendix B: CGM Practical Aspects Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A Few Hints For The CGM Crystal Oscillator Application . . . . . . . . Practical Aspects For The PLL Usage . . . . . . . . . . . . . . . . . . . . . . Printed Circuit Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 377 377 380 385 Glossary Literature Updates Literature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Microcontroller Division's Web Site . . . . . . . . . . . . . . . . . . . . . . . . . 402 MC68HC912DT128A MC68HC912DT128A Rev 2.0 MOTOROLA Table of Contents 11 Table of Contents MC68HC912DT128A MC68HC912DT128A Rev 2.0 12 Table of Contents MOTOROLA General Description General Description Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MC68HC912DT128A MC68HC912DT128A Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 17 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Introduction The MC68HC912DT128A MC68HC912DT128A microcontroller unit (MCU) is a 16-bit device composed of standard on-chip peripherals including a 16-bit central processing unit (CPU12 CPU12), 128K bytes of flash EEPROM, 8K bytes of RAM, 2K bytes of EEPROM, two asynchronous serial communications interfaces (SCI), a serial peripheral interface (SPI), an inter-IC interface (I2C), an enhanced capture timer (ECT), two 8-channel, 10-bit analog-to-digital converters (ADC), a four-channel pulse-width modulator (PWM), and three CAN 2.0 A, B software compatible modules (MSCAN12 MSCAN12). System resource mapping, clock generation, interrupt control and bus interfacing are managed by the lite integration module (LIM). The MC68HC912DT128A MC68HC912DT128A has full 16-bit data paths throughout, however, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements. In addition to the I/O ports available in each module, 16 I/O ports are available with Key-Wake-Up capability from STOP or WAIT mode. The MC68HC912DG128A MC68HC912DG128A device is similar to the MC68HC912DT128A MC68HC912DT128A, but it has only two MSCAN12 MSCAN12 modules. The entire databook applies also to the MC68HC912DG128A MC68HC912DG128A, except where differences are noted. MC68HC912DT128A MC68HC912DT128A Rev 2.0 1-gen MOTOROLA General Description 13 General Description Features · 16-bit CPU12 CPU12 ­ Upward compatible with M68HC11 M68HC11 instruction set ­ Interrupt stacking and programmer's model identical to M68HC11 M68HC11 ­ 20-bit ALU ­ Instruction queue ­ Enhanced indexed addressing · Multiplexed bus ­ Single chip or expanded ­ 16 address/16 data wide or 16 address/8 data narrow modes · Memory ­ 128K byte flash EEPROM, made of four 32K byte modules with 8K bytes protected BOOT section in each module ­ 2K byte EEPROM ­ 8K byte RAM with Vstby, made of two 4K byte modules. · Two Analog-to-digital converters ­ 2 times 8-channels, 10-bit resolution · Three 1M bit per second, CAN 2.0 A, B software compatible modules on the MC68HC912DT128A MC68HC912DT128A (two on the MC68HC912DG128A MC68HC912DG128A) ­ Two receive and three transmit buffers per CAN ­ Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit ­ Four separate interrupt channels for Rx, Tx, error and wake-up per CAN ­ Low-pass filter wake-up function ­ Loop-back for self test operation MC68HC912DT128A MC68HC912DT128A Rev 2.0 14 2-gen General Description MOTOROLA General Description Features ­ Programmable link to a timer input capture channel, for time-stamping and network synchronization. · Enhanced capture timer (ECT) ­ 16-bit main counter with 7-bit prescaler ­ 8 programmable input capture or output compare channels; 4 of the 8 input captures with buffer ­ Input capture filters and buffers, three successive captures on four channels, or two captures on four channels with a capture/compare selectable on the remaining four ­ Four 8-bit or two 16-bit pulse accumulators ­ 16-bit modulus down-counter with 4-bit prescaler ­ Four user-selectable delay counters for signal filtering · 4 PWM channels with programmable period and duty cycle ­ 8-bit 4-channel or 16-bit 2-channel ­ Separate control for each pulse width and duty cycle ­ Center- or left-aligned outputs ­ Programmable clock select logic with a wide range of frequencies · Serial interfaces ­ Two asynchronous serial communications interfaces (SCI) ­ Inter IC bus interface (I2C) ­ Synchronous serial peripheral interface (SPI) · LIM (lite integration module) ­ WCR (windowed COP watchdog, real time interrupt, clock monitor) ­ ROC (reset and clocks) ­ MEBI (multiplexed external bus interface) ­ MMI (memory map and interface) ­ INT (interrupt control) MC68HC912DT128A MC68HC912DT128A Rev 2.0 3-gen MOTOROLA General Description 15 General Description ­ BKP (breakpoints) ­ BDM (background debug mode) · Two 8-bit ports with key wake-up interrupt · Clock generation ­ Phase-locked loop clock frequency multiplier ­ Limp home mode in absence of external clock ­ Slow mode divider ­ Low power 0.5 to 16 MHz crystal oscillator reference clock · 112-Pin TQFP package ­ Up to 67 general-purpose I/O lines on the MC68HC912DT128A MC68HC912DT128A (up to 69 on the MC68HC912DG128A MC68HC912DG128A), plus up to 18 input-only lines ­ 5.0V operation at 8 MHz · Development support ­ Single-wire background debugTM mode (BDM) ­ On-chip hardware breakpoints MC68HC912DT128A MC68HC912DT128A Rev 2.0 16 4-gen General Description MOTOROLA General Description MC68HC912DT128A MC68HC912DT128A Block Diagram MC68HC912DT128A MC68HC912DT128A Block Diagram VRH0 VRL0 VRH0 ATD0 VRL0 SCI1 SDI/MISO SDO/MOSI SCK SS SPI PORT E PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 XIRQ IRQ R/W LSTRB ECLK MODA MODB DBE/CAL Lite integration module (LIM) PW0 PW1 PW2 PW3 PWM PIX0 PIX1 PIX2 PPAGE I/O SCL SDA IIC DDRA DDRB PORT B PORTH DDRH PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 KWU KWJ7 KWJ6 KWJ5 KWJ4 KWJ3 KWJ2 KWJ1 KWJ0 PORTJ PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Narrow bus CAN0 DDRJ PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 ADDR15 ADDR15 ADDR14 ADDR14 ADDR13 ADDR13 ADDR12 ADDR12 ADDR11 ADDR11 ADDR10 ADDR10 ADDR9 ADDR8 Wide bus DATA7 DATA15 DATA15 DATA6 DATA14 DATA14 DATA5 DATA13 DATA13 DATA4 DATA12 DATA12 DATA3 DATA11 DATA11 DATA2 DATA10 DATA10 DATA1 DATA9 DATA0 DATA8 CAN1 KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0 PS4 PS5 PS6 PS7 PK0 PK1 PK2 PK3 PK7 PIB7 PIB6 TxCAN2 RxCAN2 TxCAN1 RxCAN1 TxCAN0 RxCAN0 CAN2 PORT A PS0 PS1 PS2 PS3 PP0 PP1 PP2 PP3 ECS Multiplexed Address/Data Bus PORT T DDRT RxD0 TxD0 RxD1 TxD1 SCI0 EXTAL XTAL RESET PORT S Enhanced capture timer PAD10 PAD10 PAD11 PAD11 PAD12 PAD12 PAD13 PAD13 PAD14 PAD14 PAD15 PAD15 PAD16 PAD16 PAD17 PAD17 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PORT P PLL Clock Generation module IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 PORT K XFC VDDPLL VSSPLL Periodic interrupt COP watchdog Clock monitor Breakpoints DDRS BKGD Single-wire background debug module DDRP CPU12 CPU12 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 DDRK 2K byte EEPROM PAD00 PAD00 PAD01 PAD01 PAD02 PAD02 PAD03 PAD03 PAD04 PAD04 PAD05 PAD05 PAD06 PAD06 PAD07 PAD07 PORT IB AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 DDRIB 8K byte RAM VRH1 VRL1 VDDA VSSA VDDA VSSA PORT AD0 VSTBY VRH1 ATD1 VRL1 VDDA VSSA PORT AD1 128K byte flash EEPROM PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 VDD ×2 VSS ×2 Power for internal circuitry VDDX ×2 VSSX ×2 Power for I/O drivers Figure 1 MC68HC912DT128A MC68HC912DT128A Block Diagram MC68HC912DT128A MC68HC912DT128A Rev 2.0 5-gen MOTOROLA General Description 17 General Description MC68HC912DG128A MC68HC912DG128A Block Diagram VRH0 SCI1 PORT E XIRQ IRQ R/W LSTRB ECLK MODA MODB DBE/CAL Lite integration module (LIM) DDRT SDI/MISO SDO/MOSI SCK SS SPI PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 DDRS RxD0 TxD0 RxD1 TxD1 SCI0 EXTAL XTAL RESET PW0 PW1 PW2 PW3 PWM PIX0 PIX1 PIX2 PPAGE I/O ECS DDRIB SCL SDA IIC Multiplexed Address/Data Bus I/O PORT T Enhanced capture timer PORT S PLL Clock Generation module DDRP XFC VDDPLL VSSPLL IOC0 IOC1 IOC2 IOC3 IOC4 IOC5 IOC6 IOC7 PORT AD1 PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PP0 PP1 PP2 PP3 PK0 PK1 PK2 PK3 PK7 PIB7 PIB6 PIB5 PIB4 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 KWJ7 KWJ6 KWJ5 KWJ4 KWJ3 KWJ2 KWJ1 KWJ0 PORTJ KWU DDRJ Narrow bus KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0 PORTH TxCAN1 RxCAN1 DDRH CAN1 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORT B ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 PORT A DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 TxCAN0 RxCAN0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 CAN0 ADDR15 ADDR15 ADDR14 ADDR14 ADDR13 ADDR13 ADDR12 ADDR12 ADDR11 ADDR11 ADDR10 ADDR10 ADDR9 ADDR8 DDRB DATA7 DATA15 DATA15 DATA6 DATA14 DATA14 DATA5 DATA13 DATA13 DATA4 DATA12 DATA12 DATA3 DATA11 DATA11 DATA2 DATA10 DATA10 DATA1 DATA9 DATA0 DATA8 DDRA Wide bus PAD10 PAD10 PAD11 PAD11 PAD12 PAD12 PAD13 PAD13 PAD14 PAD14 PAD15 PAD15 PAD16 PAD16 PAD17 PAD17 PT0 PT1 PT2 PT3 PT4 PT5 PT6 PT7 PORT P BKGD Periodic interrupt COP watchdog Clock monitor Breakpoints AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 DDRK CPU12 CPU12 PAD00 PAD00 PAD01 PAD01 PAD02 PAD02 PAD03 PAD03 PAD04 PAD04 PAD05 PAD05 PAD06 PAD06 PAD07 PAD07 PORT K AN00 AN01 AN02 AN03 AN04 AN05 AN06 AN07 2K byte EEPROM Single-wire background debug module VDDA VSSA PORTIB 8K byte RAM VRH1 VRL1 VDDA VSSA ATD1 VRL1 VDDA VSSA PORT AD0 VSTBY VRH1 VRH0 VRL0 ATD0 VRL0 128K byte flash EEPROM PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 VDD ×2 VSS ×2 Power for internal circuitry VDDX ×2 VSSX ×2 Power for I/O drivers Figure 2 MC68HC912DG128A MC68HC912DG128A Block Diagram MC68HC912DT128A MC68HC912DT128A Rev 2.0 18 6-gen General Description MOTOROLA General Description Ordering Information Ordering Information Table 1 Device Ordering Information Temperature Package Voltage ­40 to +105°C V 8 MHz Consult factory C ­40 to +125°C 112-Pin TQFP Order Number Designator ­40 to +85°C Frequency 5V Range M Table 2 Development Tools Ordering Information Description Details Order Number Evaluation board kit EVB and user's manual only M68EVB912DG128 M68EVB912DG128 Serial Debug Interface Low voltage serial debug interface cable can be ordered separately M68SDIL12 M68SDIL12 Complete evaluation board kit EVB, MCUez debug software, SDIL low voltage serial debug interface cable M68KIT912DG128 M68KIT912DG128 Adapter 112 pin TQFP adapter is also available. M68ADP912DG128PV M68ADP912DG128PV MC68HC912DT128A MC68HC912DT128A Rev 2.0 7-gen MOTOROLA General Description 19 General Description MC68HC912DT128A MC68HC912DT128A Rev 2.0 20 8-gen General Description MOTOROLA Central Processing Unit Central Processing Unit Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Indexed Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Introduction The CPU12 CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data paths and wider internal registers (up to 20 bits) for high-speed extended math instructions. The instruction set is a proper superset of the M68HC11instruction set. The CPU12 CPU12 allows instructions with odd byte counts, including many single-byte instructions. This provides efficient use of ROM space. An instruction queue buffers program information so the CPU always has immediate access to at least three bytes of machine code at the start of every instruction. The CPU12 CPU12 also offers an extensive set of indexed addressing capabilities. MC68HC912DT128A MC68HC912DT128A Rev 2.0 1-cpu12 MOTOROLA Central Processing Unit 21 Central Processing Unit Programming Model CPU12 CPU12 registers are an integral part of the CPU and are not addressed as if they were memory locations. 7 A 0 7 B 0 8-BIT ACCUMULATORS A & B OR 15 D 0 16-BIT 16-BIT DOUBLE ACCUMULATOR D 15 IX 0 INDEX REGISTER X 15 IY 0 INDEX REGISTER Y 15 SP 0 STACK POINTER 15 PC 0 PROGRAM COUNTER S X H I N Z V C CONDITION CODE REGISTER Figure 3 Programming Model Accumulators A and B are general-purpose 8-bit accumulators used to hold operands and results of arithmetic calculations or data manipulations. Some instructions treat the combination of these two 8-bit accumulators as a 16-bit double accumulator (accumulator D). Index registers X and Y are used for indexed addressing mode. In the indexed addressing mode, the contents of a 16-bit index register are added to 5-bit, 9-bit, or 16-bit constants or the content of an accumulator to form the effective address of the operand to be used in the instruction. MC68HC912DT128A MC68HC912DT128A Rev 2.0 22 2-cpu12 Central Processing Unit MOTOROLA Central Processing Unit Data Types Stack pointer (SP) points to the last stack location used. The CPU12 CPU12 supports an automatic program stack that is used to save system context during subroutine calls and interrupts, and can also be used for temporary storage of data. The stack pointer can also be used in all indexed addressing modes. Program counter is a 16-bit register that holds the address of the next instruction to be executed. The program counter can be used in all indexed addressing modes except autoincrement/decrement. Condition Code Register (CCR) contains five status indicators, two interrupt masking bits, and a STOP disable bit. The five flags are half carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The half-carry flag is used only for BCD arithmetic operations. The N, Z, V, and C status bits allow for branching based on the results of a previous operation. Data Types The CPU12 CPU12 supports the following data types: · Bit data · 8-bit and 16-bit signed and unsigned integers · 16-bit unsigned fractions · 16-bit addresses A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. There are no special requirements for alignment of instructions or operands. MC68HC912DT128A MC68HC912DT128A Rev 2.0 3-cpu12 MOTOROLA Central Processing Unit 23 Central Processing Unit Addressing Modes Addressing modes determine how the CPU accesses memory locations to be operated upon. The CPU12 CPU12 includes all of the addressing modes of the M68HC11 M68HC11 CPU as well as several new forms of indexed addressing. Table 3 is a summary of the available addressing modes. Table 3 M68HC12 M68HC12 Addressing Mode Summary Addressing Mode Source Format INST (no externally supplied operands) INST #opr8i or INST #opr16i Abbreviation Description INH Operands (if any) are in CPU registers IMM Operand is included in instruction stream 8- or 16-bit size implied by context Direct INST opr8a DIR Extended INST opr16a INST rel8 or INST rel16 EXT REL An 8-bit or 16-bit relative offset from the current pc is supplied in the instruction INST oprx5,xysp IDX 5-bit signed constant offset from x, y, sp, or pc INST oprx3,­xys IDX Auto pre-decrement x, y, or sp by 1 ~ 8 INST oprx3,+xys IDX Auto pre-increment x, y, or sp by 1 ~ 8 INST oprx3,xys­ IDX Auto post-decrement x, y, or sp by 1 ~ 8 INST oprx3,xys+ IDX Auto post-increment x, y, or sp by 1 ~ 8 INST abd,xysp IDX INST oprx9,xysp IDX1 INST oprx16,xysp IDX2 Indexed-Indirect (16-bit offset) INST [oprx16,xysp] [IDX2] Indexed-Indirect (D accumulator offset) INST [D,xysp] [D,IDX] Inherent Immediate Relative Indexed (5-bit offset) Indexed (auto pre-decrement) Indexed (auto pre-increment) Indexed (auto postdecrement) Indexed (auto post-increment) Indexed (accumulator offset) Indexed (9-bit offset) Indexed (16-bit offset) Operand is the lower 8-bits of an address in the range $0000 ­ $00FF Operand is a 16-bit address Indexed with 8-bit (A or B) or 16-bit (D) accumulator offset from x, y, sp, or pc 9-bit signed constant offset from x, y, sp, or pc (lower 8-bits of offset in one extension byte) 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) Pointer to operand is found at. 16-bit constant offset from x, y, sp, or pc (16-bit offset in two extension bytes) MC68HC912DT128A MC68HC912DT128A Rev 2.0 24 Pointer to operand is found at. x, y, sp, or pc plus the value in D 4-cpu12 Central Processing Unit MOTOROLA Central Processing Unit Indexed Addressing Modes Indexed Addressing Modes The CPU12 CPU12 indexed modes reduce execution time and eliminate code size penalties for using the Y index register. CPU12 CPU12 indexed addressing uses a postbyte plus zero, one, or two extension bytes after the instruction opcode. The postbyte and extensions do the following tasks: · Specify which index register is used. · Determine whether a value in an accumulator is used as an offset. · Enable automatic pre- or post-increment or decrement · Specify use of 5-bit, 9-bit, or 16-bit signed offsets. Table 4 Summary of Indexed Operations Postbyte Code (xb) rr0nnnnn 111rr0zs 111rr011 rr1pnnnn 111rr1aa 111rr111 Source Code Comments Syntax ,r 5-bit constant offset n = ­16 to +15 n,r rr can specify X, Y, SP, or PC ­n,r Constant offset (9- or 16-bit signed) z-0 = 9-bit with sign in LSB of postbyte(s) n,r 1 = 16-bit ­n,r if z = s = 1, 16-bit offset indexed-indirect (see below) rr can specify X, Y, SP, or PC 16-bit offset indexed-indirect [n,r] rr can specify X, Y, SP, or PC Auto pre-decrement/increment or Auto post-decrement/increment; n,­r n,+r p = pre-(0) or post-(1), n = ­8 to ­1, +1 to +8 n,r­ n,r+ rr can specify X, Y, or SP (PC not a valid choice) Accumulator offset (unsigned 8-bit or 16-bit) aa-00 = A A,r 01 = B B,r 10 = D (16-bit) D,r 11 = see accumulator D offset indexed-indirect rr can specify X, Y, SP, or PC Accumulator D offset indexed-indirect [D,r] rr can specify X, Y, SP, or PC MC68HC912DT128A MC68HC912DT128A Rev 2.0 5-cpu12 MOTOROLA Central Processing Unit 25 Central Processing Unit Opcodes and Operands The CPU12 CPU12 uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number that can be represented by 8-bit binary numbers. To expand the number of opcodes, a second page is added to the opcode map. Opcodes on the second page are preceded by an additional byte with the value $18. To provide additional addressing flexibility, opcodes can also be followed by a postbyte or extension bytes. Postbytes implement certain forms of indexed addressing, transfers, exchanges, and loop primitives. Extension bytes contain additional program information such as addresses, offsets, and immediate data. MC68HC912DT128A MC68HC912DT128A Rev 2.0 26 6-cpu12 Central Processing Unit MOTOROLA Pinout and Signal Descriptions Pinout and Signal Descriptions Contents MC68HC912DT128A MC68HC912DT128A Pin Assignments in 112-pin QFP . . . . . . . . . . . 27 Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 MC68HC912DT128A MC68HC912DT128A Pin Assignments in 112-pin QFP The MC68HC912DT128A MC68HC912DT128A is available in a 112-pin thin quad flat pack (TQFP). Most pins perform two or more functions, as described in the Signal Descriptions. Figure 4 shows pin assignments. In expanded narrow modes the lower byte data is multiplexed with higher byte data through pins 57-64. MC68HC912DT128A MC68HC912DT128A Rev 2.0 1-pins MOTOROLA Pinout and Signal Descriptions 27 MC68HC912DT128A MC68HC912DT128A 112TQFP 112TQFP 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PAD17/AN17 PAD17/AN17 PAD07/AN07 PAD07/AN07 PAD16/AN16 PAD16/AN16 PAD06/AN06 PAD06/AN06 PAD15/AN15 PAD15/AN15 PAD05/AN05 PAD05/AN05 PAD14/AN14 PAD14/AN14 PAD04/AN04 PAD04/AN04 PAD13/AN13 PAD13/AN13 PAD03/AN03 PAD03/AN03 PAD12/AN12 PAD12/AN12 PAD02/AN02 PAD02/AN02 PAD11/AN11 PAD11/AN11 PAD01/AN01 PAD01/AN01 PAD10/AN10 PAD10/AN10 PAD00/AN00 PAD00/AN00 VRL0 VRH0 VSS VDD PA7/ADDR15/DATA15/DATA7 PA7/ADDR15/DATA15/DATA7 PA6/ADDR14/DATA14/DATA6 PA6/ADDR14/DATA14/DATA6 PA5/ADDR13/DATA13/DATA5 PA5/ADDR13/DATA13/DATA5 PA4/ADDR12/DATA12/DATA4 PA4/ADDR12/DATA12/DATA4 PA3/ADDR11/DATA11/DATA3 PA3/ADDR11/DATA11/DATA3 PA2/ADDR10/DATA10/DATA2 PA2/ADDR10/DATA10/DATA2 PA1/ADDR9/DATA9/DATA1 PA0/ADDR8/DATA8/DATA0 ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 KWH7/PH7 KWH6/PH6 KWH5/PH5 KWH4/PH4 DBE/CAL/PE7 MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSX VSTBY VDDX VDDPLL XFC VSSPLL RESET EXTAL XTAL KWH3/PH3 KWH2/PH2 KWH1/PH1 KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 PW2/PP2 PW1/PP1 PW0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 KWJ7/PJ7 KWJ6/PJ6 KWJ5/PJ5 KWJ4/PJ4 VDD PK3 VSS IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 KWJ3/PJ3 KWJ2/PJ2 KWJ1/PJ1 KWJ0/PJ0 SMODN/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 PP3/PW3 PK0/PIX0 PK1/PIX1 PK2/PIX2 PK7/ECS VDDX VSSX RxCAN0 TxCAN0 RxCAN1 TxCAN1 RxCAN2 TxCAN2 PIB6/SDA PIB7/SCL TEST PS7/SS PS6/SCK PS5/SDO/MOSI PS4/SDI/MISO PS3/TxD1 PS2/RxD1 PS1/TxD0 PS0/RxD0 VSSA VRL1 VRH1 VDDA Pinout and Signal Descriptions Note: TEST = On early production devices this pin is used for factory test purposes. It is recommended that this pin is not connected within the application, but it may be connected to VSS or 5.5V max without issue. On later production devices this pin is not bonded out. Figure 4 Pin Assignments in 112-pin QFP for MC68HC912DT128A MC68HC912DT128A MC68HC912DT128A MC68HC912DT128A Rev 2.0 28 2-pins Pinout and Signal Descriptions MOTOROLA 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 MC68HC912DG128A MC68HC912DG128A 112TQFP 112TQFP 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PAD17/AN17 PAD17/AN17 PAD07/AN07 PAD07/AN07 PAD16/AN16 PAD16/AN16 PAD06/AN06 PAD06/AN06 PAD15/AN15 PAD15/AN15 PAD05/AN05 PAD05/AN05 PAD14/AN14 PAD14/AN14 PAD04/AN04 PAD04/AN04 PAD13/AN13 PAD13/AN13 PAD03/AN03 PAD03/AN03 PAD12/AN12 PAD12/AN12 PAD02/AN02 PAD02/AN02 PAD11/AN11 PAD11/AN11 PAD01/AN01 PAD01/AN01 PAD10/AN10 PAD10/AN10 PAD00/AN00 PAD00/AN00 VRL0 VRH0 VSS VDD PA7/ADDR15/DATA15/DATA7 PA7/ADDR15/DATA15/DATA7 PA6/ADDR14/DATA14/DATA6 PA6/ADDR14/DATA14/DATA6 PA5/ADDR13/DATA13/DATA5 PA5/ADDR13/DATA13/DATA5 PA4/ADDR12/DATA12/DATA4 PA4/ADDR12/DATA12/DATA4 PA3/ADDR11/DATA11/DATA3 PA3/ADDR11/DATA11/DATA3 PA2/ADDR10/DATA10/DATA2 PA2/ADDR10/DATA10/DATA2 PA1/ADDR9/DATA9/DATA1 PA0/ADDR8/DATA8/DATA0 ADDR5/DATA5/PB5 ADDR6/DATA6/PB6 ADDR7/DATA7/PB7 KWH7/PH7 KWH6/PH6 KWH5/PH5 KWH4/PH4 ECLK/DBE/CAL/PE7 CGMTST/MODB/IPIPE1/PE6 MODA/IPIPE0/PE5 ECLK/PE4 VSSX VSTBY VDDX VDDPLL XFC VSSPLL RESET EXTAL XTAL KWH3/PH3 KWH2/PH2 KWH1/PH1 KWH0/PH0 LSTRB/TAGLO/PE3 R/W/PE2 IRQ/PE1 XIRQ/PE0 PW2/PP2 PW1/PP1 PW0/PP0 IOC0/PT0 IOC1/PT1 IOC2/PT2 IOC3/PT3 KWJ7/PJ7 KWJ6/PJ6 KWJ5/PJ5 KWJ4/PJ4 VDD PK3 VSS IOC4/PT4 IOC5/PT5 IOC6/PT6 IOC7/PT7 KWJ3/PJ3 KWJ2/PJ2 KWJ1/PJ1 KWJ0/PJ0 SMODN/TAGHI/BKGD ADDR0/DATA0/PB0 ADDR1/DATA1/PB1 ADDR2/DATA2/PB2 ADDR3/DATA3/PB3 ADDR4/DATA4/PB4 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 PP3/PW3 PK0/PIX0 PK1/PIX1 PK2/PIX2 PK7/ECS VDDX VSSX RxCAN0 TxCAN0 RxCAN1 TxCAN1 PIB4 PIB5 PIB6/SDA PIB7/SCL TEST PS7/SS PS6/SCK PS5/SDO/MOSI PS4/SDI/MISO PS3/TxD1 PS2/RxD1 PS1/TxD0 PS0/RxD0 VSSA VRL1 VRH1 VDDA Pinout and Signal Descriptions MC68HC912DT128A MC68HC912DT128A Pin Assignments in 112-pin QFP Note: TEST = On early production devices this pin is used for factory test purposes. It is recommended that this pin is not connected within the application, but it may be connected to VSS or 5.5V max without issue. On later production devices this pin is not bonded out. Figure 5 Pin Assignments in 112-pin QFP for MC68HC912DG128A MC68HC912DG128A MC68HC912DT128A MC68HC912DT128A Rev 2.0 3-pins MOTOROLA Pinout and Signal Descriptions 29 Pinout and Signal Descriptions Figure 6 112-pin QFP Mechanical Dimensions (case no. 987) MC68HC912DT128A MC68HC912DT128A Rev 2.0 30 4-pins Pinout and Signal Descriptions MOTOROLA Pinout and Signal Descriptions Power Supply Pins Power Supply Pins MC68HC912DT128A MC68HC912DT128A power and ground pins are described below and summarized in Table 5. All power supply pins must be connected to appropriate supplies. On no account must any pins be left floating. Internal Power (VDD) and Ground (VSS) Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. External Power (VDDX) and Ground (VSSX) External power and ground for I/O drivers. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded. VDDA, VSSA Provides operating voltage and ground for the analog-to-digital converter. This allows the supply voltage to the A/D to be bypassed independently. Analog to Digital Reference Voltages (VRH, VRL) VRH0, VRL0: reference voltage high and low for ATD converter 0. VRH1, VRL1: reference voltage high and low for ATD converter 1. If the ATD modules are not used, leaving VRH connected to VDD will not result in an increase of power consumption. VDDPLL, VSSPLL Provides operating voltage and ground for the Phase-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. MC68HC912DT128A MC68HC912DT128A Rev 2.0 5-pins MOTOROLA Pinout and Signal Descriptions 31 Pinout and Signal Descriptions NOTE: XFC The VSSPLL pin should always be grounded even if the PLL is not used. The VDDPLL pin should not be left floating. It is recommended to connect the VDDPLL pin to ground if the PLL is not used. PLL loop filter. Please see Appendix B: CGM Practical Aspects for information on how to calculate PLL loop filter elements. Any current leakage on this pin must be avoided. XFC R0 MCU Ca C0 VDDPLL VDDPLL Figure 7 PLL Loop FIlter Connections VSTBY Stand-by voltage supply to static RAM. Used to maintain the contents of RAM with minimal power when the rest of the chip is powered down. Table 5 MC68HC912DT128A MC68HC912DT128A Power and Ground Connection Summary Mnemonic Pin Number Description 112-pin QFP VDD 12, 65 VSS 14, 66 VDDX 42, 107 VSSX 40, 106 VDDA 85 VSSA 88 VRH1 86 VRL1 87 VRH0 67 VRL0 68 Internal power and ground. External power and ground, supply to pin drivers. Operating voltage and ground for the analog-to-digital converter, allows the supply voltage to the A/D to be bypassed independently. Reference voltages for the analog-to-digital converter 1 Reference voltages for the analog-to-digital converter 0. MC68HC912DT128A MC68HC912DT128A Rev 2.0 32 6-pins Pinout and Signal Descriptions MOTOROLA Pinout and Signal Descriptions Signal Descriptions Table 5 MC68HC912DT128A MC68HC912DT128A Power and Ground Connection Summary Mnemonic Pin Number Description 112-pin QFP VDDPLL 43 VSSPLL 45 VSTBY 41 Provides operating voltage and ground for the Phase-Locked Loop. This allows the supply voltage to the PLL to be bypassed independently. Stand-by voltage supply to maintain the contents of RAM with minimal power when the rest of the chip is powered down. Signal Descriptions Crystal Driver and External Clock Input (XTAL, EXTAL) These pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. Out of reset the frequency applied to EXTAL is twice the desired E­clock rate. All the device clocks are derived from the EXTAL input frequency. Please see Appendix B: CGM Practical Aspects for detailed information on oscillator design. NOTE: THE CRYSTAL CIRCUIT FOR COLPITTS OSCILLATOR IS CHANGED FROM THE STANDARD PIERCE OSCILLATOR. NOTE: The internal return path for the oscillator is the VSSPLL pin. Therefore it is recommended to connect the common node of the resonator and the capacitor directly to the VSSPLL pin. 2 x E crystal or ceramic resonator EXTAL MCU C C XTAL CDC* * Due to the nature of the translated ground Colpitts oscillator a DC voltage bias is applied to the crystal. Please contact the crystal manufacturer for specific DC bias conditions and recommended capacitance value (if applicable). Figure 8 Common Crystal Connections MC68HC912DT128A MC68HC912DT128A Rev 2.0 7-pins MOTOROLA Pinout and Signal Descriptions 33 Pinout and Signal Descriptions 2xE CMOS-COMPATIBLE EXTERNAL OSCILLATOR EXTAL MCU XTAL NC Figure 9 External Oscillator Connections XTAL is the crystal output.The XTAL pin must be left without terminal when an external CMOS compatible clock input is connected to the EXTAL pin. The XTAL output is normally intended to drive only a crystal. The XTAL output can be buffered with a high-impedance buffer to drive the EXTAL input of another device. In all cases take extra care in the circuit board layout around the oscillator pins. Load capacitances in the oscillator circuits include all stray layout capacitances. Refer to Figure 8 and Figure 9 for diagrams of oscillator circuits. E-Clock Output (ECLK) ECLK is the output connection for the internal bus clock. It is used to demultiplex the address and data in expanded modes and is used as a timing reference. ECLK frequency is equal to 1/2 the crystal frequency out of reset. The E-clock output is turned off in single chip user mode to reduce the effects of RFI. It can be turned on if necessary. In special single-chip mode, the E-clock is turned ON at reset and can be turned OFF. In special peripheral mode the E-clock is an input to the MCU. All clocks, including the E clock, are halted when the MCU is in STOP mode. It is possible to configure the MCU to interface to slow external memory. ECLK can be stretched for such accesses. Reset (RESET) An active low bidirectional control signal, RESET, acts as an input to initialize the MCU to a known start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or COP watchdog circuit. The MCU goes into reset asynchronously and comes out of reset synchronously. This allows the MC68HC912DT128A MC68HC912DT128A Rev 2.0 34 8-pins Pinout and Signal Descriptions MOTOROLA Pinout and Signal Descriptions Signal Descriptions part to reach a proper reset state even if the clocks have failed, while allowing synchronized operation when starting out of reset. It is important to use an external low-voltage reset circuit (such as MC34064 MC34064 or MC34164 MC34164) to prevent corruption of RAM or EEPROM due to power transitions. The reset sequence is initiated by any of the following events: · Power-on-reset (POR) · COP watchdog enabled and watchdog timer times out · Clock monitor enabled and Clock monitor detects slow or stopped clock · User applies a low level to the reset pin External circuitry connected to the reset pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within nine bus cycles after the low drive is released. Upon detection of any reset, an internal circuit drives the reset pin low and a clocked reset sequence controls when the MCU can begin normal processing. In the case of POR or a clock monitor error, a 4096 cycle oscillator startup delay is imposed before the reset recovery sequence starts (reset is driven low throughout this 4096 cycle delay). The internal reset recovery sequence then drives reset low for 16 to 17 cycles and releases the drive to allow reset to rise. Nine cycles later this circuit samples the reset pin to see if it has risen to a logic one level. If reset is low at this point, the reset is assumed to be coming from an external request and the internally latched states of the COP timeout and clock monitor failure are cleared so the normal reset vector ($FFFE:FFFF) is taken when reset is finally released. If reset is high after this nine cycle delay, the reset source is tentatively assumed to be either a COP failure or a clock monitor fail. If the internally latched state of the clock monitor fail circuit is true, processing begins by fetching the clock monitor vector ($FFFC:FFFD). If no clock monitor failure is indicated, and the latched state of the COP timeout is true, processing begins by fetching the COP vector ($FFFA:FFFB). If neither clock monitor fail nor COP timeout are pending, processing begins by fetching the normal reset vector ($FFFE:FFFF). MC68HC912DT128A MC68HC912DT128A Rev 2.0 9-pins MOTOROLA Pinout and Signal Descriptions 35 Pinout and Signal Descriptions Maskable Interrupt Request (IRQ) The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). IRQ is always enabled and configured to level-sensitive triggering at reset. It can be disabled by clearing IRQEN bit (INTCR register). When the MCU is reset the IRQ function is masked in the condition code register. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPE in the PUCR register. Nonmaskable Interrupt (XIRQ) The XIRQ input provides a means of requesting a nonmaskable interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software enables it. Because the XIRQ input is level sensitive, it can be connected to a multiple-source wired-OR network. This pin is always an input and can always be read. There is an active pull-up on this pin while in reset and immediately out of reset. The pullup can be turned off by clearing PUPE in the PUCR register. XIRQ is often used as a power loss detect interrupt. Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ must be configured for level-sensitive operation if there is more than one source of IRQ interrupt), each source must drive the interrupt input with an open-drain type of driver to avoid contention between outputs. There must also be an interlock mechanism at each interrupt source so that the source holds the interrupt line low until the MCU recognizes and acknowledges the interrupt request. If the interrupt line is held low, the MCU will recognize another interrupt as soon as the interrupt mask bit in the MCU is cleared (normally upon return from an interrupt). Mode Select (SMODN, MODA, and MODB) The state of these pins during reset determine the MCU operating mode. After reset, MODA and MODB can be configured as instruction queue tracking signals IPIPE0 and IPIPE1 in expanded modes. MODA and MODB have active pulldowns during reset. The SMODN pin has an active pullup when configured as an input. The pin can be used as BKGD or TAGHI after reset. MC68HC912DT128A MC68HC912DT128A Rev 2.0 36 10-pins Pinout and Signal Descriptions MOTOROLA Pinout and Signal Descriptions Signal Descriptions Single-Wire Background Mode Pin (BKGD) The BKGD pin receives and transmits serial background debugging commands. A special self-timing protocol is used. The BKGD pin has an active pullup when configured as an input; BKGD has no pullup control. Refer to Development Support. External Address and Data Buses (ADDR[15:0] and DATA[15:0]) External bus pins share functions with general-purpose I/O ports A and B. In single-chip operating modes, the pins can be used for I/O; in expanded modes, the pins are used for the external buses. In expanded wide mode, ports A and B are used for multiplexed 16-bit data and address buses. PA[7:0] correspond to ADDR[15:8]/DATA[15:8]; PB[7:0] correspond to ADDR[7:0]/DATA[7:0]. In expanded narrow mode, ports A and B are used for the16-bit address bus, and an 8-bit data bus is multiplexed with the most significant half of the address bus on port A. In this mode, 16-bit data is handled as two back-to-back bus cycles, one for the high byte followed by one for the low byte. PA[7:0] correspond to ADDR[15:8] and to DATA[15:8] or DATA[7:0], depending on the bus cycle. The state of the address pins should be latched at the rising edge of E. To allow for maximum address setup time at external devices, a transparent latch should be used. Read/Write (R/W) In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the read/write function is required it should be enabled by setting the RDWE bit in the PEAR register. External writes will not be possible until enabled. Low-Byte Strobe (LSTRB) In all modes this pin can be used as a general-purpose I/O and is an input with an active pull-up out of reset. If the strobe function is required, it should be enabled by setting the LSTRE bit in the PEAR register. This signal is used in write operations. Therefore external low byte writes will not be possible until this function is enabled. This pin is also used as TAGLO in Special Expanded modes and is multiplexed with the LSTRB function. MC68HC912DT128A MC68HC912DT128A Rev 2.0 11-pins MOTOROLA Pinout and Signal Descriptions 37 Pinout and Signal Descriptions Instruction Queue Tracking Signals (IPIPE1 and IPIPE0) IPIPE1 (PE6) and IPIPE0 (PE5) signals are used to track the state of the internal instruction queue. Data movement and execution state information is time-multiplexed on the two signals. Refer to Development Support. Data Bus Enable (DBE) The DBE pin (PE7) is an active low signal that will be asserted low during E-clock high time. DBE provides separation between output of a multiplexed address and the input of data. When an external address is stretched, DBE is asserted during what would be the last quarter cycle of the last E-clock cycle of stretch. In expanded modes this pin is used to enable the drive control of external buses during external reads. Use of the DBE is controlled by the NDBE bit in the PEAR register. DBE is enabled out of reset in expanded modes. Inverted E clock (ECLK) The ECLK pin (PE7) can be used to latch the address for de-multiplexing. It has the same behavior as the ECLK, except is inverted. In expanded modes this pin is used to enable the drive control of external buses during external reads. Use of the ECLK is controlled by the NDBE and DBENE bits in the PEAR register. Calibration reference (CAL) The CAL pin (PE7) is the output of the Slow Mode programmable clock divider, SLWCLK, and is used as a calibration reference. The SLWCLK frequency is equal to the crystal frequency out of reset and always has a 50% duty. If the DBE function is enabled it will override the enabled CAL output. The CAL pin output is disabled by clearing CALE bit in the PEAR register. Clock generation module test(CGMTST) The CGMTST pin (PE6) is the output of the clocks tested when CGMTE bit is set in PEAR register. The PIPOE bit must be cleared for the clocks to be tested MC68HC912DT128A MC68HC912DT128A Rev 2.0 38 12-pins Pinout and Signal Descriptions MOTOROLA Pinout and Signal Descriptions Signal Descriptions Table 6 MC68HC912DT128A MC68HC912DT128A Signal Description Summary Pin Name Shared port Pin Number Description 112-pin EXTAL - 47 XTAL - 48 RESET - 46 ADDR[7:0] DATA[7:0] PB[7:0] 31­24 ADDR[15:8] DATA[15:8] PA[7:0] 64­57 DBE PE7 36 Data bus control and, in expanded mode, enables the drive control of external buses during external reads. ECLK PE7 36 Inverted E clock used to latch the address. CAL PE7 36 CAL is the output of the Slow Mode programmable clock divider, SLWCLK, and is used as a calibration reference for functions such as time of day. It is overridden when DBE function is enabled. It always has a 50% duty. CGMTST PE6 37 Clock generation module test output. Crystal driver and external clock input pins. On reset all the device clocks are derived from the EXTAL input frequency. XTAL is the crystal output. An active low bidirectional control signal, RESET acts as an input to initialize the MCU to a known start-up state, and an output when COP or clock monitor causes a reset. External bus pins share function with general-purpose I/O ports A and B. In single chip modes, the pins can be used for I/O. In expanded modes, the pins are used for the external buses. MODB/IPIPE1, MODA/IPIPE0 PE6, PE5 37, 38 State of mode select pins during reset determine the initial operating mode of the MCU. After reset, MODB and MODA can be configured as instruction queue tracking signals IPIPE1 and IPIPE0 or as general-purpose I/O pins. ECLK PE4 39 E Clock is the output connection for the external bus clock. ECLK is used as a timing reference and for address demultiplexing. LSTRB/TAGLO PE3 53 Low byte strobe (0 = low byte valid), in all modes this pin can be used as I/O. The low strobe function is the exclusive-NOR of A0 and the internal SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin function TAGLO used in instruction tagging. See Development Support. R/W PE2 54 Indicates direction of data on expansion bus. Shares function with general-purpose I/O. Read/write in expanded modes. IRQ PE1 55 Maskable interrupt request input provides a means of applying asynchronous interrupt requests to the MCU. Either falling edge-sensitive triggering or level-sensitive triggering is program selectable (INTCR register). XIRQ PE0 56 Provides a means of requesting asynchronous nonmaskable interrupt requests after reset initialization 23 During reset, this pin determines special or normal operating mode. After reset, single-wire background interface pin is dedicated to the background debug function. Pin function TAGHI used in instruction tagging. See Development Support. SMODN/BKGD/ TAGHI - MC68HC912DT128A MC68HC912DT128A Rev 2.0 13-pins MOTOROLA Pinout and Signal Descriptions 39 Pinout and Signal Descriptions Table 6 MC68HC912DT128A MC68HC912DT128A Signal Description Summary Pin Name Shared port Pin Number Description 112-pin IX[2:0] PK[2:0] ECS PK7 PW[3:0] PP[3:0] SS PS7 96 Slave select output for SPI master mode, input for slave mode or master mode. SCK PS6 95 Serial clock for SPI system. SDO/MOSI PS5 94 Master out/slave in pin for serial peripheral interface SDI/MISO PS4 93 Master in/slave out pin for serial peripheral interface TxD1 PS3 92 SCI1 transmit pin RxD1 PS2 91 SCI1 receive pin TxD0 PS1 90 SCI0 transmit pin RxD0 PS0 89 SCI0 receive pin IOC[7:0] PT[7:0] 18­15, 7­4 AN1[7:0] PAD1[7:0] 84/82/80 /78/76/7 Analog inputs for the analog-to-digital conversion module 1 4/72/70 AN0[7:0] PAD0[7:0] 83/81/79 /77/75/7 Analog inputs for the analog-to-digital conversion module 0 3/71/69 TxCAN2(1) - 100 MSCAN2 transmit pin (MC68HC912DT128A MC68HC912DT128A only). Leave unconnected if MSCAN2 is not used. RxCAN2(1) - 101 MSCAN2 receive pin (MC68HC912DT128A MC68HC912DT128A only). TxCAN1 - 102 MSCAN1 transmit pin. Leave unconnected if MSCAN1 is not used. RxCAN1 - 103 MSCAN1 receive pin. TxCAN0 - 104 MSCAN0 transmit pin. If the MSCAN is not used, Leave unconnected if MSCAN0 is not used. RxCAN0 - 105 MSCAN0 receive pin. SCL PIB7 98 I2C bus serial clock line pin SDA PIB6 99 I2C bus serial data line pin KWJ[7:0] PJ[7:0] 8­11, 19­22 Key wake-up and general purpose I/O; can cause an interrupt when an input transitions from high to low or from low to high (KWPJ). KWH[7:0] PH[7:0] 32­35, 49­52 Key wake-up and general purpose I/O; can cause an interrupt when an input transitions from high to low or from low to high (KWPH). 1 109-111 Page Index register emulation outputs. 108 Emulation Chip select. 112, 1­3 Pulse Width Modulator channel outputs. Pins used for input capture and output compare in the timer and pulse accumulator subsystem. MC68HC912DT128A MC68HC912DT128A only MC68HC912DT128A MC68HC912DT128A Rev 2.0 40 14-pins Pinout and Signal Descriptions MOTOROLA Pinout and Signal Descriptions Port Signals Port Signals The MC68HC912DT128A MC68HC912DT128A incorporates eleven ports which are used to control and access the various device subsystems. When not used for these purposes, port pins may be used for general-purpose I/O. In addition to the pins described below, each port consists of a data register which can be read and written at any time, and, with the exception of port AD0, port AD1, PE[1:0], RxCAN and TxCAN, a data direction register which controls the direction of each pin. After reset all general purpose I/O pins are configured as input. Port A Port A pins are used for address and data in expanded modes. When this port is not used for external access such as in single-chip mode, these pins can be used as general purpose I/O. The port data register is not in the address map during expanded and peripheral mode operation. When it is in the map, port A can be read or written at anytime. Register DDRA determines whether each port A pin is an input or output. DDRA is not in the address map during expanded and peripheral mode operation. Setting a bit in DDRA makes the corresponding bit in port A an output; clearing a bit in DDRA makes the corresponding bit in port A an input. The default reset state of DDRA is all zeroes. When the PUPA bit in the PUCR register is set, all port A input pins are pulled-up internally by an active pull-up device. PUCR is not in the address map in peripheral mode. Setting the RDPA bit in register RDRIV causes all port A outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Bus Control and Input/Output. Port B Port B pins are used for address and data in expanded modes. When this port is not used for external access such as in single-chip mode, these pins can be used as general purpose I/O. The port data register is not in the address map during expanded and peripheral mode operation. When it is in the map, port B can be read or written at anytime. MC68HC912DT128A MC68HC912DT128A Rev 2.0 15-pins MOTOROLA Pinout and Signal Descriptions 41 Pinout and Signal Descriptions Register DDRB determines whether each port B pin is an input or output. DDRB is not in the address map during expanded and peripheral mode operation. Setting a bit in DDRB makes the corresponding bit in port B an output; clearing a bit in DDRB makes the corresponding bit in port B an input. The default reset state of DDRB is all zeroes. When the PUPB bit in the PUCR register is set, all port B input pins are pulled-up internally by an active pull-up device. PUCR is not in the address map in peripheral mode. Setting the RDPB bit in register RDRIV causes all port B outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Bus Control and Input/Output. Port E Port E pins operate differently from port A and B pins. Port E pins are used for bus control signals and interrupt service request signals. When a pin is not used for one of these specific functions, it can be used as general-purpose I/O. However, two of the pins (PE[1:0]) can only be used for input, and the states of these pins can be read in the port data register even when they are used for IRQ and XIRQ. The PEAR register determines pin function, and register DDRE determines whether each pin is an input or output when it is used for general-purpose I/O. PEAR settings override DDRE settings. Because PE[1:0] are input-only pins, only DDRE[7:2] have effect. Setting a bit in the DDRE register makes the corresponding bit in port E an output; clearing a bit in the DDRE register makes the corresponding bit in port E an input. The default reset state of DDRE is all zeroes. When the PUPE bit in the PUCR register is set, PE[7,3,2,1,0] are pulled up. PE[7,3,2,0] are active pull-up devices. PUPCR is not in the address map in peripheral mode. Neither port E nor DDRE is in the map in peripheral mode or in the internal map in expanded modes with EME set. Setting the RDPE bit in register RDRIV causes all port E outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not MC68HC912DT128A MC68HC912DT128A Rev 2.0 42 16-pins Pinout and Signal Descriptions MOTOROLA Pinout and Signal Descriptions Port Signals in the address map in peripheral mode. Refer to Bus Control and Input/Output. Port H Port H pins are used for key wake-ups that can be used with the pins configured as inputs or outputs. The key wake-ups are triggered with either a rising or falling edge signal (KWPH). An interrupt is generated if the corresponding bit is enabled (KWIEH). If any of the interrupts is not enabled, the corresponding pin can be used as a general purpose I/O pin. Refer to I/O Ports With Key Wake-Up. Register DDRH determines whether each port H pin is an input or output. Setting a bit in DDRH makes the corresponding bit in port H an output; clearing a bit in DDRH makes the corresponding bit in port H an input. The default reset state of DDRH is all zeroes. Register KWPH not only determines what type of edge the key wake ups are triggered, but it also determines what type of resistive load is used for port H input pins when PUPH bit is set in the PUCR register. Setting a bit in KWPH makes the corresponding key wake up input pin trigger at rising edges and loads a pull down in the corresponding port H input pin. Clearing a bit in KWPH makes the corresponding key wake up input pin trigger at falling edges and loads a pull up in the corresponding port H input pin. The default state of KWPH is all zeroes. Setting the RDPH bit in register RDRIV causes all port H outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Bus Control and Input/Output. Port J Port J pins are used for key wake-ups that can be used with the pins configured as inputs or outputs. The key wake-ups are triggered with either a rising or falling edge signal (KWPJ). An interrupt is generated if the corresponding bit is enabled (KWIEJ). If any of the interrupts is not enabled, the corresponding pin can be used as a general purpose I/O pin. Refer to I/O Ports With Key Wake-Up. Register DDRJ determines whether each port J pin is an input or output. Setting a bit in DDRJ makes the corresponding bit in port J an output; MC68HC912DT128A MC68HC912DT128A Rev 2.0 17-pins MOTOROLA Pinout and Signal Descriptions 43 Pinout and Signal Descriptions clearing a bit in DDRJ makes the corresponding bit in port J an input. The default reset state of DDRJ is all zeroes. Register KWPJ not only determines what type of edge the key wake ups are triggered, but it also determines what type of resistive load is used for port J input pins when PUPJ bit is set in the PUCR register. Setting a bit in KWPJ makes the corresponding key wake up input pin trigger at rising edges and loads a pull down in the corresponding port J input pin. Clearing a bit in KWPJ makes the corresponding key wake up input pin trigger at falling edges and loads a pull up in the corresponding port J input pin. The default state of KWPJ is all zeroes. Setting the RDPJ bit in register RDRIV causes all port J outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Bus Control and Input/Output. Port K Port K pins are used for page index emulation in expanded or peripheral modes. When page index emulation is not enabled, EMK is not set in MODE register, or the part is in single chip mode, these pins can be used for general purpose I/O. Port K bit 3 is used as a general purpose I/O pin only. The port data register is not in the address map during expanded and peripheral mode operation with EMK set. When it is in the map, port K can be read or written at anytime. Register DDRK determines whether each port K pin is an input or output. DDRK is not in the address map during expanded and peripheral mode operation with EMK set. Setting a bit in DDRK makes the corresponding bit in port K an output; clearing a bit in DDRK makes the corresponding bit in port K an input. The default reset state of DDRK is all zeroes. When the PUPK bit in the PUCR register is set, all port K input pins are pulled-up internally by an active pull-up device. PUCR is not in the address map in peripheral mode. Setting the RDPK bit in register RDRIV causes all port K outputs to have reduced drive level. RDRIV can be written once after reset. RDRIV is not in the address map in peripheral mode. Refer to Bus Control and Input/Output. MC68HC912DT128A MC68HC912DT128A Rev 2.0 44 18-pins Pinout and Signal Descriptions MOTOROLA Pinout and Signal Descriptions Port Signals Port CAN2 (MC68HC912DT12 MC68HC912DT12 8A only) The MSCAN2 uses two external pins, one input (RxCAN2) and one output (TxCAN2). The TxCAN2 output pin represents the logic level on the CAN: `0' is for a dominant state, and `1' is for a recessive state. RxCAN2 is on bit 0 of Port CAN2, TxCAN2 is on bit 1. If the MSCAN2 is not used, TxCAN2 should be left unconnected. Port CAN1 The MSCAN1 uses two external pins, one input (RxCAN1) and one output (TxCAN1). The TxCAN1 output pin represents the logic level on the CAN: `0' is for a dominant state, and `1' is for a recessive state. RxCAN1 is on bit 0 of Port CAN1, TxCAN1 is on bit 1. If the MSCAN1 is not used, TxCAN1 should be left unconnected. Port CAN0 The MSCAN0 uses two external pins, one input (RxCAN0) and one output (TxCAN0). The TxCAN0 output pin represents the logic level on the CAN: `0' is for a dominant state, and `1' is for a recessive state. RxCAN0 is on bit 0 of Port CAN0, TxCAN0 is on bit 1. If the MSCAN0 is not used, TxCAN0 should be left unconnected. Port IB Bidirectional pins to IIC bus interface subsystem. The IIC bus interface uses a Serial Data line (SDA) and Serial Clock line (SCL) for data transfer. The pins are connected to a positive voltage supply via a pull up resistor. The pull ups can be enabled internally or connected externally. The output stages have open drain outputs in order to perform the wired-AND function. When the IIC is disabled the pins can be used as general purpose I/O pins. SCL is on bit 7 of Port IB and SDA is on bit 6. On the MC68HC912DG128A MC68HC912DG128A, the remaining two pins of Port IB (PIB5 and PIB4) are controlled by registers in the IIC address space. Register DDRIB determines pin direction of port IB when used for general-purpose I/O. When DDRIB bits are set, the corresponding pin is configured for output. On reset the DDRIB bits are cleared and the corresponding pin is configured for input. When the PUPIB bit in the IBPURD register is set, all input pins are pulled up internally by an active pull-up device. Pullups are disabled after reset, except for input ports 0 through 5, which are always on regardless of PUPIB bit. MC68HC912DT128A MC68HC912DT128A Rev 2.0 19-pins MOTOROLA Pinout and Signal Descriptions 45 Pinout and Signal Descriptions Setting the RDPIB bit in the IBPURD register configures all port IB outputs to have reduced drive levels. Levels are at normal drive capability after reset. The IBPURD register can be read or written anytime after reset. Refer to section Inter-IC Bus. Port AD1 This port is an analog input interface to the analog-to-digital subsystem and used for general-purpose input. When analog-to-digital functions are not enabled, the port has eight general-purpose input pins, PAD1[7:0]. The ADPU bit in the ATD1CTL2 register enables the A/D function. Port AD1 pins are inputs; no data direction register is associated with this port. The port has no resistive input loads and no reduced drive controls. Refer to Analog-To-Digital Converter (ATD). Port AD0 This port is an analog input interface to the analog-to-digital subsystem and used for general-purpose input. When analog-to-digital functions are not enabled, the port has eight general-purpose input pins, PAD0[7:0]. The ADPU bit in the ATD0CTL2 register enables the A/D function. Port AD0 pins are inputs; no data direction register is associated with this port. The port has no resistive input loads and no reduced drive controls. Refer to Analog-To-Digital Converter (ATD). Port P The four pulse-width modulation channel outputs share general-purpose port P pins. The PWM function is enabled with the PWEN register. Enabling PWM pins takes precedence over the general-purpose port. When pulse-width modulation is not in use, the port pins may be used for general-purpose I/O. Register DDRP determines pin direction of port P when used for general-purpose I/O. When DDRP bits are set, the corresponding pin is configured for output. On reset the DDRP bits are cleared and the corresponding pin is configured for input. MC68HC912DT128A MC68HC912DT128A Rev 2.0 46 20-pins Pinout and Signal Descriptions MOTOROLA Pinout and Signal Descriptions Port Signals When the PUPP bit in the PWCTL register is set, all input pins are pulled up internally by an active pull-up device. Pullups are disabled after reset. Setting the RDPP bit in the PWCTL register configures all port P outputs to have reduced drive levels. Levels are at normal drive capability after reset. The PWCTL register can be read or written anytime after reset. Refer to Pulse-Width Modulator. Port S Port S is the 8-bit interface to the standard serial interface consisting of the two serial communications interfaces (SCI1 and SCI0) and the serial peripheral interface (SPI) subsystems. Port S pins are available for general-purpose I/O when standard serial functions are not enabled. Port S pins serve several functions depending on the various internal control registers. If WOMS bit in the SC0CR1register is set, the P-channel drivers of the output buffers are disabled (wire-or mode) for pins 0 through 3. If SWOM bit in the SP0CR1 register is set, the P-channel drivers of the output buffers are disabled (wire-or mode) for pins 4 through 7. The open drain control affects both the serial and the general-purpose outputs. If the RDPS bit in the SP0CR2 register is set, Port S pin drive capabilities are reduced. If PUPS bit in the SP0CR2 register is set, a pull-up device is activated for each port S pin programmed as a general purpose input. If the pin is programmed as a general-purpose output, the pull-up is disconnected from the pin regardless of the state of PUPS bit. See Multiple Serial Interface. Port T This port provides eight general-purpose I/O pins when not enabled for input capture and output compare in the timer and pulse accumulator subsystem. The TEN bit in the TSCR register enables the timer function. The pulse accumulator subsystem is enabled with the PAEN bit in the PACTL register. Register DDRT determines pin direction of port T when used for general-purpose I/O. When DDRT bits are set, the corresponding pin is configured for output. On reset the DDRT bits are cleared and the corresponding pin is configured for input. MC68HC912DT128A MC68HC912DT128A Rev 2.0 21-pins MOTOROLA Pinout and Signal Descriptions 47 Pinout and Signal Descriptions When the PUPT bit in the TMSK2 register is set, all input pins are pulled up internally by an active pull-up device. Pullups are disabled after reset. Setting the RDPT bit in the TMSK2 register configures all port T outputs to have reduced drive levels. Levels are at normal drive capability after reset. The TMSK2 register can be read or written anytime after reset. Refer to Enhanced Capture Timer. Table 7 MC68HC912DT128A MC68HC912DT128A Port Description Summary Port Name Pin Numbers 112-pin Data Direction Register (Address) Description Port A PA[7:0] 64-57 In/Out DDRA ($0002) Port B PB[7:0] 31­24 In/Out DDRB ($0003) Port AD1 PAD1[7:0] 84/82/80/ 78/76/74/ 72/70 In Analog-to-digital converter 1 and general-purpose I/O. Port AD0 PAD0[7:0] 83/81/79/ 77/75/73/ 71/69 In Analog-to-digital converter 0 and general-purpose I/O. 100­101 PCAN2[1] Out PCAN2[0] In PCAN2[1:0] are used with the MSCAN2 module and cannot be used as general purpose I/O (MC68HC912DT128A MC68HC912DT128A only). Port CAN1 PCAN1[1:0] 102­103 PCAN1[1] Out PCAN1[0] In PCAN1[1:0] are used with the MSCAN1 module and cannot be used as general purpose I/O. Port CAN0 PCAN0[1:0] 104­105 PCAN0[1] Out PCAN0[0] In PCAN0[1:0] are used with the MSCAN0 module and cannot be used as general purpose I/O. Port IB PIB[7:6] 98­99 In/Out DDRIB ($00E7) General purpose I/O. PIB[7:6] are used with the I-Bus module when enabled. Port IB PIB[5:4](2) 100­101 In/Out DDRIB ($00E7) General purpose I/O (MC68HC912DG128A MC68HC912DG128A only). Port E PE[7:0] 36­39, 53­56 PE[1:0] In PE[7:2] In/Out DDRE ($0009) Mode selection, bus control signals and interrupt service request signals; or general-purpose I/O. Port K PK[7,3:0] 13, 108-111 In/Out DDRK ($00FD) Page index emulation signals in expanded or peripheral mode or general-purpose I/O. Port CAN2 PCAN2[1:0] (1) Port A and port B pins are used for address and data in expanded modes. The port data registers are not in the address map during expanded and peripheral mode operation. When in the map, port A and port B can be read or written any time. DDRA and DDRB are not in the address map in expanded or peripheral modes. MC68HC912DT128A MC68HC912DT128A Rev 2.0 48 22-pins Pinout and Signal Descriptions MOTOROLA Pinout and Signal Descriptions Port Signals Table 7 MC68HC912DT128A MC68HC912DT128A Port Description Summary Port Name Pin Numbers 112-pin Data Direction Register (Address) Description Port P PP[3:0] 112, 1­3 In/Out DDRP ($0057) General-purpose I/O. PP[3:0] are used with the pulse-width modulator when enabled. Port S PS[7:0] 96­89 In/Out DDRS ($00D7) Serial communications interfaces 1 and 0 and serial peripheral interface subsystems; or general-purpose I/O. Port T PT[7:0] 18­15, 7­4 In/Out DDRT ($00AF) General-purpose I/O when not enabled for input capture and output compare in the timer and pulse accumulator subsystem. 1 MC68HC912DT128A MC68HC912DT128A only 2 MC68HC912DG128A MC68HC912DG128A only Port Pull-Up Pull-Down and Reduced Drive MCU ports can be configured for internal pull-up. To reduce power consumption and RFI, the pin output drivers can be configured to operate at a reduced drive level. Reduced drive causes a slight increase in transition time depending on loading and should be used only for ports which have a light loading. Table 1 summarizes the port pull-up default status and controls. Table 1 Port Pull-Up, Pull-Down and Reduced Drive Summary Port Resistive Name Input Loads Port A Pull-up Port B Pull-up Port E: PE7, PE[3:2] Pull-up PE[1:0] Pull-up PE[6:4] None Pull-up or Port H Pull-down Pull-up or Port J Pull-down Port K Pull-up Port P Pull-up Enable Bit Reduced Drive Control Bit Register Reset Register Reset Bit Name Bit Name (Address) State (Address) State PUCR ($000C) PUPA Disabled RDRIV ($000D) RDPA Full drive PUCR ($000C) PUPB Disabled RDRIV ($000D) RDPB Full drive PUCR ($000C) PUCR ($000C) PUPE PUPE Enabled Enabled Full drive PUCR ($000C) PUPH Disabled RDRIV ($000D) RDPH Full drive PUCR ($000C) PUPJ Disabled RDRIV ($000D) RDPJ Full drive PUCR ($000C) PWCTL ($0054) PUPK PUPP Disabled RDRIV ($000D) Disabled PWCTL ($0054) SP0CR2 Enabled ($00D1) Disabled TMSK2 ($008D) RDPK RDPP Full drive Full drive RDPS Full drive TDRB Full drive Port S Pull-up SP0CR2 ($00D1) PUPS Port T Pull-up TMSK2 ($008D) TPU MC68HC912DT128A MC68HC912DT128A Rev 2.0 23-pins MOTOROLA RDPE - RDPE Full drive RDRIV ($000D) - RDRIV ($000D) Pinout and Signal Descriptions 49 Pinout and Signal Descriptions Table 1 Port Pull-Up, Pull-Down and Reduced Drive Summary Enable Bit Port Resistive Name Input Loads Port IB[7:6] Pull-up Port Pull-up IB[5:4](1) Port AD0 None Port AD1 None Port None CAN2[1](2) Port Pull-up CAN2[0](2) Port CAN1[1] None Port CAN1[0] Pull-up Port CAN0[1] None Port CAN0[0] Pull-up 1 IBPURD ($00E5) PUPIB Disabled IBPURD ($00E5) RDPIB - - - - - - Always enabled - - Always enabled - Always enabled Full drive - - - - MC68HC912DG128A MC68HC912DG128A only 2 Register (Address) IBPURD ($00E5) Reduced Drive Control Bit Reset Register Reset Bit Name State Bit Name (Address) State PUPIB Disabled IBPURD ($00E5) RDPIB Full drive MC68HC912DT128A MC68HC912DT128A only MC68HC912DT128A MC68HC912DT128A Rev 2.0 50 24-pins Pinout and Signal Descriptions MOTOROLA Registers Registers Contents Register Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Register Block The register block can be mapped to any 2K byte boundary within the standard 64K byte address space by manipulating bits REG[15:11] in the INITRG register. INITRG establishes the upper five bits of the register block's 16-bit address. The register block occupies the first 1K byte of the 2K byte block. Default addressing (after reset) is indicated in the table below. For additional information refer to Operating Modes. Table 8 MC68HC912DT128A MC68HC912DT128A Register Map (Sheet 1 of 11) Address $0000 $0001 $0002 $0003 $0004-$ 0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 Bit 7 PA7 PB7 DDA7 DDB7 6 PA6 PB6 DDA6 DDB6 5 PA5 PB5 DDA5 DDB5 4 PA4 PB4 DDA4 DDB4 3 PA3 PB3 DDA3 DDB3 2 PA2 PB2 DDA2 DDB2 1 PA1 PB1 DDA1 DDB1 Bit 0 PA0 PB0 DDA0 DDB0 Name PORTA(1) PORTB(1) DDRA(1) DDRB(1) 0 0 0 0 0 0 0 0 Reserved(3) PE7 DDE7 NDBE SMODN PUPK RDPK 0 0 RAM15 RAM15 REG15 REG15 PE6 DDE6 CGMTE MODB PUPJ RDPJ 0 0 RAM14 RAM14 REG14 REG14 PE5 DDE5 PIPOE MODA PUPH RDPH 0 0 RAM13 RAM13 REG13 REG13 PE4 DDE4 NECLK ESTR PUPE RDPE 0 0 0 REG12 REG12 PE3 DDE3 LSTRE IVIS 0 0 0 0 0 REG11 REG11 PE2 DDE2 RDWE EBSWAI 0 0 0 0 0 0 PE1 0 CALE EMK PUPB RDPB 0 0 0 0 MC68HC912DT128A MC68HC912DT128A Rev 2.0 1-reg MOTOROLA PE0 PORTE(2) 0 DDRE(2) DBENE PEAR(3) EME MODE(3) PUPA PUCR(3) RDPA RDRIV(3) 0 Reserved(3) 0 Reserved(3) 0 INITRM MMSWAI INITRG Registers 51 Registers Table 8 MC68HC912DT128A MC68HC912DT128A Register Map (Sheet 2 of 11) Address Bit 7 6 5 $0012 EE15 EE14 EE13 $0013 ROMTST NDRF RFSTR1 $0014 RTIE RSWAI RSBCK $0015 RTIF 0 0 $0016 CME FCME FCMCOP $0017 Bit 7 6 5 $0018 ITE6 ITE8 ITEA $0019 ITD6 ITD8 ITDA $001A ITC6 ITC8 ITCA $001B ITB6 ITB8 ITBA $001C ITA6 ITA8 ITAA $001D 0 0 0 $001E IRQE IRQEN DLY $001F 1 PSEL6 PSEL5 $0020 BKEN1 BKEN0 BKPM $0021 0 BKDBE BKMBH $0022 Bit 15 14 13 $0023 Bit 7 6 5 $0024 Bit 15 14 13 $0025 Bit 7 6 5 $0026 0 0 0 $0027 0 0 0 $0028 PJ7 PJ6 PJ5 $0029 PH7 PH6 PH5 $002A DDJ7 DDJ6 DDJ5 $002B DDH7 DDH6 DDH5 $002C KWIEJ7 KWIEJ6 KWIEJ5 $002D KWIEH7 KWIEH6 KWIEH5 $002E KWIFJ7 KWIFJ6 KWIFJ5 $002F KWIFH7 KWIFH6 KWIFH5 $0030 KWPJ7 KWPJ6 KWPJ5 $0031 KWPH7 KWPH6 KWPH5 $0032 0 0 0 $0033 0 0 0 $0034­ $0037 $0038 0 0 SYN5 $0039 0 0 0 $003A TSTOUT7 TSTOUT6 TSTOUT5 $003B LOCKIF LOCK 0 $003C LOCKIE PLLON AUTO 4 EE12 RFSTR0 Reserved 0 WCOP 4 ITEC ITDC ITCC ITBC ITAC 0 0 PSEL4 0 BKMBL 12 4 12 4 0 0 PJ4 PH4 DDJ4 DDH4 KWIEJ4 KWIEH4 KWIFJ4 KWIFH4 KWPJ4 KWPH4 0 0 3 2 1 Bit 0 0 0 0 EEON EXSTR1 EXSTR0 ROMHM ROMON RTBYP RTR2 RTR1 RTR0 0 0 0 0 DISR CR2 CR1 CR0 3 2 1 Bit 0 ITEE ITF0 ITF2 ITF4 ITDE ITE0 ITE2 ITE4 ITCE ITD0 ITD2 ITD4 ITBE ITC0 ITC2 ITC4 ITAE ITB0 ITB2 ITB4 0 0 0 0 0 0 0 0 PSEL3 PSEL2 PSEL1 0 BK1ALE BK0ALE 0 0 BK1RWE BK1RW BK0RWE BK0RW 11 10 9 Bit 8 3 2 1 Bit 0 11 10 9 Bit 8 3 2 1 Bit 0 0 0 0 0 0 0 0 0 PJ3 PJ2 PJ1 PJ0 PH3 PH2 PH1 PH0 DDJ3 DDJ2 DDJ1 DDJ0 DDH3 DDH2 DDH1 DDH0 KWIEJ3 KWIEJ2 KWIEJ1 KWIEJ0 KWIEH3 KWIEH2 KWIEH1 KWIEH0 KWIFJ3 KWIFJ2 KWIFJ1 KWIFJ0 KWIFH3 KWIFH2 KWIFH1 KWIFH0 KWPJ3 KWPJ2 KWPJ1 KWPJ0 KWPH3 KWPH2 KWPH1 KWPH0 0 0 0 0 0 0 0 0 Unimplemented(4) SYN4 SYN3 SYN2 SYN1 SYN0 0 0 REFDV2 REFDV1 REFDV0 TSTOUT4 TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0 0 0 0 LHIF LHOME ACQ 0 PSTP LHIE NOLHM MC68HC912DT128A MC68HC912DT128A Rev 2.0 52 Name INITEE MISC RTICTL RTIFLG COPCTL COPRST ITST0 ITST1 ITST2 ITST3 ITST4 Reserved INTCR HPRIO BRKCT0 BRKCT1 BRKAH BRKAL BRKDH BRKDL Reserved Reserved PORTJ PORTH DDRJ DDRH KWIEJ KWIEH KWIFJ KWIFH KWPJ KWPH Reserved Reserved Reserved SYNR REFDV CGTFLG PLLFLG PLLCR 2-reg Registers MOTOROLA Registers Register Block Table 8 MC68HC912DT128A MC68HC912DT128A Register Map (Sheet 3 of 11) Address $003D $003E $003F $0040 $0041 $0042 $0043 $0044 $0045 $0046 $0047 $0048 $0049 $004A $004B $004C $004D $004E $004F $0050 $0051 $0052 $0053 $0054 $0055 $0056 $0057 $0058-$ 005F $0060 $0061 $0062 $0063 $0064 $0065 $0066 $0067 $0068 $0069 $006A­$ 006E Bit 7 0 0 OPNLE CON23 CON23 PCLK3 0 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 Bit 7 0 DISCR PP7 DDP7 6 BCSP 0 TRK CON01 CON01 PCLK2 0 Bit 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 0 DISCP PP6 DDP6 5 BCSS SLDV5 TSTCLKE PCKA2 PCLK1 0 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 0 DISCAL PP5 DDP5 4 0 SLDV4 TST4 PCKA1 PCLK0 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 PSWAI 0 PP4 DDP4 3 0 SLDV3 TST3 PCKA0 PPOL3 PWEN3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 CENTR 0 PP3 DDP3 2 MCS SLDV2 TST2 PCKB2 PPOL2 PWEN2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 RDPP 0 PP2 DDP2 1 0 SLDV1 TST1 PCKB1 PPOL1 PWEN1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PUPP 0 PP1 DDP1 Bit 0 0 SLDV0 TST0 PCKB0 PPOL0 PWEN0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 0 PSBCK 0 PP0 DDP0 Name CLKSEL SLOW CGTCTL PWCLK PWPOL PWEN PWPRES PWSCAL0 PWSCNT0 PWSCAL1 PWSCNT1 PWCNT0 PWCNT1 PWCNT2 PWCNT3 PWPER0 PWPER1 PWPER2 PWPER3 PWDTY0 PWDTY1 PWDTY2 PWDTY3 PWCTL PWTST PORTP DDRP 0 0 0 0 0 0 0 0 Reserved ADPU 0 RES10 RES10 0 SCF CCF7 SAR9 SAR1 AFFC 0 SMP1 S8C 0 CCF6 SAR8 SAR0 ASWAI 0 SMP0 SCAN 0 CCF5 SAR7 RST 0 0 0 Reserved Reserved DJM DSGN 0 S1C PRS4 PRS3 MULT CD 0 0 CCF4 CCF3 SAR6 SAR5 TSTOUT TST3 0 0 ASCIE FRZ1 PRS1 CB CC1 CCF1 SAR3 TST1 ASCIF FRZ0 PRS0 CA CC0 CCF0 SAR2 TST0 0 0 0 Reserved MC68HC912DT128A MC68HC912DT128A Rev 2.0 3-reg MOTOROLA Reserved FIFO PRS2 CC CC2 CCF2 SAR4 TST2 ATD0CTL0 ATD0CTL1 ATD0CTL2 ATD0CTL3 ATD0CTL4 ATD0CTL5 ATD0STAT0 ATD0STAT1 ATD0TESTH ATD0TESTL Registers 53 Registers Table 8 MC68HC912DT128A MC68HC912DT128A Register Map (Sheet 4 of 11) Address $006F $0070 $0071 $0072 $0073 $0074 $0075 $0076 $0077 $0078 $0079 $007A $007B $007C $007D $007E $007F $0080 $0081 $0082 $0083 $0084 $0085 $0086 $0087 $0088 $0089 $008A $008B $008C $008D $008E $008F $0090 $0091 $0092 $0093 $0094 $0095 $0096 $0097 Bit 7 PAD07 PAD07 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 IOS7 FOC7 OC7M7 OC7D7 Bit 15 Bit 7 TEN 6 PAD06 PAD06 14 Bit 6 14 Bit 6 14 Bit 6 14 Bit 6 14 Bit 6 14 Bit 6 14 Bit 6 14 Bit 6 IOS6 FOC6 OC7M6 OC7D6 14 6 TSWAI 5 PAD05 PAD05 13 0 13 0 13 0 13 0 13 0 13 0 13 0 13 0 IOS5 FOC5 OC7M5 OC7D5 13 5 TSBCK OM7 OM3 EDG7B EDG3B C7I TOI C7F TOF Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 OL7 OL3 EDG7A EDG3A C6I 0 C6F 0 14 6 14 6 14 6 14 6 OM6 OM2 EDG6B EDG2B C5I PUPT C5F 0 13 5 13 5 13 5 13 5 4 3 PAD04 PAD04 PAD03 PAD03 12 11 0 0 12 11 0 0 12 11 0 0 12 11 0 0 12 11 0 0 12 11 0 0 12 11 0 0 12 11 0 0 IOS4 IOS3 FOC4 FOC3 OC7M4 OC7M3 OC7D4 OC7D3 12 11 4 3 TFFCA Reserved OL6 OM5 OL2 OM1 EDG6A EDG5B EDG2A EDG1B C4I C3I RDPT TCRE C4F C3F 0 0 12 11 4 3 12 11 4 3 12 11 4 3 12 11 4 3 MC68HC912DT128A MC68HC912DT128A Rev 2.0 54 2 1 PAD02 PAD02 PAD01 PAD01 10 9 0 0 10 9 0 0 10 9 0 0 10 9 0 0 10 9 0 0 10 9 0 0 10 9 0 0 10 9 0 0 IOS2 IOS1 FOC2 FOC1 OC7M2 OC7M1 OC7D2 OC7D1 10 9 2 1 Reserved Bit 0 PAD00 PAD00 Bit 8 0 Bit 8 0 Bit 8 0 Bit 8 0 Bit 8 0 Bit 8 0 Bit 8 0 Bit 8 0 IOS0 FOC0 OC7M0 OC7D0 Bit 8 Bit 0 OL5 OL1 EDG5A EDG1A C2I PR2 C2F 0 10 2 10 2 10 2 10 2 OL4 OL0 EDG4A EDG0A C0I PR0 C0F 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 OM4 OM0 EDG4B EDG0B C1I PR1 C1F 0 9 1 9 1 9 1 9 1 Name PORTAD0 ADR00H ADR00H ADR00L ADR00L ADR01H ADR01H ADR01L ADR01L ADR02H ADR02H ADR02L ADR02L ADR03H ADR03H ADR03L ADR03L ADR04H ADR04H ADR04L ADR04L ADR05H ADR05H ADR05L ADR05L ADR06H ADR06H ADR06L ADR06L ADR07H ADR07H ADR07L ADR07L TIOS CFORC OC7M OC7D TCNT TCNT TSCR TQCR TCTL1 TCTL2 TCTL3 TCTL4 TMSK1 TMSK2 TFLG1 TFLG2 TC0 TC0 TC1 TC1 TC2 TC2 TC3 TC3 4-reg Registers MOTOROLA Registers Register Block Table 8 MC68HC912DT128A MC68HC912DT128A Register Map (Sheet 5 of 11) Address $0098 $0099 $009A $009B $009C $009D $009E $009F $00A0 $00A1 $00A2 $00A3 $00A4 $00A5 $00A6 $00A7 $00A8 $00A9 $00AA $00AB $00AC $00AD $00AE $00AF $00B0 $00B1 $00B2 $00B3 $00B4 $00B5 $00B6 $00B7 $00B8 $00B9 $00BA $00BB $00BC $00BD $00BE $00BF $00C0 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 0 0 Bit 7 Bit 7 Bit 7 Bit 7 MCZI MCZF 0 0 NOVW7 SH37 0 0 PT7 DDT7 0 0 Bit 7 Bit 7 Bit 7 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 Bit 15 Bit 7 BTST 6 14 6 14 6 14 6 14 6 PAEN 0 6 6 6 6 MODMC 0 0 0 NOVW6 SH26 0 0 PT6 DDT6 PBEN 0 6 6 6 6 14 6 14 6 14 6 14 6 14 6 BSPL 5 13 5 13 5 13 5 13 5 PAMOD 0 5 5 5 5 RDMCL 0 0 0 NOVW5 SH15 0 0 PT5 DDT5 0 0 5 5 5 5 13 5 13 5 13 5 13 5 13 5 BRLD 4 12 4 12 4 12 4 12 4 PEDGE 0 4 4 4 4 ICLAT 0 0 0 NOVW4 SH04 0 0 PT4 DDT4 0 0 4 4 4 4 12 4 12 4 12 4 12 4 12 4 SBR12 SBR12 3 11 3 11 3 11 3 11 3 CLK1 0 3 3 3 3 FLMC POLF3 PA3EN 0 NOVW3 TFMOD 0 0 PT3 DDT3 0 0 3 3 3 3 11 3 11 3 11 3 11 3 11 3 SBR11 SBR11 1 9 1 9 1 9 1 9 1 PAOVI PAOVF 1 1 1 1 MCPR1 POLF1 PA1EN DLY1 NOVW1 BUFEN 0 TCBYP PT1 DDT1 PBOVI PBOVF 1 1 1 1 9 1 9 1 9 1 9 1 9 1 SBR9 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 PAI PAIF Bit 0 Bit 0 Bit 0 Bit 0 MCPR0 POLF0 PA0EN DLY0 NOVW0 LATQ 0 0 PT0 DDT0 0 0 Bit 0 Bit 0 Bit 0 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 Bit 8 Bit 0 SBR8 Name TC4 TC4 TC5 TC5 TC6 TC6 TC7 TC7 PACTL PAFLG PACN3 PACN2 PACN1 PACN0 MCCTL MCFLG ICPAR DLYCT ICOVW ICSYS Reserved TIMTST PORTT DDRT PBCTL PBFLG PA3H PA2H PA1H PA0H MCCNTH MCCNTL TC0H TC0H TC1H TC1H TC2H TC2H TC3H TC3H SC0BDH MC68HC912DT128A MC68HC912DT128A Rev 2.0 5-reg MOTOROLA 2 10 2 10 2 10 2 10 2 CLK0 0 2 2 2 2 MCEN POLF2 PA2EN 0 NOVW2 PACMX 0 0 PT2 DDT2 0 0 2 2 2 2 10 2 10 2 10 2 10 2 10 2 SBR10 SBR10 Registers 55 Registers Table 8 MC68HC912DT128A MC68HC912DT128A Register Map (Sheet 6 of 11) Address $00C1 $00C2 $00C3 $00C4 $00C5 $00C6 $00C7 $00C8 $00C9 $00CA $00CB $00CC $00CD $00CE $00CF $00D0 $00D1 $00D2 $00D3 $00D4 $00D5 $00D6 $00D7 $00D8­$ 00DF $00E0 $00E1 $00E2 $00E3 $00E4 $00E5 $00E6 $00E7 $00E8­ $00EB $00EC­$ 00ED $00EE $00EF $00F0 $00F1 Bit 7 SBR7 LOOPS TIE TDRE 0 R8 R7/T7 BTST SBR7 LOOPS TIE TDRE 0 R8 R7/T7 SPIE 0 0 SPIF 0 Bit 7 PS7 DDS7 6 SBR6 WOMS TCIE TC 0 T8 R6/T6 BSPL SBR6 WOMS TCIE TC 0 T8 R6/T6 SPE 0 0 WCOL 0 6 PS6 DDS6 5 SBR5 RSRC RIE RDRF 0 0 R5/T5 BRLD SBR5 RSRC RIE RDRF 0 0 R5/T5 SWOM 0 0 0 0 5 PS5 DDS5 4 SBR4 M ILIE IDLE 0 0 R4/T4 SBR12 SBR12 SBR4 M ILIE IDLE 0 0 R4/T4 MSTR 0 0 MODF 0 4 PS4 DDS4 3 SBR3 WAKE TE OR 0 0 R3/T3 SBR11 SBR11 SBR3 WAKE TE OR 0 0 R3/T3 CPOL PUPS 0 0 0 3 PS3 DDS3 2 SBR2 ILT RE NF 0 0 R2/T2 SBR10 SBR10 SBR2 ILT RE NF 0 0 R2/T2 CPHA RDPS SPR2 0 0 2 PS2 DDS2 1 SBR1 PE RWU FE 0 0 R1/T1 SBR9 SBR1 PE RWU FE 0 0 R1/T1 SSOE SSWAI SPR1 0 0 1 PS1 DDS1 Bit 0 SBR0 PT SBK PF RAF 0 R0/T0 SBR8 SBR0 PT SBK PF RAF 0 R0/T0 LSBF SPC0 SPR0 0 0 Bit 0 PS0 DDS0 Name SC0BDL SC0CR1 SC0CR2 SC0SR1 SC0SR2 SC0DRH SC0DRL SC1BDH SC1BDL SC1CR1 SC1CR2 SC1SR1 SC1SR2 SC1DRH SC1DRL SP0CR1 SP0CR2 SP0BR SP0SR Reserved SP0DR PORTS DDRS 0 0 0 0 0 0 0 0 Reserved ADR7 0 IBEN TCF D7 0 PIB7 DDRIB7 ADR6 0 IBIE IAAS D6 0 PIB6 DDRIB6 ADR5 IBC5 MS/SL IBB D5 0 PIB5 DDRIB5 ADR4 IBC4 Tx/Rx IBAL D4 RDPIB PIB4 DDRIB4 ADR3 IBC3 TXAK 0 D3 0 PIB3 DDRIB3 ADR2 IBC2 RSTA SRW D2 0 PIB2 DDRIB2 ADR1 IBC1 0 IBIF D1 0 PIB1 DDRIB1 0 IBC0 IBSWAI RXAK D0 PUPIB PIB0 DDRIB0 IBAD IBFD IBCR IBSR IBDR IBPURD PORTIB DDRIB Unimplemented(4) 0 0 0 0 EEDIV7 EEDIV6 NOBDML NOSHW SHPROT 1 0 0 0 0 0 0 0 0 0 0 EEDIV9 EEDIV8 EEDIV5 EEDIV4 EEDIV3 EEDIV2 EEDIV1 EEDIV0 Reserved 1 EESWAI PROTLCK EERC BPROT5 BPROT4 BP