MC68HC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E

MC68HRC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HC903KL3E/KK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E Data Sheet M68HC08

MC68HC908JL3/JK3E/JK1E MC68HC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HC903KL3E/KK3E MC68HC903KL3E/KK3E MC68HC08JL3E/JK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E MC68HRC08JL3E/JK3E Data Sheet M68HC08 M68HC08 Microcontrollers MC68HC908JL3E MC68HC908JL3E Rev. 4 10/2006 freescale.com MC68HC908JL3/JK3E/JK1E MC68HC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HRC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HLC908JL3/JK3E/JK1E MC68HC908KL3E/KK3E MC68HC908KL3E/KK3E MC68HC08JL3E/JK3E MC68HC08JL3E/JK3E MC68HRC08JL3E/JK3E MC68HRC08JL3E/JK3E Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2004, 2006. All rights reserved. MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 3 The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History Date Revision Level Page Number(s) Description Table 4-1. Instruction Set Summary - Updated table to include the WAIT instruction. 5.7.1 Break Status Register (BSR) - Updated for clarity. 63 5.7.2 Reset Status Register (RSR) - Updated description for clarity. 64 7.4 Security - Updated to reflect the correct RAM location ($80) to determine if the security code has been entered correctly. 80 8.9.1 TIM Status and Control Register (TSC) - Added note to definition of TSTOP bit. 89 10.1 Introduction - Added note regarding 20-pin devices. 103 15.4.3 Break Status Register - Updated for clarity. 132 Chapter 17 Mechanical Specifications - Updated package drawings to the latest available. October 2006 42 147 4 Added appendix B for ROM parts. May 2002 167170 Added appendix A for low-volt devices. Dec 2002 159166 Added appendix C for ADC-less parts. Nov 2004 153224 3 2 1 Updated Monitor Mode Circuit (Figure 7-1) and Monitor Mode Entry Requirements and Options (Table 7-1) in Monitor ROM section. First general release. 76, 77 - MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 4 Freescale Semiconductor List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Chapter 3 Configuration Registers (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Chapter 5 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Chapter 6 Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Chapter 7 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Chapter 8 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Chapter 9 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Chapter 10 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Chapter 11 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Chapter 12 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Chapter 13 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Chapter 14 Low Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Chapter 15 Break Module (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Chapter 16 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Chapter 17 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Chapter 18 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Appendix A MC68HLC908JL3E/JK3E/JK1E MC68HLC908JL3E/JK3E/JK1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Appendix B MC68H MC68H(R)C08JL3E/JK3E C08JL3E/JK3E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 Appendix C MC68HC908KL3E/KK3E MC68HC908KL3E/KK3E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 5 List of Chapters MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 6 Freescale Semiconductor Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 16 17 18 20 Chapter 2 Memory 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Program Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 21 27 28 28 29 30 30 31 31 33 Chapter 3 Configuration Registers (CONFIG) 3.1 3.2 3.3 3.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 35 35 36 Chapter 4 Central Processor Unit (CPU) 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 37 37 38 38 39 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 7 Table of Contents 4.3.4 4.3.5 4.4 4.5 4.5.1 4.5.2 4.6 4.7 4.8 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 40 41 41 41 41 41 42 47 Chapter 5 System Integration Module (SIM) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Clock Start-Up from POR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.5 LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 51 51 51 51 52 52 52 53 54 54 54 55 55 55 55 55 55 55 57 58 58 59 59 60 60 60 60 61 61 62 63 63 64 65 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 8 Freescale Semiconductor Chapter 6 Oscillator (OSC) 6.1 6.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.5 6.5.1 6.5.2 6.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-tal Oscillator (MC68HC908JL3E/JK3E/JK1E MC68HC908JL3E/JK3E/JK1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC Oscillator (MC68HRC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . X-tal Oscillator Clock (XTALCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 67 67 69 69 69 69 69 69 69 69 70 70 70 70 Chapter 7 Monitor ROM (MON) 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.4 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 71 71 73 75 76 76 76 77 79 Chapter 8 Timer Interface Module (TIM) 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 81 81 82 84 84 84 84 84 85 86 86 87 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 9 Table of Contents 8.5 8.6 8.6.1 8.6.2 8.7 8.8 8.9 8.9.1 8.9.2 8.9.3 8.9.4 8.9.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Counter Registers (TCNTH:TCNTL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Counter Modulo Registers (TMODH:TMODL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Channel Status and Control Registers (TSC0:TSC1). . . . . . . . . . . . . . . . . . . . . . . . . . TIM Channel Registers (TCH0H/L:TCH1H/L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 88 88 88 88 89 89 89 91 91 92 95 Chapter 9 Analog-to-Digital Converter (ADC) 9.1 9.2 9.3 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.4 9.5 9.5.1 9.5.2 9.6 9.6.1 9.7 9.7.1 9.7.2 9.7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Chapter 10 Input/Output (I/O) Ports 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Port A Input Pull-up Enable Register (PTAPUE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 105 105 106 107 108 108 108 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 10 Freescale Semiconductor 10.4 Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3 Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 110 111 112 Chapter 11 External Interrupt (IRQ) 11.1 11.2 11.3 11.3.1 11.4 11.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Status and Control Register (INTSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 113 113 115 115 116 Chapter 12 Keyboard Interrupt Module (KBI) 12.1 12.2 12.3 12.4 12.4.1 12.5 12.5.1 12.5.2 12.6 12.6.1 12.6.2 12.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 117 117 118 119 119 120 121 121 121 121 121 Chapter 13 Computer Operating Properly (COP) 13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.3.5 13.3.6 13.3.7 13.4 13.5 13.6 13.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2OSCOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 123 124 124 124 124 124 124 124 125 125 125 125 125 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 11 Table of Contents 13.7.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.7.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 13.8 COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Chapter 14 Low Voltage Inhibit (LVI) 14.1 14.2 14.3 14.4 14.5 14.5.1 14.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 127 127 128 128 128 128 Chapter 15 Break Module (BREAK) 15.1 15.2 15.3 15.3.1 15.3.2 15.3.3 15.3.4 15.4 15.4.1 15.4.2 15.4.3 15.4.4 15.5 15.5.1 15.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Status and Control Register (BRKSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 129 129 130 130 130 130 131 131 132 132 133 133 133 133 Chapter 16 Electrical Specifications 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 16.10 16.11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 135 136 136 137 138 139 140 141 142 143 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 12 Freescale Semiconductor 16.12 ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 16.13 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Chapter 17 Mechanical Specifications 17.1 17.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Chapter 18 Ordering Information 18.1 18.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Appendix A MC68HLC908JL3E/JK3E/JK1E MC68HLC908JL3E/JK3E/JK1E A.1 A.2 A.3 A.4 A.5 A.5.1 A.5.2 A.5.3 A.5.4 A.5.5 A.5.6 A.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Voltage Inhibit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 159 159 159 159 159 160 161 161 162 163 164 Appendix B MC68H MC68H(R)C08JL3E/JK3E C08JL3E/JK3E B.1 B.2 B.3 B.4 B.5 B.5.1 B.5.2 B.5.3 B.6 B.7 B.7.1 B.7.2 B.7.3 B.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Option Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Option Register 1 (MOR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Option Register 2 (MOR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 165 167 168 168 168 168 169 169 170 170 171 172 173 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 13 Table of Contents Appendix C MC68HC908KL3E/KK3E MC68HC908KL3E/KK3E C.1 C.2 C.3 C.4 C.5 C.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 175 175 178 178 178 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 14 Freescale Semiconductor Chapter 1 General Description 1.1 Introduction The MC68H MC68H(R)C908JL3E C908JL3E is a member of the low-cost, high-performance M68HC08 M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 M68HC08 central processor unit (CPU08 CPU08) and are available with a variety of modules, memory sizes and types, and package types. A list of MC68H MC68H(R)C908JL3E C908JL3E device variations is shown in Table 1-1. Table 1-1. Summary of Device Variations Device Type Operating Voltage Oscillator Option MC68HC908JL3E MC68HC908JL3E 20 MC68HC908JK3E MC68HC908JK3E 20 MC68HC908JK1E MC68HC908JK1E MC68HRC908JL3E MC68HRC908JL3E 20 MC68HRC908JK3E MC68HRC908JK3E 20 MC68HRC908JK1E MC68HRC908JK1E 28 MC68HLC908JL3E MC68HLC908JL3E 20 MC68HLC908JK3E MC68HLC908JK3E 20 MC68HLC908JK1E MC68HLC908JK1E 28 MC68HC08JL3E MC68HC08JL3E 20 MC68HC08JK3E MC68HC08JK3E 28 MC68HRC08JL3E MC68HRC08JL3E 20 MC68HRC08JK3E MC68HRC08JK3E 28 MC68HC908KL3E MC68HC908KL3E 20 Memory Device 28 ADC Pin Count 28 LVI MC68HC908KK3E MC68HC908KK3E 4,096 bytes Flash XTAL 1,536 bytes Flash Flash 3V, 5V Yes Yes 4,096 bytes Flash RC 1,536 bytes Flash Low Voltage Flash(1) 4,096 bytes Flash 2.2 to 5.5V No Yes XTAL 1,536 bytes Flash XTAL ROM(2) 3V, 5V Yes Yes 4,096 bytes ROM RC Flash, ADC-less(3) 3V, 5V Yes No XTAL 4,096 bytes Flash 1. Low-voltage Flash devices are documented in Appendix A MC68HLC908JL3E/JK3E/JK1E MC68HLC908JL3E/JK3E/JK1E. 2. ROM devices are documented in Appendix B MC68H MC68H(R)C08JL3E/JK3E C08JL3E/JK3E. 3. Flash, ADC-less devices are documented in Appendix C MC68HC908KL3E/KK3E MC68HC908KL3E/KK3E. All references to the MC68H MC68H(R)C908JL3E C908JL3E in this data book apply equally to the MC68H MC68H(R)C908JK3E C908JK3E and MC68H MC68H(R)C908JK1E C908JK1E, unless otherwise stated. MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 15 General Description 1.2 Features Features of the MC68H MC68H(R)C908JL3E C908JL3E include the following: · EMC enhanced version of MC68H MC68H(R)C908JL3/JK3/JK1 C908JL3/JK3/JK1 · High-performance M68HC08 M68HC08 architecture · Fully upward-compatible object code with M6805 M6805, M146805 M146805, and M68HC05 M68HC05 Families · Low-power design; fully static with stop and wait modes · Maximum internal bus frequency: 8-MHz at 5V operating voltage 4-MHz at 3V operating voltage · Oscillator options: Crystal oscillator for MC68HC908JL3E/JK3E/JK1E MC68HC908JL3E/JK3E/JK1E RC oscillator for MC68HRC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E · User program Flash memory with security(1) feature 4,096 bytes for MC68H MC68H(R)C908JL3E/JK3E C908JL3E/JK3E 1,536 bytes for MC68H MC68H(R)C908JK1E C908JK1E · 128 bytes of on-chip RAM · 2-channel, 16-bit timer interface module (TIM) · 12-channel, 8-bit analog-to-digital converter (ADC) · 23 general purpose I/O ports for MC68H MC68H(R)C908JL3E C908JL3E: 7 keyboard interrupt with internal pull-up (6 keyboard interrupt for MC68HC908JL3E MC68HC908JL3E) 10 LED drivers (sink) 2 × 25mA open-drain I/O with pull-up · 15 general purpose I/O ports for MC68H MC68H(R)C908JK3E/JK1E C908JK3E/JK1E: 1 keyboard interrupt with internal pull-up (MC68HRC908JK3E/JK1E MC68HRC908JK3E/JK1E only) 4 LED drivers (sink) 2 × 25mA open-drain I/O with pull-up 10-channel ADC · System protection features: Optional computer operating properly (COP) reset Optional low-voltage detection with reset and selectable trip points for 3V and 5V operation Illegal opcode detection with reset Illegal address detection with reset · Master reset pin with internal pull-up and power-on reset · IRQ with schmitt-trigger input and programmable pull-up · 28-pin PDIP, 28-pin SOIC, and 48-pin LQFP packages for MC68H MC68H(R)C908JL3E C908JL3E · 20-pin PDIP and 20-pin SOIC packages for MC68H MC68H(R)C908JK3E/JK1E C908JK3E/JK1E 1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the Flash difficult for unauthorized users. MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 16 Freescale Semiconductor MCU Block Diagram 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68H MC68H(R)C908JL3E C908JL3E. INTERNAL BUS M68HC08 M68HC08 CPU ARITHMETIC/LOGIC UNIT (ALU) CONTROL AND STATUS REGISTERS - 64 BYTES 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE USER FLASH: MC68H MC68H(R)C908JK3E/JL3E C908JK3E/JL3E - 4,096 BYTES MC68H MC68H(R)C908JK1E C908JK1E - 1,536 BYTES USER RAM - 128 BYTES PORTA KEYBOARD INTERRUPT MODULE DDRA PORTB 2-CHANNEL TIMER INTERFACE MODULE OSC1 ¥ OSC2 DDRB BREAK MODULE PTD7* PTD6* PTD5/TCH1 PTD4/TCH0 PTD3/ADC8 PTD2/ADC9 PTD1/ADC10 PTD1/ADC10 PTD0/ADC11 PTD0/ADC11 MC68HC908JL3E/JK3E/JK1E MC68HC908JL3E/JK3E/JK1E X-TAL OSCILLATOR COMPUTER OPERATING PROPERLY MODULE MC68HRC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E * RST DDRD RC OSCILLATOR POWER-ON RESET MODULE SYSTEM INTEGRATION MODULE LOW-VOLTAGE INHIBIT MODULE * IRQ # PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTB4/ADC4 PTB3/ADC3 PTB2/ADC2 PTB1/ADC1 PTB0/ADC0 MONITOR ROM - 960 BYTES USER FLASH VECTOR SPACE - 48 BYTES PTA6/KBI6*¥ PTA5/KBI5* PTA4/KBI4* PTA3/KBI3* PTA2/KBI2* PTA1/KBI1* PTA0/KBI0* PORTD CPU REGISTERS # EXTERNAL INTERRUPT MODULE VDD POWER VSS ADC REFERENCE * Pin contains integrated pull-up device. * Pin contains programmable pull-up device. 25mA open-drain if output pin. LED direct sink pin. # Pins available on MC68H MC68H(R)C908JL3E C908JL3E only. ¥ Shared pin: MC68HC908JL3E/JK3E/JK1E MC68HC908JL3E/JK3E/JK1E - OSC2 MC68HRC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E - RCCLK/PTA6/KBI6 Figure 1-1. MCU Block Diagram MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 17 General Description 1.4 Pin Assignments IRQ 1 28 RST PTA0/KBI0 2 27 PTA5/KBI5 VSS 3 26 PTD4/TCH0 OSC1 4 25 PTD5/TCH1 OSC2/RCCLK/PTA6/KBI 5 24 PTD2/ADC9 PTA1/KBI1 6 23 PTA4/KBI4 VDD 7 22 PTD3/ADC8 PTA2/KBI2 8 21 PTB0/ADC0 PTA3/KBI3 9 20 PTB1/ADC1 PTB7/ADC7 10 19 PTD1/ADC10 PTD1/ADC10 PTB6/ADC6 11 18 PTB2/ADC2 PTB5/ADC5 12 17 PTB3/ADC3 PTD7 13 16 PTD0/ADC11 PTD0/ADC11 PTD6 14 15 PTB4/ADC4 MC68H MC68H(R)C908JL3E C908JL3E Figure 1-2. 28-Pin PDIP/SOIC Pin Assignment IRQ 1 20 RST VSS 2 19 PTD4/TCH0 OSC1 3 18 PTD5/TCH1 OSC2/RCCLK/PTA6/KBI 4 17 PTD2/ADC9 VDD 5 16 PTD3/ADC8 PTB7/ADC7 6 15 PTB0/ADC0 PTB6/ADC6 7 14 PTB1/ADC1 PTB5/ADC5 8 13 PTB2/ADC2 PTD7 9 12 PTB3/ADC3 PTD6 10 11 PTB4/ADC4 Pins not available on 20-pin packages PTA0/KBI0 PTD0/ADC11 PTD0/ADC11 PTA1/KBI1 PTD1/ADC10 PTD1/ADC10 PTA2/KBI2 PTA3/KBI3 PTA4/KBI4 PTA5/KBI5 Internal pads are unconnected. MC68H MC68H(R)C908JK3E/JK1E C908JK3E/JK1E Figure 1-3. 20-Pin PDIP/SOIC Pin Assignment MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 18 Freescale Semiconductor NC VSS PTA0/KBI0 IRQ RST PTA5/KBI5 PTD4/TCH0 PTD5/TCH1 NC 46 45 44 43 42 41 40 39 38 37 NC NC 48 NC 47 Pin Assignments 36 NC NC 1 NC 2 35 NC OSC1 3 34 NC OSC2/RCCLK/PTA6/KBI6 4 33 PTD2/ADC9 PTA1/KBI1 5 32 PTA4/KBI4 NC 6 31 PTD3/ADC8 MC68H MC68H(R)C908JL3E C908JL3E 26 NC 25 NC NC 24 23 NC 13 14 NC 12 NC 11 22 NC PTB2/ADC2 PTD1/ADC10 PTD1/ADC10 21 27 PTB3/ADC3 10 20 PTB7/ADC7 PTD0/ADC11 PTD0/ADC11 PTB1/ADC1 19 28 PTB4/ADC4 9 18 PTA3KBI3 PTD6 PTB0/ADC0 17 29 PTD7 8 16 PTA2/KBI2 PTB5/ADC5 NC 15 30 PTB6/ADC6 7 NC VDD NC: No connection Figure 1-4. 48-Pin LQFP Pin Assignment MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 19 General Description 1.5 Pin Functions Description of the pin functions are provided in Table 1-2. Table 1-2. Pin Functions PIN NAME VDDJL3JL3 PIN DESCRIPTION IN/OUT VOLTAGE LEVEL In 5V or 3V Out 0V Power supply. VSS Power supply ground RST RESET input, active low. With Internal pull-up and Schmitt trigger input. Input VDD to VTST IRQ External IRQ pin. With software programmable internal pull-up and schmitt trigger input. This pin is also used for mode entry selection. Input VDD to VTST In Analog Out Analog MC68HRC908JL3E/JK3E/JK1E MC68HRC908JL3E/JK3E/JK1E: Default is RC oscillator clock output, RCCLK. Shared with PTA6/KBI6, with programmable pull-up. In/Out VDD 7-bit general purpose I/O port. In/Out VDD Shared with 7 keyboard interrupts KBI[0:6]. In VDD Each pin has programmable internal pull-up device. In VDD PTA[0:5] have LED direct sink capability In VSS In/Out VDD In Analog 8-bit general purpose I/O port. In/Out VDD PTD[3:0] shared with 4 ADC inputs, ADC[8:11]. Input Analog PTD[4:5] shared with TIM channels, TCH0 and TCH1. In/Out VDD In VSS In/Out VDD OSC1 X-tal or RC oscillator input. MC68HC908JL3E/JK3E/JK1E MC68HC908JL3E/JK3E/JK1E: X-tal oscillator output, this is the inverting OSC1 signal. OSC2 PTA[0:6] 8-bit general purpose I/O port. PTB[0:7] Shared with 8 ADC inputs, ADC[0:7]. PTD[0:7] PTD[2:3], PTD[6:7] have LED direct sink capability PTD[6:7] can be configured as 25mA open-drain output with pull-up. NOTE On the MC68H MC68H(R)C908JK3E/JK1E C908JK3E/JK1E, the following pins are not available: PTA0, PTA1, PTA2, PTA3, PTA4, PTA5, PTD0, and PTD1. MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 20 Freescale Semiconductor Chapter 2 Memory 2.1 Introduction The CPU08 CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 2-1, includes: · 4,096 bytes of user Flash - MC68H MC68H(R)C908JL3E/JK3E C908JL3E/JK3E 1,536 bytes of user Flash - MC68H MC68H(R)C908JK1E C908JK1E · 128 bytes of RAM · 48 bytes of user-defined vectors · 960 bytes of Monitor ROM 2.2 I/O Section Addresses $0000$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have the following addresses: · $FE00; Break Status Register, BSR · $FE01; Reset Status Register, RSR · $FE03; Break Flag Control Register, BFCR · $FE04; Interrupt Status Register 1, INT1 · $FE05; Interrupt Status Register 2, INT2 · $FE06; Interrupt Status Register 3, INT3 · $FE08; Flash Control Register, FLCR · $FE09; Flash Block Protect Register, FLBPR · $FE0C; Break Address Register High, BRKH · $FE0D; Break Address Register Low, BRKL · $FE0E; Break Status and Control Register, BRKSCR · $FFFF; COP Control Register, COPCTL 2.3 Monitor ROM The 960 bytes at addresses $FC00$FDFF and $FE10$FFCF are reserved ROM addresses that contain the instructions for the monitor functions. (See Chapter 7 Monitor ROM (MON).) MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 21 Memory $0000 $003F I/O REGISTERS 64 BYTES $0040 $007F RESERVED 64 BYTES $0080 $00FF RAM 128 BYTES $0100 $EBFF UNIMPLEMENTED 60,160 BYTES $EC00 $FBFF FLASH MEMORY MC68H MC68H(R)C908JL3E/JK3E C908JL3E/JK3E 4,096 BYTES $FC00 $FDFF MONITOR ROM 512 BYTES $FE00 BREAK STATUS REGISTER (BSR) $FE01 RESET STATUS REGISTER (RSR) $FE02 RESERVED (UBAR) $FE03 BREAK FLAG CONTROL REGISTER (BFCR) $FE04 INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER 3 (INT3) $FE07 RESERVED $FE08 FLASH CONTROL REGISTER (FLCR) $FE09 FLASH BLOCK PROTECT REGISTER (FLBPR) $FE0A RESERVED $FE0B RESERVED $FE0C BREAK ADDRESS HIGH REGISTER (BRKH) $FE0D BREAK ADDRESS LOW REGISTER (BRKL) $FE0E BREAK STATUS AND CONTROL REGISTER (BRKSCR) $FE0F RESERVED $FE10 $FFCF MONITOR ROM 448 BYTES $FFD0 $FFFF USER VECTORS 48 BYTES UNIMPLEMENTED 62,720 BYTES $0100 $F5FF FLASH MEMORY MC68H MC68H(R)C908JK1E C908JK1E 1,536 BYTES $F600 $FBFF Figure 2-1. Memory Map MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 22 Freescale Semiconductor Monitor ROM Addr. $0000 Register Name Bit 7 Read: Port A Data Register Write: (PTA) Reset: Read: $0001 Port B Data Register Write: (PTB) Reset: 0 6 5 4 3 2 1 Bit 0 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTB2 PTB1 PTB0 PTD2 PTD1 PTD0 Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 Unaffected by reset Read: $0002 Unimplemented Write: $0003 Read: Port D Data Register Write: (PTD) Reset: $0004 Read: Data Direction Register A Write: (DDRA) Reset: Read: $0005 Data Direction Register B Write: (DDRB) Reset: PTD7 PTD6 PTD5 PTD4 PTD3 Unaffected by reset 0 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 0 0 0 0 SLOWD7 SLOWD6 PTDPU7 PTDPU6 0 0 0 0 0 0 0 0 PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 0 0 0 0 0 0 0 0 R = Reserved Read: $0006 Unimplemented Write: $0007 Read: Data Direction Register D Write: (DDRD) Reset: Read: $0008 $0009 Unimplemented Write: $000A Read: Port D Control Register Write: (PDCR) Reset: Read: $000B $000C Unimplemented Write: $000D Read: Port A Input Pull-up Enable Write: Register (PTAPUE) Reset: $000E $0019 Read: Unimplemented Write: = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 4) MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 23 Memory Addr. Register Name Bit 7 Read: $001A $001B Keyboard Status and Control Write: Register (KBSCR) Reset: Read: Keyboard Interrupt Enable Write: Register (KBIER) Reset: 6 5 4 3 2 0 0 0 0 KEYF 0 1 ACKK 0 Bit 0 IMASKK MODEK 0 0 0 0 0 0 0 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 0 0 0 0 0 IRQF IMASK MODE 0 Read: $001C $001D Unimplemented Write: IRQ Status and Control Read: Register Write: (INTSCR) Reset: Read: $001E $001F Configuration Register 2 Write: (CONFIG2) Reset: Read: Configuration Register 1 Write: (CONFIG1) Reset: 0 ACK 0 0 0 0 0 0 0 0 IRQPUD R R LVIT1 LVIT0 R R R 0 0 0 0* 0* 0 0 0 COPRS R R LVID R SSREC STOP COPD 0 0 0 0 0 0 0 0 PS2 PS1 PS0 One-time writable register after each reset. * LVIT1 and LVIT0 reset to 0 by a power-on reset (POR) only. Read: TIM Status and Control Write: Register (TSC) Reset: TOF 0 0 $0021 $0022 $0023 TSTOP 0 0 1 0 0 0 0 0 Read: TIM Counter Register High Write: (TCNTH) Reset: Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 0 0 0 0 0 0 0 0 Read: $0020 TOIE Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 1 1 1 1 1 1 1 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 1 1 1 1 1 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TIM Counter Register Write: Low (TCNTL) Reset: Read: TIM Counter Modulo Register Write: High (TMODH) Reset: Read: $0024 $0025 TIM Counter Modulo Register Write: Low (TMODL) Reset: Read: TIM Channel 0 Status and Write: Control Register (TSC0) Reset: Read: $0026 TIM Channel 0 Register High Write: (TCH0H) Reset: 0 CH0F 0 TRST Indeterminate after reset = Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 4) MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 24 Freescale Semiconductor Monitor ROM Addr. Register Name Bit 7 Read: $0027 $0028 TIM Channel 0 Register Low Write: (TCH0L) Reset: Read: TIM Channel 1 Status and Write: Control Register (TSC1) Reset: Read: $0029 $002A TIM Channel 1 Register High Write: (TCH1H) Reset: Read: TIM Channel 1 Register Low Write: (TCH1L) Reset: $002B $003B Read: ADC Status and Control Write: Register (ADSCR) Reset: 5 4 3 2 1 Bit 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Indeterminate after reset CH1F 0 0 CH1IE MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit2 Bit1 Bit0 ADCH2 ADCH1 ADCH0 Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Indeterminate after reset Unimplemented Write: $003C 6 Read: Read: $003D $003E COCO AIEN ADCO ADCH3 0 0 0 1 1 1 1 1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADC Data Register Write: (ADR) Reset: Read: ADC Input Clock Register Write: (ADICLK) Reset: ADCH4 Indeterminate after reset 0 0 0 0 0 0 0 0 0 0 0 R R R R ADIV2 ADIV1 ADIV0 0 0 R R Read: $003F $FE00 Unimplemented Write: Read: Break Status Register Write: (BSR) Reset: SBSW See note R 0 Note: Writing a 0 clears SBSW. $FE01 Read: Reset Status Register Write: (RSR) POR: Read: $FE02 Reserved Write: $FE03 Read: Break Flag Control Write: Register (BFCR) Reset: POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 R R R R R R R R BCFE R R R R R R R R = Reserved 0 = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 4) MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 25 Memory Addr. $FE05 Bit 7 6 5 4 3 2 1 Bit 0 Read: $FE04 Register Name 0 IF5 IF4 IF3 0 IF1 0 0 Interrupt Status Register 1 Write: (INT1) Reset: R R R R R R R R 0 0 0 0 0 0 0 0 Read: Interrupt Status Register 2 Write: (INT2) Reset: IF14 0 0 0 0 0 0 0 R R R R R R R R $FE06 0 0 0 0 0 0 0 0 Read: 0 0 0 0 0 0 0 IF15 Interrupt Status Register 3 Write: (INT3) Reset: R R R R R R R R 0 0 0 0 0 0 0 0 R R R R R R R R 0 0 0 0 HVEN MASS ERASE PGM 0 0 0 0 0 0 0 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 0 0 0 0 0 0 0 0 R R R R R R R R Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 0 0 0 0 0 0 0 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 BRKE BRKA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read: $FE07 Reserved Write: $FE08 Read: Flash Control Register Write: (FLCR) Reset: $FE09 Read: Flash Block Protect Write: Register (FLBPR) Reset: Read: $FE0A $FE0B Reserved Write: $FE0C Read: Break Address High Write: Register (BRKH) Reset: Read: $FE0D $FE0E $FFFF Break Address Low Write: Register (BRKL) Reset: Read: Break Status and Control Write: Register (BRKSCR) Reset: Read: COP Control Register Write: (COPCTL) Reset: Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 4) MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 26 Freescale Semiconductor Random-Access Memory (RAM) Table 2-1. Vector Addresses Vector Priority INT Flag Address Lowest - $FFD0 $FFDD Not Used $FFDE ADC Conversion Complete Vector (High) $FFDF ADC Conversion Complete Vector (Low) $FFE0 Keyboard Vector (High) $FFE1 Keyboard Vector (Low) IF15 IF14 IF13 IF6 IF5 IF4 IF3 IF2 IF1 - Highest - - Vector Not Used $FFF2 TIM Overflow Vector (High) $FFF3 TIM Overflow Vector (Low) $FFF4 TIM Channel 1 Vector (High) $FFF5 TIM Channel 1 Vector (Low) $FFF6 TIM Channel 0 Vector (High) $FFF7 TIM Channel 0 Vector (Low) - Not Used $FFFA IRQ Vector (High) $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) $FFFD SWI Vector (Low) $FFFE Reset Vector (High) $FFFF Reset Vector (Low) 2.4 Random-Access Memory (RAM) Addresses $0080 through $00FF are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 128 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE For M6805 M6805 compatibility, the H register is not stacked. MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 27 Memory During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. 2.5 Flash Memory This sub-section describes the operation of the embedded Flash memory. The Flash memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. Device $EC00- EC00-$FBFF 4,096 $EC00- EC00-$FBFF MC68H MC68H(R)C908JK1E C908JK1E $FE09 4,096 MC68H MC68H(R)C908JK3E C908JK3E $FE08 Memory Address Range MC68H MC68H(R)C908JL3E C908JL3E Addr. Flash Memory Size (Bytes) 1,536 $F600- F600-$FBFF Register Name Flash Control Register (FLCR) Flash Block Protect Register (FLBPR) Read: Write: Reset: Read: Write: Reset: Bit 7 0 6 0 5 0 4 0 0 0 0 BPR7 BPR6 BPR5 0 0 0 = Unimplemented 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 0 BPR4 BPR3 BPR2 BPR1 BPR0 0 0 0 0 0 Figure 2-3. Flash I/O Register Summary 2.6 Functional Description The Flash memory consists of an array of 4,096 or 1,536 bytes with an additional 48 bytes for user vectors. The minimum size of Flash memory that can be erased is 64 bytes (a page); and the maximum size of Flash memory that can be programmed in a program cycle is 32 bytes (a row). Program and erase operations are facilitated through control bits in the Flash Control Register (FLCR). Details for these operations appear later in this section. The address ranges for the user memory and vectors are: · $EC00$FBFF; user memory; 4,096 bytes; MC68H MC68H(R)C908JL3E/JK3E C908JL3E/JK3E $F600$FBFF; user memory; 1,536 bytes; MC68H MC68H(R)C908JK1E C908JK1E · $FFD0$FFFF; user interrupt vectors; 48 bytes NOTE An erased bit reads as 1 and a programmed bit reads as 0. A security feature prevents viewing of the Flash contents.(1) 1. No security feature is absolutely secure. However, Freescale's strategy is to make reading or copying the Flash difficult for unauthorized users. MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 28 Freescale Semiconductor Flash Control Register 2.7 Flash Control Register The Flash Control Register controls Flash program and erase operations. Address: $FE08 Bit 7 Read: 6 5 4 0 0 0 0 0 0 0 Write: Reset: 0 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 = Unimplemented Figure 2-4. Flash Control Register (FLCR) HVEN - High Voltage Enable Bit This read/write bit enables high voltage from the charge pump to the memory for either program or erase operation. It can only be set if either PGM=1 or ERASE=1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS - Mass Erase Control Bit This read/write bit configures the memory for mass erase operation or page erase operation when the ERASE bit is set. 1 = Mass erase operation selected 0 = Page erase operation selected ERASE - Erase Control Bit This read/write bit configures the memory for erase operation. This bit and the PGM bit should not be set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation not selected PGM - Program Control Bit This read/write bit configures the memory for program operation. This bit and the ERASE bit should not be set to 1 at the same time. 1 = Program operation selected 0 = Program operation not selected MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 29 Memory 2.8 Flash Page Erase Operation Use the following procedure to erase a page of Flash memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 48-byte user interrupt vectors area also forms a page. Any page within the 4K bytes user memory area ($EC00$FBFF) can be erased alone. The 48-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass erase is required to erase this page. 1. Set the ERASE bit and clear the MASS bit in the Flash Control Register. 2. Write any data to any Flash address within the page address range desired. 3. Wait for a time, tnvs (10s). 4. Set the HVEN bit. 5. Wait for a time tErase (1ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvh (5s). 8. Clear the HVEN bit. 9. After time, trcv (1s), the memory can be accessed in read mode again. NOTE Programming and erasing of Flash locations cannot be performed by code being executed from the Flash memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 2.9 Flash Mass Erase Operation Use the following procedure to erase the entire Flash memory: 1. Set both the ERASE bit and the MASS bit in the Flash Control Register. 2. Write any data to any Flash location within the Flash memory address range. 3. Wait for a time, tnvs (10s). 4. Set the HVEN bit. 5. Wait for a time tMErase (4ms). 6. Clear the ERASE bit. 7. Wait for a time, tnvh1 (100s). 8. Clear the HVEN bit. 9. After time, trcv (1s), the memory can be accessed in read mode again. NOTE Programming and erasing of Flash locations cannot be performed by code being executed from the Flash memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 30 Freescale Semiconductor Flash Program Operation 2.10 Flash Program Operation Programming of the Flash memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this step-by-step procedure to program a row of Flash memory (Figure 2-5 shows a flowchart of the programming algorithm): 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Write any data to any Flash location within the address range of the row to be programmed. 3. Wait for a time, tnvs (10s). 4. Set the HVEN bit. 5. Wait for a time, tpgs (5s). 6. Write data to the byte being programmed. 7. Wait for time, tPROG (30s). 8. Repeat step 6 and 7 until all the bytes within the row are programmed. 9. Clear the PGM bit. 10. Wait for time, tnvh (5s). 11. Clear the HVEN bit. 12. After time, trcv (1s), the memory can be accessed in read mode again. This program sequence is repeated throughout the memory until all data is programmed. NOTE The time between each Flash address change (step 6 to step 6), or the time between the last Flash addressed programmed to clearing the PGM bit (step 6 to step 10), must not exceed the maximum programming time, tPROG max. NOTE Programming and erasing of Flash locations cannot be performed by code being executed from the Flash memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. 2.11 Flash Protection Due to the ability of the on-board charge pump to erase and program the Flash memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a Flash Block Protect Register (FLBPR). The FLBPR determines the range of the Flash memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the Flash memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either ERASE or PROGRAM operations. MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 31 Memory 1 Set PGM bit Algorithm for programming a row (32 bytes) of Flash memory 2 Write any data to any Flash address within the row address range desired 3 Wait for a time, tnvs 4 Set HVEN bit 5 Wait for a time, tpgs 6 7 Write data to the Flash address to be programmed Wait for a time, tPROG Completed programming this row? Y N 9 The time between each Flash address change (step 6 to step 6), or the time between the last Flash address programmed to clearing PGM bit (step 6 to step 9) must not exceed the maximum programming time, tPROG max. Clear PGM bit 10 Wait for a time, tnvh 11 Clear HVEN bit 12 NOTE: Wait for a time, trcv This row program algorithm assumes the row/s to be programmed are initially erased. End of Programming Figure 2-5. Flash Programming Flowchart MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 32 Freescale Semiconductor Flash Block Protect Register 2.12 Flash Block Protect Register The Flash Block Protect Register is implemented as an 8-bit I/O register. The value in this register determines the starting address of the protected range within the Flash memory. Address: $FE09 Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 0 0 0 0 0 0 0 0 Figure 2-6. Flash Block Protect Register (FLBPR) BPR[7:0] - Flash Block Protect Register Bit 7 to Bit 0 BPR[7:1] represent bits [12:6] of a 16-bit memory address. Bits [15:13] are 1's and bits [5:0] are 0's. 16-bit memory address Start address of Flash block protect 1 1 1 0 0 0 0 0 0 BPR[7:1] BPR0 is used only for BPR[7:0] = $FF, for no block protection. The resultant 16-bit address is used for specifying the start address of the Flash memory for block protection. The Flash is protected from this start address to the end of Flash memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page boundaries - 64 bytes) within the Flash memory. Examples of protect start address: BPR[7:0] Start of Address of Protect Range $00$60 The entire Flash memory is protected. $62 or $63 (0110 001x) $EC40 (1110 1100 0100 0000) $64 or $65 (0110 010x) $EC80 (1110 1100 1000 0000) $68 or $69 (0110 100x) $ED00 (1110 1101 0000 0000) and so on. $DE or $DF (1101 111x) $FBC0 (1111 1011 1100 0000) $FE (1111 1110) $FFC0 (1111 1111 1100 0000) $FF The entire Flash memory is not protected. Note: The end address of the protected range is always $FFFF. MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 33 Memory MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 34 Freescale Semiconductor Chapter 3 Configuration Registers (CONFIG) 3.1 Introduction This section describes the configuration registers (CONFIG1 and CONFIG2). The configuration registers enables or disables the following options: · Stop mode recovery time (32 × 2OSCOUT cycles or 4096 × 2OSCOUT cycles) · STOP instruction · Computer operating properly module (COP) · COP reset period (COPRS), 8176 × 2OSCOUT or 262,128 × 2OSCOUT · Enable LVI circuit · Select LVI trip voltage 3.2 Functional Description The configuration register is used in the initialization of various options. The configuration register can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU it is recommended that this register be written immediately after reset. The configuration register is located at $001E and $001F, and may be read at anytime. NOTE The CONFIG registers are one-time writable by the user after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 3-1 and Figure 3-2. 3.3 Configuration Register 1 (CONFIG1) Address: $001F Bit 7 Write: Reset: 6 5 4 3 2 1 Bit 0 COPRS R R LVID R SSREC STOP COPD 0 0 0 0 0 0 0 0 R Read: = Reserved Figure 3-1. Configuration Register 1 (CONFIG1) COPRS - COP reset period selection bit 1 = COP reset cycle is 8176 × 2OSCOUT 0 = COP reset cycle is 262,128 × 2OSCOUT MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 35 Configuration Registers (CONFIG) LVID - Low Voltage Inhibit Disable Bit 1 = Low Voltage Inhibit disabled 0 = Low Voltage Inhibit enabled SSREC - Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 × 2OSCOUT cycles instead of a 4096 × 2OSCOUT cycle delay. 1 = Stop mode recovery after 32 × 2OSCOUT cycles 0 = Stop mode recovery after 4096 × 2OSCOUT cycles NOTE Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. STOP - STOP Instruction Enable STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD - COP Disable Bit COPD disables the COP module. (See Chapter 13 Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled 3.4 Configuration Register 2 (CONFIG2) Address: $001E Bit 7 6 5 4 3 2 1 Bit 0 IRQPUD R R LVIT1 LVIT0 R R R Reset: 0 0 0 Not affected Not affected 0 0 0 POR: 0 0 0 0 0 0 0 0 R = Reserved Read: Write: Figure 3-2. Configuration Register 2 (CONFIG2) IRQPUD - IRQ Pin Pull-up control bit 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ pin and VDD LVIT1, LVIT0 - Low Voltage Inhibit trip voltage selection bits Detail description of the LVI control signals is given in Chapter 14 Low Voltage Inhibit (LVI) MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 36 Freescale Semiconductor Chapter 4 Central Processor Unit (CPU) 4.1 Introduction The M68HC08 M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 M68HC05 CPU. The CPU08 CPU08 Reference Manual (document order number CPU08RM/AD CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 4.2 Features Features of the CPU include: · Object code fully upward-compatible with M68HC05 M68HC05 Family · 16-bit stack pointer with stack manipulation instructions · 16-bit index register with x-register manipulation instructions · 8-MHz CPU internal bus frequency · 64-Kbyte program/data memory space · 16 addressing modes · Memory-to-memory data moves without using accumulator · Fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions · Enhanced binary-coded decimal (BCD) data handling · Modular architecture with expandable internal bus definition for extension of addressing range beyond 64 Kbytes · Low-power stop and wait modes 4.3 CPU Registers Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map. MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 37 Central Processor Unit (CPU) 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG Figure 4-1. CPU Registers 4.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Unaffected by reset Figure 4-2. Accumulator (A) 4.3.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 X X X X X X X X Read: Write: Reset: X = Indeterminate Figure 4-3. Index Register (H:X) MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 38 Freescale Semiconductor CPU Registers 4.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Read: Write: Reset: Figure 4-4. Stack Pointer (SP) NOTE The location of the stack is arbitrary and may be relocated anywhere in random-access memory (RAM). Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations. 4.3.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Loaded with vector from $FFFE and $FFFF Figure 4-5. Program Counter (PC) MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 39 Central Processor Unit (CPU) 4.3.5 Condition Code Register The 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. Bits 6 and 5 are set permanently to 1. The following paragraphs describe the functions of the condition code register. Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0 V 1 1 H I N Z C X 1 1 X 1 X X X X = Indeterminate Figure 4-6. Condition Code Register (CCR) V - Overflow Flag The CPU sets the overflow flag when a two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and BLT use the overflow flag. 1 = Overflow 0 = No overflow H - Half-Carry Flag The CPU sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (ADD) or add-with-carry (ADC) operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic operations. The DAA instruction uses the states of the H and C flags to determine the appropriate correction factor. 1 = Carry between bits 3 and 4 0 = No carry between bits 3 and 4 I - Interrupt Mask When the interrupt mask is set, all maskable CPU interrupts are disabled. CPU interrupts are enabled when the interrupt mask is cleared. When a CPU interrupt occurs, the interrupt mask is set automatically after the CPU registers are saved on the stack, but before the interrupt vector is fetched. 1 = Interrupts disabled 0 = Interrupts enabled NOTE To maintain M6805 M6805 Family compatibility, the upper byte of the index register (H) is not stacked automatically. If the interrupt service routine modifies H, then the user must stack and unstack H using the PSHH and PULH instructions. After the I bit is cleared, the highest-priority interrupt request is serviced first. A return-from-interrupt (RTI) instruction pulls the CPU registers from the stack and restores the interrupt mask from the stack. After any reset, the interrupt mask is set and can be cleared only by the clear interrupt mask software instruction (CLI). N - Negative Flag The CPU sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = Negative result 0 = Non-negative result MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 40 Freescale Semiconductor Arithmetic/Logic Unit (ALU) Z - Zero Flag The CPU sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = Zero result 0 = Non-zero result C - Carry/Borrow Flag The CPU sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. Some instructions - such as bit test and branch, shift, and rotate - also clear or set the carry/borrow flag. 1 = Carry out of bit 7 0 = No carry out of bit 7 4.4 Arithmetic/Logic Unit (ALU) The ALU performs the arithmetic and logic operations defined by the instruction set. Refer to the CPU08 CPU08 Reference Manual (document order number CPU08RM/AD CPU08RM/AD) for a description of the instructions and addressing modes and more detail about the architecture of the CPU. 4.5 Low-Power Modes The WAIT and STOP instructions put the MCU in low power-consumption standby modes. 4.5.1 Wait Mode The WAIT instruction: · Clears the interrupt mask (I bit) in the condition code register, enabling interrupts. After exit from wait mode by interrupt, the I bit remains clear. After exit by reset, the I bit is set. · Disables the CPU clock 4.5.2 Stop Mode The STOP instruction: · Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts. After exit from stop mode by external interrupt, the I bit remains clear. After exit by reset, the I bit is set. · Disables the CPU clock After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay. 4.6 CPU During Break Interrupts If a break module is present on the MCU, the CPU starts a break interrupt by: · Loading the instruction register with the SWI instruction · Loading the program counter with $FFFC:$FFFD or with $FEFC:$FEFD in monitor mode The break interrupt begins after completion of the CPU instruction in progress. If the break address register match occurs on the last cycle of a CPU instruction, the break interrupt begins immediately. A return-from-interrupt instruction (RTI) in the break routine ends the break interrupt and returns the MCU to normal operation if the break interrupt has been deasserted. MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 41 Central Processor Unit (CPU) 4.7 Instruction Set Summary Table 4-1 provides a summary of the M68HC08 M68HC08 instruction set. ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADC opr,SP ADC opr,SP ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X ADD opr,SP ADD opr,SP V H I N Z C A (A) + (M) + (C) Add with Carry A (A) + (M) Add without Carry IMM DIR EXT IX2 IX1 IX SP1 SP2 A9 B9 C9 D9 E9 F9 9EE9 9ED9 ii dd hh ll ee ff ff IMM DIR EXT IX2 IX1 IX SP1 SP2 AB BB CB DB EB FB 9EEB 9EDB ii dd hh ll ee ff ff ff ee ff Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 4-1. Instruction Set Summary (Sheet 1 of 6) 2 3 4 4 3 2 4 5 ff ee ff 2 3 4 4 3 2 4 5 AIS #opr Add Immediate Value (Signed) to SP SP (SP) + (16 « M) IMM A7 ii 2 AIX #opr Add Immediate Value (Signed) to H:X H:X (H:X) + (16 « M) IMM AF ii 2 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X AND opr,SP AND opr,SP ASL opr ASLA ASLX ASL opr,X ASL ,X ASL opr,SP A (A) & (M) Logical AND Arithmetic Shift Left (Same as LSL) C BCC rel Branch if Carry Bit Clear BCLR n, opr b0 PC (PC) + 2 + rel ? (C) = 0 Mn 0 Clear Bit n in M 38 dd 48 58 68 ff 78 9E68 ff 4 1 1 4 3 5 C b7 ff ee ff DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 37 dd 47 57 67 ff 77 9E67 ff 4 1 1 4 3 5 b0 Arithmetic Shift Right A4 B4 C4 D4 E4 F4 9EE4 9ED4 0 b7 ASR opr ASRA ASRX ASR opr,X ASR opr,X ASR opr,SP 0 IMM DIR EXT IX2 IX1 IX SP1 SP2 REL 24 rr 3 DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 11 13 15 17 19 1B 1D 1F dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 BCS rel Branch if Carry Bit Set (Same as BLO) PC (PC) + 2 + rel ? (C) = 1 REL 25 rr 3 BEQ rel Branch if Equal PC (PC) + 2 + rel ? (Z) = 1 REL 27 rr 3 BGE opr Branch if Greater Than or Equal To (Signed Operands) PC (PC) + 2 + rel ? (N V) = 0 REL 90 rr 3 BGT opr Branch if Greater Than (Signed Operands) PC (PC) + 2 + rel ? (Z) | (N V) = 0 REL 92 rr 3 BHCC rel Branch if Half Carry Bit Clear PC (PC) + 2 + rel ? (H) = 0 REL 28 rr BHCS rel Branch if Half Carry Bit Set PC (PC) + 2 + rel ? (H) = 1 REL 29 rr BHI rel Branch if Higher PC (PC) + 2 + rel ? (C) | (Z) = 0 REL 22 rr 3 3 3 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 42 Freescale Semiconductor Instruction Set Summary V H I N Z C BHS rel Branch if Higher or Same (Same as BCC) BIH rel BIL rel PC (PC) + 2 + rel ? (C) = 0 REL Branch if IRQ Pin High PC (PC) + 2 + rel ? IRQ = 1 Branch if IRQ Pin Low PC (PC) + 2 + rel ? IRQ = 0 BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BIT opr,SP BIT opr,SP Bit Test BLE opr Branch if Less Than or Equal To (Signed Operands) (A) & (M) Cycles Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 4-1. Instruction Set Summary (Sheet 2 of 6) 24 rr 3 REL 2F rr 3 REL 2E rr 3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 rr 3 0 IMM DIR EXT IX2 IX1 IX SP1 SP2 PC (PC) + 2 + rel ? (Z) | (N V) = 1 REL A5 B5 C5 D5 E5 F5 9EE5 9ED5 93 BLO rel Branch if Lower (Same as BCS) PC (PC) + 2 + rel ? (C) = 1 REL 25 rr 3 BLS rel Branch if Lower or Same PC (PC) + 2 + rel ? (C) | (Z) = 1 REL 23 rr 3 BLT opr Branch if Less Than (Signed Operands) PC (PC) + 2 + rel ? (N V) =1 REL 91 rr 3 BMC rel Branch if Interrupt Mask Clear PC (PC) + 2 + rel ? (I) = 0 REL 2C rr 3 BMI rel Branch if Minus PC (PC) + 2 + rel ? (N) = 1 REL 2B rr 3 BMS rel Branch if Interrupt Mask Set PC (PC) + 2 + rel ? (I) = 1 REL 2D rr 3 3 BNE rel Branch if Not Equal PC (PC) + 2 + rel ? (Z) = 0 REL 26 rr BPL rel Branch if Plus PC (PC) + 2 + rel ? (N) = 0 REL 2A rr 3 BRA rel Branch Always PC (PC) + 2 + rel REL 20 rr 3 01 03 05 07 09 0B 0D 0F dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 PC (PC) + 3 + rel ? (Mn) = 0 BRCLR n,opr,rel Branch if Bit n in M Clear BRN rel PC (PC) + 2 Branch Never rr 3 00 02 04 06 08 0A 0C 0E dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) 10 12 14 16 18 1A 1C 1E dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 PC (PC) + 2; push (PCL) SP (SP) 1; push (PCH) SP (SP) 1 PC (PC) + rel REL AD rr 4 PC (PC) + 3 + rel ? (A) (M) = $00 PC (PC) + 3 + rel ? (A) (M) = $00 PC (PC) + 3 + rel ? (X) (M) = $00 PC (PC) + 3 + rel ? (A) (M) = $00 PC (PC) + 2 + rel ? (A) (M) = $00 PC (PC) + 4 + rel ? (A) (M) = $00 DIR IMM IMM IX1+ IX+ SP1 31 41 51 61 71 9E61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 Mn 1 Set Bit n in M BSR rel 21 DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) PC (PC) + 3 + rel ? (Mn) = 1 BRSET n,opr,rel Branch if Bit n in M Set BSET n,opr DIR (b0) DIR (b1) DIR (b2) DIR (b3) DIR (b4) DIR (b5) DIR (b6) DIR (b7) Branch to Subroutine CBEQ opr,rel CBEQA #opr,rel CBEQX #opr,rel Compare and Branch if Equal CBEQ opr,X+,rel CBEQ X+,rel CBEQ opr,SP,rel REL CLC Clear Carry Bit C0 0 INH 98 1 CLI Clear Interrupt Mask I0 0 INH 9A 2 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 Freescale Semiconductor 43 Central Processor Unit (CPU) CLR opr CLRA CLRX CLRH CLR opr,X CLR ,X CLR opr,SP CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X CMP opr,SP CMP opr,SP M $00 A $00 X $00 H $00 M $00 M $00 M $00 (A) (M) Clear Compare A with M Complement (One's Complement) CPHX #opr CPHX opr Compare H:X with M CPX #opr CPX opr CPX opr CPX ,X CPX opr,X CPX opr,X CPX opr,SP CPX opr,SP Decimal Adjust A Decrement DIV Divide INC opr INCA INCX INC opr,X INC ,X INC opr,SP Exclusive OR M with A Increment M (M) = $FF (M) A (A) = $FF (M) X (X) = $FF (M) M (M) = $FF (M) M (M) = $FF (M) M (M) = $FF (M) (A)10 A1 B1 C1 D1 E1 F1 9EE1 9ED1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 IMM DIR 65 75 ii ii+1 dd 3 4 IMM DIR EXT IX2 IX1 IX SP1 SP2 A3 B3 C3 D3 E3 F3 9EE3 9ED3 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 INH 72 U M (M) 1 A (A) 1 X (X) 1 M (M) 1 M (M) 1 M (M) 1 A (H:A)/(X) H Remainder 0 M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 M (M) + 1 DIR INH INH IX1 IX SP1 INH 33 dd 43 53 63 ff 73 9E63 ff 3 1 1 1 3 2 4 0 A (A) 1 or M (M) 1 or X (X) 1 PC (PC) + 3 + rel ? (result) 0 DIR PC (PC) + 2 + rel ? (result) 0 INH PC (PC) + 2 + rel ? (result) 0 INH PC (PC) + 3 + rel ? (result) 0 IX1 PC (PC) + 2 + rel ? (result) 0 IX PC (PC) + 4 + rel ? (result) 0 SP1 A (A M) 3F dd 4F 5F 8C 6F ff 7F 9E6F ff DIR INH INH 1 IX1 IX SP1 (X) (M) DBNZ opr,rel DBNZA rel DBNZX rel Decrement and Branch if Not Zero DBNZ opr,X,rel DBNZ X,rel DBNZ opr,SP,rel DEC opr DECA DECX DEC opr,X DEC ,X DEC opr,SP IMM DIR EXT IX2 IX1 IX SP1 SP2 (H:X) (M:M + 1) Compare X with M DAA DIR INH INH 0 0 1 INH IX1 IX SP1 Cycles V H I N Z C COM opr COMA COMX COM opr,X COM ,X COM opr,SP EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X EOR opr,SP EOR opr,SP Effect on CCR Description Operand Operation Opcode Source Form Address Mode Table 4-1. Instruction Set Summary (Sheet 3 of 6) 3B 4B 5B 6B 7B 9E6B ff ee ff 4 1 1 4 3 5 2 dd rr rr rr ff rr rr ff rr 3A dd 4A 5A 6A ff 7A 9E6A ff 52 5 3 3 5 4 6 4 1 1 4 3 5 7 IMM DIR EXT IX2 IX1 IX SP1 SP2 A8 B8 C8 D8 E8 F8 9EE8 9ED8 ii dd hh ll ee ff ff DIR INH INH IX1 IX SP1 3C dd 4C 5C 6C ff 7C 9E6C ff ff ee ff 2 3 4 4 3 2 4 5 4 1 1 4 3 5 MC68HC908JL3E MC68HC908JL3E Family Data Sheet, Rev. 4 44 Freescale Semiconductor Instruction Set Summary JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X PC Jump Address DIR EXT IX2 IX1 IX BC CC DC EC FC dd hh ll ee ff ff 2 3 4 3 2 PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) 1 Push (PCH); SP (SP) 1 PC Unconditional Address DIR EXT IX2 IX1 IX BD CD DD ED FD dd hh ll ee ff ff 4 5 6 5 4 A6 B6 C6 D6 E6 F6 9EE6 9ED6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ii jj dd 3 4 ii dd hh ll ee ff ff 2 3 4 4 3 2 4 5 V H I N Z C Jump Jump to Subroutine LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDA opr,SP LDA opr,SP Load A from M LDHX #opr LDHX opr Load H:X from M LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LDX opr,SP LDX opr,SP LSL opr LSLA LSLX LSL opr,X LSL ,X LSL opr,SP A (M) Logical Shift Right Move MUL Unsigned multiply X:A (X) × (A) ff ee ff 38 dd 48 58 68 ff 78 9E68 ff 4 1 1 4 3 5 0 C H:X (H:X) + 1 (IX+D, DIX+) AE BE CE DE EE FE 9EEE 9EDE DIR INH INH IX1 IX SP1 DIR INH INH IX1 IX SP1 34 dd 44 54 64 ff 74 9E64 ff 4 1 1 4 3 5 b0 (M)Destination (M)Source 45 55 0 0 Negate (Two's Complement) IMM DIR EXT IX2 IX1 IX SP1 SP2 b0 b7 IMM DIR 0 C b7 IMM DIR EXT IX2 IX1 IX SP1 SP2 0 X (M) Logical Shift Left (Same as ASL) MOV opr,opr MOV opr,X+ MOV #opr,opr MOV X+,opr 0 H:X (M:M + 1) Load X from M LSR opr LSRA LSRX LSR opr,X LSR ,X LSR opr,SP NEG opr NEGA NEGX NEG opr,X NEG ,X NEG opr,SP Effect on CCR Description 0 DD DIX+ IMD IX+D 0 0 INH M (M) = $