MC68HC908JL8 MC68HC908JK8 MC68HC908KL8 MC68HC08JL8 MC68HC08JK8 M68HC08 - Datasheet Archive

 

MC68HC908JK8 MC68HC908KL8 MC68HC08JL8 MC68HC08JK8 Data Sheet M68HC08 Microcontrollers MC68HC908JL8 Rev. 3.1 3/2005 freescale.com

 

MC68HC908JL8 MC68HC908JL8 MC68HC908JK8 MC68HC908JK8 MC68HC908KL8 MC68HC908KL8 MC68HC08JL8 MC68HC08JL8 MC68HC08JK8 MC68HC08JK8 Data Sheet M68HC08 M68HC08 Microcontrollers MC68HC908JL8 MC68HC908JL8 Rev. 3.1 3/2005 freescale.com MC68HC908JL8 MC68HC908JL8 MC68HC908JK8 MC68HC908JK8 MC68HC908KL8 MC68HC908KL8 MC68HC08JL8 MC68HC08JL8 MC68HC08JK8 MC68HC08JK8 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2005. All rights reserved. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 3 Revision History Date Revision Level Mar 2005 3.1 Page Number(s) Description Added IRQ timing to Table 17-5 . Control Timing (5V) and Table 17-8 . Control Timing (3V) 188, 190 Chapter 9 Serial Communications Interface (SCI) - Corrected SCI module clock source from OSCCLK to Bus Clock throughout. 121­206 Figure 13-2 . Keyboard Interrupt Block Diagram - Removed incorrect Schmitt trigger in block diagram. Nov 2002 2 176 201 Added Appendix B MC68HC908KL8 MC68HC908KL8. 3 14.7.2 Stop Mode - STOP_ICLKDIS bit does not affect stop mode conditions for COP. Replaced section with new text. Added Appendix A MC68HC08JL8 MC68HC08JL8 - ROM parts. Nov 2004 168 207 First general release. - MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 4 Freescale Semiconductor List of Chapters Chapter 1 General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Chapter 3 Configuration and Mask Option Registers (CONFIG & MOR) . . . . . . . . . . . . . . 41 Chapter 4 Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Chapter 5 System Integration Module (SIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Chapter 6 Oscillator (OSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Chapter 7 Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Chapter 8 Timer Interface Module (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Chapter 9 Serial Communications Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Chapter 10 Analog-to-Digital Converter (ADC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 Chapter 11 Input/Output (I/O) Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Chapter 12 External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Chapter 13 Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Chapter 14 Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Chapter 15 Low Voltage Inhibit (LVI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Chapter 16 Break Module (BREAK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Chapter 17 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Chapter 18 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Chapter 19 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Appendix A MC68HC08JL8 MC68HC08JL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Appendix B MC68HC908KL8 MC68HC908KL8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 5 List of Chapters MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 6 Freescale Semiconductor Table of Contents Chapter 1 General Description 1.1 1.2 1.3 1.4 1.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 17 18 20 21 Chapter 2 Memory 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Page Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Mass Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FLASH Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 25 25 33 33 33 34 34 35 35 38 38 Chapter 3 Configuration and Mask Option Registers (CONFIG & MOR) 3.1 3.2 3.3 3.4 3.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 1 (CONFIG1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register 2 (CONFIG2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Option Register (MOR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 41 42 43 43 Chapter 4 Central Processor Unit (CPU) 4.1 4.2 4.3 4.3.1 4.3.2 4.3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 45 46 46 46 47 MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 7 Table of Contents 4.3.4 4.3.5 4.4 4.5 4.5.1 4.5.2 4.6 4.7 4.8 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic/Logic Unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 48 49 49 49 49 50 50 50 Chapter 5 System Integration Module (SIM) 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 Clock Start-Up from POR or LVI Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.3 Clocks in Stop Mode and Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 External Pin Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 Active Resets from Internal Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.1 Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.2 Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.3 Illegal Opcode Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2.5 Low-Voltage Inhibit (LVI) Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 SIM Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 SIM Counter During Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 SIM Counter During Stop Mode Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.3 SIM Counter and Reset States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Exception Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1.1 Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1.2 SWI Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Interrupt Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2.1 Interrupt Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2.2 Interrupt Status Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2.3 Interrupt Status Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.4 Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.5 Status Flag Protection in Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 Break Status Register (BSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.2 Reset Status Register (RSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.3 Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 63 63 63 63 64 64 64 65 66 66 66 66 67 67 67 67 67 67 69 70 70 71 72 72 72 72 73 73 73 74 75 75 76 77 MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 8 Freescale Semiconductor Chapter 6 Oscillator (OSC) 6.1 6.2 6.2.1 6.2.2 6.3 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.4.6 6.4.7 6.4.8 6.5 6.5.1 6.5.2 6.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Input Pin (OSC1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Crystal Amplifier Output Pin (OSC2/RCCLK/PTA6/KBI6) . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Enable Signal (SIMOSCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XTAL Oscillator Clock (XTALCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RC Oscillator Clock (RCCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Out 2 (2OSCOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator Out (OSCOUT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Oscillator Clock (ICLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Oscillator During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 79 80 81 81 82 82 82 82 82 82 82 83 83 83 83 83 83 Chapter 7 Monitor ROM (MON) 7.1 7.2 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.4 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Entering Monitor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Echoing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Break Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 ROM-Resident Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 PRGRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 MON_PRGRNGE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 MON_ERARNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 MON_LDRNGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 EE_WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 EE_READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 9 Table of Contents Chapter 8 Timer Interface Module (TIM) 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Input Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3 Output Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3.1 Unbuffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.3.2 Buffered Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4 Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.1 Unbuffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.2 Buffered PWM Signal Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.4.3 PWM Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.1 TIM Clock Pin (ADC12/T2CLK ADC12/T2CLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.8.2 TIM Channel I/O Pins (PTD4/T1CH0, PTD5/T1CH1, PTE0/T2CH0, PTE1/T2CH1) . . . . . 8.9 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9.1 TIM Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9.2 TIM Counter Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9.3 TIM Counter Modulo Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9.4 TIM Channel Status and Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9.5 TIM Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 105 105 106 108 108 108 109 109 109 110 111 111 112 112 112 112 113 113 113 113 114 114 115 116 117 119 Chapter 9 Serial Communications Interface (SCI) 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2.2 Character Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2.3 Break Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2.4 Idle Characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2.5 Inversion of Transmitted Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2.6 Transmitter Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3.1 Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 121 121 123 123 124 124 125 125 125 126 126 126 126 MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 10 Freescale Semiconductor 9.4.3.2 Character Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3.3 Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3.4 Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3.5 Baud Rate Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3.6 Receiver Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3.7 Receiver Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3.8 Error Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.6 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.1 TxD (Transmit Data). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.7.2 RxD (Receive Data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.1 SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.2 SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.3 SCI Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.4 SCI Status Register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.5 SCI Status Register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.6 SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.8.7 SCI Baud Rate Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 128 129 130 131 132 132 133 133 133 133 133 133 133 134 134 136 138 139 142 142 143 Chapter 10 Analog-to-Digital Converter (ADC) 10.1 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.4 10.5 10.5.1 10.5.2 10.6 10.6.1 10.7 10.7.1 10.7.2 10.7.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Port I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accuracy and Precision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Voltage In (ADCVIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Input Clock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 145 145 146 147 147 147 147 147 147 147 148 148 148 148 148 150 150 MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 11 Table of Contents Chapter 11 Input/Output (I/O) Ports 11.1 11.2 11.2.1 11.2.2 11.2.3 11.3 11.3.1 11.3.2 11.4 11.4.1 11.4.2 11.4.3 11.5 11.5.1 11.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A Input Pull-Up Enable Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register D (DDRD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D Control Register (PDCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 153 153 153 155 156 156 156 157 158 158 160 160 160 161 Chapter 12 External Interrupt (IRQ) 12.1 12.2 12.3 12.3.1 12.4 12.5 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IRQ Status and Control Register (INTSCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 163 163 164 165 166 Chapter 13 Keyboard Interrupt Module (KBI) 13.1 13.2 13.3 13.4 13.4.1 13.5 13.5.1 13.5.2 13.6 13.6.1 13.6.2 13.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Status and Control Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Keyboard Module During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 167 167 168 169 169 169 170 171 171 171 171 Chapter 14 Computer Operating Properly (COP) 14.1 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 12 Freescale Semiconductor 14.3 14.3.1 14.3.2 14.3.3 14.3.4 14.3.5 14.3.6 14.3.7 14.4 14.5 14.6 14.7 14.7.1 14.7.2 14.8 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ICLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPCTL Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reset Vector Fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPD (COP Disable). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COPRS (COP Rate Select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 174 174 174 174 174 174 175 175 175 175 175 176 176 176 Chapter 15 Low Voltage Inhibit (LVI) 15.1 15.2 15.3 15.4 15.5 15.5.1 15.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . LVI Control Register (CONFIG2/CONFIG1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 177 177 178 178 178 178 Chapter 16 Break Module (BREAK) 16.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.4 16.4.1 16.4.2 16.4.3 16.4.4 16.5 16.5.1 16.5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flag Protection During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CPU During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM During Break Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Module Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Status and Control Register (BRKSCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Flag Control Register (BFCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 179 179 180 180 180 180 181 181 181 182 183 183 183 183 MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 13 Table of Contents Chapter 17 Electrical Specifications 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 17.9 17.10 17.11 17.12 17.13 17.14 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Typical Supply Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 185 186 186 187 188 188 189 190 191 192 193 193 194 Chapter 18 Mechanical Specifications 18.1 18.2 18.3 18.4 18.5 18.6 18.7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-Pin Plastic Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-Pin Small Outline Integrated Circuit Package (SOIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-Pin Plastic Dual In-Line Package (PDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-Pin Small Outline Integrated Circuit Package (SOIC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-Pin Shrink Dual In-Line Package (SDIP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-Pin Low-Profile Quad Flat Pack (LQFP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 195 196 196 197 197 198 Chapter 19 Ordering Information 19.1 19.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Appendix A MC68HC08JL8 MC68HC08JL8 A.1 A.2 A.3 A.4 A.5 A.6 A.7 A.7.1 A.8 A.9 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mask Option Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC08JL8 MC68HC08JL8 Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 201 201 202 204 204 204 204 205 206 MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 14 Freescale Semiconductor Appendix B MC68HC908KL8 MC68HC908KL8 B.1 B.2 B.3 B.4 B.5 B.6 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reserved Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MC68HC908KL8 MC68HC908KL8 Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 207 207 210 210 210 MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 15 Table of Contents MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 16 Freescale Semiconductor Chapter 1 General Description 1.1 Introduction The MC68HC908JL8 MC68HC908JL8 is a member of the low-cost, high-performance M68HC08 M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the family use the enhanced M68HC08 M68HC08 central processor unit (CPU08 CPU08) and are available with a variety of modules, memory sizes and types, and package types. Table 1-1. Summary of Devices Generic Part Description Pin Count MC68HC908JL8 MC68HC908JL8 FLASH part 28 or 32 MC68HC908JK8 MC68HC908JK8 FLASH part 20 MC68HC08JL8 MC68HC08JL8 ROM part for MC68HC908JL8 MC68HC908JL8 28 or 32 MC68HC08JK8 MC68HC08JK8 ROM part for MC68HC908JK8 MC68HC908JK8 20 MC68HC908KL8 MC68HC908KL8 ADC-less MC68HC908JL8 MC68HC908JL8 28 or 32 1.2 Features Features of the MC68HC908JL8 MC68HC908JL8 include the following: · High-performance M68HC08 M68HC08 architecture · Fully upward-compatible object code with M6805 M6805, M146805 M146805, and M68HC05 M68HC05 Families · Low-power design; fully static with stop and wait modes · Maximum internal bus frequency: ­ 8-MHz at 5V operating voltage ­ 4-MHz at 3V operating voltage · Oscillator options: ­ Crystal or resonator ­ RC oscillator · 8,192 bytes user program FLASH memory with security(1) feature · 256 bytes of on-chip RAM · Two 16-bit, 2-channel timer interface modules (TIM1 and TIM2) with selectable input capture, output compare, and PWM capability on each channel; external clock input option on TIM2 · 13-channel, 8-bit analog-to-digital converter (ADC) · Serial communications interface module (SCI) · 26 general-purpose input/output (I/O) ports: ­ 8 keyboard interrupt with internal pull-up 1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 17 General Description · · · · · · · ­ 11 LED drivers (sink) ­ 2 × 25mA open-drain I/O with pull-up Resident routines for in-circuit programming and EEPROM emulation System protection features: ­ Optional computer operating properly (COP) reset, driven by internal RC oscillator ­ Optional low-voltage detection with reset and selectable trip points for 3V and 5V operation ­ Illegal opcode detection with reset ­ Illegal address detection with reset Master reset pin with internal pull-up and power-on reset IRQ with schmitt-trigger input and programmable pull-up 20-pin dual in-line package (PDIP), 20-pin small outline integrated package (SOIC), 28-pin PDIP, 28-pin SOIC, 32-pin shrink dual in-line package (SDIP), and 32-pin low-profile quad flat pack (LQFP) Specific features of the MC68HC908JL8 MC68HC908JL8 in 28-pin packages are: ­ 23 general-purpose I/Os only ­ 7 keyboard interrupt with internal pull-up ­ 10 LED drivers (sink) ­ 12-channel ADC ­ Timer I/O pins on TIM1 only Specific features of the MC68HC908JL8 MC68HC908JL8 in 20-pin packages are: ­ 15 general-purpose I/Os only ­ 1 keyboard interrupt with internal pull-up ­ 4 LED drivers (sink) ­ 10-channel ADC ­ Timer I/O pins on TIM1 only Features of the CPU08 CPU08 include the following: · Enhanced HC05 programming model · Extensive loop control functions · 16 addressing modes (eight more than the HC05) · 16-bit index register and stack pointer · Memory-to-memory data transfers · Fast 8 × 8 multiply instruction · Fast 16/8 divide instruction · Binary-coded decimal (BCD) instructions · Optimization for controller applications · Efficient C language support 1.3 MCU Block Diagram Figure 1-1 shows the structure of the MC68HC908JL8 MC68HC908JL8. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 18 Freescale Semiconductor MCU Block Diagram INTERNAL BUS CONTROL AND STATUS REGISTERS - 64 BYTES USER FLASH - 8,192 BYTES PORTA ARITHMETIC/LOGIC UNIT (ALU) PTA7/KBI7* PTA6/KBI6*¥ PTA5/KBI5* PTA4/KBI4* PTA3/KBI3* PTA2/KBI2* PTA1/KBI1* PTA0/KBI0* PTB7/ADC7 PTB6/ADC6 PTB5/ADC5 PTB4/ADC4 PTB3/ADC3 PTB2/ADC2 PTB1/ADC1 PTB0/ADC0 KEYBOARD INTERRUPT MODULE 8-BIT ANALOG-TO-DIGITAL CONVERTER MODULE DDRA CPU REGISTERS PORTB M68HC08 M68HC08 CPU 2-CHANNEL TIMER INTERFACE MODULE 1 2-CHANNEL TIMER INTERFACE MODULE 2 MONITOR ROM - 959 BYTES USER FLASH VECTORS - 36 BYTES RC OSCILLATOR POWER-ON RESET MODULE * RST SYSTEM INTEGRATION MODULE LOW-VOLTAGE INHIBIT MODULE * IRQ EXTERNAL INTERRUPT MODULE VDD POWER VSS ADC REFERENCE COMPUTER OPERATING PROPERLY MODULE PTE INTERNAL OSCILLATOR ## # PTD7/RxD* PORTD OSC2/RCCLK ADC12/T2CLK ADC12/T2CLK SERIAL COMMUNICATIONS INTERFACE MODULE DDRE ¥ CRYSTAL OSCILLATOR BREAK MODULE DDRD OSC1 DDRB USER RAM - 256 BYTES # PTD6/TxD* PTD5/T1CH1 PTD4/T1CH0 PTD3/ADC8 PTD2/ADC9 PTD1/ADC10 PTD1/ADC10 PTD0/ADC11 PTD0/ADC11 ## PTE1/T2CH1 # PTE0/T2CH0 * Pin contains integrated pull-up device. * Pin contains programmable pull-up device. 25mA open-drain if output pin. LED direct sink pin. ¥ Shared pin: OSC2/RCCLK/PTA6/KBI6. # Pins available on 32-pin packages only. ## Pins available on 28-pin and 32-pin packages only. Figure 1-1. MC68HC908JL8 MC68HC908JL8 Block Diagram MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 19 General Description ADC12/T2CLK ADC12/T2CLK PTA7/KBI7 RST PTA5/KBI5 29 28 27 26 25 PTD4/T1CH0 IRQ 30 OSC1 1 PTA0/KBI0 32 VSS 31 1.4 Pin Assignments 24 PTD5/T1CH1 21 PTD3/ADC8 PTA2/KBI2 5 20 PTB0/ADC0 PTA3/KBI3 6 19 PTB1/ADC1 PTB7/ADC7 7 18 PTD1/ADC10 PTD1/ADC10 15 17 PTB2/ADC2 PTB3/ADC3 16 PTB5/ADC5 9 10 PTB6/ADC6 8 PTD0/ADC11 PTD0/ADC11 4 14 VDD PTB4/ADC4 PTA4/KBI4 13 22 PTE1/T2CH1 3 12 PTA1/KBI1 PTE0/T2CH0 PTD2/ADC9 11 23 PTD6/TxD 2 PTD7/RxD OSC2/RCCLK/PTA6/KBI6 Figure 1-2. 32-Pin LQFP Pin Assignment IRQ 1 32 ADC12/T2CLK ADC12/T2CLK PTA0/KBI0 2 31 PTA7/KBI7 VSS 3 30 RST OSC1 4 29 PTA5/KBI5 OSC2/RCCLK/PTA6/KBI6 5 28 PTD4/T1CH0 PTA1/KBI1 6 27 PTD5/T1CH1 VDD 7 26 PTD2/ADC9 PTA2/KBI2 8 25 PTA4/KBI4 PTA3/KBI3 9 24 PTD3/ADC8 PTB7/ADC7 10 23 PTB0/ADC0 PTB6/ADC6 11 22 PTB1/ADC1 PTB5/ADC5 12 21 PTD1/ADC10 PTD1/ADC10 PTD7/RxD 13 20 PTB2/ADC2 PTD6/TxD 14 19 PTB3/ADC3 PTE0/T2CH0 15 18 PTD0/ADC11 PTD0/ADC11 PTE1/T2CH1 16 17 PTB4/ADC4 Figure 1-3. 32-Pin SDIP Pin Assignment MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 20 Freescale Semiconductor Pin Functions IRQ 1 28 RST PTA0/KBI0 2 27 PTA5/KBI5 VSS 3 26 PTD4/T1CH0 OSC1 4 25 PTD5/T1CH1 OSC2/RCCLK/PTA6/KBI6 5 24 PTD2/ADC9 PTA1/KBI1 6 23 PTA4/KBI4 VDD 7 22 PTD3/ADC8 PTA2/KBI2 8 21 PTB0/ADC0 PTA3/KBI3 9 20 PTB1/ADC1 PTB7/ADC7 10 19 PTD1/ADC10 PTD1/ADC10 PTB6/ADC6 11 18 PTB2/ADC2 PTB5/ADC5 12 17 PTB3/ADC3 PTD7/RxD 13 16 PTD0/ADC11 PTD0/ADC11 PTD6/TxD 14 15 PTB4/ADC4 Pins not available on 28-pin packages PTE0/T2CH0 PTE1/T2CH1 ADC12/T2CLK ADC12/T2CLK PTA7/KBI7 Internal pads are unconnected. Set these unused port I/Os to output low. Figure 1-4. 28-Pin PDIP/SOIC Pin Assignment IRQ 1 20 RST VSS 2 19 PTD4/T1CH0 OSC1 3 18 PTD5/T1CH1 OSC2/RCCLK/PTA6/KBI6 4 17 PTD2/ADC9 VDD 5 16 PTD3/ADC8 PTB7/ADC7 6 15 PTB0/ADC0 PTA3/KBI3 PTE0/T2CH0 PTB6/ADC6 7 14 PTB1/ADC1 PTA4/KBI4 PTE1/T2CH1 PTB5/ADC5 8 13 PTB2/ADC2 PTA5/KBI5 PTD7/RxD 9 12 PTB3/ADC3 PTD6/TxD 10 11 PTB4/ADC4 Pins not available on 20-pin packages PTA0/KBI0 PTD0/ADC11 PTD0/ADC11 PTA1/KBI1 PTD1/ADC10 PTD1/ADC10 PTA2/KBI2 ADC12/T2CLK ADC12/T2CLK PTA7/KBI7 Internal pads are unconnected. Set these unused port I/Os to output low. The 20-pin MC68HC908JL8 MC68HC908JL8 is designated MC68HC908JK8 MC68HC908JK8. Figure 1-5. 20-Pin PDIP/SOIC Pin Assignment 1.5 Pin Functions Description of the pin functions are provided in Table 1-2. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 21 General Description Table 1-2. Pin Functions IN/OUT VOLTAGE LEVEL In 5V or 3V Out 0V In/Out VDD External IRQ pin; with programmable internal pull-up and schmitt trigger input. In VDD Used for monitor mode entry. In VDD to VTST Crystal or RC oscillator input. In VDD OSC2: crystal oscillator output; inverted OSC1 signal. Out VDD RCCLK: RC oscillator clock output. Out VDD In/Out VDD ADC12 ADC12: channel-12 input of ADC. In VSS to VDD T2CLK: external input clock for TIM2. In VDD In/Out VDD Each pin has programmable internal pull-up when configured as input. In VDD Pins as keyboard interrupts, KBI0­KBI7. In VDD PTA0­PTA5 and PTA7 have LED direct sink capability. Out VSS PTA6 as OSC2/RCCLK. Out VDD In/Out VDD In VSS to VDD 8-bit general purpose I/O port; with programmable internal pull-ups on PTD6­PTD7. In/Out VDD PTD0­PTD3 as ADC input channels, ADC11 ADC11­ADC8. Input VSS to VDD Out VSS PTD4 as T1CH0 of TIM1. In/Out VDD PTD5 as T1CH1 of TIM1. In/Out VDD PTD6­PTD7 have configurable 25mA open-drain output. Out VSS PTD6 as TxD of SCI. Out VDD PTD7 as RxD of SCI. In VDD PIN NAME PIN DESCRIPTION VDD Power supply. VSS Power supply ground. RST Reset input, active low; with internal pull-up and schmitt trigger input. IRQ OSC1 OSC2/RCCLK Pin as PTA6/KBI6 (see PTA0­PTA7). ADC12/T2CLK ADC12/T2CLK 8-bit general purpose I/O port. PTA0­PTA7 8-bit general purpose I/O port. PTB0­PTB7 Pins as ADC input channels, ADC0­ADC7. PTD2­PTD3 and PTD6­PTD7 have LED direct sink capability PTD0­PTD7 MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 22 Freescale Semiconductor Pin Functions Table 1-2. Pin Functions (Continued) IN/OUT VOLTAGE LEVEL 2-bit general purpose I/O port. In/Out VDD PTE0 as T2CH0 of TIM2. In/Out VDD PTE1 as T2CH1 of TIM2. In/Out VDD PIN NAME PTE0­PTE1 PIN DESCRIPTION NOTE Devices in 28-pin packages, the following pins are not available: PTA7/KBI7, PTE0/T2CH0, PTE1/T2CH1, and ADC12/T2CLK ADC12/T2CLK. Devices in 20-pin packages, the following pins are not available: PTA0/KBI0­PTA5/KBI5, PTD0/ADC11 PTD0/ADC11, PTD1/ADC10 PTD1/ADC10, PTA7/KBI7, PTE0/T2CH0, PTE1/T2CH1, and ADC12/T2CLK ADC12/T2CLK. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 23 General Description MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 24 Freescale Semiconductor Chapter 2 Memory 2.1 Introduction The CPU08 CPU08 can address 64-kbytes of memory space. The memory map, shown in Figure 2-1, includes: · 8,192 bytes of user FLASH memory · 36 bytes of user-defined vectors · 959 bytes of monitor ROM 2.2 I/O Section Addresses $0000­$003F, shown in Figure 2-2, contain most of the control, status, and data registers. Additional I/O registers have the following addresses: · $FE00; Break Status Register, BSR · $FE01; Reset Status Register, RSR · $FE02; Reserved · $FE03; Break Flag Control Register, BFCR · $FE04; Interrupt Status Register 1, INT1 · $FE05; Interrupt Status Register 2, INT2 · $FE06; Interrupt Status Register 3, INT3 · $FE07; Reserved · $FE08; FLASH Control Register, FLCR · $FE09; Reserved · $FE0A; Reserved · $FE0B; Reserved · $FE0C; Break Address Register High, BRKH · $FE0D; Break Address Register Low, BRKL · $FE0E; Break Status and Control Register, BRKSCR · $FE0F; Reserved · $FFCF; FLASH Block Protect Register, FLBPR (FLASH register) · $FFD0; Mask Option Register, MOR (FLASH register) · $FFFF; COP Control Register, COPCTL 2.3 Monitor ROM The 959 bytes at addresses $FC00­$FDFF and $FE10­$FFCE are reserved ROM addresses that contain the instructions for the monitor functions. (See Chapter 7 Monitor ROM (MON).) MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 25 Memory $0000 $003F I/O REGISTERS 64 BYTES $0040 $005F RESERVED 32 BYTES $0060 $015F RAM 256 BYTES $0160 $DBFF UNIMPLEMENTED 55,968 BYTES $DC00 $FBFF FLASH MEMORY 8,192 BYTES $FC00 $FDFF MONITOR ROM 512 BYTES $FE00 BREAK STATUS REGISTER (BSR) $FE01 RESET STATUS REGISTER (RSR) $FE02 RESERVED $FE03 BREAK FLAG CONTROL REGISTER (BFCR) $FE04 INTERRUPT STATUS REGISTER 1 (INT1) $FE05 INTERRUPT STATUS REGISTER 2 (INT2) $FE06 INTERRUPT STATUS REGISTER 3 (INT3) $FE07 RESERVED $FE08 FLASH CONTROL REGISTER (FLCR) $FE09 $FF0B RESERVED $FE0C BREAK ADDRESS HIGH REGISTER (BRKH) $FE0D BREAK ADDRESS LOW REGISTER (BRKL) $FE0E BREAK STATUS AND CONTROL REGISTER (BRKSCR) $FE0F RESERVED $FE10 $FFCE MONITOR ROM 447 BYTES $FFCF FLASH BLOCK PROTECT REGISTER (FLBPR) $FFD0 MASK OPTION REGISTER (MOR) $FFD1 $FFDB RESERVED 11 BYTES $FFDC $FFFF USER FLASH VECTORS 36 BYTES Figure 2-1. Memory Map MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 26 Freescale Semiconductor Monitor ROM Addr. $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0012 Register Name Read: Port A Data Register (PTA) Write: Reset: Read: Port B Data Register (PTB) Write: Reset: Read: Unimplemented Write: Read: Port D Data Register (PTD) Write: Reset: Read: Data Direction Register A Write: (DDRA) Reset: Read: Data Direction Register B Write: (DDRB) Reset: Read: Unimplemented Write: Read: Data Direction Register D Write: (DDRD) Reset: Read: Port E Data Register Write: (PTE) Reset: Read: Unimplemented Write: Read: Port D Control Register Write: (PDCR) Reset: Bit 7 6 5 4 3 2 1 Bit 0 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTB2 PTB1 PTB0 PTD2 PTD1 PTD0 Unaffected by reset PTB7 PTB6 PTB5 PTB4 PTB3 Unaffected by reset PTD7 PTD6 PTD5 PTD4 PTD3 Unaffected by reset DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 0 0 0 0 0 0 0 0 DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 0 0 0 0 0 0 0 0 DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 0 0 0 0 0 0 0 0 PTE1 PTE0 Unaffected by reset 0 0 0 0 0 0 0 0 SLOWD7 SLOWD6 PTDPU7 0 0 PTDPU6 0 0 DDRE1 DDRE0 0 0 Read: Unimplemented Write: Read: Data Direction Register E Write: (DDRE) Reset: 0 0 0 0 0 0 Port A Input Pull-up Read: PTA6EN PTAPUE6 PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0 Enable Register Write: (PTAPUE) Reset: 0 0 0 0 0 0 0 0 PTA7 Input Pull-up Read: PTAPUE7 Enable Register Write: (PTA7PUE) Reset: 0 0 0 0 0 0 0 0 Read: Unimplemented Write: U = Unaffected X = Indeterminate = Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 5) MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 27 Memory Addr. $0013 $0014 $0015 Register Name SCI Control Register 1 (SCC1) SCI Control Register 2 (SCC2) SCI Control Register 3 (SCC3) $0016 SCI Status Register 1 (SCS1) $0017 SCI Status Register 2 (SCS2) $0018 SCI Data Register (SCDR) $0019 SCI Baud Rate Register (SCBR) $001A $001B $001C Bit 7 Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Keyboard Status and Read: Control Register Write: (KBSCR) Reset: Keyboard Interrupt Read: Enable Register Write: (KBIER) Reset: 6 5 4 3 2 1 Bit 0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY 0 0 0 0 0 0 0 0 SCTIE TCIE SCRIE ILIE TE RE RWU SBK 0 R8 0 0 0 0 0 0 0 T8 DMARE DMATE ORIE NEIE FEIE PEIE U SCTE U TC 0 SCRF 0 IDLE 0 OR 0 NF 0 FE 0 PE 1 1 0 0 0 0 0 BKF 0 RPF 0 R7 T7 0 R6 T6 0 R5 T5 0 R2 T2 0 R1 T1 0 R0 T0 0 0 R4 R3 T4 T3 Unaffected by reset SCP1 SCP0 R SCR2 SCR1 SCR0 0 0 0 0 0 0 0 0 0 0 0 0 KEYF 0 ACKK IMASKK MODEK 0 0 0 0 0 0 0 0 KBIE7 KBIE6 KBIE5 KBIE4 KBIE3 KBIE2 KBIE1 KBIE0 0 0 0 0 0 0 0 0 IMASK MODE 0 Read: Unimplemented Write: 0 0 0 0 IRQF IRQ Status and Control Read: Register Write: (INTSCR) Reset: 0 0 0 0 0 Read: IRQPUD R R LVIT1 LVIT0 Configuration Register 2 $001E Write: (CONFIG2) Reset: 0 0 0 0* 0* Read: COPRS R R LVID R Configuration Register 1 Write: $001F (CONFIG1) Reset: 0 0 0 0 0 One-time writable register after each reset. * LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only. $001D $0020 $0021 TIM1 Status and Control Read: Register Write: (T1SC) Reset: TIM1 Counter Register Read: High Write: (T1CNTH) Reset: U = Unaffected TOF 0 TOIE TSTOP 0 TRST 0 0 ACK 0 R R 0 0 0 STOP_ ICLKDIS 0 SSREC STOP COPD 0 0 0 PS2 PS1 PS0 0 0 1 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 0 R 0 = Reserved 0 0 0 X = Indeterminate 0 0 0 = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 5) MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 28 Freescale Semiconductor Monitor ROM Addr. $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 $002A $002B $002F $0030 $0031 $0032 $0033 $0034 Register Name TIM1 Counter Register Read: Low Write: (T1CNTL) Reset: TIM Counter Modulo Read: Register High Write: (TMODH) Reset: TIM1 Counter Modulo Read: Register Low Write: (T1MODL) Reset: TIM1 Channel 0 Status Read: and Control Register Write: (T1SC0) Reset: TIM1 Channel 0 Read: Register High Write: (T1CH0H) Reset: TIM1 Channel 0 Read: Register Low Write: (T1CH0L) Reset: TIM1 Channel 1 Status Read: and Control Register Write: (T1SC1) Reset: TIM1 Channel 1 Read: Register High Write: (T1CH1H) Reset: TIM1 Channel 1 Read: Register Low Write: (T1CH1L) Reset: Bit 7 6 5 4 3 2 1 Bit 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 1 1 1 1 1 1 1 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 1 1 1 1 1 1 1 CH0F 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit2 Bit1 Bit0 Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Indeterminate after reset CH1F 0 CH1IE 0 0 Bit15 Bit14 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 0 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit2 Bit1 Bit0 PS2 PS1 PS0 Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Indeterminate after reset Read: Unimplemented Write: TIM2 Status and Control Read: Register Write: (T2SC) Reset: TIM2 Counter Register Read: High Write: (T2CNTH) Reset: TIM2 Counter Register Read: Low Write: (T2CNTL) Reset: TIM2 Counter Modulo Read: Register High Write: (T2MODH) Reset: TIM2 Counter Modulo Read: Register Low Write: (T2MODL) Reset: U = Unaffected TOF 0 TOIE TSTOP 0 TRST 0 0 0 1 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 0 0 0 0 0 0 0 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 1 1 1 1 1 1 1 1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1 R 1 = Reserved 1 1 1 X = Indeterminate 1 1 1 = Unimplemented Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 5) MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 29 Memory Addr. $0035 $0036 $0037 $0038 $0039 $003A $003B $003C $003D $003E $003F Register Name TIM2 Channel 0 Status Read: and Control Register Write: (T2SC0) Reset: TIM2 Channel 0 Read: Register High Write: (T2CH0H) Reset: TIM2 Channel 0 Read: Register Low Write: (T2CH0L) Reset: TIM2 Channel 1 Status Read: and Control Register Write: (T2SC1) Reset: TIM2 Channel 1 Read: Register High Write: (T2CH1H) Reset: TIM2 Channel 1 Read: Register Low Write: (T2CH1L) Reset: 6 5 4 3 2 1 Bit 0 CH0F 0 CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX 0 0 0 0 0 0 0 0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit2 Bit1 Bit0 Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Indeterminate after reset CH1F 0 CH1IE 0 0 Bit15 Bit14 0 MS1A ELS1B ELS1A TOV1 CH1MAX 0 0 0 0 0 0 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit2 Bit1 Bit0 Indeterminate after reset Bit7 Bit6 Bit5 Bit4 Bit3 Indeterminate after reset Read: Unimplemented Write: ADC Status and Control Read: Register Write: (ADSCR) Reset: Read: ADC Data Register Write: (ADR) Reset: Read: ADC Input Clock Register Write: (ADICLK) Reset: Read: Unimplemented Write: Read: $FE00 Break Status Register (BSR) Write: Reset: Note: Writing a logic 0 clears SBSW. Read: $FE01 Reset Status Register (RSR) Write: POR: Read: $FE02 Reserved Write: $FE03 Bit 7 Break Flag Control Read: Register Write: (BFCR) Reset: U = Unaffected COCO 0 AD7 AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 0 AD6 0 AD5 1 AD4 1 AD3 1 AD2 1 AD1 1 AD0 0 0 0 0 0 Indeterminate after reset 0 0 ADIV2 ADIV1 ADIV0 0 0 0 0 0 0 R R R R R R POR PIN COP ILOP ILAD MODRST LVI 0 1 0 0 0 0 0 0 0 R R R R R R R R BCFE R R R R R R R R = Reserved 0 X = Indeterminate = Unimplemented SBSW See note 0 R Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 5) MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 30 Freescale Semiconductor Monitor ROM Addr. Register Name $FE04 Interrupt Status Register 1 (INT1) $FE05 Interrupt Status Register 2 (INT2) $FE06 Interrupt Status Register 3 (INT3) $FE07 Reserved $FE08 $FE09 $FE0B $FE0C $FE0D $FE0E Read: Write: Reset: Read: Write: Reset: Read: Write: Reset: Read: Write: Read: FLASH Control Register Write: (FLCR) Reset: Read: Reserved Write: Break Address High Read: Register Write: (BRKH) Reset: Break Address low Read: Register Write: (BRKL) Reset: Break Status and Control Read: Register Write: (BRKSCR) Reset: Bit 7 IF6 R 0 IF14 R 0 0 R 0 6 IF5 R 0 IF13 R 0 0 R 0 5 IF4 R 0 IF12 R 0 0 R 0 4 IF3 R 0 IF11 R 0 0 R 0 3 0 R 0 0 R 0 0 R 0 2 IF1 R 0 0 R 0 0 R 0 1 0 R 0 IF8 R 0 0 R 0 Bit 0 0 R 0 IF7 R 0 IF15 R 0 R R R R R R R R 0 0 0 0 HVEN MASS ERASE PGM 0 0 0 0 0 0 0 0 R R R R R R R R Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 0 0 0 0 0 0 0 0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 0 BRKE BRKA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 R R FLASH Block Protect Read: BPR7 Register Write: # (FLBPR) Reset: Read: OSCSEL Mask Option Register $FFD0 Write: (MOR)# Reset: # Non-volatile FLASH registers; write by programming. $FFCF $FFFF Read: COP Control Register Write: (COPCTL) Reset: U = Unaffected Unaffected by reset; $FF when blank R X = Indeterminate R R R R Unaffected by reset; $FF when blank Low byte of reset vector Writing clears COP counter (any value) Unaffected by reset = Unimplemented R = Reserved Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 5) MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 31 Memory . Table 2-1. Vector Addresses Vector Priority INT Flag Address - $FFD0 $FFDD Not Used $FFDE ADC Conversion Complete Vector (High) $FFDF ADC Conversion Complete Vector (Low) $FFE0 Keyboard Interrupt Vector (High) $FFE1 Keyboard Interrupt Vector (Low) $FFE2 SCI Transmit Vector (High) $FFE3 SCI Transmit Vector (Low) $FFE4 SCI Receive Vector (High) $FFE5 SCI Receive Vector (Low) $FFE6 SCI Error Vector (High) $FFE7 SCI Error Vector (Low) Lowest IF15 IF14 IF13 IF12 IF11 IF10 IF9 IF8 IF7 IF6 IF5 IF4 IF3 IF2 - Vector Not Used $FFEC TIM2 Overflow Vector (High) $FFED TIM2 Overflow Vector (Low) $FFEE TIM2 Channel 1 Vector (High) $FFEF TIM2 Channel 1 Vector (Low) $FFF0 TIM2 Channel 0 Vector (High) $FFF1 TIM2 Channel 0 Vector (Low) $FFF2 TIM1 Overflow Vector (High) $FFF3 TIM1 Overflow Vector (Low) $FFF4 TIM1 Channel 1 Vector (High) $FFF5 TIM1 Channel 1 Vector (Low) $FFF6 TIM1 Channel 0 Vector (High) $FFF7 TIM1 Channel 0 Vector (Low) - Not Used - - $FFFA IRQ Vector (High) $FFFB IRQ Vector (Low) $FFFC SWI Vector (High) $FFFD SWI Vector (Low) $FFFE IF1 Reset Vector (High) $FFFF Reset Vector (Low) Highest MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 32 Freescale Semiconductor Random-Access Memory (RAM) 2.4 Random-Access Memory (RAM) Addresses $0060 through $015F are RAM locations. The location of the stack RAM is programmable. The 16-bit stack pointer allows the stack to be anywhere in the 64-Kbyte memory space. NOTE For correct operation, the stack pointer must point only to RAM locations. Within page zero are 160 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for I/O control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access efficiently all page zero RAM locations. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. NOTE For M6805 M6805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE Be careful when using nested subroutines. The CPU may overwrite data in the RAM during a subroutine or during the interrupt stacking operation. 2.5 FLASH Memory This sub-section describes the operation of the embedded FLASH memory. The FLASH memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. 2.6 Functional Description The FLASH memory consists of an array of 8,192 bytes for user memory plus a block of 36 bytes for user interrupt vectors. An erased bit reads as logic 1 and a programmed bit reads as a logic 0. The FLASH memory page size is defined as 64 bytes, and is the minimum size that can be erased in a page erase operation. Program and erase operations are facilitated through control bits in FLASH control register (FLCR). The address ranges for the FLASH memory are: · $DC00­$FBFF; user memory; 12,288 bytes · $FFDC­$FFFF; user interrupt vectors; 36 bytes Programming tools are available from Motorola. Contact your local Motorola representative for more information. NOTE A security feature prevents viewing of the FLASH contents.(1) 1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 33 Memory 2.7 FLASH Control Register The FLASH control register (FCLR) controls FLASH program and erase operations. Address: $FE08 Bit 7 Read: 6 5 4 0 0 0 0 0 0 0 0 Write: Reset: 3 2 1 Bit 0 HVEN MASS ERASE PGM 0 0 0 0 Figure 2-3. FLASH Control Register (FLCR) HVEN - High Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MASS - Mass Erase Control Bit This read/write bit configures the memory for mass erase operation or page erase operation when the ERASE bit is set. 1 = Mass erase operation selected 0 = Page erase operation selected ERASE - Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Erase operation selected 0 = Erase operation not selected PGM - Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be equal to 1 or set to 1 at the same time. 1 = Program operation selected 0 = Program operation not selected 2.8 FLASH Page Erase Operation Use the following procedure to erase a page of FLASH memory. A page consists of 64 consecutive bytes starting from addresses $XX00, $XX40, $XX80 or $XXC0. The 36-byte user interrupt vectors area also forms a page. Any page within the 8,192 bytes user memory area ($DC00­$FBFF) can be erased alone. The 36-byte user interrupt vectors cannot be erased by the page erase operation because of security reasons. Mass erase is required to erase this page. 1. Set the ERASE bit and clear the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH address within the page address range desired. 4. Wait for a time, tnvs (10µs). 5. Set the HVEN bit. 6. Wait for a time terase (4ms). MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 34 Freescale Semiconductor FLASH Mass Erase Operation 7. 8. 9. 10. Clear the ERASE bit. Wait for a time, tnvh (5µs). Clear the HVEN bit. After time, trcv (1µs), the memory can be accessed in read mode again. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 2.9 FLASH Mass Erase Operation Use the following procedure to erase the entire FLASH memory: 1. Set both the ERASE bit and the MASS bit in the FLASH control register. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the FLASH memory address range. 4. Wait for a time, tnvs (10µs). 5. Set the HVEN bit. 6. Wait for a time tmerase (4ms). 7. Clear the ERASE bit. 8. Wait for a time, tnvh1 (100µs). 9. Clear the HVEN bit. 10. After time, trcv (1µs), the memory can be accessed in read mode again. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order as shown, but other unrelated operations may occur between the steps. 2.10 FLASH Program Operation Programming of the FLASH memory is done on a row basis. A row consists of 32 consecutive bytes starting from addresses $XX00, $XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0 or $XXE0. Use this step-by-step procedure to program a row of FLASH memory: (Figure 2-4 shows a flowchart of the programming algorithm.) 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read the FLASH block protect register. 3. Write any data to any FLASH location within the address range of the row to be programmed. 4. Wait for a time, tnvs (10µs). 5. Set the HVEN bit. 6. Wait for a time, tpgs (5µs). 7. Write data to the FLASH address to be programmed. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 35 Memory 8. Wait for time, tprog (30µs). 9. Repeat steps 7 and 8 until all bytes within the row are programmed. 10. Clear the PGM bit. 11. Wait for time, tnvh (5µs). 12. Clear the HVEN bit. 13. After time, trcv (1µs), the memory can be accessed in read mode again. This program sequence is repeated throughout the memory until all data is programmed. NOTE The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH addressed programmed to clearing the PGM bit (step 7 to step 10), must not exceed the maximum programming time, tprog max. NOTE Programming and erasing of FLASH locations cannot be performed by code being executed from the FLASH memory. While these operations must be performed in the order shown, other unrelated operations may occur between the steps. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 36 Freescale Semiconductor FLASH Program Operation 1 Algorithm for programming a row (32 bytes) of FLASH memory 2 Set PGM bit Read the FLASH block protect register 3 Write any data to any FLASH location within the address range of the row to be programmed 4 Wait for a time, tnvs 5 6 7 8 Set HVEN bit Wait for a time, tpgs Write data to the FLASH address to be programmed Wait for a time, tprog Completed programming this row? Y N 10 The time between each FLASH address change (step 7 to step 7), or the time between the last FLASH address programmed to clearing PGM bit (step 7 to step 10) must not exceed the maximum programming time, tprog max. Clear PGM bit 11 Wait for a time, tnvh 12 Clear HVEN bit 13 NOTE: Wait for a time, trcv This row program algorithm assumes the row/s to be programmed are initially erased. End of programming Figure 2-4. FLASH Programming Flowchart MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 37 Memory 2.11 FLASH Block Protection Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made to protect blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by use of a FLASH block protect register (FLBPR). The FLBPR determines the range of the FLASH memory which is to be protected. The range of the protected area starts from a location defined by FLBPR and ends to the bottom of the FLASH memory ($FFFF). When the memory is protected, the HVEN bit cannot be set in either erase or program operations. NOTE In performing a program or erase operation, the FLASH block protect register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit When the FLBPR is program with all 0's, the entire memory is protected from being programmed and erased. When all the bits are erased (all 1's), the entire memory is accessible for program and erase. When bits within the FLBPR are programmed, they lock a block of memory, address ranges as shown in 2.12 FLASH Block Protect Register. Once the FLBPR is programmed with a value other than $FF, any erase or program of the FLBPR or the protected block of FLASH memory is prohibited. The FLBPR itself can be erased or programmed only with an external voltage, VTST, present on the IRQ pin. This voltage also allows entry from reset into the monitor mode. 2.12 FLASH Block Protect Register The FLASH block protect register (FLBPR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. The value in this register determines the starting location of the protected range within the FLASH memory. Address: $FFCF Bit 7 Read: Write: Reset: 6 5 4 3 2 1 Bit 0 BPR7 BPR6 BPR5 BPR4 BPR3 BPR2 BPR1 BPR0 Unaffected by reset; $FF when blank Non-volatile FLASH register; write by programming. Figure 2-5. FLASH Block Protect Register (FLBPR) BPR[7:0] - FLASH Block Protect Bits BPR[7:0] represent bits [13:6] of a 16-bit memory address. Bits [15:14] are logic 1's and bits [5:0] are logic 0's. 16-bit memory address Start address of FLASH block protect 1 1 0 0 0 0 0 0 BPR[7:0] MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 38 Freescale Semiconductor FLASH Block Protect Register The resultant 16-bit address is used for specifying the start address of the FLASH memory for block protection. The FLASH is protected from this start address to the end of FLASH memory, at $FFFF. With this mechanism, the protect start address can be XX00, XX40, XX80, or XXC0 (at page boundaries - 64 bytes) within the FLASH memory. Examples of protect start address: BPR[7:0] Start of Address of Protect Range (1) $00­$70 The entire FLASH memory is protected. $71 (0111 0001) $DC40 (1101 1100 0100 0000) $72 (0111 0010) $DC80 (1101 1100 1000 0000) $73 (0111 0011) $DCC0 (1101 1100 1100 0000) and so on. $FD (1111 1101) $FF40 (1111 1111 0100 0000) $FE (1111 1110) $FF80 (1111 1111 1000 0000) $FF The entire FLASH memory is not protected. 1. The end address of the protected range is always $FFFF. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 39 Memory MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 40 Freescale Semiconductor Chapter 3 Configuration and Mask Option Registers (CONFIG & MOR) 3.1 Introduction This section describes the configuration registers, CONFIG1 and CONFIG2; and the mask option register (MOR). The configuration registers enable or disable these options: · Computer operating properly module (COP) · COP timeout period (213 ­24 or 218 ­24 ICLK cycles) · · · · · · Internal oscillator during stop mode Low voltage inhibit (LVI) module LVI module voltage trip point selection STOP instruction Stop mode recovery time (32 or 4096 ICLK cycles) Pull-up on IRQ pin The mask option register selects the oscillator option: · Crystal or RC 3.2 Functional Description The configuration registers are used in the initialization of various options. The configuration registers can be written once after each reset. All of the configuration register bits are cleared during reset. Since the various options affect the operation of the MCU, it is recommended that these registers be written immediately after reset. The configuration registers are located at $001E and $001F. The configuration registers may be read at anytime. NOTE The options except LVIT[1:0] are one-time writable by the user after each reset. The LVIT[1:0] bits are one-time writable by the user only after each POR (power-on reset). The CONFIG registers are not in the FLASH memory but are special registers containing one-time writable latches after each reset. Upon a reset, the CONFIG registers default to predetermined settings as shown in Figure 3-1 and Figure 3-2. The mask option register (MOR) is used to select the oscillator option for the MCU: crystal oscillator or RC oscillator. The MOR is implemented as a byte in FLASH memory. Hence, writing to the MOR requires programming the byte. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 41 Configuration and Mask Option Registers (CONFIG & MOR) 3.3 Configuration Register 1 (CONFIG1) Address: $001F Bit 7 Write: Reset: 6 5 4 3 2 1 Bit 0 COPRS R R LVID R SSREC STOP COPD 0 0 0 0 0 0 0 0 R Read: = Reserved Figure 3-1. Configuration Register 1 (CONFIG1) COPRS - COP Rate Select Bit COPRS selects the COP time-out period. Reset clears COPRS. (See Chapter 14 Computer Operating Properly (COP).) 1 = COP timeout period is (213 ­ 24) ICLK cycles 0 = COP timeout period is (218 ­ 24) ICLK cycles LVID - Low Voltage Inhibit Disable Bit LVID disables the LVI module. Reset clears LVID. (See Chapter 15 Low Voltage Inhibit (LVI).) 1 = Low voltage inhibit disabled 0 = Low voltage inhibit enabled SSREC - Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 ICLK cycles instead of a 4096 ICLK cycle delay. 1 = Stop mode recovery after 32 ICLK cycles 0 = Stop mode recovery after 4096 ICLK cycles NOTE Exiting stop mode by pulling reset will result in the long stop recovery. If using an external crystal, do not set the SSREC bit. STOP - STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD - COP Disable Bit COPD disables the COP module. Reset clears COPD. (See Chapter 14 Computer Operating Properly (COP).) 1 = COP module disabled 0 = COP module enabled MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 42 Freescale Semiconductor Configuration Register 2 (CONFIG2) 3.4 Configuration Register 2 (CONFIG2) Address: $001E Bit 7 Write: Reset: POR: 6 5 4 3 2 1 Bit 0 IRQPUD R R LVIT1 LVIT0 R R STOP_ ICLKDIS 0 0 0 0 0 0 0 0 0 0 0 0 R Read: = Reserved Not affected Not affected 0 0 One-time writable register after each reset. LVIT1 and LVIT0 reset to logic 0 by a power-on reset (POR) only. Figure 3-2. Configuration Register 2 (CONFIG2) IRQPUD - IRQ Pin Pull-Up Disable Bit IRQPUD disconnects the internal pull-up on the IRQ pin. 1 = Internal pull-up is disconnected 0 = Internal pull-up is connected between IRQ pin and VDD LVIT1, LVIT0 - LVI Trip Voltage Selection Bits Detail description of trip voltage selection is given in Chapter 15 Low Voltage Inhibit (LVI). STOP_ICLKDIS - Internal Oscillator Stop Mode Disable Bit Setting STOP_ICLKDIS disables the internal oscillator during stop mode. When this bit is cleared, the internal oscillator continues to operate in stop mode. Reset clears this bit. 1 = Internal oscillator disabled during stop mode 0 = Internal oscillator enabled during stop mode 3.5 Mask Option Register (MOR) The mask option register (MOR) is implemented as a byte within the FLASH memory, and therefore can only be written during a programming sequence of the FLASH memory. This register is read after a power-on reset to determine the type of oscillator selected. (See Chapter 6 Oscillator (OSC).) Address: $FFD0 Bit 7 Read: Write: Erased: 6 5 4 3 2 1 Bit 0 OSCSEL R R R R R R R 1 1 1 1 1 1 1 1 Reset: Unaffected by reset Non-volatile FLASH register; write by programming. R = Reserved Figure 3-3. Mask Option Register (MOR) OSCSEL - Oscillator Select Bit OSCSEL selects the oscillator type for the MCU. The erased or unprogrammed state of this bit is logic 1, selecting the crystal oscillator option. This bit is unaffected by reset. 1 = Crystal oscillator 0 = RC oscillator MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 43 Configuration and Mask Option Registers (CONFIG & MOR) Bits 6­0 - Should be left as logic 1's. NOTE When Crystal oscillator is selected, the OSC2/RCCLK/PTA6/KBI6 pin is used as OSC2; other functions such as PTA6/KBI6 will not be available. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 44 Freescale Semiconductor Chapter 4 Central Processor Unit (CPU) 4.1 Introduction The M68HC08 M68HC08 CPU (central processor unit) is an enhanced and fully object-code-compatible version of the M68HC05 M68HC05 CPU. The CPU08 CPU08 Reference Manual (Motorola document order number CPU08RM/AD CPU08RM/AD) contains a description of the CPU instruction set, addressing modes, and architecture. 4.2 Features · · · · · · · · · · · Object code fully upward-compatible with M68HC05 M68HC05 Family 16-bit stack pointer with stack manipulation instructions 16-Bit Index Register with X-Register Manipulation Instructions 8-MHz CPU Internal Bus Frequency 64-Kbyte Program/Data Memory Space 16 Addressing Modes Memory-to-Memory Data Moves without Using Accumulator Fast 8-Bit by 8-Bit Multiply and 16-Bit by 8-Bit Divide Instructions Enhanced Binary-Coded Decimal (BCD) Data Handling Modular Architecture with Expandable Internal Bus Definition for Extension of Addressing Range beyond 64 Kbytes Low-Power Stop and Wait Modes MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 45 Central Processor Unit (CPU) 4.3 CPU Registers Figure 4-1 shows the five CPU registers. CPU registers are not part of the memory map. 0 7 ACCUMULATOR (A) 0 15 H X INDEX REGISTER (H:X) 15 0 STACK POINTER (SP) 15 0 PROGRAM COUNTER (PC) 7 0 V 1 1 H I N Z C CONDITION CODE REGISTER (CCR) CARRY/BORROW FLAG ZERO FLAG NEGATIVE FLAG INTERRUPT MASK HALF-CARRY FLAG TWO'S COMPLEMENT OVERFLOW FLAG Figure 4-1. CPU Registers 4.3.1 Accumulator The accumulator is a general-purpose 8-bit register. The CPU uses the accumulator to hold operands and the results of arithmetic/logic operations. Bit 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Unaffected by reset Figure 4-2. Accumulator (A) 4.3.2 Index Register The 16-bit index register allows indexed addressing of a 64-Kbyte memory space. H is the upper byte of the index register, and X is the lower byte. H:X is the concatenated 16-bit index register. In the indexed addressing modes, the CPU uses the contents of the index register to determine the conditional address of the operand. The index register can serve also as a temporary data storage location. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 46 Freescale Semiconductor CPU Registers Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 X X X X X X X X Read: Write: Reset: X = Indeterminate Figure 4-3. Index Register (H:X) 4.3.3 Stack Pointer The stack pointer is a 16-bit register that contains the address of the next location on the stack. During a reset, the stack pointer is preset to $00FF. The reset stack pointer (RSP) instruction sets the least significant byte to $FF and does not affect the most significant byte. The stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. In the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. The CPU uses the contents of the stack pointer to determine the conditional address of the operand. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Read: Write: Reset: Figure 4-4. Stack Pointer (SP) NOTE The location of the stack is arbitrary and may be relocated anywhere in RAM. Moving the SP out of page 0 ($0000 to $00FF) frees direct address (page 0) space. For correct operation, the stack pointer must point only to RAM locations. 4.3.4 Program Counter The program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. Normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. During reset, the program counter is loaded with the reset vector address located at $FFFE and $FFFF. The vector address is the address of the first instruction to be executed after exiting the reset state. MC68HC908JL8/JK8 MC68HC908JL8/JK8 · MC68HC08JL8/JK8 MC68HC08JL8/JK8 · MC68HC908KL8 MC68HC908KL8 Data Sheet, Rev. 3.1 Freescale Semiconductor 47 Central Processor Unit (CPU) Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 Read: Write: Reset: Loaded with Vector from $FFFE and $FFFF Figure 4-5. Program Counter (PC) 4.