MC68HC908AZ60/D MC68HC908AZ60 MC68HC708AZ60 MSCAN08 ADC-15 M68HC08 CPU08 - Datasheet Archive

 

MC68HC908AZ60 MC68HC708AZ60 HCMOS Microcontroller Unit TECHNICAL DATA List of Sections List of Sections List of Sections . . . .

 

MC68HC908AZ60/D MC68HC908AZ60/D MC68HC908AZ60 MC68HC908AZ60 MC68HC708AZ60 MC68HC708AZ60 HCMOS Microcontroller Unit TECHNICAL DATA List of Sections List of Sections List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FLASH-1 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 FLASH-2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 EEPROM-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 EEPROM-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Central Processor Unit (CPU) . . . . . . . . . . . . . . . . . . . . . 93 System Integration Module (SIM). . . . . . . . . . . . . . . . . 115 Clock Generator Module (CGM). . . . . . . . . . . . . . . . . 139 Configuration Register (CONFIG-1) . . . . . . . . . . . . . . . 167 Configuration Register (CONFIG-2) . . . . . . . . . . . . . . . 171 Break Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 © Motorola, Inc., 1998 MOTOROLA MC68HC908AZ60 MC68HC908AZ60 List of Sections 1 List of Sections Monitor ROM (MON) . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Computer Operating Properly Module (COP) . . . . . . 193 Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . . . . . . . . . . 199 External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . 205 Serial Communications Interface Module (SCI). . . . . 213 Serial Peripheral Interface Module (SPI) . . . . . . . . . . . 251 Timer Interface Module B (TIMB) . . . . . . . . . . . . . . . . . 283 Modulo Timer (TIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 CAN I/O Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 MSCAN Controller (MSCAN08 MSCAN08). . . . . . . . . . . . . . . . . . . 345 Keyboard Module (KBD). . . . . . . . . . . . . . . . . . . . . . . . 401 Timer Interface Module A (TIMA-6) . . . . . . . . . . . . . . . 409 Analog-to-Digital Converter (ADC-15 ADC-15) . . . . . . . . . . . . 441 Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 Appendix A: MC68HC708AZ60 MC68HC708AZ60 . . . . . . . . . . . . . . . . . . 469 Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 Literature Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 MC68HC908AZ60 MC68HC908AZ60 2 List of Sections MOTOROLA Table of Contents Table of Contents List of Sections Table of Contents General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Memory Map Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 RAM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 FLASH-1 Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FLASH Charge Pump Frequency Control . . . . . . . . . . . . . . . . . . . . . 43 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . . . . . . 45 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 FLASH-1 Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 FLASH-2 Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 FLASH-2 Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 MC68HC908AZ60 MC68HC908AZ60 MOTOROLA Table of Contents 3 Table of Contents FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 FLASH Charge Pump Frequency Control . . . . . . . . . . . . . . . . . . . . .57 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . . . . . .59 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 EEPROM-1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 EEPROM-2 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 Central Processor Unit (CPU) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 System Integration Module (SIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . . . . . .119 Reset and System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 Program Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 MC68HC908AZ60 MC68HC908AZ60 4 Table of Contents MOTOROLA Table of Contents Clock Generator Mo dule (CGM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CGM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . . . . . . 139 140 140 141 151 153 159 159 160 161 Configuration Register (CONFIG-1) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Configuration Register (CONFIG-2) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Break Module Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 173 173 174 176 178 Monitor ROM (MON) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 181 182 182 Computer Operatin g Properly Module ( COP) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 193 194 195 197 197 197 198 MC68HC908AZ60 MC68HC908AZ60 MOTOROLA Table of Contents 5 Table of Contents COP Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . .198 Low-Voltage Inhibit (LVI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 LVI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 External Interrupt M odule (IRQ) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206 IRQ Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209 IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . .210 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . .211 Serial Communicati ons Interface Modul e (SCI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232 SCI During Break Module Interrupts . . . . . . . . . . . . . . . . . . . . . . . . .233 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .233 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 Serial Peripheral Int erface Module (SPI) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 Pin Name and Register Name Conventions . . . . . . . . . . . . . . . . . . .253 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .254 Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271 MC68HC908AZ60 MC68HC908AZ60 6 Table of Contents MOTOROLA Table of Contents SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Timer Interface Mod ule B (TIMB) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIMB During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 284 284 287 294 295 296 297 298 Modulo Timer (TIM) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM Counter Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 309 310 310 312 312 313 314 CAN I/O Ports Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 320 321 323 326 329 332 336 339 341 MSCAN Controller (MSCAN08 MSCAN08) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 346 347 348 349 MC68HC908AZ60 MC68HC908AZ60 MOTOROLA Table of Contents 7 Table of Contents Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .354 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358 Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .364 Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369 Programmer's Model of Message Storage . . . . . . . . . . . . . . . . . . . .369 Programmer's Model of Control Registers . . . . . . . . . . . . . . . . . . . .377 Keyboard Module ( KBD) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .401 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .402 Keyboard Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .405 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406 Keyboard Module During Break Interrupts . . . . . . . . . . . . . . . . . . . .406 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .407 Timer Interface Mod ule A (TIMA-6) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .413 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .422 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423 TIMA During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .426 Analog-to-Digital Co nverter (ADC-15 ADC-15) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .441 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .442 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .445 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .445 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .446 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447 Specifications Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453 MC68HC908AZ60 MC68HC908AZ60 8 Table of Contents MOTOROLA Table of Contents Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Mechanical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467 Appendix A: MC68HC708AZ60 MC68HC708AZ60 One Time Programmable HC08 Microcontroller . . . . . . . . . . . . . . . 469 Index Glossary Literature Updates Literature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mfax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola SPS World Marketing World Wide Web Server . . . . . . . . Microcontroller Division's Web Site . . . . . . . . . . . . . . . . . . . . . . . . . 491 492 492 492 492 MC68HC908AZ60 MC68HC908AZ60 MOTOROLA Table of Contents 9 Table of Contents MC68HC908AZ60 MC68HC908AZ60 10 Table of Contents MOTOROLA General Description General Description Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Power Supply Pins (VDD and VSS) . . . . . . . . . . . . . . . . . . . . . . . . 17 Oscillator Pins (OSC1 and OSC2) . . . . . . . . . . . . . . . . . . . . . . . . . 17 External Reset Pin (RST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 External Interrupt Pin (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Analog Power Supply Pin (VDDA) . . . . . . . . . . . . . . . . . . . . . . . . . 18 Analog Ground Pin (VSSA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 External Filter Capacitor Pin (CGMXFC) . . . . . . . . . . . . . . . . . . . . 18 Port A Input/Output (I/O) Pins (PTA7­PTA0) . . . . . . . . . . . . . . . . . 18 Port B I/O Pins (PTB7/ATD7­PTB0/ATD0) . . . . . . . . . . . . . . . . . . 18 Port C I/O Pins (PTC5­PTC0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Port D I/O Pins (PTD7­PTD0/ATD8) . . . . . . . . . . . . . . . . . . . . . . . 19 Port E I/O Pins (PTE7/SPSCK­PTE0/TxD) . . . . . . . . . . . . . . . . . . 19 Port F I/O Pins (PTF6­PTF0/TACH2). . . . . . . . . . . . . . . . . . . . . . . 19 Port G I/O Pins (PTG2/KBD2­PTG0/KBD0). . . . . . . . . . . . . . . . . . 19 Port H I/O Pins (PTH1/KBD4­PTH0/KBD3) . . . . . . . . . . . . . . . . . . 19 CAN Transmit Pin (CANTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 CAN Receive Pin (CANRx). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MC Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Introduction The MC68HC908AZ60 MC68HC908AZ60 is a member of the low-cost, high-performance M68HC08 M68HC08 Family of 8-bit microcontroller units (MCUs). The M68HC08 M68HC08 Family is based on the customer-specified integrated circuit (CSIC) design strategy. All MCUs in the family use the enhanced M68HC08 M68HC08 MC68HC908AZ60 MC68HC908AZ60 1-gen MOTOROLA General Description 11 General Description central processor unit (CPU08 CPU08) and are available with a variety of modules, memory sizes and types, and package types. This part is designed to emulate the MC68HC08AZxx automotive family. In AZxx mode the MC68HC908AZ60 MC68HC908AZ60 offers extra features which are not available on the MC68HC08AZ32 MC68HC08AZ32 device. It is the user's responsibility to ensure compatibility between the features used on the MC68HC908AZ60 MC68HC908AZ60 and those which are available on the device which will ultimately be used in the application. Features Features of the MC68HC908AZ60 MC68HC908AZ60 include: · High-Performance M68HC08 M68HC08 Architecture · Fully Upward-Compatible Object Code with M6805 M6805, M146805 M146805, and M68HC05 M68HC05 Families · 8.4 MHz Internal Bus Frequency · 60 Kbytes of FLASH Electrically Erasable Read-Only Memory (FLASH) · FLASH Data Security · 1 Kbyte of On-Chip Electrically Erasable Programmable Read-Only Memory with Security Option (EEPROM) · 2 Kbyte of On-Chip RAM · Clock Generator Module (CGM) · Serial Peripheral Interface Module (SPI) · Serial Communications Interface Module (SCI) · 8-Bit, 15-Channel Analog-to-Digital Converter (ADC-15 ADC-15) · 16-Bit, 6-Channel Timer Interface Module (TIMA-6) · Periodic Interrupt Timer (TIM) · System Protection Features MC68HC908AZ60 MC68HC908AZ60 12 2-gen General Description MOTOROLA General Description Features ­ Computer Operating Properly (COP) with Optional Reset ­ Low-Voltage Detection with Optional Reset ­ Illegal Opcode Detection with Optional Reset ­ Illegal Address Detection with Optional Reset · Low-Power Design (Fully Static with Stop and Wait Modes) · Master Reset Pin and Power-On Reset Features of the CPU08 CPU08 include: · Enhanced HC05 Programming Model · Extensive Loop Control Functions · 16 Addressing Modes (Eight More Than the HC05) · 16-Bit Index Register and Stack Pointer · Memory-to-Memory Data Transfers · Fast 8 × 8 Multiply Instruction · Fast 16/8 Divide Instruction · Binary-Coded Decimal (BCD) Instructions · Optimization for Controller Applications · C Language Support · 16-Bit, 2-Channel Timer Interface Module (TIMB) · 5-Bit Keyboard Interrupt Module · MSCAN Controller (Motorola Scalable CAN) implements CAN 2.0b Protocol as Defined in BOSCH Specification September 1991 MC68HC908AZ60 MC68HC908AZ60 3-gen MOTOROLA General Description 13 General Description MCU Block Diagram Figure 1 shows the structure of the MC68HC908AZ60 MC68HC908AZ60. MC68HC908AZ60 MC68HC908AZ60 14 4-gen General Description MOTOROLA DDRA LOW-VOLTAGE INHIBIT MODULE USER RAM - 2048BYTES 2048BYTES TIMER A 6 CHANNEL INTERFACE MODULE SERIAL PERIPHERAL INTERFACE MODULE IRQ MODULE KEYBOARD INTERRUPT MODULE POWER-ON RESET MODULE VSS VDD VDDA VSSA PTE SYSTEM INTEGRATION MODULE POWER AVSS/VREFL VDDAREF PTG IRQ SERIAL COMMUNICATIONS INTERFACE MODULE PTH RST CLOCK GENERATOR MODULE DDRH DDRG OSC1 OSC2 CGMXFC DDRE TIMER B INTERFACE MODULE PTD7 PTD6/ATD14/TACLK PTD6/ATD14/TACLK PTD5/ATD13 PTD5/ATD13 PTD4/ATD12/TBCLK PTD4/ATD12/TBCLK PTD3/ATD11 PTD3/ATD11 PTD2/ATD10 PTD2/ATD10 PTD1/ATD9­PTD0/ATD8 PTF USER FLASH VECTOR SPACE - 52 BYTES PTC5­PTC3 PTC2/MCLK PTC1­PTC0 DDRF COMPUTER OPERATING PROPERLY MODULE MONITOR ROM - 224 BYTES General Description USER EEPROM - 1024 BYTES PTA USER FLASH - 60 kBYTES PTB BREAK MODULE DDRB CONTROL AND STATUS REGISTERS - 62 BYTES PTB7/ATD7­PTB0/ATD0 DDRC ANALOG-TO-DIGITAL MODULE PTD ARITHMETIC/LOGIC UNIT (ALU) PTA7­PTA0 DDRD CPU REGISTERS VREFH PTC 5-gen MOTOROLA M68HC08 M68HC08 CPU PTE7/SPSCK PTE6/MOSI PTE5/MISO PTE4/SS PTE3/TACH1 PTE2/TACH0 PTE1/RxD PTE0/TxD PTF6 PTF5/TBCH1­PTF4/TBCH0 PTF3/TACH5-PTF2/TACH4 PTF1/TACH3 PTF0/TACH2 PTG2/KBD2­PTG0/KBD0 PTH1/KBD4­PTH0/KBD3 MSCAN MODULE General Description MCU Block Diagram 15 MC68HC908AZ60 MC68HC908AZ60 Figure 1. MCU Block Diagram for the MC68HC908AZ60 MC68HC908AZ60 (64-Pin QFP) CANRx CANTx General Description Pin Assignments PTC1 PTC0 OSC1 OSC2 CGMXFC VSSA VDDA VREFH PTD7 PTD6/ATD14/TACLK PTD6/ATD14/TACLK PTD5/ATD13 PTD5/ATD13 PTD4/ATD12/TBCLK PTD4/ATD12/TBCLK 61 60 59 58 57 56 55 54 53 52 51 50 PTC4 1 PTH1/KBD4 PTC2/MCLK 62 49 PTC3 64 PTC5 63 Figure 2 shows the MC68HC908AZ60 MC68HC908AZ60 pin assignments. 48 PTH0/KBD3 41 PTB7/ATD7 CANRx 9 40 PTB6/ATD6 CANTx 10 39 PTB5/ATD5 PTF5/TBCH1 11 38 PTB4/ATD4 PTF6 12 37 PTB3/ATD3 PTE0/TxD 13 36 PTB2/ATD2 PTE1/RxD 14 35 PTB1/ATD1 PTE2/TACH0 15 34 PTB0/ATD0 33 PTA7 PTA6 32 31 PTE4/SS 17 18 PTE3/TACH1 16 PTA5 8 30 PTF4/TBCH0 PTA4 PTD0/ATD8 29 42 PTA3 7 28 PTF3/TACH5 PTA2 PTD1/ATD9 27 43 PTA1 6 26 PTF2/TACH4 PTA0 VDDAREF 25 44 PTG2/KBD2 5 24 PTF1/TACH3 PTG1/KBD1 AVSS /VREFL 23 45 PTG0/KBD0 4 22 PTF0/TACH2 VDD PTD2/ATD10 PTD2/ATD10 21 46 VSS 3 20 RST PTE7/SPSCK PTD3/ATD11 PTD3/ATD11 19 47 PTE6/MOSI 2 PTE5/MISO IRQ Figure 2. MC68HC908AZ60 MC68HC908AZ60 (64-Pin QFP) NOTE: The following pin descriptions are just a quick reference. For a more detailed representation, see CAN I/O Ports on page 319. MC68HC908AZ60 MC68HC908AZ60 16 6-gen General Description MOTOROLA General Description Pin Assignments Power Supply Pins (VDD and VSS) VDD and VSS are the power supply and ground pins. The MCU operates from a single power supply. Fast signal transitions on MCU pins place high, short-duration current demands on the power supply. To prevent noise problems, take special care to provide power supply bypassing at the MCU as shown in Figure 3. Place the C1 bypass capacitor as close to the MCU as possible. Use a high-frequency response ceramic capacitor for C1. C2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. MCU V SS V DD C1 0.1 µF + C2 V DD NOTE: Component values shown represent typical applications. Figure 3. Power supply bypassing VSS is also the ground for the port output buffers and the ground return for the serial clock in the serial peripheral interface module (SPI). See Serial Peripheral Interface Module (SPI) on page 251 NOTE: Oscillator Pins (OSC1 and OSC2) VSS must be grounded for proper MCU operation. The OSC1 and OSC2 pins are the connections for the on-chip oscillator circuit. See Clock Generator Module (CGM) on page 139 MC68HC908AZ60 MC68HC908AZ60 7-gen MOTOROLA General Description 17 General Description External Reset Pin (RST) A logic 0 on the RST pin forces the MCU to a known startup state. RST is bidirectional, allowing a reset of the entire system. It is driven low when any internal reset source is asserted. (See System Integration Module (SIM) on page 115 for more information). External Interrupt Pin (IRQ) IRQ is an asynchronous external interrupt pin. (See External Interrupt Module (IRQ) on page 205). Analog Power Supply Pin (VDDA) VDDA is the power supply pin for the analog portion of the chip. This pin will supply the clock generator module (CGM). (See Clock Generator Module (CGM) on page 139). Analog Ground Pin (VSSA) The VSSA analog ground pin is used only for the ground connections for the analog sections of the circuit and should be decoupled as per the VSS digital ground pin. The analog sections consist of a clock generator module (CGM). (See Clock Generator Module (CGM) on page 139). External Filter Capacitor Pin (CGMXFC) CGMXFC is an external filter capacitor connection for the CGM. See Clock Generator Module (CGM) on page 139 Port A Input/Output (I/O) Pins (PTA7­PTA0) PTA7­PTA0 are general-purpose bidirectional I/O port pins. See CAN I/O Ports on page 319. Port B I/O Pins (PTB7/ATD7ÐPTB0/ ATD0) Port B is an 8-bit special function port that shares all eight pins with the analog-to-digital converter (ADC). See Analog-to-Digital Converter (ADC-15 ADC-15) on page 441 and CAN I/O Ports on page 319. Port C I/O Pins (PTC5ÐPTC0) PTC5­PTC3 and PTC1­PTC0 are general-purpose bidirectional I/O port pins. PTC2/MCLK is a special function port that shares its pin with MC68HC908AZ60 MC68HC908AZ60 18 8-gen General Description MOTOROLA General Description Pin Assignments the system clock which has a frequency equivalent to the system clock. See CAN I/O Ports on page 319. Port D I/O Pins (PTD7ÐPTD0/ATD8) Port D is an 8-bit special-function port that shares seven of its pins with the analog-to-digital converter module (ADC-15 ADC-15), one of its pins with the timer interface module (TIMA), and one more of its pins with the timer interface module (TIMB). See Timer Interface Module A (TIMA-6) on page 409, Analog-to-Digital Converter (ADC-15 ADC-15) on page 441and CAN I/O Ports on page 319. Port E I/O Pins (PTE7/SPSCKÐPTE0/ TxD) Port E is an 8-bit special function port that shares two of its pins with the timer interface module (TIMA), four of its pins with the serial peripheral interface module (SPI), and two of its pins with the serial communication interface module (SCI). (See Serial Communications Interface Module (SCI) on page 213, Serial Peripheral Interface Module (SPI) on page 251, Timer Interface Module A (TIMA-6) on page 409, and CAN I/O Ports on page 319). Port F I/O Pins (PTF6ÐPTF0/TACH2) Port F is a 7-bit special function port that shares its pins with the timer interface module (TIMB). Six of its pins are shared with the timer interface module (TIMA-6). See Timer Interface Module A (TIMA-6) on page 409, Timer Interface Module B (TIMB) on page 283, and CAN I/O Ports on page 319. Port G I/O Pins (PTG2/KBD2ÐPTG0 /KBD0) Port G is a 3-bit special function port that shares all of its pins with the keyboard interrupt module (KBD). (See Keyboard Module (KBD) on page 401 and CAN I/O Ports on page 319). Port H I/O Pins (PTH1/KBD4ÐPTH0/ KBD3) Port H is a 2-bit special-function port that shares all of its pins with the keyboard interrupt module (KBD). (See Keyboard Module (KBD) on page 401 and CAN I/O Ports on page 319.) MC68HC908AZ60 MC68HC908AZ60 9-gen MOTOROLA General Description 19 General Description CAN Transmit Pin (CANTx) This pin is the digital output from the CAN module (CANTx). (See MSCAN Controller (MSCAN08 MSCAN08) on page 345). CAN Receive Pin (CANRx) This pin is the digital input to the CAN module (CANRx). (See MSCAN Controller (MSCAN08 MSCAN08) on page 345). Table 1. External Pins Summary Pin Name Function Driver Type Hysteresis Reset State PTA7­PTA0 General-Purpose I/O Dual State No Input Hi-Z PTB7/ATD7­PTB0/ATD0 General-Purpose I/O ADC Channel Dual State No Input Hi-Z PTC5­PTC0 General-Purpose I/O Dual State No Input Hi-Z PTD7 General Purpose I/O/ Dual State No Input Hi-Z PTD6/ATD14/TACLK PTD6/ATD14/TACLK * ADC Channel General-Purpose I/O ADC Channel/Timer External Input Clock Dual State No Input Hi-Z General-Purpose I/O ADC Channel Dual State No Input Hi-Z General-Purpose I/O ADC Channel/Timer External Input Clock Dual State No PTD5/ATD13 PTD5/ATD13 * ADC Channel PTD4/ATD12/TBCLK PTD4/ATD12/TBCLK * ADC Channel Input Hi-Z PTD3/ATD11 PTD3/ATD11­PTD0/ATD8 *ADC Channels General-Purpose I/O ADC Channel Dual State PTE7/SPSCK General-Purpose I/O SPI Clock Dual State Open Drain Yes Input Hi-Z PTE6/MOSI General-Purpose I/O SPI Data Path Dual State Open Drain Yes Input Hi-Z PTE5/MISO General-Purpose I/O SPI Data Path Dual State Open Drain Yes Input Hi-Z PTE4/SS General-Purpose I/O SPI Slave Select Dual State Yes Input Hi-Z PTE3/TACH1 General-Purpose I/O Timer Channel 1 Dual State Yes Input Hi-Z PTE2/TACH0 General-Purpose I/O Timer Channel 0 Dual State Yes Input Hi-Z PTE1/RxD General-Purpose I/O SCI Receive Data Dual State Yes Input Hi-Z MC68HC908AZ60 MC68HC908AZ60 20 No Input Hi-Z 10-gen General Description MOTOROLA General Description Pin Assignments Table 1. External Pins Summary (Continued) Pin Name Function Driver Type Hysteresis Reset State PTE0/TxD General-Purpose I/O SCI Transmit Data Dual State No Input Hi-Z PTF6 General-Purpose I/O Dual State No Input Hi-Z PTF5/TBCH1­PTF4/TBCH0 General-Purpose I/O/Timer B Channel Dual State Yes Input Hi-Z PTF3/TACH5 General-Purpose I/O Timer A Channel 5 Dual State Yes Input Hi-Z PTF2/TACH4 General-Purpose I/O Timer A Channel 4 Dual State Yes Input Hi-Z PTF1/TACH3 General-Purpose I/O Timer A Channel 3 Dual State Yes Input Hi-Z PTF0/TACH2 General-Purpose I/O Timer A Channel 2 Dual State Yes Input Hi-Z PTG2/KBD2­PTG0/KBD0 General-Purpose I/O/ Keyboard Wakeup Pin Dual State Yes Input Hi-Z PTH1/KBD4 ­PTH0/KBD3 General-Purpose I/O/ Keyboard Wakeup Pin Dual State Yes Input Hi-Z VDD Chip Power Supply N/A N/A N/A VSS Chip Ground N/A N/A N/A AVDD/VDDAREF ADC Power Supply/ ADC Reference Voltage N/A N/A N/A AVSS/VREFL ADC Ground/ADC Reference Voltage N/A N/A N/A VREFH A/D Reference Voltage N/A N/A N/A OSC1 External Clock In N/A N/A Input Hi-Z OSC2 External Clock Out N/A N/A Output CGMXFC PLL Loop Filter Cap N/A N/A N/A IRQ External Interrupt Request N/A N/A Input Hi-Z RST Reset N/A N/A Output Low CANRx CAN Serial Input N/A Yes Input Hi-Z CANTx CAN Serial Output Output No Output MC68HC908AZ60 MC68HC908AZ60 11-gen MOTOROLA General Description 21 General Description Table 2. Clock Source Summary Module Clock Source ADC CGMXCLK or Bus Clock CAN CGMXCLK or CGMOUT COP CGMXCLK CPU Bus Clock EEPROM RC OSC or Bus Clock SPI Bus Clock/SPSCK SCI CGMXCLK TIMA-6 Bus Clock or PTD6/ATD14/TACLK PTD6/ATD14/TACLK TIMB Bus Clock or PTD4/TBCLK TIM Bus Clock SIM CGMOUT and CGMXCLK IRQ Bus Clock BRK Bus Clock LVI Bus Clock CGM OSC1 and OSC2 MC68HC908AZ60 MC68HC908AZ60 22 12-gen General Description MOTOROLA General Description Ordering Information Ordering Information This section contains instructions for ordering the MC68HC908AZ60 MC68HC908AZ60 and the MC68HC708AZ60 MC68HC708AZ60. MC Order Numbers Table 3. MC Order Numbers MC Order Number Operating Temperature Range MC68HC908AZ60CFU MC68HC908AZ60CFU ­ 40 °C to + 85°C MC68HC908AZ60VFU MC68HC908AZ60VFU ­ 40 °C to + 105 °C MC68HC908AZ60MFU MC68HC908AZ60MFU - 40 °C to + 125 °C MC68HC708AZ60CFU MC68HC708AZ60CFU -40°C to +85°C MC68HC708AZ60VFU MC68HC708AZ60VFU ­ 40 °C to + 105 °C MC68HC708AZ60MFU MC68HC708AZ60MFU - 40 °C to + 125 °C MC68HC908AZ60 MC68HC908AZ60 MOTOROLA General Description 23 General Description MC68HC908AZ60 MC68HC908AZ60 24 General Description MOTOROLA Memory Map Memory Map Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 I/O Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Introduction The CPU08 CPU08 can address 64 Kbytes of memory space. The memory map, shown in Figure 1, includes: · 60 Kbytes of FLASH EEPROM · 2048 Bytes of RAM · 1024 Bytes of EEPROM with Protect Option · 52 Bytes of User-Defined Vectors · 224 Bytes of Monitor ROM The following definitions apply to the memory map representation of reserved and unimplemented locations. · Reserved - Accessing a reserved location can have unpredictable effects on MCU operation. · Unimplemented - Accessing an unimplemented location causes an illegal address reset if illegal address resets are enabled. MC68HC908AZ60 MC68HC908AZ60 1-mem MOTOROLA Memory Map 25 Memory Map Figure 1. Memory Map $0000 $0000 I/O REGISTERS (64 BYTES) $003F $003F $0040 $0040 I/O REGISTERS, 16 BYTES $004F $004F $0050 $0050 RAM-1, 512 BYTES $044F $044F $0450 $0450 FLASH-2, 176 BYTES $04FF $04FF $0500 $0500 CAN CONTROL AND MESSAGE BUFFERS, 128 BYTES $057F $057F $0580 $0580 FLASH-2, 128 BYTES $05FF $05FF $0600 $0600 EEPROM-2, 512 BYTES $07FF $07FF $0800 $0800 EEPROM-1, 512 BYTES $09FF $09FF $0A00 $0A00 RAM-2 , 1024 BYTES $0DFF $0DFF $0E00 $0E00 FLASH-2, 29,184 BYTES $7FFF $7FFF $8000 $8000 FLASH-1, 32,256BYTES 256BYTES $FDFF $FDFF $FE00 SIM BREAK STATUS REGISTER (SBSR) $FE00 $FE01 SIM RESET STATUS REGISTER (SRSR) $FE01 $FE02 RESERVED $FE02 $FE03 SIM BREAK FLAG CONTROL REGISTER (SBFCR) $FE03 MC68HC908AZ60 MC68HC908AZ60 26 2-mem Memory Map MOTOROLA Memory Map Introduction Figure 1. Memory Map (Continued) $FE04 RESERVED $FE04 $FE05 RESERVED $FE05 $FE06 UNIMPLEMENTED $FE06 $FE07 RESERVED $FE07 $FE08 RESERVED $FE08 $FE09 CONFIGURATION WRITE-ONCE REGISER (CONFIG-2) $FE09 $FE0A RESERVED $FE0A $FE0B FLASH CONTROL REGISTER (FLCR1) $FE0B $FE0C BREAK ADDRESS REGISTER HIGH (BRKH) $FE0C $FE0D BREAK ADDRESS REGISTER LOW (BRKL) $FE0D $FE0E BREAK STATUS AND CONTROL REGISTER (BSCR) $FE0E $FE0F LVI STATUS REGISTER (LVISR) $FE0F $FE10 RESERVED $FE10 $FE11 FLASH CONTROL REGISTER (FLCR2) $FE11 $FE12 $FE12 UNIMPLEMENTED (5BYTES) $FE17 $FE17 $FE18 EEPROM NON-VOLATILE REGISTER (EENVR2) $FE18 $FE19 EEPROM CONTROL REGISTER (EECR2) $FE19 $FE1A RESERVED $FE1A $FE1B EEPROM ARRAY CONFIGURATION (EEACR2) $FE1B $FE1C EEPROM NON-VOLATILE REGISTER (EENVR1) $FE1C $FE1D EEPROM CONTROL REGISTER (EECR1) $FE1D $FE1E RESERVED $FE1E $FE1F EEPROM ARRAY CONFIGURATION (EEACR1) $FE1F $FE20 $FE20 MONITOR ROM (224 BYTES) $FEFF $FEFF $FF00 $FF7F UNIMPLEMENTED (128 BYTES) $FF00 $FF7F $FF80 FLASH BLOCK PROTECT REGISTER (FLBPR1) $FF80 $FF81 FLASH BLOCK PROTECT REGISTER (FLBPR2) $FF81 $FF82 $FF82 RESERVED (75 BYTES) $FFCB $FFCB MC68HC908AZ60 MC68HC908AZ60 3-mem MOTOROLA Memory Map 27 Memory Map Figure 1. Memory Map (Continued) $FFCC $FFCC VECTORS (52BYTES 52BYTES) $FFFF $FFFF I/O Section Addresses $0000­$003F, shown in Figure 2, contain most of the control, status, and data registers. Additional I/O registers have these addresses: · $FE00 (SIM break status register, SBSR) · $FE01 (SIM reset status register, SRSR) · $FE03 (SIM break flag control register, SBFCR) · $FE09 (configuration write-once register, CONFIG-2) · $FE0B (FLASH control register, FLCR1) · $FE0C and $FE0D (break address registers, BRKH and BRKL) · $FE0E (break status and control register, BRKSCR) · $FE0F (LVI status register, LVISR) · $FE11 (FLASH control register, FLCR2) · $FE18 (EEPROM non-volatile register, EENVR2) · $FE19 (EEPROM control register, EECR2) · $FE1B (EEPROM array configuration register, EEACR2) · $FE1C (EEPROM non-volatile register, EENVR1) · $FE1D (EEPROM control register, EECR1) · $FE1F (EEPROM array configuration register, EEACR1) · $FF80 (FLASH block protect register, FLBPR1) · $FF81 (FLASH block protect register, FLBPR2) · $FFFF (COP control register, COPCTL) Table 1 is a list of vector locations. MC68HC908AZ60 MC68HC908AZ60 28 4-mem Memory Map MOTOROLA Memory Map I/O Section Addr. Register Name $0000 Port A Data Register (PTA) $0001 Port B Data Register (PTB) $0002 Port C Data Register (PTC) $0003 Port D Data Register (PTD) Bit 7 Read: Write: Read: Write: Read: 6 5 4 3 2 1 Bit 0 PTA7 PTA6 PTA5 PTA4 PTA3 PTA2 PTA1 PTA0 PTB7 PTB6 PTB5 PTB4 PTB3 PTB2 PTB1 PTB0 0 0 PTC5 PTC4 PTC3 PTC2 PTC1 PTC0 PTD7 PTD6 PTD5 PTD4 PTD3 PTD2 PTD1 PTD0 Write: Read: Write: $0004 Data Direction Register A Read: DDRA7 (DDRA) Write: DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 $0005 Data Direction Register B Read: DDRB7 (DDRB) Write: DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 $0006 Data Direction Register C Read: MCLKEN (DDRC) Write: DDRC5 DDRC4 DDRC3 DDRC2 DDRC1 DDRC0 $0007 Data Direction Register D Read: DDRD7 (DDRD) Write: DDRD6 DDRD5 DDRD4 DDRD3 DDR2 DDRD1 DDRD0 PTE6 PTE5 PTE4 PTE3 PTE2 PTE1 PTE0 PTF6 PTF5 PTF4 PTF3 PTF2 PTF1 PTF0 0 0 0 0 0 PTG2 PTG1 PTG0 0 0 0 0 0 0 PTH1 PTH0 $0008 Port E Data Register (PTE) $0009 Port F Data Register (PTF) $000A Port G Data Register (PTG) $000B Port H Data Register (PTH) Read: Write: Read: PTE7 0 Write: Read: 0 Write: Read: Write: $000C Data Direction Register E Read: DDRE7 (DDRE) Write: DDRE6 DDRE5 DDRE4 DDRE3 DDRE2 DDRE1 DDRE0 $000D Data Direction Register F Read: (DDRF) Write: 0 DDRF6 DDRF5 DDRF4 DDRF3 DDRF2 DDRF1 DDRF0 $000E Data Direction Register G Read: (DDRG) Write: 0 0 0 0 0 DDRG2 DDRG1 DDRG0 $000F Data Direction Register H Read: (DDRH) Write: 0 0 0 0 0 0 DDRH1 DDRH0 SPRIE R SPMSTR CPOL CPHA SPWOM SPE SPTIE $0010 SPI Control Register (SPCR) Read: Write: Figure 2. Control, Status, and Data Registers (Sheet 1 of 6) MC68HC908AZ60 MC68HC908AZ60 5-mem MOTOROLA Memory Map 29 Memory Map Addr. Register Name Bit 7 6 5 4 = Unimplemented $0011 SPI Status and Control Read: Register (SPSCR) Write: $0012 SPI Data Register (SPDR) $0013 SCI Control Register 1 (SCC1) $0014 SCI Control Register 2 (SCC2) $0015 SCI Control Register 3 (SCC3) $0016 SCI Status Register 1 (SCS1) $0017 SCI Status Register 2 (SCS2) $0018 SCI Data Register (SCDR) $0019 SCI Baud Rate Register (SCBR) SPRF ERRIE R 2 1 Bit 0 = Reserved OVRF MODF SPTE MODFE N SPR1 SPR0 Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 LOOPS ENSCI TXINV M WAKE ILTY PEN PTY SCTIE TCIE SCRIE ILIE TE RE RWU SBK T8 R R ORIE NEIE FEIE PEIE SCTE TC SCRF IDLE OR NF FE PE 0 0 0 0 0 0 BKF RPF Read: R7 R6 R5 R4 R3 R2 R1 R0 Write: T7 T6 T5 T4 T3 T2 T1 T0 Read: 0 0 SCP1 SCP0 SCR2 SCR1 SCR0 0 0 0 Read: Write: Read: Write: Read: R8 Write: Read: Write: Read: Write: Write: $001A IRQ Status and Control Read: Register (ISCR) Write: 0 $001B Keyboard Status and Control Read: Register (KBSCR) Write: 0 $001C PLL Control Register (PCTL) Read: Write: 0 PLLF PLLIE $001E PLL Programming Register Read: (PPG) Write: KEYF 0 TOF 0 0 IMASK1 MODE1 IMASKK MODEK 1 1 1 1 0 0 0 0 MUL4 VRS7 VRS6 VRS5 VRS4 LVIPWR SSREC COPL STOP COPD 0 0 PS2 PS1 PS0 KBIE2 KBIE1 KBIE0 PLLON BCS ACQ XLD MUL5 R LVIRST TSTOP 0 0 LOCK Configuration Write-Once Read: LVISTOP Register (CONFIG-1) Write: Keyboard Interrupt Enable Register Read: (KBIE) Write: 0 TOIE MUL7 $0021 0 MUL6 AUTO Timer A Status and Control Read: Register (TASC) Write: 0 ACKK PLL Bandwidth Control Read: Register (PBWC) Write: $0020 IRQF1 ACK1 $001D $001F 3 TRST KBIE4 KBIE3 Figure 2. Control, Status, and Data Registers (Sheet 2 of 6) MC68HC908AZ60 MC68HC908AZ60 30 6-mem Memory Map MOTOROLA Memory Map I/O Section Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 $0022 Timer A Counter Register Read: High (TACNTH) Write: Bit 15 14 13 12 11 10 9 Bit 8 $0023 Timer A Counter Register Read: Low (TACNTL) Write: Bit 7 6 5 4 3 2 1 Bit 0 $0024 Timer A Modulo Register Read: High (TAMODH) Write: Bit 15 14 13 12 11 10 9 Bit 8 $0025 Timer A Modulo Register Read: Low (TAMODL) Write: Bit 7 6 5 4 3 2 1 Bit 0 $0026 Timer A Channel 0 Status and Read: Control Register (TASC0) Write: CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX $0027 Timer A Channel 0 Register Read: High (TACH0H) Write: Bit 15 14 13 12 11 10 9 Bit 8 $0028 Timer A Channel 0 Register Read: Low (TACH0L) Write: Bit 7 6 5 4 3 2 1 Bit 0 $0029 Timer A Channel 1 Status and Read: Control Register (TASC1) Write: MS1A ELS1B ELS1A TOV1 CH1MAX $002A Timer A Channel 1 Register Read: High (TACH1H) Write: Bit 15 14 13 12 11 10 9 Bit 8 $002B Timer A Channel 1 Register Read: Low (TACH1L) Write: Bit 7 6 5 4 3 2 1 Bit 0 $002C Timer A Channel 2 Status and Read: Control Register (TASC2) Write: CH2IE MS2B MS2A ELS2B ELS2A TOV2 CH2MAX $002D Timer A Channel 2 Register Read: High (TACH2H) Write: Bit 15 14 13 12 11 10 9 Bit 8 $002E Timer A Channel 2 Register Read: Low (TACH2L) Write: Bit 7 6 5 4 3 2 1 Bit 0 $002F Timer A Channel 3 Status and Read: Control Register (TASC3) Write: MS3A ELS3B ELS3A TOV3 CH3MAX $0030 Timer A Channel 3 Register Read: High (TACH3H) Write: Bit 15 14 13 12 11 10 9 Bit 8 $0031 Timer A Channel 3 Register Read: Low (TACH3L) Write: Bit 7 6 5 4 3 2 1 Bit 0 $0032 Timer A Channel 4 Status and Read: Control Register (TASC4) Write: CH4IE MS4B MS4A ELS4B ELS4A TOV4 CH4MAX $0033 Timer A Channel 4 Register High Read: (TACH4H) Write: 14 13 12 11 10 9 Bit 8 CH0F 0 CH1F 0 CH2F 0 CH3F 0 CH4F 0 Bit 15 0 CH1IE 0 CH3IE Figure 2. Control, Status, and Data Registers (Sheet 3 of 6) MC68HC908AZ60 MC68HC908AZ60 7-mem MOTOROLA Memory Map 31 Memory Map Addr. Register Name Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 MS5A ELS5B ELS5A TOV5 CH5MAX $0034 Timer A Channel 4 Register Low Read: (TACH4L) Write: $0035 Timer A Channel 5 Status and Read: Control Register (TASC5) Write: $0036 Timer A Channel 5 Register Read: High (TACH5H) Write: Bit 15 14 13 12 11 10 9 Bit 8 $0037 Timer A Channel 5 Register Read: Low (TACH5L) Write: Bit 7 6 5 4 3 2 1 Bit 0 $0038 Analog-to-Digital Status and Read: COCO Control Register (ADSCR) Write: AIEN ADCO ADCH4 ADCH3 ADCH2 ADCH1 ADCH0 AD6 AD5 AD4 AD3 AD2 AD1 AD0 ADIV1 ADIV0 ADICLK 0 0 0 0 TOIE TSTOP PS2 PS1 PS0 $0039 $003A Analog-to-Digital Data Register Read: (ADR) Write: CH5F 0 AD7 Analog-to-Digital Input Clock Read: ADIV2 Register (ADICLK) Write: 0 CH5IE $0040 Timer B Status and Control Read: Register (TBSCR) Write: TOF $0041 Timer B Counter Register High Read: (TBCNTH) Write: Bit 15 14 13 12 11 10 9 Bit 8 $0042 Timer B Counter Register Low Read: (TBCNTL) Write: Bit 7 6 5 4 3 2 1 Bit 0 $0043 Timer B Modulo Register High Read: (TBMODH) Write: Bit 15 14 13 12 11 10 9 Bit 8 $0044 Timer B Modulo Register Low Read: (TBMODL) Write: Bit 7 6 5 4 3 2 1 Bit 0 $0045 Timer B CH0 Status and Control Read: Register (TBSC0) Write: CH0IE MS0B MS0A ELS0B ELS0A TOV0 CH0MAX $0046 Timer B CH0 Register High Read: (TBCH0H) Write: Bit 15 14 13 12 11 10 9 Bit 8 $0047 Timer B CH0 Register Low Read: (TBCH0L) Write: Bit 7 6 5 4 3 2 1 Bit 0 MS1A ELS1B ELS1A TOV1 CH1MAX $0048 Timer B CH1 Status and Control Read: Register (TBSC1) Write: CH0F 0 CH1F 0 0 CH1IE 0 0 TRST $0049 Timer B CH1 Register High Read: (TBCH1H) Write: Bit 15 14 13 12 11 10 9 Bit 8 $004A Timer B CH1 Register Low Read: (TBCH1L) Write: Bit 7 6 5 4 3 2 1 Bit 0 Figure 2. Control, Status, and Data Registers (Sheet 4 of 6) MC68HC908AZ60 MC68HC908AZ60 32 8-mem Memory Map MOTOROLA Memory Map I/O Section Addr. Register Name Bit 7 6 5 TOIE TSTOP 4 3 0 0 2 1 Bit 0 PS2 PS1 PS0 $004B TIM Status and Control Register Read: (TSC) Write: TOF $004C TIM Counter Register High Read: (TCNTH) Write: Bit 15 14 13 12 11 10 9 Bit 8 $004D TIM Counter Register Low Read: (TCNTL) Write: Bit 7 6 5 4 3 2 1 Bit 0 $004E TIM Modulo Register High Read: (TMODH) Write: Bit 15 14 13 12 11 10 9 Bit 8 $004F TIM Modulo Register Low Read: (TMODL) Write: Bit 7 6 5 4 3 2 1 Bit 0 $FE00 SIM Break Status Register Read: (SBSR) Write: R R R R R R SBSW R POR PIN COP ILOP ILAD 0 LVI 0 BCFE R R R R R R R 0 0 0 MSCAND 0 0 0 AZxx FDIV0 BLK1 BLK0 HVEN VERF ERASE PGM $FE01 SIM Reset Status Register (SRSR) Read: Write: $FE03 SIM Break Flag Control Register Read: (SBFCR) Write: $FE09 Configuration Write-Once Register Read: (CONFIG-2) Write: Flash Control Register Read: FDIV1 (FLCR1) Write: $FE0B TRST $FE0C Break Address Register High Read: (BRKH) Write: Bit 15 14 13 12 11 10 9 Bit 8 $FE0D Break Address Register Low Read: (BRKL) Write: Bit 7 6 5 4 3 2 1 Bit 0 $FE0E Break Status and Control Read: Register (BRKSCR) Write: BRKE BRKA 0 0 0 0 0 0 0 0 0 0 0 0 0 FDIV0 BLK1 BLK0 HVEN VERF ERASE PGM CON2 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 EEOFF EERAS1 EERAS0 EELAT $FE0F LVI Status Register (LVISR) Write: Flash Control Register Read: FDIV1 (FLCR2) Write: $FE11 $FE18 Read: LVIOUT EEPROM Nonvolatile Register Read: (EENVR2) Write: $FE19 $FE1A EERA EEPROM Control Read: EEBCLK Register (EECR2) Write: Reserved Read: Write: R 0 R R R R R 0 R EEPGM R Figure 2. Control, Status, and Data Registers (Sheet 5 of 6) MC68HC908AZ60 MC68HC908AZ60 9-mem MOTOROLA Memory Map 33 Memory Map Addr. Register Name Bit 7 $FE1B EEPROM Array Control Register Read: (EEACR2) Write: $FE1C EEPROM Nonvolatile Register Read: (EENVR1) Write: 6 5 EERA CON2 CON1 EERA CON2 EEPROM Control Read: EEBCLK Register (EECR1) Write: $FE1D $FE1E Reserved Read: Write: 0 2 1 Bit 0 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 CON1 EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 EEOFF EERAS1 EERAS0 EELAT R R R EERA CON2 CON1 4 R 3 R 0 EEPGM R R R EEPRTCT EEBP3 EEBP2 EEBP1 EEBP0 $FE1F EEPROM Array Control Register Read: (EEACR1) Write: $FF80 FLASH Block Protect Register Read: (FLBPR1) Write: BPR3 BPR2 BPR1 BPR0 $FF81 FLASH Block Protect Register Read: (FLBPR2) Write: BPR3 BPR2 BPR1 BPR0 $FFFF COP Control Register (COPCTL) Read: LOW BYTE OF RESET VECTOR Write: WRITING TO $FFFF CLEARS COP COUNTER Figure 2. Control, Status, and Data Registers (Sheet 6 of 6) MC68HC908AZ60 MC68HC908AZ60 34 10-mem Memory Map MOTOROLA Memory Map I/O Section Table 1. Vector Addresses Address Vector $FFCD TIMA Channel 5 Vector (Low) TIMA Channel 4 Vector (High) $FFCF TIMA Channel 4 Vector (Low) $FFD0 ADC Vector (High) $FFD1 ADC Vector (Low) $FFD2 Keyboard Vector (High) $FFD3 Keyboard Vector (Low) $FFD4 SCI Transmit Vector (High) $FFD5 SCI Transmit Vector (Low) $FFD6 SCI Receive Vector (High) $FFD7 SCI Receive Vector (Low) $FFD8 SCI Error Vector (High) $FFD9 SCI Error Vector (Low) $FFDA CAN Transmit Vector (High) $FFDB CAN Transmit Vector (Low) $FFDC CAN Receive Vector (High) $FFDD CAN Receive Vector (Low) $FFDE CAN Error Vector (High) $FFDF CAN Error Vector (Low) $FFE0 CAN Wakeup Vector (High) $FFE1 CAN Wakeup Vector (Low) $FFE2 SPI Transmit Vector (High) $FFE3 SPI Transmit Vector (Low) $FFE4 SPI Receive Vector (High) $FFE5 SPI Receive Vector (Low) $FFE6 TIMB Overflow Vector (High) $FFE7 TIMB Overflow Vector (Low) $FFE8 TIMB CH1 Vector (High) $FFE9 TIMB CH1 Vector (Low) $FFEA TIMB CH0 Vector (High) $FFEB TIMB CH0 Vector (Low) $FFEC TIMA Overflow Vector (High) $FFED TIMA Overflow Vector (Low) $FFEE TIMA CH3 Vector (High) $FFEF Priority TIMA Channel 5 Vector (High) $FFCE Low $FFCC TIMA CH3 Vector (Low) MC68HC908AZ60 MC68HC908AZ60 11-mem MOTOROLA Memory Map 35 Memory Map Table 1. Vector Addresses (Continued) Address Vector TIMA CH2 Vector (Low) $FFF2 TIMA CH1 Vector (High) $FFF3 TIMA CH1 Vector (Low) $FFF4 TIMA CH0 Vector (High) $FFF5 TIMA CH0 Vector (Low) $FFF6 TIM Vector (High) $FFF7 TIM Vector (Low) $FFF8 PLL Vector (High) $FFF9 PLL Vector (Low) $FFFA IRQ1 Vector (High) $FFFB IRQ1 Vector (Low) $FFFC SWI Vector (High) $FFFD High TIMA CH2 Vector (High) $FFF1 Priority $FFF0 SWI Vector (Low) $FFFE Reset Vector (High) $FFFF Reset Vector (Low) MC68HC908AZ60 MC68HC908AZ60 36 12-mem Memory Map MOTOROLA RAM RAM Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Introduction This section describes the 2048 bytes of random-access memory (RAM). Functional Description Addresses $0050 through $044F and $0A00 through $0DFF are RAM locations. The location of the stack RAM is programmable with the reset stack pointer instruction (RSP). The 16-bit stack pointer allows the stack RAM to be anywhere in the 64K-byte memory space. NOTE: For correct operation, the stack pointer must point only to RAM locations. Within page zero are 176 bytes of RAM. Because the location of the stack RAM is programmable, all page zero RAM locations can be used for input/output (I/O) control and user data or code. When the stack pointer is moved from its reset location at $00FF, direct addressing mode instructions can access all page zero RAM locations efficiently. Page zero RAM, therefore, provides ideal locations for frequently accessed global variables. Before processing an interrupt, the CPU uses five bytes of the stack to save the contents of the CPU registers. MC68HC908AZ60 MC68HC908AZ60 1-ram MOTOROLA RAM 37 RAM NOTE: For M68HC05 M68HC05, M6805 M6805, and M146805 M146805 compatibility, the H register is not stacked. During a subroutine call, the CPU uses two bytes of the stack to store the return address. The stack pointer decrements during pushes and increments during pulls. NOTE: Be careful when using nested subroutines. The CPU could overwrite data in the RAM during a subroutine or during the interrupt stacking operation. MC68HC908AZ60 MC68HC908AZ60 38 2-ram RAM MOTOROLA FLASH-1 Memory ROM Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 FLASH-1 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 FLASH Charge Pump Frequency Control. . . . . . . . . . . . . . . . . . . . . . 43 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . . . . . . 45 Smart Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 FLASH-1 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 FLASH-2 Block Protect Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Introduction This section describes the operation of the embedded FLASH-1 memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908AZ60 MC68HC908AZ60 1-flash-1 MOTOROLA FLASH-1 Memory 39 FLASH-1 Memory Functional Description The FLASH memory physically consists of two independent arrays of 32K bytes with an additional 52 bytes of user vectors and two bytes of block protection. An erased bit reads as a logic 0 and a programmed bit reads as a logic 1. Program and erase operations are facilitated through control bits in a memory mapped register. Details for these operations appear later in this section. Memory in the FLASH array is organized into pages within rows. There are 8 pages of memory per row with 8 bytes per page. The minimum erase block size is a single row, 64 bytes. Programming is performed on a per page basis; eight bytes at a time. The address ranges for the user memory, control register and vectors are: · $8000­$FDFF · $FF80-FF81 FF80-FF81 (Block Protect Registers) · $FE0B FLASH Control Register · $FFCC-$FFFF (These locations are reserved for user-defined interrupt and reset vectors.) When programming the FLASH, just enough program time must be used to program a page. Too much program time can result in a program disturb condition; in which case an erased bit on the row being programmed becomes unintentionally programmed. Program disturb is avoided by using an iterative program and margin read technique known as the smart programming algorithm. The smart programming algorithm is required whenever programming the FLASH (See FLASH Program/Margin Read Operation on page 45). As well, to avoid the program disturb issue, each storage page of the row should not be programmed more than once before it is erased. The 8 program cycle maximum per row aligns with the architecture's 8 pages of storage per row. The margin read step of the smart programming algorithm is used to insure programmed bits are programmed to sufficient margin for data retention over the device lifetime. Below is the row architecture for this array: MC68HC908AZ60 MC68HC908AZ60 40 2-flash-1 FLASH-1 Memory MOTOROLA FLASH-1 Memory FLASH-1 Control Register · $8000-$803F (Row0) · $8040-$807F (Row1) · $8080-$80BF (Row2) · - · $FFC0-$FFFF(Row 511) Programming tools are available from Motorola. Contact your local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents.1 FLASH-1 Control Register The FLASH-1 control register controls FLASH-1 program, erase, and margin read operations. Address: $FE0B Bit 7 6 5 4 3 2 1 Bit 0 FDIV1 FDIV0 BLK1 BLK0 HVEN MARGIN ERASE PGM 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 1. FLASH-1 Control Register (FLCR1) FDIV1 - Frequency Divide Control Bit This read/write bit together with FDIV0 selects the factor by which the charge pump clock is divided from the system clock. See FLASH Charge Pump Frequency Control on page 43. 1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908AZ60 MC68HC908AZ60 3-flash-1 MOTOROLA FLASH-1 Memory 41 FLASH-1 Memory FDIV0 - Frequency Divide Control Bit This read/write bit together with FDIV1 selects the factor by which the charge pump clock is divided from the system clock. See FLASH Charge Pump Frequency Control on page 43. BLK1- Block Erase Control Bit This read/write bit together with BLK0 allows erasing of blocks of varying size. See FLASH Erase Operation on page 43 for a description of available block sizes. BLK0 - Block Erase Control Bit This read/write bit together with BLK1 allows erasing of blocks of varying size. See FLASH Erase Operation on page 43 for a description of available block sizes. HVEN - High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program/margin read or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MARGIN - Margin Read Control Bit This read/write bit configures the memory for margin read operation. MARGIN cannot be set if the HVEN = 1. MARGIN will automatically return to unset (0) if asserted when HVEN = 1. 1 = Margin read operation selected 0 = Margin read operation unselected ERASE - Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be set at the same time. 1 = Erase operation selected 0 = Erase operation unselected MC68HC908AZ60 MC68HC908AZ60 42 4-flash-1 FLASH-1 Memory MOTOROLA FLASH-1 Memory FLASH Charge Pump Frequency Control PGM - Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be set at the same time. 1 = Program operation selected 0 = Program operation unselected FLASH Charge Pump Frequency Control The internal charge pump, required for program, margin read, and erase operations, is designed to operate most efficiently with a 2MHz clock. The charge pump clock is derived from the bus clock. Table 1 shows how the FDIV bits are used to select a charge pump frequency based on the bus clock frequency. Program, margin read and erase operations cannot be performed if the bus clock frequency is below 2 MHz. Table 1. Charge Pump Clock Frequency FDIV1 Pump Clock Frequency Bus Clock Frequency 0 0 Bus Frequency ÷ 1 2 MHz ± 10% 0 1 Bus Frequency ÷ 2 4 MHz ± 10% 1 0 Bus Frequency ÷ 2 4 MHz ± 10% 1 NOTE: FDIV0 1 Bus Frequency ÷ 4 8 MHz ± 10% FDIV1 and FDIV2 must be set to the same value in both flash arrays. FLASH Erase Operation Memory Characteristics on page 465 has a detailed description of the times used in this algorithm. Use the following procedure to erase a block of FLASH memory: 1. Set the ERASE bit, the BLK0, BLK1, FDIV0, and FDIV1 bits in the FLASH-1 control register. See Table 2 for block sizes. See Table 1 for FDIV settings. MC68HC908AZ60 MC68HC908AZ60 5-flash-1 MOTOROLA FLASH-1 Memory 43 FLASH-1 Memory 2. Insure target portion of array is unprotected, read the block protect register: address $FF80. See FLASH Block Protection on page 48 and FLASH-1 Block Protect Register on page 49 for more information. 3. Write to any FLASH address with any data within the block address range desired. 4. Set the HVEN bit. 5. Wait for a time, tERASE. 6. Clear the HVEN bit. 7. Wait for a time, t KILL, for the high voltages to dissipate. 8. Clear the ERASE bit. 9. After time tHVD, the memory can be accessed in read mode again. NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Table 2 shows the various block sizes which can be erased in one erase operation. Table 2. Erase Block Sizes BLK1 BLK0 Block Size, Addresses Cared 0 0 Full Array: 24 Kbytes 0 1 One-Half Array: 16 Kbytes (A14 ) 1 0 Eight Rows: 512 Bytes (A14­A9) 1 1 Single Row: 64 Bytes (A14­A6) In step 2 of the erase operation, the cared addresses are latched and used to determine the location of the block to be erased. For instance, with BLK0 = BLK1 = 0, writing to any Flash address in the range $8000 to $FFFF will enable the full-array erase. MC68HC908AZ60 MC68HC908AZ60 44 6-flash-1 FLASH-1 Memory MOTOROLA FLASH-1 Memory FLASH Program/Margin Read Operation FLASH Program/Margin Read Operation NOTE: After a total of 8 program operations have been applied to a row, the row must be erased before further programming in order to avoid program disturb. An erased byte will read $00. Programming of the FLASH memory is done on a page basis. A page consists of eight consecutive bytes starting from address $XXX0 or $XXX8. The purpose of the margin read mode is to ensure that data has been programmed with sufficient margin for long-term data retention. While performing a margin read the operation is the same as for ordinary read mode except that a built-in counter stretches the data access for an additional eight cycles to allow sensing of the lower cell current. Margin read mode imposes a more stringent read condition on the bitcell to insure the bitcell is programmed with enough margin for long-term data retention. During these eight cycles the COP counter continues to run. The user must account for these extra cycles within COP feed loops. A margin read cycle can only follow a page programming operation. To program and margin read the FLASH memory, use the following algorithm. Memory Characteristics on page 465, has a detailed description of the times used in this algorithm. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read from the block protect register. 3. Write data to the eight bytes of the page being programmed. This requires eight separate write operations. 4. Set the HVEN bit. 5. Wait for time, tPROG. 6. Clear the HVEN bit. 7. Wait for time, tHVTV. 8. Set the MARGIN bit. 9. Wait for time, tVTP. 10. Clear the PGM bit. 11. Wait for time, tHVD. MC68HC908AZ60 MC68HC908AZ60 7-flash-1 MOTOROLA FLASH-1 Memory 45 FLASH-1 Memory 12. Read back data in margin read mode. This is done in eight separate read operations which are each stretched by eight cycles. 13. Clear the MARGIN bit. NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. This program/margin read sequence is repeated throughout the memory until all data is programmed. The Smart Programming Algorithm is always required when programming any part of the array. This algorithm insures the minimum possible program time and avoids the deleterious program disturb effect. (See FLASH Erase Operation on page 43). NOTE: In order to ensure proper FLASH read operation after completion of the smart programming algorithm, a series of 500 dummy FLASH reads must be performed of any address before accurate data is read from the FLASH. MC68HC908AZ60 MC68HC908AZ60 46 8-flash-1 FLASH-1 Memory MOTOROLA FLASH-1 Memory FLASH Program/Margin Read Operation Smart Programming Algorithm Program FLASH 2TS Page Program/Margin Read Procedure Note: This algorithm is mandatory for programming the FLASH 2TS. Set Interrupt Mask: SEI Instruction Note: This page program algorithm assumes the page/s to be programmed are initially erased. Initialize Attempt Counter to Zero Set PGM Bit and FDIV bits Read Flash Block Protect Register Write Data to Selected Page Set HVEN Bit Wait tSTEP Clear HVEN Bit Wait tHVTV Set MARGIN Bit Wait tVTP Clear PGM Bit Wait tHVD Margin Read Page of Data Clear MARGIN Bit Increment Attempt Counter N Margin Read Data Equal To Write Data? Y Clear MARGIN Bit N Attempt Count Equal To flsPULSES? Clear Interrupt Mask: CLI Instr. Y Programming Operation Failed MC68HC908AZ60 MC68HC908AZ60 9-flash-1 MOTOROLA Programming Operation Complete FLASH-1 Memory 47 FLASH-1 Memory FLASH Block Protection NOTE: In performing a program or erase operation the FLASH Block Protect Register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by reserving a location in the memory for block protect information and requiring that this location be read from to enable setting of the HVEN bit. When the block protect register is read, its contents are latched by the FLASH control logic. If the address range for an erase or program operation includes a protected block, the PGM or ERASE bit is cleared which prevents the HVEN bit in the FLASH control register from being set so that no high voltage is allowed in the array. When the block protect register is erased (all 0s), the entire memory is accessible for program and erase. When bits within the register are programmed, they lock blocks of memory address ranges as shown in FLASH-1 Block Protect Register on page 49. The block protect register itself can be erased or programmed only with an external voltage VHI present on the IRQ pin. The presence of VHI on the IRQ pin also allows entry in to monitor mode out of reset. Therefore, the ability to change the block protect register is voltage dependent and can occur in either user or monitor modes. MC68HC908AZ60 MC68HC908AZ60 48 10-flash-1 FLASH-1 Memory MOTOROLA FLASH-1 Memory FLASH-1 Block Protect Register FLASH-1 Block Protect Register The block protect register is implemented as a byte within the FLASH-1 memory. Each bit, when programmed, protects a range of addresses in the FLASH-1 array. Address: $FF80 Bit 7 5 4 0 0 0 3 2 1 Bit 0 BPR3 Read: 6 0 BPR2 BPR1 BPR0 0 0 0 0 Write: Reset: 0 0 0 0 = Unimplemented Figure 2. FLASH-1 Block Protect Register (FLBPR1) BPR3 - Block Protect Register Bit 3 This bit protects the memory contents in the address range $C000 to $FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR2 - Block Protect Register Bit 2 This bit protects the memory contents in the address range $A000 to $FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR1 - Block Protect Register Bit 1 This bit protects the memory contents in the address range $9000 to $FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program MC68HC908AZ60 MC68HC908AZ60 11-flash-1 MOTOROLA FLASH-1 Memory 49 FLASH-1 Memory BPR0 - Block Protect Register Bit 0 This bit protects the memory contents in the address range $8000 to $FFFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program By programming the block protect bits, a portion of the memory will be locked so that no further erase or program operations may be performed. Programming more than one bit at a time is redundant. If both bit 1 and bit 2 are set, for instance, the address range $9000 through $FFFF is locked. If all bits are erased, then all of the memory is available for erase and program. The presence of a voltage VHI on the IRQ pin will bypass the block protection so that all of the memory, including the block protect register, is open for program and erase operations. FLASH-2 Block Protect Register NOTE: This block protect register controls the FLASH-2 array block protection. However, since it is physically located in FLASH-1 array, the FLASH-1 control register must be used to program/erase this register. The block protect register is implemented as a byte within the FLASH-1 memory. Each bit, when programmed, protects a range of addresses in the FLASH-2 array. Address: $FF81 Bit 7 5 4 0 0 0 3 2 1 Bit 0 BPR3 Read: 6 0 BPR2 BPR1 BPR0 0 0 0 0 Write: Reset: 0 0 0 0 = Unimplemented Figure 3. FLASH-2 Block Protect Register (FLBPR2) MC68HC908AZ60 MC68HC908AZ60 50 12-flash-1 FLASH-1 Memory MOTOROLA FLASH-1 Memory FLASH-2 Block Protect Register BPR3 - Block Protect Register Bit 3 This bit protects the memory contents in the address range $4000 to $7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR2 - Block Protect Register Bit 2 This bit protects the memory contents in the address range $2000 to $7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR1 - Block Protect Register Bit 1 This bit protects the memory contents in the address range $1000 to $7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program BPR0 - Block Protect Register Bit 0 This bit protects the memory contents in the address range $0450 to $7FFF. 1 = Address range protected from erase or program 0 = Address range open to erase or program By programming the block protect bits, a portion of the memory will be locked so that no further erase or program operations may be performed. Programming more than one bit at a time is redundant. If both bit 1 and bit 2 are set, for instance, the address range $1000 through $FFFF is locked. If all bits are erased, then all of the memory is available for erase and program. The presence of a voltage VHI on the IRQ pin will bypass the block protection so that all of the memory, including the block protect register, is open for program and erase operations. MC68HC908AZ60 MC68HC908AZ60 13-flash-1 MOTOROLA FLASH-1 Memory 51 FLASH-1 Memory Low-Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes. WAIT Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The WAIT instruction should not be executed while performing a program or erase operation on the FLASH. When the MCU is put into wait mode, the charge pump for the FLASH is disabled so that either a program or erase operation will not continue. If the memory is in either program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1, HVEN = 1), then it will remain in that mode during wait. Exit from wait must now be done with a reset rather than an interrupt because if exiting wait with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. STOP Mode When the MCU is put into stop mode, if the FLASH is in read mode, it will be put into low power standby. The STOP instruction should not be executed while performing a program or erase operation on the FLASH. When the MCU is put into stop mode, the charge pump for the FLASH is disabled so that either a program or erase operation will not continue. If the memory is in either program mode (PGM = 1, HVEN = 1) or erase mode (ERASE = 1, HVEN = 1), then it will remain in that mode during stop. Exit from stop must now be done with a reset rather than an interrupt because if exiting stop with an interrupt, the memory will not be in read mode and the interrupt vector cannot be read from the memory. MC68HC908AZ60 MC68HC908AZ60 52 14-flash-1 FLASH-1 Memory MOTOROLA FLASH-2 Memory ROM Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 FLASH Charge Pump Frequency Control. . . . . . . . . . . . . . . . . . . . . . 57 FLASH Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 FLASH Program/Margin Read Operation . . . . . . . . . . . . . . . . . . . . . . 59 Smart Programming Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 FLASH Block Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 WAIT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Introduction This section describes the operation of the embedded FLASH-2 memory. This memory can be read, programmed, and erased from a single external supply. The program and erase operations are enabled through the use of an internal charge pump. MC68HC908AZ60 MC68HC908AZ60 15-flash-2 MOTOROLA FLASH-2 Memory 53 FLASH-2 Memory Functional Description The FLASH-2 memory is an array of up to 29,616 bytes. An erased bit reads as a logic 0 and a programmed bit reads as a logic 1. Program and erase operations are facilitated through control bits in a memory mapped register. Details for these operations appear later in this section. Memory in the FLASH array is organized into pages within rows. There are 8 pages of memory per row with 8 bytes per page. The minimum erase block size is a single row, 64 bytes. Programming is performed on a per page basis; eight bytes at a time. The address ranges for the user memory and the control register are: · $0450­$05FF · $0E00­$7FFF · $FE11 FLASH-2 Control Register When programming the FLASH, just enough program time must be used to program a page. Too much program time can result in a program disturb condition; in which case an erased bit on the row being programmed becomes unintentionally programmed. Program disturb is avoided by using an iterative program and margin read technique known as the smart programming algorithm. The smart programming algorithm is required whenever programming the FLASH (See FLASH Program/Margin Read Operation on page 59). As well, to avoid the program disturb issue each storage page of the row should not be programmed more than once before it is erased. The 8 program cycle maximum per row aligns with the architecture's 8 pages of storage per row. The margin read step of the smart programming algorithm is used to insure programmed bits are programmed to sufficient margin for data retention over the device lifetime. Below is the row architecture for this array: · $0450-$048F (Row 0) · $0E00- 0E00-$0E3FF (Row 1) · $7FC0-$7FFF (Row 511) MC68HC908AZ60 MC68HC908AZ60 54 16-flash-2 FLASH-2 Memory MOTOROLA FLASH-2 Memory FLASH Control Register Programming tools are available from Motorola. Contact your local Motorola representative for more information. NOTE: A security feature prevents viewing of the FLASH contents.1 FLASH Control Register The FLASH-2 control register controls FLASH-2 program, erase, and margin read operations. Address: $FE11 Bit 7 6 5 4 3 2 1 Bit 0 FDIV1 FDIV0 BLK1 BLK0 HVEN MARGIN ERASE PGM 0 0 0 0 0 0 0 0 Read: Write: Reset: Figure 1. FLASH-2 Control Register (FLCR2) FDIV1 - Frequency Divide Control Bit This read/write bit together with FDIV0 selects the factor by which the charge pump clock is divided from the system clock. See FLASH Charge Pump Frequency Control on page 57. FDIV0 - Frequency Divide Control Bit This read/write bit together with FDIV1 selects the factor by which the charge pump clock is divided from the system clock. See FLASH Charge Pump Frequency Control on page 57. BLK1- Block Erase Control Bit This read/write bit together with BLK0 allows erasing of blocks of varying size. See FLASH Erase Operation on page 57 for a description of available block sizes. 1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or copying the FLASH difficult for unauthorized users. MC68HC908AZ60 MC68HC908AZ60 17-flash-2 MOTOROLA FLASH-2 Memory 55 FLASH-2 Memory BLK0 - Block Erase Control Bit This read/write bit together with BLK1 allows erasing of blocks of varying size. See FLASH Erase Operation on page 57 for a description of available block sizes. HVEN - High-Voltage Enable Bit This read/write bit enables the charge pump to drive high voltages for program and erase operations in the array. HVEN can only be set if either PGM = 1 or ERASE = 1 and the proper sequence for program/margin read or erase is followed. 1 = High voltage enabled to array and charge pump on 0 = High voltage disabled to array and charge pump off MARGIN - Margin Read Control Bit This read/write bit configures the memory for margin read operation. MARGIN cannot be set if the HVEN = 1. MARGIN will automatically return to unset (0) if asserted when HVEN = 1. 1 = Margin read operation selected 0 = Margin read operation unselected ERASE - Erase Control Bit This read/write bit configures the memory for erase operation. ERASE is interlocked with the PGM bit such that both bits cannot be set at the same time. 1 = Erase operation selected 0 = Erase operation unselected PGM - Program Control Bit This read/write bit configures the memory for program operation. PGM is interlocked with the ERASE bit such that both bits cannot be set at the same time. 1 = Program operation selected 0 = Program operation unselected MC68HC908AZ60 MC68HC908AZ60 56 18-flash-2 FLASH-2 Memory MOTOROLA FLASH-2 Memory FLASH Charge Pump Frequency Control FLASH Charge Pump Frequency Control The internal charge pump, required for program, margin read, and erase operations, is designed to operate most efficiently with a 2MHz clock. The charge pump clock is derived from the bus clock. Table 1 shows how the FDIV bits are used to select a charge pump frequency based on the bus clock frequency. Program, margin read and erase operations cannot be performed if the bus clock frequency is below 2 MHz. Table 1. Charge Pump Clock Frequency FDIV1 Pump Clock Frequency Bus Clock Frequency 0 0 Bus Frequency ÷ 1 2 MHz ± 10% 0 1 Bus Frequency ÷ 2 4 MHz ± 10% 1 0 Bus Frequency ÷ 2 4 MHz ± 10% 1 NOTE: FDIV0 1 Bus Frequency ÷ 4 8 MHz ± 10% FDIV1 and FDIV2 must be set to the same value in both flash arrays. FLASH Erase Operation Memory Characteristics on page 465 has a detailed description of the times used in this algorithm. Use the following procedure to erase a block of FLASH-2 memory: 1. Set the ERASE bit, the BLK0, BLK1, FDIV0, and FDIV1 bits in the FLASH control register. See Table 2 for block sizes. See Table 1 for FDIV settings. 2. Insure target portion of array is unprotected, read the block protect register: address $FF81. See Section FLASH Block Protection on page 62 and Section FLASH Block Protect Register on page 62 for more information. 3. Write to any FLASH address with any data within the block address range desired. 4. Set the HVEN bit. 5. Wait for a time, tERASE. MC68HC908AZ60 MC68HC908AZ60 19-flash-2 MOTOROLA FLASH-2 Memory 57 FLASH-2 Memory 6. Clear the HVEN bit. 7. Wait for a time, t KILL, for the high voltages to dissipate. 8. Clear the ERASE bit. 9. After time tHVD, the memory can be accessed in read mode again. NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. Table 2 shows the various block sizes which can be erased in one erase operation. Table 2. Erase Block Sizes BLK1 BLK0 Block Size, Addresses Cared 0 0 Full Array: 24 Kbytes 0 1 One-Half Array: 16 Kbytes (A14 ) 1 0 Eight Rows: 512 Bytes (A14­A9) 1 1 Single Row: 64 Bytes (A14­A6) In step 2 of the erase operation, the cared addresses are latched and used to determine the location of the block to be erased. For instance, with BLK0 = BLK1 = 0, writing to any Flash address in the range $0450-$05FF or $0E00- 0E00-$7FFF will enable the full-array erase. MC68HC908AZ60 MC68HC908AZ60 58 20-flash-2 FLASH-2 Memory MOTOROLA FLASH-2 Memory FLASH Program/Margin Read Operation FLASH Program/Margin Read Operation NOTE: After a total of 8 program operations have been applied to a row, the row must be erased before further programming in order to avoid program disturb. An erased byte will read $00. Programming of the FLASH memory is done on a page basis. A page consists of eight consecutive bytes starting from address $XXX0 or $XXX8. The purpose of the margin read mode is to ensure that data has been programmed with sufficient margin for long-term data retention. While performing a margin read the operation is the same as for ordinary read mode except that a built-in counter stretches the data access for an additional eight cycles to allow sensing of the lower cell current. Margin read mode imposes a more stringent read condition on the bitcell to insure the bitcell is programmed with enough margin for long-term data retention. During these eight cycles the COP counter continues to run. The user must account for these extra cycles within COP feed loops. A margin read cycle can only follow a page programming operation. To program and margin read the FLASH memory, use the following algorithm. Memory Characteristics on page 465 has a detailed description of the times used in this algorithm. 1. Set the PGM bit. This configures the memory for program operation and enables the latching of address and data for programming. 2. Read from the block protect register. 3. Write data to the eight bytes of the page being programmed. This requires eight separate write operations. 4. Set the HVEN bit. 5. Wait for time, tPROG. 6. Clear the HVEN bit. 7. Wait for time, tHVTV. 8. Set the MARGIN bit. 9. Wait for time, tVTP. 10. Clear the PGM bit. 11. Wait for time, tHVD. MC68HC908AZ60 MC68HC908AZ60 21-flash-2 MOTOROLA FLASH-2 Memory 59 FLASH-2 Memory 12. Read back data in margin read mode. This is done in eight separate read operations which are each stretched by eight cycles. 13. Clear the MARGIN bit. NOTE: While these operations must be performed in the order shown, other unrelated operations may occur between the steps. This program/margin read sequence is repeated throughout the memory until all data is programmed. The Smart Programming Algorithm is always required when programming any part of the array. This algorithm insures the minimum possible program time and avoids the deleterious program disturb effect. (See FLASH Erase Operation on page 57). NOTE: In order to ensure proper FLASH read operation after completion of the smart programming algorithm, a series of 500 dummy FLASH reads must be performed of any address before accurate data is read from the FLASH. MC68HC908AZ60 MC68HC908AZ60 60 22-flash-2 FLASH-2 Memory MOTOROLA FLASH-2 Memory FLASH Program/Margin Read Operation Smart Programming Algorithm Program FLASH 2TS Page Program/Margin Read Procedure Note: This algorithm is mandatory for programming the FLASH 2TS. Set Interrupt Mask: SEI Instruction Note: This page program algorithm assumes the page/s to be programmed are initially erased. Initialize Attempt Counter to Zero Set PGM Bit and FDIV bits Read Flash Block Protect Register Write Data to Selected Page Set HVEN Bit Wait tSTEP Clear HVEN Bit Wait tHVTV Set MARGIN Bit Wait tVTP Clear PGM Bit Wait tHVD Margin Read Page of Data Clear MARGIN Bit Increment Attempt Counter N Margin Read Data Equal To Write Data? Y Clear MARGIN Bit N Attempt Count Equal To flsPULSES? Clear Interrupt Mask: CLI Instr. Y Programming Operation Failed MC68HC908AZ60 MC68HC908AZ60 23-flash-2 MOTOROLA Programming Operation Complete FLASH-2 Memory 61 FLASH-2 Memory FLASH Block Protection NOTE: In performing a program or erase operation the FLASH Block Protect Register must be read after setting the PGM or ERASE bit and before asserting the HVEN bit. Due to the ability of the on-board charge pump to erase and program the FLASH memory in the target application, provision is made for protecting blocks of memory from unintentional erase or program operations due to system malfunction. This protection is done by reserving a location in the memory for block protect information and requiring that this location be read before setting the HVEN bit. When the block protect register is read, its contents are latched by the FLASH control logic. If the address range for an erase or program operation includes a protected block, the PGM or ERASE bit is cleared which prevents the HVEN bit in the FLASH control register from being set so that no high voltage is allowed in the array. When the block protect register is erased (all 0s), the entire memory is accessible for program and erase. When bits within the register are programmed, they lock blocks of memory address ranges as shown in FLASH Block Protect Register on page 62. The block protect register itself can be erased or programmed only with an external voltage VHI present on the IRQ pin. The presence of VHI on the IRQ pin also allows entry in to monitor mode out of reset. Therefore, the ability to change the block protect register is voltage dependent and can occur in either user or monitor modes. FLASH Block Protect Register The block protect register for FLASH-2 is physically implemented as a byte within the FLASH-1 memory. Please refer to the FLASH-1 memory section, FLASH-2 Block Protect Register on page 50 for definition of this register. Each bit, when programmed, protects a range of addresses in the FLASH-2 array. MC68HC908AZ60 MC68HC908AZ60 62 24-flash-2 FLASH-2 Memory MOTOROLA FLASH-2 Memory Low-Power Modes Low-Power Modes The WAIT and STOP instructions put the MCU in low power consumption standby modes. WAIT Mode Putting the MCU into wait mode while the FLASH is in read mode does not affect the operation of the FLASH memory directly, but there will not be any memory activity since the CPU is inactive. The WAIT instruction should not be executed while performing a prog