MC68HC11KW1/D MC68HC11KW1 F23FRC MMDS11 SPGMR11 M68HC11 RS232 ADDR15 ADDR14 - Datasheet Archive

 

MC68HC11KW1 HC11 TECHNICAL DATA MC68HC11KW1 TECHNICAL DATA !MOTOROLA !MOTOROLA MC68HC11KW1 High-density complementary metal oxide

 

MC68HC11KW1/D MC68HC11KW1/D MC68HC11KW1 MC68HC11KW1 HC11 TECHNICAL DATA MC68HC11KW1 MC68HC11KW1 TECHNICAL DATA !MOTOROLA !MOTOROLA MC68HC11KW1 MC68HC11KW1 High-density complementary metal oxide semiconductor (HCMOS) microcontroller unit All Trade Marks recognized. This document contains information on new products. Specifications and information herein are subject to change without notice. All products are sold on Motorola's Terms & Conditions of Supply. In ordering a product covered by this document the Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part of a contract (with the exception of the contents of this Notice). A copy of Motorola's Terms & Conditions of Supply is available on request. Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and !are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office. This document supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn. © MOTOROLA LTD., 1997 TPG 1 Conventions Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low signal, eg: RESET. Because the bits in any one register are not necessarily linked by a common function, the description of a register may appear in several sections referring to different aspects of device operation. A full description of a bit is given only in a section in which it has relevance. Elsewhere, it appears shaded in the register diagram and is only briefly described. When the state of a bit on reset is described as `x', this means that its state depends on factors such as the operating mode selected. A `u' indicates that the bit's state on reset is undefined. TPG 2 TABLE OF CONTENTS Paragraph Number TITLE Page Number 1 INTRODUCTION 1.1 1.2 Features.1-1 Mask option .1-2 2 PIN DESCRIPTIONS 2.1 RESET.2-2 2.2 Crystal driver and external clock input (XTAL, EXTAL).2-3 2.3 VDD and VSS .2-4 2.4 E clock output (E) .2-4 2.5 XOUT.2-4 2.6 Interrupt request (IRQ) .2-4 2.7 Nonmaskable interrupt (XIRQ) .2-5 2.8 MODA and MODB (MODA/LIR and MODB/VSTBY) .2-5 2.9 VRH and VRL .2-6 2.10 R/W.2-6 2.11 Port signals .2-6 2.11.1 Port A .2-6 2.11.2 Port B .2-8 2.11.3 Port C .2-8 2.11.4 Port D .2-8 2.11.5 Port E .2-9 2.11.6 Port F .2-9 2.11.7 Port G.2-9 2.11.8 Port H .2-10 2.11.9 Port J.2-10 2.11.10 Port K .2-10 TPG MC68HC11KW1 MC68HC11KW1 TABLE OF CONTENTS MOTOROLA i 3 Paragraph Number TITLE Page Number 3 CENTRAL PROCESSING UNIT 3.1 Registers .3-1 3.1.1 Accumulators A, B and D.3-2 3.1.2 Index register X (IX) .3-2 3.1.3 Index register Y (IY) .3-2 3.1.4 Stack pointer (SP).3-2 3.1.5 Program counter (PC).3-4 3.1.6 Condition code register (CCR).3-4 3.1.6.1 Carry/borrow (C) .3-5 3.1.6.2 Overflow (V) .3-5 3.1.6.3 Zero (Z) .3-5 3.1.6.4 Negative (N) .3-5 3.1.6.5 Interrupt mask (I).3-5 3.1.6.6 Half carry (H).3-6 3.1.6.7 X interrupt mask (X) .3-6 3.1.6.8 Stop disable (S).3-6 3.2 Data types .3-6 3.3 Opcodes and operands .3-7 3.4 Addressing modes.3-7 3.5 Immediate (IMM) .3-7 3.5.1 Direct (DIR).3-7 3.5.2 Extended (EXT) .3-8 3.5.3 Indexed (IND, X; IND, Y).3-8 3.5.4 Inherent (INH) .3-8 3.5.5 Relative (REL).3-8 3.6 Instruction set .3-8 4 OPERATING MODES AND ON-CHIP MEMORY 4.1 Operating modes .4-1 4.1.1 Single chip operating mode .4-1 4.1.2 Expanded operating mode.4-1 4.1.3 Special test mode .4-2 4.1.4 Special bootstrap mode .4-2 4.2 On-chip memory.4-3 4.2.1 Mapping allocations .4-3 4.2.1.1 RAM .4-4 4.2.1.2 Bootloader ROM .4-4 4.2.2 Registers.4-4 4.3 System initialization .4-10 4.3.1 Mode selection.4-10 4.3.1.1 HPRIO - Highest priority I-bit interrupt & misc. register .4-11 TPG MOTOROLA ii TABLE OF CONTENTS MC68HC11KW1 MC68HC11KW1 4 Paragraph Number TITLE Page Number 4.3.2 Initialization .4-12 4.3.2.1 CONFIG - System configuration register .4-12 4.3.2.2 INIT - RAM and I/O mapping register .4-13 4.3.2.3 INIT2 - EEPROM mapping register.4-15 4.3.2.4 OPTION - System configuration options register 1.4-15 4.3.2.5 OPT2 - System configuration options register 2 .4-17 4.3.2.6 BPROT - Block protect register.4-18 4.3.2.7 TMSK2 - Timer interrupt mask register 2 .4-20 4.3.2.8 TCTL4 and TCTL6 - Timer 2 and 3 control registers .4-21 4.4 Memory expansion .4-22 4.4.1 Memory expansion logic .4-22 4.4.2 Extended addressing .4-23 4.4.3 Memory expansion examples .4-24 4.4.4 MMSIZ - Memory mapping window size register.4-29 4.4.5 MMWBR ­ Memory mapping window base register .4-30 4.4.6 MM1CR, MM2CR ­ Memory mapping window 1 and 2 control registers .4-31 4.4.7 PGAR - Port G assignment register .4-32 4.5 Chip selects .4-32 4.5.1 Chip select priorities.4-33 4.5.2 Program chip select .4-33 4.5.3 I/O chip select .4-33 4.5.4 CSCTL - Chip select control register .4-34 4.5.5 General-purpose chip selects .4-35 4.5.5.1 GPCS1A - General-purpose chip select 1 address register .4-35 4.5.5.2 GPCS1C - General-purpose chip select 1 control register .4-36 4.5.5.3 GPCS2A - General-purpose chip select 2 address register .4-37 4.5.5.4 GPCS2C - General-purpose chip select 2 control register .4-37 4.5.6 One chip select driving another .4-38 4.5.7 Clock stretching .4-39 4.5.7.1 CSCSTR - Chip select clock stretch register .4-39 4.6 EEPROM and CONFIG register .4-41 4.6.1 EEPROM .4-41 4.6.1.1 PPROG - EEPROM programming control register .4-41 4.6.1.2 EEPROM bulk erase .4-43 4.6.1.3 EEPROM row erase .4-43 4.6.1.4 EEPROM byte erase .4-44 4.6.2 CONFIG register programming .4-44 4.6.3 RAM and EEPROM security .4-45 5 RESETS AND INTERRUPTS 5.1 Resets .5-1 5.1.1 Power-on reset .5-1 5.1.2 External reset (RESET) .5-2 TPG MC68HC11KW1 MC68HC11KW1 TABLE OF CONTENTS MOTOROLA iii 5 Paragraph Number TITLE Page Number 5.1.3 COP reset .5-2 5.1.3.1 COPRST - Arm/reset COP timer circuitry register.5-3 5.1.4 Clock monitor reset .5-3 5.1.5 OPTION - System configuration options register 1 .5-4 5.1.6 CONFIG - Configuration control register .5-5 5.2 Effects of reset.5-6 5.2.1 Central processing unit .5-7 5.2.2 Memory map.5-7 5.2.3 Parallel I/O .5-7 5.2.4 Timer 1.5-7 5.2.5 Timers 2 and 3.5-8 5.2.6 Real-time interrupt (RTI) .5-8 5.2.7 Pulse accumulator .5-8 5.2.8 Computer operating properly (COP).5-8 5.2.9 Serial communications interface (SCI).5-8 5.2.10 Serial peripheral interface (SPI).5-9 5.2.11 Analog-to-digital converter.5-9 5.2.12 System.5-9 5.3 Reset and interrupt priority .5-9 5.3.1 HPRIO - Highest priority I-bit interrupt and misc. register .5-10 5.4 Interrupts .5-13 5.4.1 Interrupt recognition and register stacking.5-13 5.4.2 Nonmaskable interrupt request (XIRQ) .5-14 5.4.3 Illegal opcode trap .5-14 5.4.4 Software interrupt .5-14 5.4.5 Maskable interrupts .5-15 5.4.6 Reset and interrupt processing.5-15 5.5 Low power operation .5-15 5.5.1 WAIT .5-15 5.5.2 STOP .5-16 6 PARALLEL INPUT/OUTPUT 6.1 6.1.1 6.1.2 6.2 6.2.1 6.2.2 6.3 6.3.1 6.3.2 6.4 6.4.1 Port A.6-2 PORTA - Port A data register .6-2 DDRA - Data direction register for port A .6-2 Port B.6-3 PORTB - Port B data register .6-3 DDRB - Data direction register for port B .6-3 Port C .6-4 PORTC - Port C data register.6-4 DDRC - Data direction register for port C.6-4 Port D .6-5 PORTD - Port D data register.6-5 TPG MOTOROLA iv TABLE OF CONTENTS MC68HC11KW1 MC68HC11KW1 6 Paragraph Number 6.4.2 6.5 6.5.1 6.6 6.6.1 6.6.2 6.7 6.7.1 6.7.2 6.7.3 6.8 6.8.1 6.8.2 6.9 6.9.1 6.9.2 6.10 6.10.1 6.10.2 6.11 6.11.1 6.12 6.12.1 6.12.2 TITLE Page Number DDRD - Data direction register for port D.6-5 Port E.6-6 PORTE - Port E data register .6-6 Port F .6-7 PORTF - Port F data register.6-7 DDRF - Data direction register for port F.6-7 Port G .6-8 PORTG - Port G data register .6-8 DDRG - Data direction register for port G .6-9 PGAR - Port G assignment register .6-9 Port H.6-10 PORTH - Port H data register.6-10 DDRH - Data direction register for port H.6-10 Port J .6-11 PORTJ - Port J data register .6-11 DDRJ - Data direction register for port J .6-11 Port K.6-12 PORTK - Port K data register .6-12 DDRK - Data direction register for port K .6-12 Internal pull-up resistors .6-13 PPAR - Port pull-up assignment register .6-13 System configuration .6-14 OPT2 - System configuration options register 2.6-14 CONFIG - System configuration register .6-15 7 SERIAL COMMUNICATIONS INTERFACE 7.1 7.2 7.3 7.4 7.4.1 7.4.2 7.5 7.6 7.6.1 7.6.2 7.6.3 7.6.4 7.6.5 7.6.6 7.7 7.7.1 Data format .7-2 Transmit operation .7-2 Receive operation.7-2 Wake-up feature .7-4 Idle-line wake-up .7-4 Address-mark wake-up .7-4 SCI error detection .7-5 SCI registers .7-5 SCBDH, SCBDL - SCI baud rate control registers .7-6 SCCR1 - SCI control register 1 .7-7 SCCR2 - SCI control register 2 .7-9 SCSR1 - SCI status register 1.7-10 SCSR2 - SCI status register 2.7-11 SCDRH, SCDRL - SCI data high/low registers .7-12 Status flags and interrupts.7-12 Receiver flags .7-13 TPG MC68HC11KW1 MC68HC11KW1 TABLE OF CONTENTS MOTOROLA v 7 Paragraph Number TITLE Page Number 8 SERIAL PERIPHERAL INTERFACE 8.1 8.2 8.2.1 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.4 8.5 8.5.1 8.5.2 8.5.3 8.5.4 Functional description .8-1 SPI transfer formats.8-2 Clock phase and polarity controls.8-3 SPI signals .8-3 Master in slave out.8-4 Master out slave in.8-4 Serial clock .8-4 Slave select.8-4 SPI system errors .8-5 SPI registers .8-5 SPCR - SPI control register.8-6 SPSR - SPI status register .8-8 SPDR - SPI data register .8-9 OPT2 - System configuration options register 2.8-9 9 TIMING SYSTEM 9.1 Timer 1 .9-1 9.1.1 Timer 1 structure.9-3 9.1.2 Input capture.9-4 9.1.2.1 TCTL2 - Timer control register 2.9-6 9.1.2.2 TIC1­TIC3 - Timer input capture registers .9-7 9.1.2.3 TI4/O5 - Timer input capture 4/output compare 5 register.9-7 9.1.3 Output compare .9-8 9.1.3.1 TOC1­TOC4 - Timer output compare registers.9-9 9.1.3.2 CFORC - Timer compare force register .9-9 9.1.3.3 OC1M - Output compare 1 mask register.9-10 9.1.3.4 OC1D - Output compare 1 data register.9-10 9.1.3.5 TCNT - Timer counter register .9-11 9.1.3.6 TCTL1 - Timer control register 1.9-11 9.1.3.7 TMSK1 - Timer interrupt mask register 1.9-12 9.1.3.8 TFLG1 - Timer interrupt flag register 1 .9-13 9.1.3.9 TMSK2 - Timer interrupt mask register 2.9-14 9.1.3.10 TFLG2 - Timer interrupt flag register 2 .9-15 9.2 Timer 2 .9-15 9.2.1 Output compare .9-18 9.2.2 Input capture.9-18 9.2.3 F23FRC F23FRC - Compare force register for Timers 2 and 3. .9-18 9.2.4 T2C4 - Timer 2 channel 4 register.9-19 9.2.5 T2OC1­T2OC3 - Timer 2 output compare registers .9-19 9.2.6 TCNT2 - Timer 2 counter register.9-20 TPG MOTOROLA vi TABLE OF CONTENTS MC68HC11KW1 MC68HC11KW1 8 Paragraph Number TITLE Page Number 9.2.7 TCTL3 - Timer control register 3 (Timer 2) .9-20 9.2.8 TCTL4 - Timer control register 4 (Timer 2) .9-21 9.2.9 T2MSK - Timer 2 interrupt mask register.9-22 9.2.10 T2FLG - Timer 2 interrupt flag register .9-23 9.3 Timer 3 .9-24 9.3.1 T3C4 - Timer 3 channel 4 register .9-24 9.3.2 T3OC1­T3OC3 - Timer 3 output compare registers .9-26 9.3.3 TCNT3 - Timer 3 counter register.9-26 9.3.4 TCTL5 - Timer control register 5 (Timer 3) .9-27 9.3.5 TCTL6 - Timer control register 6 (Timer 3) .9-27 9.3.6 T3MSK - Timer 3 interrupt mask register.9-29 9.3.7 T3FLG - Timer 3 interrupt flag register .9-30 9.4 Real-time interrupt .9-31 9.4.1 TMSK2 - Timer interrupt mask register 2.9-31 9.4.2 TFLG2 - Timer interrupt flag register 2 .9-32 9.4.3 PACTL - Pulse accumulator control register .9-33 9.5 Computer operating properly watchdog function .9-33 9.6 Pulse accumulator .9-33 9.6.1 PACTL - Pulse accumulator control register .9-35 9.6.2 PACNT - Pulse accumulator count register .9-36 9.6.3 Pulse accumulator status and interrupt bits .9-36 9.6.3.1 TMSK2 - Timer interrupt mask 2 register .9-36 9.6.3.2 TFLG2 - Timer interrupt flag 2 register .9-36 9.7 Pulse-width modulation (PWM) timer .9-37 9.7.1 PWM timer block diagram .9-38 9.7.2 PWCLK - PWM clock prescaler and 16-bit select register.9-38 9.7.2.1 16-bit PWM function .9-38 9.7.2.2 Clock prescaler selection .9-40 9.7.3 PWPOL - PWM timer polarity & clock source select register .9-41 9.7.4 PWSCAL - PWM timer prescaler register.9-41 9.7.5 PWEN - PWM timer enable register .9-42 9.7.6 PWCNT1­4 - PWM timer counter registers 1 to 4.9-43 9.7.7 PWPER1­4 - PWM timer period registers 1 to 4.9-43 9.7.8 PWDTY1­4 - PWM timer duty cycle registers 1 to 4.9-44 9.7.9 Boundary cases .9-44 10 ANALOG-TO-DIGITAL CONVERTER 10.1 Conversion process .10-2 10.2 Channel assignments .10-2 10.3 Single channel operation .10-3 10.3.1 4-conversion, single scan.10-4 10.3.2 4-conversion, continuous scan.10-4 10.3.3 8-conversion, single scan.10-4 TPG MC68HC11KW1 MC68HC11KW1 TABLE OF CONTENTS MOTOROLA vii 9 Paragraph Number 10.3.4 10.4 10.4.1 10.4.2 10.4.3 10.4.4 10.5 10.6 10.7 10.7.1 10.7.2 10.7.3 TITLE Page Number 8-conversion, continuous scan .10-4 Multiple channel operation.10-4 4-channel single scan .10-5 4-channel continuous scan .10-5 8-channel single scan .10-5 8-channel continuous scan .10-5 Power-up and clock select.10-5 Operation in STOP and WAIT modes.10-6 Registers .10-6 ADCTL - A/D control and status register .10-6 ADFRQ - A/D converter frequency select register .10-7 ADR1 - ADR8 A/D result registers .10-8 A ELECTRICAL SPECIFICATIONS A.1 A.2 A.3 A.4 A.5 A.5.1 A.5.2 A.5.3 A.5.4 A.6 Maximum ratings . A-1 Thermal characteristics and power considerations . A-2 Test methods . A-3 DC electrical characteristics . A-4 Control timing . A-5 Peripheral port timing. A-8 Analog-to-digital converter characteristics. A-10 Serial peripheral interface timing . A-11 Non-multiplexed expansion bus timing . A-14 EEPROM characteristics . A-15 B MECHANICAL DATA B.1 Packaging . B-1 C DEVELOPMENT SYSTEMS C.1 C.2 C.3 EVS - Evaluation system. C-1 MMDS11 MMDS11 - Motorola modular development system . C-2 SPGMR11 SPGMR11 - Serial peripheral system . C-2 TPG MOTOROLA viii TABLE OF CONTENTS MC68HC11KW1 MC68HC11KW1 10 LIST OF FIGURES Figure Number 1-1 2-1 2-2 2-3 2-4 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 5-1 5-2 5-3 5-4 5-5 5-6 7-1 7-2 7-3 8-1 8-2 9-1 9-2 9-3 9-4 9-5 9-6 9-7 A-1 A-2 TITLE Page Number MC68HC11KW1 MC68HC11KW1 block diagram.1-3 MC68HC11KW1 MC68HC11KW1 100-pin TQFP.2-1 External reset circuitry.2-2 Oscillator connections .2-3 RAM stand-by connections.2-5 Programming model .3-1 Stacking operations .3-3 MC68HC11KW1 MC68HC11KW1 memory map.4-3 RAM and register overlap.4-14 Memory map example of memory expansion.4-25 Schematic example of memory expansion .4-26 Memory map example of memory expansion.4-27 Schematic example of memory expansion .4-28 Processing flow out of reset (1 of 2) .5-17 Processing flow out of reset (2 of 2) .5-18 Interrupt priority resolution (1 of 3) .5-19 Interrupt priority resolution (2 of 3) .5-20 Interrupt priority resolution (3 of 3) .5-21 Interrupt source resolution within the SCI subsystem .5-22 SCI baud rate generator circuit diagram.7-1 SCI block diagram .7-3 Interrupt source resolution within SCI.7-14 SPI block diagram.8-2 SPI transfer format.8-3 Timer clock divider chains .9-2 Timer 1 capture/compare block diagram .9-5 Timer 2 capture/compare block diagram .9-17 Timer 3 capture/compare block diagram .9-25 Pulse accumulator block diagram.9-34 PWM timer block diagram.9-39 PWM duty cycle.9-44 Test methods . A-3 Timer inputs. A-5 TPG MC68HC11KW1 MC68HC11KW1 LIST OF FIGURES MOTOROLA xi 11 Figure Number A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 B-1 B-2 TITLE Page Number Reset timing .A-6 Interrupt timing .A-6 STOP recovery timing .A-7 WAIT recovery timing .A-7 Port read timing diagram .A-8 Port G control timing.A-8 Port write timing diagram.A-9 SPI master timing (CPHA = 0) .A-12 SPI master timing (CPHA = 1) .A-12 SPI slave timing (CPHA = 0) .A-13 SPI slave timing (CPHA = 1) .A-13 Expansion bus timing .A-15 100-pin TQFP .B-1 100-pin TQFP mechanical dimensions.B-2 TPG MOTOROLA xii LIST OF FIGURES MC68HC11KW1 MC68HC11KW1 12 LIST OF TABLES Table Number 2-1 3-1 3-2 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 5-1 5-2 5-3 5-4 5-5 6-1 7-1 8-1 9-1 9-2 9-3 TITLE Page Number Port signal functions .2-7 Reset vector comparison.3-4 Instruction set .3-9 Example bootloader baud rates.4-2 Register and control bit assignments .4-5 Registers with limited write access.4-10 Hardware mode select summary.4-11 RAM and register remapping.4-14 EEPROM remapping .4-15 XCLK frequencies.4-18 EEPROM block protect.4-19 CPU address and address expansion signals.4-24 Window size select .4-29 Memory expansion window base address.4-30 Chip select priorities .4-33 Program chip select size .4-34 General purpose chip select priority.4-35 General-purpose chip select 1 size control .4-37 General-purpose chip select 2 size control .4-38 One chip select driving another .4-39 Chip select control parameter summary.4-40 Erase mode selection .4-42 COP timer rate select .5-2 Reset cause, reset vector and operating mode .5-6 Highest priority interrupt selection .5-11 Interrupt and reset vector assignments .5-12 Stacking order on entry to interrupts .5-13 Port configuration .6-1 Example SCI baud rate control values .7-7 SPI clock rates.8-7 Timer 1 resolution and capacity.9-3 RTI periodic rates .9-31 Pulse accumulator timing .9-34 TPG MC68HC11KW1 MC68HC11KW1 LIST OF TABLES MOTOROLA xiii 13 Table Number 9-4 10-1 C-1 TITLE Page Number Clock A and clock B prescalers . 9-40 Channel assignments. 10-3 M68HC11 M68HC11 development tools . C-1 TPG MOTOROLA xiv LIST OF TABLES MC68HC11KW1 MC68HC11KW1 14 1 1 INTRODUCTION The MC68HC11KW1 MC68HC11KW1 8-bit microcontroller is a member of the M68HC11 M68HC11 family of HCMOS microcontrollers. It has 640 bytes of EEPROM and 768 bytes of RAM. Making use of a 100-pin TQFP package, a non-multiplexed expanded bus is a feature of this device. The main timer system includes three input captures, four output compares and a software selectable input capture or output compare. There are two additional 16-bit timers, each with three output compares and one software selectable input capture or output compare. Other major features of this device are: a 10-channel, 10-bit resolution A/D converter, four PWM timer channels, an SPI (serial peripheral interface) and an enhanced SCI (serial communications interface). In common with other family members, the MC68HC11KW1 MC68HC11KW1 also includes an 8-bit pulse accumulator circuit, a real time interrupt facility, and a computer operating properly watchdog system. This device is intended for use in expanded memory applications. 1.1 Features · Low power, high performance M68HC11 M68HC11 CPU core with 4MHz internal bus frequency · 768 bytes of RAM · 640 bytes of byte-erasable EEPROM, with on-chip charge pump · 448 bytes of boot ROM · Up to 70 general purpose I/O lines, plus up to 10 input-only lines · Non-multiplexed address and data buses, permitting direct access to the full 64K byte address map · Memory expansion unit, with six address extension lines, allowing up to (for example) sixteen 32K byte banks of external memory to be addressed in either of two bank windows · Four external chip selects · 16-bit timer with 3/4 input captures and 5/4 output compares; pulse accumulator and COP watchdog timer · Real-time interrupt circuit TPG MC68HC11KW1 MC68HC11KW1 INTRODUCTION MOTOROLA 1-1 15 1 · Two additional 16-bit timers, each with 3 output compares and one input capture or output compare (may be externally clocked, if required, for external event counter operation) · SCI subsystem (NRZ type for compatibility with standard RS232 RS232 systems) with parity and a modulus prescaler · SPI subsystem, with software selectable MSB/LSB first option and increased baud rate selection range · 10-channel, 10-bit analog-to-digital converter · Four 8-bit PWM timer channels · Available in 100-pin TQFP package 1.2 Mask option There is a single mask option on the MC68HC11KW1 MC68HC11KW1, which is programmed during manufacture and must be specified on the order form: · Security option (available/unavailable). See Section 4.6.3 TPG MOTOROLA 1-2 INTRODUCTION MC68HC11KW1 MC68HC11KW1 16 Periodic interrupt COP watchdog OC4/IC1 OC3 OC2 OC1 ECIN Timer 3 SS SCK MOSI MISO TXD RXD SPI+ SCI+ 640 bytes EEPROM 768 bytes RAM AN0 XIRQ IRQ RESET LIR/MODA VSTBY/MODB Interrupts & mode select XTAL EXTAL R/W E XOUT Oscillator VDD VSS AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 10-channel, 10-bit A/D converter Chip selects 3 PWM 3 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 AN1 XA18 XA17 XA16 XA15 XA14 XA13 Memory expansion M68HC11 M68HC11 CPU Port A Timer 1 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Port E Timer 2 OC1/PAI OC1/OC2 OC1/OC3 OC1/OC4 IC4/OC1/OC5 IC1 IC2 IC3 CSPROG CSGP2 CSGP1 CSIO PW4 PW3 PW2 PW1 VRH VRL VDDAD PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 VSSAD Port G Port J Pulse accumulator PG7 PG6 PG5 PG4 PG3 PG2 PG1 PG0 Port H PK7 PK6 PK5 PK4 PK3 PK2 PK1 PK0 OC4/IC1 OC3 OC2 OC1 ECIN Port K PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 Port D 1 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 ADDR15 ADDR15 ADDR14 ADDR14 ADDR13 ADDR13 ADDR12 ADDR12 ADDR11 ADDR11 ADDR0 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Port B Port F Port C PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Non-multiplexed address and data buses Figure 1-1 MC68HC11KW1 MC68HC11KW1 block diagram TPG MC68HC11KW1 MC68HC11KW1 INTRODUCTION MOTOROLA 1-3 17 1 THIS PAGE LEFT BLANK INTENTIONALLY TPG MOTOROLA 1-4 INTRODUCTION MC68HC11KW1 MC68HC11KW1 18 2 2 PIN DESCRIPTIONS 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PK5/OC2 PK6/OC3 PK7/C4 PB0/ADDR8 PB1/ADDR9 PB2/ADDR10 PB2/ADDR10 PB3/ADDR11 PB3/ADDR11 PB4/ADDR12 PB4/ADDR12 PB5/ADDR13 PB5/ADDR13 PB6/ADDR14 PB6/ADDR14 PB7/ADDR15 PB7/ADDR15 VDD VSS PA0/IC3/OC1 PA1/IC2/OC1 PA2/IC1/OC1 PA3/IC4/OC5/OC1 PA4/OC4/OC1 PA5/OC3/OC1 PA6/OC2/OC1 PA7/PAI/OC1 PD7 PD6 PD5/SS PD4/SCK The MC68HC11KW1 MC68HC11KW1 is available packaged in a 100-pin thin quad flat pack (TQFP), as shown in Figure 2-1. Most pins on this MCU serve two or more functions, as described in the following paragraphs. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PD3/MOSI PD2/MISO PD1/TXD PD0/RXD MODA/LIR MODB/VSTBY RESET XTAL EXTAL XOUT E VDD VSS PC7/DATA7 PC6/DATA6 PC5/DATA5 PC4/DATA4 PC3/DATA3 PC2/DATA2 PC1/DATA1 PC0/DATA0 IRQ PF0/ADDR0 PF1/ADDR1 PF2/ADDR2 VRH VRL VDDAD PE7/AN9 PE6/AN8 PE5/AN7 PE4/AN6 PE3/AN5 PE2/AN4 PE1/AN3 PE0/AN2 VSSAD PJ0 PJ1 PJ2 PJ3/ECIN PJ4/OC1 PJ5/OC2 PJ6/OC3 PJ7/C4 PF7/ADDR7 PF6/ADDR6 PF5/ADDR5 PF4/ADDR4 PF3/ADDR3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PK4/OC1 PK3/ECIN PK2 PK1 PK0 PH0/PWM1 PH1/PWM2 PH2/PWM3 PH3/PWM4 PH4/CSIO PH5/CSGP1 PH6/CSGP2 PH7/CSPROG R/W XIRQ VDD VSS PG0/XA13 PG0/XA13 PG1/XA14 PG1/XA14 PG2/XA15 PG2/XA15 PG3/XA16 PG3/XA16 PG4/XA17 PG4/XA17 PG5/XA18 PG5/XA18 PG6/AN0 PG7/AN1 Figure 2-1 MC68HC11KW1 MC68HC11KW1 100-pin TQFP TPG MC68HC11KW1 MC68HC11KW1 PIN DESCRIPTIONS MOTOROLA 2-1 19 2.1 2 RESET An active-low, bidirectional control signal, RESET acts as an input to initialize the MCU to a known start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in either the clock monitor or the COP watchdog circuit. The CPU distinguishes between internal and external reset conditions by sensing whether the reset pin rises to a logic one in less than four E clock cycles after an internal reset has been released. It is therefore not advisable to connect an external resistor-capacitor (RC) power-up delay circuit to the reset pin of M68HC11 M68HC11 devices because the circuit charge time constant can cause the device to misinterpret the type of reset that occurred. Refer to Section 5 for further information. Figure 2-2 illustrates a typical reset circuit that includes an external switch together with a low voltage inhibit circuit, to prevent power transitions, or RAM or EEPROM corruption. VDD VDD 2 4.7 k IN RESET VDD Manual reset 1 MC34064 MC34064 GND 3 To M68HC11 M68HC11 RESET 4.7 k 4.7 k 1µF 2 IN RESET 1 MC34164 MC34164 GND 3 Figure 2-2 External reset circuitry TPG MOTOROLA 2-2 PIN DESCRIPTIONS MC68HC11KW1 MC68HC11KW1 20 2.2 Crystal driver and external clock input (XTAL, EXTAL) These two pins provide the interface for either a crystal or a CMOS compatible clock to control the internal clock generator circuitry. The frequency applied to these pins must be four times higher than the desired E clock rate. Refer to Figure 2-3. 2 The XTAL pin is normally left unconnected when an external CMOS compatible clock input is connected to the EXTAL pin. The XTAL output is normally intended to drive only a crystal. The XTAL output can be buffered with a high-impedance buffer, or it can be used to drive the EXTAL input of another M68HC11 M68HC11 family device. In all cases, use caution when designing circuitry associated with the oscillator pins. 25 pF EXTAL (a) Common crystal connections M68HC11 M68HC11 4¥E crystal 10 M XTAL 25 pF External oscillator EXTAL (b) External oscillator connections M68HC11 M68HC11 XTAL NC 25 pF 220 EXTAL EXTAL M68HC11 M68HC11 10 M 4¥E crystal M68HC11 M68HC11 XTAL NC 25 pF XTAL (c) One crystal driving two MCUs Note: capacitor values include all stray capacitance. Figure 2-3 Oscillator connections TPG MC68HC11KW1 MC68HC11KW1 PIN DESCRIPTIONS MOTOROLA 2-3 21 2.3 2 VDD and VSS Power is supplied to the microcontroller via these pins. VDD is the positive supply and VSS is ground. The MCU operates from a 5V (nominal) power supply. It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins. These short rise and fall times place very high short-duration current demands on the power supply. To prevent noise problems, special care must be taken to provide good power supply bypassing at the MCU. Bypass capacitors should have good high-frequency characteristics and be as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded. The MC68HC11KW1 MC68HC11KW1 has four VDD pins and four VSS pins. One pair of these pins is reserved for supplying power to the analog-to-digital converter (VDDAD, VSSAD); the remaining pins are used for the internal logic, and to supply power to the port logic on either half of the chip. 2.4 E clock output (E) E is the output connection for the internally generated E clock. The signal from E is used as a timing reference. The frequency of the E clock output is one quarter that of the input frequency at the XTAL and EXTAL pins. When E clock output is low, an internal process is taking place; when it is high, data is being accessed. All clocks, including the E clock, are halted when the MCU is in STOP mode. The E clock output can be turned off in single-chip modes to reduce the effects of RFI (see Section 4.3.2.5). 2.5 XOUT The XOUT pin outputs the buffered CLKX signal, if enabled by the XCLK bit in the CONFIG register. The frequency of CLKX can be selected using two bits in the OPT2 register (XDV1 and XDV2). On reset, CLKX has the same frequency as EXTAL (4E). See Section 4. Note that the phase relationship between CLKX and EXTAL cannot be predicted. 2.6 Interrupt request (IRQ) The IRQ input provides a means of applying asynchronous interrupt requests to the MCU. Either falling-edge-sensitive triggering or level-sensitive triggering is program selectable (OPTION register). IRQ is always configured to level-sensitive-triggering at reset. Note: Connect an external pull-up resistor, typically 4.7 k, to VDD when IRQ is used in a level sensitive wired-OR configuration. See also Section 2.7. TPG MOTOROLA 2-4 PIN DESCRIPTIONS MC68HC11KW1 MC68HC11KW1 22 2.7 Nonmaskable interrupt (XIRQ) The XIRQ input provides a means of requesting a nonmaskable interrupt after reset initialization. During reset, the X bit in the condition code register (CCR) is set and any interrupt is masked until MCU software enables it. XIRQ is often used as a power loss detect interrupt. 2 Whenever XIRQ or IRQ is used with multiple interrupt sources (IRQ must be configured for level-sensitive operation if there is more than one source of interrupt), each source must drive the interrupt input with an open-drain type of driver to avoid contention between outputs. There should be a single pull-up resistor near the MCU interrupt input pin (typically 4.7 k). There must also be an interlock mechanism at each interrupt source so that the source holds the interrupt line low until the MCU recognizes and acknowledges the interrupt request. If one or more interrupt source is still pending after the MCU services a request, the interrupt line will still be held low and the MCU will be interrupted again as soon as the interrupt mask bit in the MCU is cleared (normally upon return from an interrupt). Refer to Section 5. 2.8 MODA and MODB (MODA/LIR and MODB/VSTBY) During reset, MODA and MODB select one of the four operating modes. Refer to Section 4. After the operating mode has been selected, the LIR pin provides an open-drain output (driven low) to indicate that execution of an instruction has begun. In order to detect consecutive instructions in a high-speed application, this signal drives high for a short time to prevent false triggering. A series of E clock cycles occurs during execution of each instruction. The LIR signal goes low during the first E clock cycle of each instruction (opcode fetch). This output is provided for assistance in program debugging, and its operation is controlled by the LIRDV bit in the OPT2 register. The VSTBY pin is used to input RAM stand-by power. The MCU is powered from the VDD pin unless the difference between the level of VSTBY and VDD is greater than one MOS threshold (about 0.7 volts). When these voltages differ by more than 0.7 volts, the internal RAM and part of the reset logic are powered from VSTBY rather than VDD. This allows RAM contents to be retained without VDD power applied to the MCU. Reset must be driven low before VDD is removed and must remain low until VDD has been restored to a valid level. VDD 4.7k VDD 4.8 V NiCd VOUT To MODB/VSTBY pin of M68HC11 M68HC11 MAX 690 (+) VBATT Figure 2-4 RAM stand-by connections TPG MC68HC11KW1 MC68HC11KW1 PIN DESCRIPTIONS MOTOROLA 2-5 23 2.9 2 VRH and VRL These pins provide the reference voltages for the analog-to-digital converter. 2.10 R/W In expanded and test modes, R/W performs the read/write function. R/W signals the direction of transfers on the external data bus. A high on this pin indicates that a read cycle is in progress. In single chip mode the R/W signal is driven low. 2.11 Port signals The MC68HC11KW1 MC68HC11KW1 includes 80 pins that are arranged into ten 8-bit ports (A, B, C, D, E, F, G, H, J and K). All the port pins are bidirectional, except for PG7, PG6 and port E pins [7:0]; these are input only. Most of the bidirectional ports serve a purpose other than I/O, depending on the operating mode or peripheral function selected. The input-only pins may be used as general-purpose inputs, or as inputs to the A/D converter. Note that ports B, C, and F are available for I/O functions only in single chip and bootstrap modes. Refer to Table 2-1 for details of the port signals' functions in different operating modes. Note: When using the information about port functions, do not confuse pin function with the electrical state of the pin at reset. All general purpose I/O pins configured as inputs at reset are in a high-impedance state. Port data registers reflect the functional state of the port at reset. The pin function is mode dependent. 2.11.1 Port A Port A is an 8-bit, general-purpose I/O port with a data register (PORTA) and a data direction register (DDRA). Port A pins share functions with the main 16-bit timer system, Timer 1 (see Section 9 for further information). PORTA can be read at any time and always returns the pin level. If written, PORTA stores the data in internal latches. The pins are driven only if they are configured as outputs. Writes to PORTA do not change the pin state when the pins are configured for timer output compares. Out of reset, port A pins [7:0] are general purpose high-impedance inputs. When the functions associated with these pins are disabled, the bits in DDRA govern the I/O state of the associated pin. For further information, refer to Section 6. TPG MOTOROLA 2-6 PIN DESCRIPTIONS MC68HC11KW1 MC68HC11KW1 24 Table 2-1 Port signal functions Port/bit PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PB[7:0] PC[7:0] PD[7,6] PD5 PD4 PD3 PD2 PD1 PD0 PE[7:0] PF[7:0] PG[7,6] PG[5:0] PH7 PH6 PH5 PH4 PH[3:0] PJ7 PJ6 PJ5 PJ4 PJ3 PJ[2,0] PK7 PK6 PK5 PK4 PK3 PK[2,0] 2 Single chip and Expanded multiplexed and bootstrap mode special test mode PA7/PAI and/or OC1 PA6/OC2 and/or OC1 PA5/OC3 and/or OC1 PA4/OC4 and/or OC1 PA3/OC5/IC4 and/or OC1 PA2/IC1 PA1/IC2 PA0/IC3 PB[7:0] ADDR[15:8] PC[7:0] DATA[7:0] PD[7, 6] PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TXD PD0/RXD Input only / analog inputs PF[7:0] ADDR[7:0] Input only / analog inputs PG[5:0] PG[5:0] / XA[18:13] PH7 PH7 / CSPROG PH6 PH6 / CSGP2 PH5 PH5 / CSGP1 PH4 PH4 / CSIO PH[3:0] / PWM[4:1] PJ7 / C4 PJ6 / OC3 PJ5 / OC2 PJ4 / OC1 PJ3 / ECIN PJ[2,0] PK7 / C4 PK6 / OC3 PK5 / OC2 PK4 / OC1 PK3 / ECIN PK[2,0] TPG MC68HC11KW1 MC68HC11KW1 PIN DESCRIPTIONS MOTOROLA 2-7 25 2.11.2 2 Port B Port B is an 8-bit, general-purpose I/O port with a data register (PORTB) and a data direction register (DDRB). In single chip mode, port B pins are general purpose I/O pins (PB[7:0]). In expanded mode, port B pins act as the high-order address lines (ADDR[15:8]) of the address bus. PORTB can be read at any time and always returns the pin level. If PORTB is written, the data is stored in internal latches. The pins are driven only if they are configured as outputs in single chip or bootstrap mode. For further information, refer to Section 6. Port B pins include on-chip pull-up devices which can be enabled or disabled via the port pull-up assignment register (PPAR). 2.11.3 Port C Port C is an 8-bit, general-purpose I/O port with a data register (PORTC) and a data direction register (DDRC). In single chip mode, port C pins are general purpose I/O pins (PC[7:0]). In the expanded mode, port C pins are configured as data bus pins (DATA[7:0]). PORTC can be read at any time; inputs return the pin level and outputs return the pin driver input level. If PORTC is written, the data is stored in internal latches. The pins are driven only if they are configured as outputs in single chip or bootstrap mode. Port C pins are general purpose inputs out of reset in single chip and bootstrap modes. In expanded and test modes, these pins are data bus lines out of reset. The CWOM control bit in the OPT2 register disables port C's p-channel output drivers. Because the n-channel driver is not affected by CWOM, setting CWOM causes port C to become an open-drain-type output port suitable for wired-OR operation. In wired-OR mode (PORTC bits at logic level zero), the pins are actively driven low by the n-channel driver. When a port C bit is at logic level one, the associated pin is in a high impedance state as neither the n-channel nor the p-channel devices are active. It is customary to have an external pull-up resistor on lines that are driven by open-drain devices. Port C can only be configured for wired-OR operation when the MCU is in single chip mode. For further information, refer to Section 6. 2.11.4 Port D Port D, an 8-bit, general-purpose I/O port, has a data register (PORTD) and a data direction register (DDRD). All the port D pins can be used for general purpose I/O, and pins [5:0] can also be used for the serial peripheral interface (SPI, pins [5:2]) and the serial communications interface (SCI, pins [1,0]). PORTD can be read at any time; inputs return the pin level and outputs return the pin driver input level. If PORTD is written, the data is stored in internal latches. The pins are driven only if port D is configured for general purpose output. TPG MOTOROLA 2-8 PIN DESCRIPTIONS MC68HC11KW1 MC68HC11KW1 26 The DWOM bit in SPCR disables the p-channel output drivers of pins D[5:2], and the WOMS bit in SCCR1 disables those of pins D[1,0]. Because the n-channel driver is not affected by DWOM or WOMS, setting either bit causes the corresponding port D pins to become open-drain-type outputs suitable for wired-OR operation. In wired-OR mode (PORTD bits at logic level zero), the pins are actively driven low by the n-channel driver. When a port D bit is at logic level one, the associated pin is in a high impedance state as neither the n-channel nor the p-channel devices are active. It is customary to have an external pull-up resistor on lines that are driven by open-drain devices. Port D can be configured for wired-OR operation when the MCU is in single chip or expanded mode. 2 For further information, refer to Section 6, Section 7 (SCI) and Section 8 (SPI). 2.11.5 Port E Port E pins can be used as the analog inputs for the analog-to-digital converter, or as general-purpose inputs. For further information, refer to Section 6 and Section 10 (A/D). 2.11.6 Port F Port F is an 8-bit, general-purpose I/O port with a data register (PORTF) and a data direction register (DDRF). In single chip mode, port F pins are general purpose I/O pins (PF[7:0]). In expanded mode, port F pins act as the low-order address lines (ADDR[7:0]) of the address bus. PORTF can be read at any time and always returns the pin level. If PORTF is written, the data is stored in internal latches. The pins are driven only if they are configured as outputs in single chip or bootstrap mode. Port F pins include on-chip pull-up devices that can be enabled or disabled via the port pull-up assignment register (PPAR). For further information, refer to Section 6. 2.11.7 Port G In normal modes, Port G is an 8-bit general-purpose port with 6 I/O lines (PG[5:0]), and two input only lines (PG[7, 6]). Associated with port G are a data register (PORTG), a data direction register (DDRG) and an assignment register (PGAR). Pins [7, 6] can be used as general-purpose inputs, or as inputs to the analog-to-digital converter. The functions of pins [5:0] are controlled by bits in the port G assignment register (PGAR), which select whether the pins are used for general purpose I/O, or, in expanded mode, for the memory expansion lines XA[18:13]. PORTG can be read at any time and always returns the pin level. If PORTG is written, the data is stored into an internal latch. The pin is driven only if it is configured as an output. Pins [5:0] have on-chip pull-up devices that can be enabled or disabled via the port pull-up assignment register (PPAR). Refer to Section 6, Section 10 (A/D) and Section 4. TPG MC68HC11KW1 MC68HC11KW1 PIN DESCRIPTIONS MOTOROLA 2-9 27 2.11.8 2 Port H Port H is an 8-bit general-purpose I/O port with a data register (PORTH) and a data direction register (DDRH). Port H lines can be used for general-purpose I/O, for chip select lines (PH[7:4]), and for the pulse width modulation timer (PWM, PH[3:0]). PORTH can be read at any time and always returns the pin level. If PORTH is written, the data is stored into an internal latch. The pin is driven only if it is configured as an output. Port H pins include on-chip pull-up devices that can be enabled or disabled via the port pull-up assignment register (PPAR). For further information, refer to Section 6, Section 9 (Timing system) and Section 4. 2.11.9 Port J Port J is an 8-bit, general-purpose I/O port with a data register (PORTJ) and a data direction register (DDRJ). Port J lines can be used for general-purpose I/O, and pins [7:3] share functions with one of the 16-bit timers, Timer 2. PORTJ can be read at any time and always returns the pin level. If written, PORTJ stores the data in internal latches. The pins are driven only if they are configured as outputs. Writes to PORTJ do not change the pin state when the pins are configured for timer output compares. Out of reset, port J pins [7:0] are general purpose high-impedance inputs. When the functions associated with these pins are disabled, the bits in DDRJ govern the I/O state of the associated pin. For further information, refer to Section 6 and Section 9 (Timing system). 2.11.10 Port K Port K is an 8-bit general-purpose I/O port with a data register (PORTK) and a data direction register (DDRK). Port K lines can be used for general-purpose I/O, and pins [7:3] share functions with one of the 16-bit timers, Timer 3. PORTK can be read at any time and always returns the pin level. If written, PORTK stores the data in internal latches. The pins are driven only if they are configured as outputs. Writes to PORTK do not change the pin state when the pins are configured for timer output compares. Out of reset, port K pins [7:0] are general purpose high-impedance inputs. When the functions associated with these pins are disabled, the bits in DDRK govern the I/O state of the associated pin. For further information, refer to Section 6 and Section 9 (Timing system). TPG MOTOROLA 2-10 PIN DESCRIPTIONS MC68HC11KW1 MC68HC11KW1 28 3 3 CENTRAL PROCESSING UNIT This section discusses the M68HC11 M68HC11 central processing unit (CPU) architecture, its addressing modes and the instruction set. For more detailed information on the instruction set, refer to the M68HC11 M68HC11 Reference Manual (M68HC11RM/AD M68HC11RM/AD). The CPU is designed to treat all peripheral, I/O and memory locations identically, as addresses in the 64Kbyte memory map. This is referred to as memory-mapped I/O. There are no special instructions for I/O that are separate from those used for memory. This architecture also allows accessing an operand from an external memory location with no execution-time penalty. 3.1 Registers M68HC11 M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations. The seven registers are shown in Figure 3-1 and are discussed in the following paragraphs. 7 15 Accumulator A 0 7 Accumulator B Double accumulator D 0 0 A:B D 15 Index register X 0 IX 15 Index register Y 0 IY 15 Stack pointer 0 SP 15 Program counter 0 PC Condition code register S X H I N Z V C CCR Carry Overßow Zero Negative I Interrupt mask Half carry (from bit 3) X Interrupt mask Stop disable Figure 3-1 Programming model TPG MC68HC11KW1 MC68HC11KW1 CENTRAL PROCESSING UNIT MOTOROLA 3-1 29 3.1.1 3 Accumulators A, B and D Accumulators A and B are general purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. For some instructions, these two accumulators are treated as a single double-byte (16-bit) accumulator called accumulator D. Although most operations can use accumulators A or B interchangeably, the following exceptions apply: · The ABX and ABY instructions add the contents of 8-bit accumulator B to the contents of 16-bit register X or Y, but there are no equivalent instructions that use A instead of B. · The TAP and TPA instructions transfer data from accumulator A to the condition code register, or from the condition code register to accumulator A, however, there are no equivalent instructions that use B rather than A. · The decimal adjust accumulator A (DAA) instruction is used after binary-coded decimal (BCD) arithmetic operations, but there is no equivalent BCD instruction to adjust accumulator B. · The add, subtract, and compare instructions associated with both A and B (ABA, SBA, and CBA) only operate in one direction, making it important to plan ahead to ensure the correct operand is in the correct accumulator. 3.1.2 Index register X (IX) The IX register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an instruction to create an effective address. The IX register can also be used as a counter or as a temporary storage register. 3.1.3 Index register Y (IY) The 16-bit IY register performs an indexed mode function similar to that of the IX register. However, most instructions using the IY register require an extra byte of machine code and an extra cycle of execution time because of the way the opcode map is implemented. Refer to Section 3.3 for further information. 3.1.4 Stack pointer (SP) The M68HC11 M68HC11 CPU has an automatic program stack. This stack can be located anywhere in the address space and can be any size up to the amount of memory available in the system. Normally the SP is initialized by one of the first instructions in an application program. The stack is configured as a data structure that grows downward from high memory to low memory. Each time a new byte is pushed onto the stack, the SP is decremented. Each time a byte is pulled from the stack, the SP is incremented. At any given time, the SP holds the 16-bit address of the next free location in the stack. Figure 3-2 is a summary of SP operations. TPG MOTOROLA 3-2 CENTRAL PROCESSING UNIT MC68HC11KW1 MC68HC11KW1 30 JSR, Jump to subroutine Main program PC DIRECT RTN 3 BSR, Branch to subroutine Stack Main program PC $9D = JSR dd Next instruction $8D = BSR rr Next instruction RTN SPÐ2 SPÐ1 SP RTNH RTNL Main program PC IND, X RTN $AD = JSR ff Next instruction Main program PC IND, Y RTN $18 = PRE $AD = JSR ff Next instruction SWI, Software interrupt Main program Stack SPÐ2 SPÐ1 SP RTNH RTNL PC RTN $3F = SWI WAI, Wait for interrupt Main program Main program PC EXTEND RTN PC RTN $BD = JSR hh ll Next instruction $3E = WAI Stack SPÐ9 SPÐ8 SPÐ7 SPÐ6 SPÐ5 SPÐ4 SPÐ3 SPÐ2 SPÐ1 SP Condition Code Accumulator B Accumulator A Index register (IXH) Index register (IXL) Index register (IYH) Index register (IYL) RTNH RTNL RTI, Return from interrupt Interrupt program PC $3B = RTI RTS, Return from subroutine Main program PC $39 = RTS Stack SP SP+1 SP+2 RTNH RTNL Stack SP SP+1 SP+2 SP+3 SP+4 SP+5 SP+6 SP+7 SP+8 SP+9 Condition Code Accumulator B Accumulator A Index register (IXH) Index register (IXL) Index register (IYH) Index register (IYL) RTNH RTNL LEGEND RTN Address of the next instruction in the main program, to be executed on return from subroutine RTNH More signiÞcant byte of return address RTNL Less signiÞcant byte of return address Shaded cells show stack pointer position after the operation is complete dd 8-bit direct address ($0000Ð$00FF); the high byte is assumed to be $00 ff 8-bit positive offset ($00 to $FF (0 to 256) is added to the index register contents hh High order byte of 16-bit extended address ll Low order byte of 16-bit extended address rr Signed relative offset ($80 to $7F (Ð128 to +127); offset is relative to the address following the offset byte Figure 3-2 Stacking operations TPG MC68HC11KW1 MC68HC11KW1 CENTRAL PROCESSING UNIT MOTOROLA 3-3 31 3 When a subroutine is called by a jump to subroutine (JSR) or branch to subroutine (BSR) instruction, the address of the instruction after the JSR or BSR is automatically pushed onto the stack, less significant byte first. When the subroutine is finished, a return from subroutine (RTS) instruction is executed. The RTS pulls the previously stacked return address from the stack, and loads it into the program counter. Execution then continues at this recovered return address. When an interrupt is recognized, the current instruction finishes normally, the return address (the current value in the program counter) is pushed onto the stack, all of the CPU registers are pushed onto the stack, and execution continues at the address specified by the vector for the interrupt. At the end of the interrupt service routine, an RTI instruction is executed. The RTI instruction causes the saved registers to be pulled off the stack in reverse order. Program execution resumes at the return address. There are instructions that push and pull the A and B accumulators and the X and Y index registers. These instructions are often used to preserve program context. For example, pushing accumulator A onto the stack when entering a subroutine that uses accumulator A, and then pulling accumulator A off the stack just before leaving the subroutine, ensures that the contents of a register will be the same after returning from the subroutine as it was before starting the subroutine. 3.1.5 Program counter (PC) The program counter, a 16-bit register, contains the address of the next instruction to be executed. After reset, the program counter is initialized from one of six possible vectors, depending on operating mode and the cause of reset. Table 3-1 Reset vector comparison Normal Test or Boot 3.1.6 POR or RESET pin $FFFE, $FFFF $BFFE, $BFFF Clock monitor $FFFC, $FFFD $BFFE, $BFFF COP watchdog $FFFA, $FFFB $BFFE, $BFFF Condition code register (CCR) This 8-bit register contains five condition code indicators (C, V, Z, N, and H), two interrupt masking bits, (IRQ and XIRQ) and a stop disable bit (S). In the M68HC11 M68HC11 CPU, condition codes are automatically updated by most instructions. For example, load accumulator A (LDAA) and store accumulator A (STAA) instructions automatically set or clear the N, Z, and V condition code flags. Pushes, pulls, add B to X (ABX), add B to Y (ABY), and transfer/exchange instructions do not affect the condition codes. Refer to Table 3-2, which shows the condition codes that are affected by a particular instruction. TPG MOTOROLA 3-4 CENTRAL PROCESSING UNIT MC68HC11KW1 MC68HC11KW1 32 3.1.6.1 Carry/borrow (C) The C-bit is set if the arithmetic logic unit (ALU) performs a carry or borrow during an arithmetic operation. The C-bit also acts as an error flag for multiply and divide operations. Shift and rotate instructions operate with and through the carry bit to facilitate multiple-word shift operations. 3.1.6.2 3 Overflow (V) The overflow bit is set if an operation causes an arithmetic overflow. Otherwise, the V-bit is cleared. 3.1.6.3 Zero (Z) The Z-bit is set if the result of an arithmetic, logic, or data manipulation operation is zero. Otherwise, the Z-bit is cleared. Compare instructions do an internal implied subtraction and the condition codes, including Z, reflect the results of that subtraction. A few operations (INX, DEX, INY, and DEY) affect the Z-bit and no other condition flags. For these operations, only = and conditions can be determined. 3.1.6.4 Negative (N) The N-bit is set if the result of an arithmetic, logic, or data manipulation operation is negative; otherwise, the N-bit is cleared. A result is said to be negative if its most significant bit (MSB) is set (MSB = 1). A quick way to test whether the contents of a memory location has the MSB set is to load it into an accumulator and then check the status of the N-bit. 3.1.6.5 Interrupt mask (I) The interrupt request (IRQ) mask (I-bit) is a global mask that disables all maskable interrupt sources. While the I-bit is set, interrupts can become pending, but the operation of the CPU continues uninterrupted until the I-bit is cleared. After any reset, the I-bit is set by default and can only be cleared by a software instruction. When an interrupt is recognized, the I-bit is set after the registers are stacked, but before the interrupt vector is fetched. After the interrupt has been serviced, a return from interrupt instruction is normally executed, restoring the registers to the values that were present before the interrupt occurred. Normally, the I-bit is zero after a return from interrupt is executed. Although the I-bit can be cleared within an interrupt service routine, `nesting' interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism. Refer to Section 5. TPG MC68HC11KW1 MC68HC11KW1 CENTRAL PROCESSING UNIT MOTOROLA 3-5 33 3.1.6.6 3 Half carry (H) The H-bit is set when a carry occurs between bits 3 and 4 of the arithmetic logic unit during an ADD, ABA, or ADC instruction. Otherwise, the H-bit is cleared. Half carry is used during BCD operations. 3.1.6.7 X interrupt mask (X) The XIRQ mask (X) bit disables interrupts from the XIRQ pin. After any reset, X is set by default and must be cleared by a software instruction. When an XIRQ interrupt is recognized, the X- and I-bits are set after the registers are stacked, but before the interrupt vector is fetched. After the interrupt has been serviced, an RTI instruction is normally executed, causing the registers to be restored to the values that were present before the interrupt occurred. The X interrupt mask bit is set only by hardware RESET or XIRQ acknowledge). X is cleared only by program instruction (TAP, where the associated bit of A is 0; or RTI, where bit 6 of the value loaded into the CCR from the stack has been cleared). There is no hardware action for clearing X. 3.1.6.8 Stop disable (S) Setting the STOP disable (S) bit prevents the STOP instruction from putting the M68HC11 M68HC11 into a low-power stop condition. If the STOP instruction is encountered by the CPU while the S-bit is set, it is treated as a no-operation (NOP) instruction, and processing continues to the next instruction. S is set by reset - STOP disabled by default. 3.2 Data types The M68HC11 M68HC11 CPU supports the following data types: · Bit data · 8-bit and 16-bit signed and unsigned integers · 16-bit unsigned fractions · 16-bit addresses A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. Because the M68HC11 M68HC11 is an 8-bit CPU, there are no special requirements for alignment of instructions or operands. TPG MOTOROLA 3-6 CENTRAL PROCESSING UNIT MC68HC11KW1 MC68HC11KW1 34 3.3 Opcodes and operands The M68HC11 M68HC11 family of microcontrollers uses 8-bit opcodes. Each opcode identifies a particular instruction and associated addressing mode to the CPU. Several opcodes are required to provide each instruction with a range of addressing capabilities. Only 256 opcodes would be available if the range of values were restricted to the number able to be expressed in 8-bit binary numbers. 3 A four-page opcode map has been implemented to expand the number of instructions. An additional byte, called a prebyte, directs the processor from page 0 of the opcode map to one of the other three pages. As its name implies, the additional byte precedes the opcode. A complete instruction consists of a prebyte, if any, an opcode, and zero, one, two, or three operands. The operands contain information the CPU needs for executing the instruction. Complete instructions can be from one to five bytes long. 3.4 Addressing modes Six addressing modes; immediate, direct, extended, indexed, inherent, and relative, detailed in the following paragraphs, can be used to access memory. All modes except inherent mode use an effective address. The effective address is the memory address from which the argument is fetched or stored, or the address from which execution is to proceed. The effective address can be specified within an instruction, or it can be calculated. 3.5 Immediate (IMM) In the immediate addressing mode an argument is contained in the byte(s) immediately following the opcode. The number of bytes following the opcode matches the size of the register or memory location being operated on. There are two, three, and four (if prebyte is required) byte immediate instructions. The effective address is the address of the byte following the instruction. 3.5.1 Direct (DIR) In the direct addressing mode, the low-order byte of the operand address is contained in a single byte following the opcode, and the high-order byte of the address is assumed to be $00. Addresses $00­$FF are thus accessed directly, using two-byte instructions. Execution time is reduced by eliminating the additional memory access required for the high-order address byte. In most applications, this 256-byte area is reserved for frequently referenced data. In M68HC11 M68HC11 MCUs, the memory map can be configured for combinations of internal registers, RAM, or external memory to occupy these addresses. TPG MC68HC11KW1 MC68HC11KW1 CENTRAL PROCESSING UNIT MOTOROLA 3-7 35 3.5.2 3 Extended (EXT) In the extended addressing mode, the effective address of the argument is contained in two bytes following the opcode byte. These are three-byte instructions (or four-byte instructions if a prebyte is required). One or two bytes are needed for the opcode and two for the effective address. 3.5.3 Indexed (IND, X; IND, Y) In the indexed addressing mode, an 8-bit unsigned offset contained in the instruction is added to the value contained in an index register (IX or IY) - the sum is the effective address. This addressing mode allows referencing any memory location in the 64Kbyte address space. These are two- to five-byte instructions, depending on whether or not a prebyte is required. 3.5.4 Inherent (INH) In the inherent addressing mode, all the information necessary to execute the instruction is contained in the opcode. Operations that use only the index registers or accumulators, as well as control instructions with no arguments, are included in this addressing mode. These are one or two-byte instructions. 3.5.5 Relative (REL) The relative addressing mode is used only for branch instructions. If the branch condition is true, an 8-bit signed offset included in the instruction is added to the contents of the program counter to form the effective branch address. Otherwise, control proceeds to the next instruction. These are usually two-byte instructions. 3.6 Instruction set Refer to Table 3-2, which shows all the M68HC11 M68HC11 instructions in all possible addressing modes. For each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in CPU E clock cycles. TPG MOTOROLA 3-8 CENTRAL PROCESSING UNIT MC68HC11KW1 MC68HC11KW1 36 Table 3-2 Instruction set (Page 1 of 6) Addressing mode Mnemonic Operation Description ABA Add accumulators A+BA INH ABX Add B to X IX + (00:B) IX ABY Add B to Y IY + (00:B) IY ADCA (opr) Add with carry to A A+M+CA ADCB (opr) Add with carry to B ADDA (opr) Instruction Opcode Operand Condition codes Cycles S X H I N Z V C 1B Ñ 2 Ñ Ñ Ñ INH 3A Ñ 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ INH 18 3A Ñ 4 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ A A A A A IMM DIR EXT IND, X IND, Y 89 99 B9 A9 18 A9 ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ B+M+CB B B B B B IMM DIR EXT IND, X IND, Y C9 D9 F9 E9 18 E9 ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ Add memory to A A+MA A A A A A IMM DIR EXT IND, X IND, Y 8B 9B BB AB 18 AB ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ ADDB (opr) Add memory to B B+MB B B B B B IMM DIR EXT IND, X IND, Y CB DB FB EB 18 EB ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ ADDD (opr) Add 16-bit to D D + (M:M+1) D IMM DIR EXT IND, X IND, Y C3 D3 F3 E3 18 E3 jj kk dd hh ll ff ff 4 5 6 6 7 Ñ Ñ Ñ Ñ ANDA (opr) AND A with memory A¥MA A A A A A IMM DIR EXT IND, X IND, Y 84 94 B4 A4 18 A4 ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ Ñ 0 Ñ ANDB (opr) AND B with memory B¥MB B B B B B IMM DIR EXT IND, X IND, Y C4 D4 F4 E4 18 E4 ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ Ñ 0 Ñ ASL (opr) Arithmetic shift left EXT IND, X IND, Y 78 68 18 68 hh ll ff ff 6 6 7 Ñ Ñ Ñ Ñ ASLA Arithmetic shift left A ASLB Arithmetic shift left B ASLD Arithmetic shift left D 0 C b7 b0 INH 48 Ñ 2 Ñ Ñ Ñ Ñ B INH 58 Ñ 2 Ñ Ñ Ñ Ñ INH 05 Ñ 3 Ñ Ñ Ñ Ñ hh ll ff ff 6 6 7 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ 0 C b15 ASR A 3 b0 Arithmetic shift right EXT IND, X IND, Y C b7 b0 ASRA Arithmetic shift right A ASRB Arithmetic shift right B BCC (rel) Branch if carry clear C=0? BCLR (opr) (msk) Clear bit(s) M ¥ (MM) M 77 67 18 67 A INH 47 Ñ 2 B INH 57 Ñ 2 Ñ Ñ Ñ Ñ REL 24 rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ dd mm ff mm ff mm 6 7 8 Ñ Ñ Ñ Ñ 0 Ñ DIR IND, X IND, Y 15 1D 18 1D BCS (rel) Branch if carry set C=1? REL 25 rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BEQ (rel) Branch if equal to zero Z=1? REL 27 rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BGE (rel) Branch if zero NV=0? REL 2C rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BGT (rel) Branch if > zero Z + (N V) = 0 ? REL 2E rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BHI (rel) Branch if higher C+Z=0? REL 22 rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ TPG MC68HC11KW1 MC68HC11KW1 CENTRAL PROCESSING UNIT MOTOROLA 3-9 37 Table 3-2 Instruction set (Page 2 of 6) Addressing mode Mnemonic Description BHS (rel) 3 Operation Branch if higher or same C=0? BITA (opr) Bit(s) test A with memory A¥M A A A A A IMM DIR EXT IND, X IND, Y BITB (opr) Bit(s) test B with memory B¥M B B B B B IMM DIR EXT IND, X IND, Y REL Instruction Opcode 24 Operand Condition codes Cycles S X H I N Z V C rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ 85 95 B5 A5 18 A5 ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ Ñ 0 Ñ C5 D5 F5 E5 18 E5 ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ Ñ 0 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BLE (rel) Branch if zero Z + (N V) = 1 ? REL 2F rr 3 BLO (rel) Branch if lower C=1? REL 25 rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BLS (rel) Branch if lower or same C+Z=1? REL 23 rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BLT (rel) Branch if < zero NV=1? REL 2D rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BMI (rel) Branch if minus N=1? REL 2B rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BNE (rel) Branch if zero Z=0? REL 26 rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BPL(rel) Branch if plus N=0? REL 2A rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ REL 20 rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ 6 7 8 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BRA (rel) Branch always 1=1? BRCLR(opr) (msk) (rel) Branch if bit(s) clear M ¥ mm = 0 ? DIR IND, X IND, Y REL 13 1F 18 1F 21 dd mm rr ff mm rr ff mm rr BRN (rel) Branch never 1=0? 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BRSET(opr) (msk) (rel) Branch if bit(s) set M ¥ mm = 0 ? DIR IND, X IND, Y 12 1E 18 1E dd mm rr ff mm rr ff mm rr rr 6 7 8 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BSET (opr) (msk) Set bit(s) M + mm M DIR IND, X IND, Y 14 1C 18 1C dd mm ff mm ff mm 6 7 8 Ñ Ñ Ñ Ñ 0 Ñ BSR (rel) Branch to subroutine see Figure 3-2 REL 8D rr 6 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BVC (rel) Branch if overßow clear V=0? REL 28 rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ BVS (rel) Branch if overßow set V=1? REL 29 rr 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ CBA Compare A with B AÐB INH 11 Ñ 2 Ñ Ñ Ñ Ñ CLC Clear carry bit 0C INH 0C Ñ 2 Ñ Ñ Ñ Ñ Ñ Ñ Ñ 0 0E Ñ 2 Ñ Ñ Ñ 0 Ñ Ñ Ñ Ñ hh ll ff ff 6 6 7 Ñ Ñ Ñ Ñ 0 1 0 0 CLI Clear interrupt mask 0I INH CLR (opr) Clear memory byte 0M DIR IND, X IND, Y CLRA Clear accumulator A 0A A INH 4F Ñ 2 Ñ Ñ Ñ Ñ 0 1 0 0 CLRB Clear accumulator B 0B B INH 5F Ñ 2 Ñ Ñ Ñ Ñ 0 1 0 0 CLV Clear overßow ßag 0V INH 0A Ñ 2 Ñ Ñ Ñ Ñ Ñ Ñ 0 Ñ CMPA (opr) Compare A with memory AÐM A A A A A IMM DIR EXT IND, X IND, Y 81 91 B1 A1 18 A1 ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ Ñ CMPB (opr) Compare B with memory BÐM B B B B B IMM DIR EXT IND, X IND, Y C1 D1 F1 E1 18 E1 ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ Ñ COM (opr) Ones complement memory byte $FF Ð M M EXT IND, X IND, Y 73 63 18 63 hh ll ff ff 6 6 7 Ñ Ñ Ñ Ñ 0 1 7F 6F 18 6F COMA Ones complement A $FF Ð A A A INH 43 Ñ 2 Ñ Ñ Ñ Ñ 0 1 COMB Ones complement B $FF Ð B B B INH 53 Ñ 2 Ñ Ñ Ñ Ñ 0 1 TPG MOTOROLA 3-10 CENTRAL PROCESSING UNIT MC68HC11KW1 MC68HC11KW1 38 Table 3-2 Instruction set (Page 3 of 6) Mnemonic Operation CPD (opr) Compare D with memory (16-bit) Addressing mode Description D Ð (M:M+1) Instruction Condition codes Opcode Operand Cycles S X H IMM DIR EXT IND, X IND, Y 1A 1A 1A 1A CD 83 93 B3 A3 A3 jj kk dd hh ll ff ff 5 6 7 7 7 Ñ Ñ Ñ Ñ I N Z V C CPX (opr) Compare IX with memory (16-bit) IX Ð (M:M+1) IMM DIR EXT IND, X IND, Y 8C 9C BC AC CD AC jj kk dd hh ll ff ff 4 5 6 6 7 Ñ Ñ Ñ Ñ CPY (opr) Compare IY with memory (16-bit) IY Ð (M:M+1) IMM DIR EXT IND, X IND, Y 18 18 18 1A 18 jj kk dd hh ll ff ff 5 6 7 7 7 Ñ Ñ Ñ Ñ DAA Decimal adjust A adjust sum to BCD DEC (opr) Decrement memory byte MÐ1M 3 INH EXT IND, X IND, Y 8C 9C BC AC AC 19 7A 6A 18 6A Ñ 2 Ñ Ñ Ñ Ñ ? hh ll ff ff 6 6 7 Ñ Ñ Ñ Ñ Ñ DECA Decrement accumulator A AÐ1A A INH 4A Ñ 2 Ñ Ñ Ñ Ñ Ñ DECB Decrement accumulator B BÐ1B B INH 5A Ñ 2 Ñ Ñ Ñ Ñ Ñ DES Decrement stack pointer SP Ð 1 SP INH 34 Ñ 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ DEX Decrement index register X IX Ð 1 IX INH 09 Ñ 3 Ñ Ñ Ñ Ñ Ñ Ñ Ñ DEY Decrement index register Y IY Ð 1 IY INH 18 09 Ñ 4 Ñ Ñ Ñ Ñ Ñ Ñ Ñ EORA (opr) Exclusive OR A with memory AMA A A A A A IMM DIR EXT IND, X IND, Y 88 98 B8 A8 18 A8 ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ Ñ 0 Ñ EORB (opr) Exclusive OR B with memory BMA B B B B B IMM DIR EXT IND, X IND, Y C8 D8 F8 E8 18 E8 ii dd hh ll ff ff 2 3 4 4 5 Ñ Ñ Ñ Ñ 0 Ñ FDIV Fractional divide, 16 by 16 D / IX IX; r D INH 03 Ñ 41 Ñ Ñ Ñ Ñ Ñ IDIV Integer divide, 16 by 16 D / IX IX; r D INH 02 Ñ 41 Ñ Ñ Ñ Ñ Ñ 0 INC (opr) Increment memory byte M+1M hh ll ff ff 6 6 7 Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ Ñ EXT IND, X IND, Y 7C 6C 18 6C INCA Increment accumulator