MC68HC05P6 HC705P6 HC05C4AGRS/D HC05C5GRS/ HC705C5GRS/D MC68HC705C8AD/ 705C4A - Datasheet Archive

 

MC68HC05P6 Technical Update contains updates to documented information appearing in other Motorola technical documents as well as

 

TECHNICAL UPDATE MC68HC05P6 MC68HC05P6 Technical Update contains updates to documented information appearing in other Motorola technical documents as well as new information not covered elsewhere. We are confident that your Motorola product will satisfy your design needs. This Technical Update and the accompanying manuals and reference documentation are designed to be helpful, informative, and easy to use. Should your application generate a question or a problem not covered in the current documentation, please call your local Motorola distributor or sales office. Technical experts at these locations are eager to help you make the best use of your Motorola product. As appropriate, these experts will coordinate with their counterparts in the factory to answer your questions or solve your problems. To obtain the latest document, call your local Motorola sales office. Motorola reserves the right to make changes without further notice to any products herein. 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MC68HC05P6 MC68HC05P6 TABLE OF CONTENTS Modules Computer Operating Properly (COP) .3 COP Timeout Period . 3 CPU .4 Correction to SUB in Applications Guide . 4 External Interrupt Timing. 4 I Bit in CCR During Stop Mode. 5 BSET and BCLR are Read-Modify-Write Instructions. 5 I Bit in CCR During Wait Mode . 6 Timer .7 Input Capture/Output Compare Code Snippet . 7 Interrupt Driven Output Compare Code . 9 Input Capture Test. 11 Analog to Digital .13 A/D Example Code . 13 A/D Converter Source Impedance . 15 A/D Accuracy Specification. 16 MOTOROLA Table of Contents Page 2 MC68HC05P6 MC68HC05P6 TECHNICAL UPDATE Modules Computer Operating Properly (COP) COP0COP_A Revision History Date 7/7/95 Revision 1.00 Description Includes tracker HC705P6 HC705P6.012 COP Timeout Period Reference Documents: HC05C4AGRS/D HC05C4AGRS/D Rev. 1.1, page 21; HC05C5GRS/ HC05C5GRS/ D Rev. 1.2, page 24; HC705C5GRS/D HC705C5GRS/D Rev. 1.3, page 49; MC68HC705C8AD/ MC68HC705C8AD/ D Rev. 4.0, page 14 (705C4A 705C4A); MC68HC705C8AD/D MC68HC705C8AD/D Rev. 4.0, page 3 1(705C8A 705C8A); MC68HC705C8AD/D MC68HC705C8AD/D Rev. 4.0, page 51 (HSC705C8A HSC705C8A); MC68HC05C12/D MC68HC05C12/D, page 5-2; HC05P1AGRS/D HC05P1AGRS/D Rev. 1.02, page 17; MC68HC05P4/D MC68HC05P4/D, page 4-2; HC05P5GRS/D HC05P5GRS/D Rev. 1.3, page 35; MC68HC05P7/D MC68HC05P7/D, page 4-2; HC05P15GRS/D HC05P15GRS/D Rev. 0.0, page 33; HC05P18GRS/D HC05P18GRS/D Rev. 0.5, page 12 Tracker Number: HC705P6 HC705P6.012 Revision: 1.00 The timeout period for the COP0COP_A computer operating properly watchdog timer is a direct function of the crystal frequency. The equation is: Timeout Period = 262,144 -Fxtal For example, the timeout period for a 4-MHz crystal is 65.536 ms. MOTOROLA Modules Page 3 MC68HC05P6 MC68HC05P6 CPU HC05CPU HC05CPU Revision History Date 5/3/95 Revision 1.00 Description Includes trackers HC05CPU HC05CPU.001, HC705C8 HC705C8.002R2 002R2, HC705C8 HC705C8.017, HC705C8 HC705C8.018R2 018R2, and HC705C8019 HC705C8019. Correction to SUB in Applications Guide Reference Documents: M68HC05 M68HC05 Applications Guide MC68HC05AG/AD MC68HC05AG/AD, page A-62; M68HC05 M68HC05 Applications Guide MC68HC05AG/AD MC68HC05AG/AD Rev. 1, page A-62 Tracker Number: HC05CPU HC05CPU.001 Revision: 1.00 Replace the C bit description with: The C bit (carry flag) in the condition code register gets set if the absolute value of the contents of memory is larger than the absolute value of the accumulator, cleared otherwise. External Interrupt Timing Reference Documents: MC68HC705C8/D MC68HC705C8/D Rev. 1, page 3-5; MC68HC05B6/ MC68HC05B6/ D, Rev. 3, page 11-11, note 4; MC68HC705C8/D MC68HC705C8/D, Rev. 1, page 3-5; MC68HC05C9/D MC68HC05C9/D, page 13-7, note 3; MC68HC05C12/D MC68HC05C12/D, page 13-9, note 4; MC68HC05D9/D MC68HC05D9/D, Rev. 1, page 10-4, note 1; MC68HC05J3/D MC68HC05J3/D, page 9-6, note 3; and MC68HC05X16/D MC68HC05X16/D, page 12-6, note 4 Tracker Number: HC705C8 HC705C8.002 Revision: 2.00 This time (Tilil) is obtained by adding 19 instruction cycles to the total number of cycles needed to complete the service routine. The return to interrupt (RTI) is included in the 19 cycles. MOTOROLA Modules Page 4 MC68HC05P6 MC68HC05P6 I Bit in CCR During Stop Mode Reference Document: M68HC05 M68HC05 Applications Guide, page 3-93 Tracker Number: HC705C8 HC705C8.017 Revision: 1.00 The stop mode flow chart shows that the I bit is set when stop mode is entered. However, this is not true. The I bit actually is cleared when stop mode is entered so that an external IRQ may release the processor from stop mode. This error is present in the original applications guide as well as the revision. BSET and BCLR are Read-Modify-Write Instructions Reference Documents: MC68HC705C8/D MC68HC705C8/D Rev. 1, page 7-6; MC68HC05J1/ MC68HC05J1/ D Rev. 1, page 5-7; MC68HC05J3/D MC68HC05J3/D, page 8-4; MC68HC705J2/D MC68HC705J2/D, page 416; HC05J3/705J3 HC05J3/705J3 Technical Data - MC68HC05J3/D MC68HC05J3/D, page 8-6; MC68HC05K1/D MC68HC05K1/D, page 10-10; MC68HC705K1/D MC68HC705K1/D, page 11-10 Tracker Number: HC705C8 HC705C8.018 Revision: 2.00 In many data books, the read-modify-write instruction table located in the instruction set and addressing mode section does not list the BSET and BCLR instructions. These data books list BSET and BCLR as bit-manipulation instructions only. While this is correct, it is not complete. These operations use a read-modify-write method to accomplish their task and, therefore, should be included in the table of readmodify-write instructions. NOTE: These instructions do not use the same addressing modes as the other read-modify-write instructions. Only direct addressing is valid for BSET and BCLR. Because BSET and BCLR are read-modify-write instructions, they may not be used with write-only registers. These registers will read back undefined data. Therefore, a readmodify-write operation will read undefined data, modify it as appropriate, and then write it back to the register. Because the original data is undefined, the data written back will be undefined also. MOTOROLA Modules Page 5 MC68HC05P6 MC68HC05P6 I Bit in CCR During Wait Mode Reference Document: M68HC05 M68HC05 Applications Guide, page 3-93 Tracker Number: HC705C8 HC705C8.019 Revision: 1.00 The wait mode flow chart does not show that the I bit gets cleared upon entering wait mode. The I bit is cleared when wait is entered. An external IRQ or any of the internal interrupts (timer, SCI, SPI) can release the processor from wait mode. This error is present in the original applications guide as well as the revision. MOTOROLA Modules Page 6 MC68HC05P6 MC68HC05P6 Timer TIM1IC1OC_A Revision History Date Revision 7/7/95 1.00 Description Includes trackers HC05C4 HC05C4.002R2 002R2, HC05C4 HC05C4.003R2 003R2, and HC705P9 HC705P9.005R2 005R2. Input Capture/Output Compare Code Snippet Reference Document: Not applicable Tracker Number: HC05C4 HC05C4.002 Revision: 2.00 * * * * * * * * * Program Name: ICOCC4.ASM Revision: 1.0 Date: 9/6/93 Written By: Mark Johnson Motorola CSIC Applications * Assembled Under: P&E Microcomputer Systems * IASM05 IASM05 Version 3.02m * * * * * Revision History * * * * * Revision 1.00 9/1/93 Original Release * * * * Program Description: * * This was written for the timer module TIM1IC1OC_A and tested * on the HC05C4 HC05C4. In order to use this with other HC05 MCU's, * reset vectors and memory map equates may have to be changed. * See the Technical Databook for the appropriate part for this * memory map information. * * This simple program was written to demonstrate the input * capture and output compare functions of the MC68HC MC68HC(8)05C4 * timer. The routine generates a level transition on port A * which is fed into the input capture pin (TCAP). When * the input capture occurs an offset of 50us is added to * value in the input capture registers and stored in the * output compare registers. The output compare generates * a level transition on the TCMP pin and then the entire * process is repeated. * * MOTOROLA Modules Page 7 MC68HC05P6 MC68HC05P6 * The program was run on the M68HC05EVM M68HC05EVM using the * following setup conditions: * * 1) HC705C8 HC705C8 Resident Processor * 2) Fop = 2MHz * 3) Pin 11 (PA0) on target header J19 jumpered to pin * 37 (TCAP). * 4) The user should see a level transition on the * TCMP pin approximately* 50us after the level * transition on port A. * * *NOTE: The level transition on the TCMP pin will occur at * 50us + 1 count of the free-running counter = 52us. * This is the result of an internal synchronization * delay which occurs during an input capture. * (1 count = 4 internal bus cycles) * * * Register Equates * porta equ $00 ;port A data register ddra equ $04 ;port A data dir. reg. tcr equ $12 ;timer control register tsr equ $13 ;timer status register inpcaph equ $14 ;input capture (MSB) inpcapl equ $15 ;input capture (LSB) outcomph equ $16 ;output compare (MSB) outcompl equ $17 ;output compare (LSB) * * RAM Variables * org $50 ;RAM address space templ rmb 1 ;storage for O/C low byte * * Beginning of main routine * org $200 ;EPROM/ROM address space start lda #$ff sta ddra ;all port A pins are outputs clra sta porta ;output a low on port A lda #3 sta tcr ;IEDG = positive edge ;OLVL = high output loop lda tsr ;read timer status register lda outcompl ;clear OCF com porta ;toggle port A lda #!25 ;I/C low byte offset add inpcapl ;add I/C low byte value sta templ ;save new value in temp storage lda inpcaph ;get high byte of I/C reg. adc #0 ;add carry from last addition sta outcomph ;store value to O/C high byte lda templ ;get low byte offset sta outcompl ;store value in O/C low byte lda inpcapl ;enable input captures brclr 6,tsr,* ;wait for output compare lda tcr ;get Timer Control Register eor #3 ;toggle IEDG and OLVL sta tcr ;store new IEDG and OLVL values bra loop ;repeat process indefinitely * * Reset vector setup * org $1ffe fdb start MOTOROLA Modules Page 8 MC68HC05P6 MC68HC05P6 Interrupt Driven Output Compare Code Reference Document: MC68HC05C4/D MC68HC05C4/D (ADI-991-R2 ADI-991-R2), page 4-7 Tracker Number: HC05C4 HC05C4.003 Revision: 2.00 The following code uses the output compare function driven by an interrupt to produce a square wave. The code was tested with an HC705C8 HC705C8 on the HC05EVM HC05EVM board and will work on an HC05C4 HC05C4. * * * Program Name: 7C8_OCI.ASM (Square wave generation on OC) * Revision: 1.00 * Date: September 29, 1993 * * Written By: Mark Glenewinkel * Motorola CSIC Applications * * Assembled Under: P&E Microcomputer Systems IASM05 IASM05 * * * * * Revision History * * * * * Rev 1.00 09/29/93 M.R. Glenewinkel * Initial Release * * * * Program Description: * * This was written for the timer module TIM1IC1OC_A and tested * on the HC05C4 HC05C4. In order to use this with other HC05 MCU's, * reset vectors and memory map equates may have to be changed. * See the Technical Databook for the appropriate part for this * memory map information. * * This program uses the Output Compare function of the * timer to generate a square wave. The output compare * interrupt is utilized to take care of adding the * appropriate value to the 16 bit output compare * register to create the square wave. With some * modification, this routine can perform pulse width * modulation. * * Use the HC705C8 HC705C8 resident MCU on the HC05EVM HC05EVM to * run this test. * Download the program. * Make sure the PC is at $1000. Type GO. * OR, hit USER RESET on the EVM. * Look at pin #35 of header J19. This is the Timer * Compare Output pin (TCMP) of the timer. You should * see a 3.906kHz square wave on this pin with a * 256 usec period. * Press ABORT on the EVM to halt program execution. * * MOTOROLA Modules Page 9 MC68HC05P6 MC68HC05P6 * TCR TSR OCH OCL TCH TCL TEMP Equates equ equ equ equ equ equ equ * Start of program * org $1000 ;start of user code lda #$41 sta cli TCR ;output compare interrupt ; enabled, output level 0 ;store to timer ctrl reg ;clear the I bit in CCR START DUMLOOP bra for 705C8 705C8 $12 $13 $16 $17 $18 $19 $50 DUMLOOP ;timer ctrl reg ;timer status reg ;output compare high reg ;output compare low reg ;timer counter high reg ;timer counter low reg ;temp loc for OCL ;dummy loop waiting for ; timer interrupt * OCISR Interrupt Service Routine lda TSR * ;read timer status ; to clear flag * Flip the OLVL bit in the TCR reg lda TCR ;load ACCA w/ TCR eor #$01 ;flip bit 0 of ACCA sta TCR ;store ACCA to TCR * * * * Add 64 counts to timer counter reg With a 2 MHz internal bus clock, the timer count period is 2 usec. 64 counts of the timer counter will produce a square wave half cycle of 128 usecs. lda #$40 ;load #$40 into acca add OCL ;add OCL to ACCA sta TEMP ;store res to temp loc lda #$00 ;add $00 to out comp hi adc OCH ; with carry sta OCH ;store res to out comp hi lda TEMP ;store temp to out sta OCL ; comp low rti * ;return from interrupt Set up vectors org $1FF8 dw OCISR ;define timer ; interrupt vector org dw MOTOROLA $1FFE START ;define reset vector Modules Page 10 MC68HC05P6 MC68HC05P6 Input Capture Test Reference Document: Not applicable Tracker Number: HC705P9 HC705P9.005 Revision: 2.00 This program tests the input capture module TIM1IC1OC_A on the HC705P9 HC705P9 on the HC05P9EVS HC05P9EVS. * * * Program Name: P9_INCAP.ASM (Input Capture Test for the P9EVS) * Revision: 1.00 * Date: June 7, 1993 * * Written By: Mark Glenewinkel * Motorola CSIC Applications * * Assembled Under: P&E Microcomputer Systems IASM05 IASM05 * * * * * Revision History * * * * * Rev 1.00 06/07/93 M.R. Glenewinkel * Initial Release * * * * Program Description: * * This was written for the timer module TIM1IC1OC_A and tested * on the HC705P9 HC705P9. In order to use this with other HC05 MCU's, * reset vectors and memory map equates may have to be changed. * See the Technical Databook for the appropriate part for this * memory map information. * * Tests the Input capture pin. * Use the HC705P9 HC705P9 resident MCU on the HC05P9EVS HC05P9EVS to * run this test. * Jumper pins PA0 and PD7/TCAP on Target Header P4. * We will use Port A, bit 0 to toggle the TCAP pin. * Download the program. * Make sure the PC is at $100. * Type GO. * ABORT the program and look at locations $80-$83. * After the first Input Capture, the Input Capture * Registers High and Low are loaded into RAM * location $80 and $81, respectively. After the * second Input Capture, the Input Capture Registers * High and Low are loaded into RAM location $82 * and $83, respectively. * If you trace this program, the Input capture * flag will look like its not being set when you * view with the emulator software. Remember, the * flag gets cleared when a read of ICL and TSR occurs. * The emulator software does this automatically when * reading those locations to display in the * emulator window. * * MOTOROLA Modules Page 11 MC68HC05P6 MC68HC05P6 * PORTA PORTB PORTC DDRA DDRB DDRC DDRD TCR TSR ICRH ICRL Equates EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU EQU $00 $01 $02 $04 $05 $06 $07 $12 $13 $14 $15 TEMP1 TEMP2 TEMP3 TEMP4 EQU EQU EQU EQU $0080 $0081 $0082 $0083 * Start of code ORG #$00 PORTA ;falling edge created ; on PortD/TCAP LDA AND BEQ TSR #$80 LOOP ;wait in loop for flag ; to be set ICRH TEMP1 ICRL TEMP2 ;write counter values ;in memory LDA STA LDA STA #$02 TCR #$FF PORTA ;set InCap to rising edge LDA AND BEQ TSR #$80 LOOP2 ;wait in loop for flag ; to be set LDA STA LDA STA LOOP3 #$00 TCR TSR ICRL LDA STA LDA STA LOOP2 #$FF PORTA #$00 DDRD #$FF DDRA DDRC LDA STA LOOP LDA STA LDA STA LDA STA STA LDA STA LDA LDA START $0100 ICRH TEMP3 ICRL TEMP4 ;write counter values ;in memory NOP BRA LOOP3 MOTOROLA ;start of program ;PortA is $FF ;PortD is input ;PortA is output ;set InCap to fall edge ;look at tsr ;look at input reg low ;this clears any flags ;rising edge created ; on PortD/TCAP Modules Page 12 MC68HC05P6 MC68HC05P6 Analog to Digital ATD4X8NVRL_A Revision History Date Revision 7/7/95 1.00 Description Includes trackers HC05P6 HC05P6.005, HC705P9 HC705P9.002, and HC705P9 HC705P9.010. A/D Example Code Reference Document: MC68HC05P6/D MC68HC05P6/D, page 10-1 Tracker Number: HC05P6 HC05P6.005 Revision: 1.00 The following code shows a simple routine that will read AN0 of the A/D converter. Port C bit 6 is the A/D converter input AN0. The code was tested on an M68HC05P9EVS M68HC05P9EVS evaluation system. It is assumed the reader is familiar with the IASM05 IASM05 assembler and the EVM05 EVM05 debugger from P&E Microcomputer Systems. These P&E software programs are used to assemble, download, and run the code. If the reader is unfamiliar with emulating the HC05P6 HC05P6 on the P9EVS, consult the P9EVS user's manual, M68HC05P9EVS/D1 M68HC05P9EVS/D1, for that system. This code was tested on the HC05P6 HC05P6 but can be used on other parts that have the ATD4X8NVRL_A module. Due to differences in memory maps, equates and orgs for RAM, EPROM, and RESET vectors may need to be changed. Consult the applicable MCU data book for specific part information. Assemble the following lines of code. * ADSCR ADDR WAIT CHCK ;a/d status and ctrl reg ;a/d data reg ORG START Equates EQU $1E EQU $1D $100 ;start of program LDA STA #$20 ADSCR ;turn on the a/d converter LDA DECA BNE #33T LDA STA LDA AND #$20 ADSCR ADSCR #$80 MOTOROLA ;execute loop for 100 usecs ; so a/d can warm up WAIT ;start a conversion ;check if conversion ; complete flag (COCO) Modules Page 13 MC68HC05P6 MC68HC05P6 BNE ; is set LDA ADDR ;when conversion done ; put answer in ACCA BRA LOOP ;loop forever ORG DW LOOP CHCK $1FFE $0100 ;define reset vector The connections needed for this routine are: Port C7, VRH -> - +5 Volts | / \ Port C6, AN0 -> / 10-K Potential \ / | VSS -> - GND The VRH is connected to +5 volts. The HC05P6 HC05P6 does not have a low voltage reference for its A/D. The VRL is connected to the chip's VSS. Connect the GND pin of the voltage divider potential to VSS. The potential will vary the voltage between VRH and VSS. This voltage is also fed into the converter channel AN0. To predict what the A/D converter will read, use this relationship: A/D reading pot voltage on AN0 - = -255 5 volts MOTOROLA Modules Page 14 MC68HC05P6 MC68HC05P6 Run the code by using these steps: 1. Download the code into the EVS with the EVM05 EVM05 software. 2. Set the program counter to $100. 3. 'PC 100' 4. Type 'GO' 5. The routine will run and eventually hit the infinite loop. Press the ABORT button on the EVS to get out of the loop. 6. The A/D reading is in accumulator A, which is shown on the EVM05 EVM05 screen. Various voltage inputs with their appropriate A/D readings: 1. 0.0 V -> $00 2. 1.0 V -> $33 3. 2.5 V -> $80 4. 4.0 V -> $CC 5. 5.0 V -> $FF The reading may be off by a couple of least significant bits (LSB) due to system noise. A/D Converter Source Impedance Reference Documents: MC68HC705P9 MC68HC705P9 Rev. 1, page 3-8; MC68HC05P6 MC68HC05P6, page 13-7; MC68HC705P6 MC68HC705P6 Rev. 1, page 13-7; MC68HC05P9 MC68HC05P9, page 10-7; MC68HC705P9 MC68HC705P9 Rev. 1, page 13-8 Tracker Number: HC705P9 HC705P9.002 Revision: 1.00 Note 3 in the data books states: 3. Source impedances greater than 10 k adversely affect internal RC charging time during input sampling. The A/D converter on the HC705P9 HC705P9 is a successive approximation converter. Thirty-two cycles are necessary for the A/D to execute one conversion. The first 12 cycles sample the voltage on the A/D input pin by charging an internal capacitor. During the last 20 cycles, a comparator successively compares the output of an internal D/A converter to the sampled analog input. Control logic changes the D/A converter value bit by bit until the D/A value and the sampled input match. Note 3 refers to the first 12 cycles of the conversion process. If the source impedance is larger than 10 k, more time will be needed for the internal RC charging of the capacitor MOTOROLA Modules Page 15 MC68HC05P6 MC68HC05P6 to reach the voltage on the A/D input. The higher source impedance will affect A/D accuracy. A/D Accuracy Specification Reference Documents: MC68HC705P9 MC68HC705P9, page 13-8; MC68HC05P6 MC68HC05P6, page 137; MC68HC705P6 MC68HC705P6 Rev. 1, page 13-7; MC68HC05P9 MC68HC05P9, page 10-7; MC68HC705P9 MC68HC705P9 Rev. 1, page 13-8 Tracker Number: HC705P9 HC705P9.010 Revision: 1.00 The A/D converter's accuracy specification has caused some confusion because of differing ways it can be interpreted. The specification currently states: Characteristic Min Absolute Accuracy (4.0 > V > VDD) (Note 2) - Max +/- 1-1/2 Unit LSB The correct reading is "plus or minus 1.5 LSBs." However, some customers incorrectly read this as "plus or minus 1.0 LSB down to 0.5 LSBs" or as "plus or minus 1.5 LSBs." MOTOROLA Modules Page 16