M68300 MC68332 CH370 CPU32 M68000 M68MMDS1632 M68MEVB1632 YFFA00 YFFA02 YFFA04 - Datasheet Archive

 

M68300 Family Freescale Semiconductor, Inc. MC68332 User's Manual © MOTOROLA, INC. 1995 © Freescale Semiconductor,

 

Freescale Semiconductor M68300 M68300 Family Freescale Semiconductor, Inc. MC68332 MC68332 User's Manual © MOTOROLA, INC. 1995 © Freescale Semiconductor, Inc., 2004. All rights reserved. For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. How to Reach Us: Home Page: www.freescale.com Freescale Semiconductor, Inc. E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. 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For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Paragraph Title Page SECTION 1 INTRODUCTION SECTION 2NOMENCLATURE Freescale Semiconductor, Inc. 2.1 2.2 2.3 2.4 2.5 Symbols and Operators . 2-1 CPU32 CPU32 Registers . 2-2 Pin and Signal Mnemonics . 2-3 Register Mnemonics . 2-4 Conventions . 2-5 SECTION 3OVERVIEW 3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.2 3.3 3.4 3.5 3.6 3.6.1 3.6.2 3.7 3.7.1 3.7.2 MC68332 MC68332 Features . 3-1 System Integration Module (SIM) . 3-1 Central Processing Unit (CPU) . 3-1 Time Processor Unit (TPU) . 3-1 Queued Serial Module (QSM) . 3-2 Static RAM Module with TPU Emulation Capability (TPURAM) . 3-2 System Block Diagram and Pin Assignment Diagrams . 3-2 Pin Descriptions . 3-5 Signal Descriptions . 3-7 Intermodule Bus . 3-9 System Memory Map . 3-9 Internal Register Map . 3-10 Address Space Maps . 3-10 System Reset . 3-15 SIM Reset Mode Selection . 3-15 MCU Module Pin Function During Reset . 3-16 SECTION 4 SYSTEM INTEGRATION MODULE 4.1 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.2.8 4.2.9 General . 4-1 System Configuration and Protection . 4-2 Module Mapping . 4-3 Interrupt Arbitration . 4-3 Show Internal Cycles . 4-4 Factory Test Mode . 4-4 Register Access . 4-4 Reset Status . 4-4 Bus Monitor . 4-5 Halt Monitor . 4-5 Spurious Interrupt Monitor . 4-5 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Freescale Semiconductor, Inc. Paragraph (Continued) Title Page 4.2.10 Software Watchdog . 4-5 4.2.11 Periodic Interrupt Timer . 4-7 4.2.12 Low-Power Stop Operation . 4-8 4.2.13 Freeze Operation . 4-9 4.3 System Clock . 4-9 4.3.1 Clock Sources . 4-10 4.3.2 Clock Synthesizer Operation . 4-10 4.3.3 External Bus Clock . 4-15 4.3.4 Low-Power Operation . 4-15 4.3.5 Loss of Reference Signal . 4-16 4.4 External Bus Interface . 4-17 4.4.1 Bus Signals . 4-18 4.4.1.1 Address Bus . 4-18 4.4.1.2 Address Strobe . 4-18 4.4.1.3 Data Bus . 4-18 4.4.1.4 Data Strobe . 4-18 4.4.1.5 Read/Write Signal . 4-18 4.4.1.6 Size Signals . 4-19 4.4.1.7 Function Codes . 4-19 4.4.1.8 Data and Size Acknowledge Signals . 4-19 4.4.1.9 Bus Error Signal . 4-20 4.4.1.10 Halt Signal . 4-20 4.4.1.11 Autovector Signal . 4-20 4.4.2 Dynamic Bus Sizing . 4-20 4.4.3 Operand Alignment . 4-21 4.4.4 Misaligned Operands . 4-22 4.4.5 Operand Transfer Cases . 4-22 4.5 Bus Operation . 4-22 4.5.1 Synchronization to CLKOUT . 4-23 4.5.2 Regular Bus Cycles . 4-23 4.5.2.1 Read Cycle . 4-24 4.5.2.2 Write Cycle . 4-25 4.5.3 Fast Termination Cycles . 4-26 4.5.4 CPU Space Cycles . 4-27 4.5.4.1 Breakpoint Acknowledge Cycle . 4-28 4.5.4.2 LPSTOP Broadcast Cycle . 4-31 4.5.5 Bus Exception Control Cycles . 4-31 4.5.5.1 Bus Errors . 4-33 4.5.5.2 Double Bus Faults . 4-33 4.5.5.3 Retry Operation . 4-34 4.5.5.4 Halt Operation . 4-34 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Freescale Semiconductor, Inc. Paragraph 4.5.6 4.5.6.1 4.5.6.2 4.6 4.6.1 4.6.2 4.6.3 4.6.3.1 4.6.3.2 4.6.3.3 4.6.4 4.6.5 4.6.5.1 4.6.5.2 4.6.6 4.6.7 4.6.8 4.6.9 4.7 4.7.1 4.7.2 4.7.3 4.7.4 4.7.5 4.8 4.8.1 4.8.1.1 4.8.1.2 4.8.1.3 4.8.1.4 4.8.2 4.8.3 4.8.4 4.9 4.9.1 4.9.2 4.9.3 4.10 (Continued) Title Page External Bus Arbitration . 4-35 Slave (Factory Test) Mode Arbitration . 4-36 Show Cycles . 4-36 Reset . 4-37 Reset Exception Processing . 4-37 Reset Control Logic . 4-38 Reset Mode Selection . 4-38 Data Bus Mode Selection . 4-39 Clock Mode Selection . 4-41 Breakpoint Mode Selection . 4-41 MCU Module Pin Function During Reset . 4-41 Pin State During Reset . 4-42 Reset States of SIM Pins . 4-42 Reset States of Pins Assigned to Other MCU Modules . 4-43 Reset Timing . 4-43 Power-On Reset . 4-44 Reset Processing Summary . 4-45 Reset Status Register . 4-46 Interrupts . 4-46 Interrupt Exception Processing . 4-46 Interrupt Priority and Recognition . 4-46 Interrupt Acknowledge and Arbitration . 4-47 Interrupt Processing Summary . 4-48 Interrupt Acknowledge Bus Cycles . 4-49 Chip Selects . 4-49 Chip-Select Registers . 4-51 Chip-Select Pin Assignment Registers . 4-52 Chip-Select Base Address Registers . 4-53 Chip-Select Option Registers . 4-53 PORTC Data Register . 4-55 Chip-Select Operation . 4-55 Using Chip-Select Signals for Interrupt Acknowledge . 4-55 Chip-Select Reset Operation . 4-56 Parallel Input/Output Ports . 4-58 Pin Assignment Registers . 4-58 Data Direction Registers . 4-58 Data Registers . 4-58 Factory Test . 4-58 SECTION 5 CENTRAL PROCESSING UNIT 5.1 General . 5-1 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Freescale Semiconductor, Inc. Paragraph (Continued) Title Page 5.2 CPU32 CPU32 Registers . 5-2 5.2.1 Data Registers . 5-3 5.2.2 Address Registers . 5-5 5.2.3 Program Counter . 5-5 5.2.4 Control Registers . 5-5 5.2.4.1 Status Register . 5-5 5.2.4.2 Alternate Function Code Registers . 5-6 5.2.5 Vector Base Register (VBR) . 5-6 5.3 Memory Organization . 5-6 5.4 Virtual Memory . 5-8 5.5 Addressing Modes . 5-8 5.6 Processing States . 5-8 5.7 Privilege Levels . 5-9 5.8 Instructions . 5-9 5.8.1 M68000 M68000 Family Compatibility . 5-12 5.8.2 Special Control Instructions . 5-13 5.8.2.1 Low Power Stop (LPSTOP) . 5-13 5.8.2.2 Table Lookup and Interpolate (TBL) . 5-13 5.9 Exception Processing . 5-13 5.9.1 Exception Vectors . 5-13 5.9.2 Types of Exceptions . 5-14 5.9.3 Exception Processing Sequence . 5-15 5.10 Development Support . 5-15 5.10.1 M68000 M68000 Family Development Support . 5-15 5.10.2 Background Debugging Mode . 5-16 5.10.2.1 Enabling BDM . 5-17 5.10.2.2 BDM Sources . 5-17 5.10.2.3 Entering BDM . 5-18 5.10.2.4 BDM Commands . 5-19 5.10.2.5 Background Mode Registers . 5-20 5.10.2.6 Returning from BDM . 5-20 5.10.2.7 Serial Interface . 5-20 5.10.3 Recommended BDM Connection . 5-22 5.10.4 Deterministic Opcode Tracking . 5-22 5.10.5 On-Chip Breakpoint Hardware . 5-23 5.11 Loop Mode Instruction Execution . 5-23 SECTION 6QUEUED SERIAL MODULE 6.1 6.2 6.2.1 General . 6-1 QSM Registers and Address Map . 6-2 QSM Global Registers . 6-2 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Freescale Semiconductor, Inc. Paragraph (Continued) Title Page 6.2.1.1 Low-Power Stop Operation . 6-2 6.2.1.2 Freeze Operation . 6-3 6.2.1.3 QSM Interrupts . 6-3 6.2.2 QSM Pin Control Registers . 6-3 6.3 Queued Serial Peripheral Interface . 6-4 6.3.1 QSPI Registers . 6-6 6.3.1.1 Control Registers . 6-7 6.3.1.2 Status Register . 6-7 6.3.2 QSPI RAM . 6-7 6.3.2.1 Receive RAM . 6-7 6.3.2.2 Transmit RAM . 6-8 6.3.2.3 Command RAM . 6-8 6.3.3 QSPI Pins . 6-8 6.3.4 QSPI Operation . 6-9 6.3.5 QSPI Operating Modes . 6-10 6.3.5.1 Master Mode . 6-17 6.3.5.2 Master Wraparound Mode . 6-20 6.3.5.3 Slave Mode . 6-20 6.3.5.4 Slave Wraparound Mode . 6-22 6.3.6 Peripheral Chip Selects . 6-22 6.4 Serial Communication Interface . 6-22 6.4.1 SCI Registers . 6-22 6.4.1.1 Control Registers . 6-22 6.4.1.2 Status Register . 6-25 6.4.1.3 Data Register . 6-25 6.4.2 SCI Pins . 6-25 6.4.3 SCI Operation . 6-25 6.4.3.1 Definition of Terms . 6-25 6.4.3.2 Serial Formats . 6-26 6.4.3.3 Baud Clock . 6-26 6.4.3.4 Parity Checking . 6-27 6.4.3.5 Transmitter Operation . 6-27 6.4.3.6 Receiver Operation . 6-28 6.4.3.7 Idle-Line Detection . 6-29 6.4.3.8 Receiver Wakeup . 6-30 6.4.3.9 Internal Loop . 6-30 6.5 QSM Initialization . 6-31 SECTION 7TIME PROCESSOR UNIT 7.1 7.2 General . 7-1 TPU Components . 7-2 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Freescale Semiconductor, Inc. Paragraph 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.4 7.4.1 7.4.2 7.4.3 7.4.4 7.4.5 7.4.6 7.4.7 7.4.8 7.4.9 7.4.10 7.4.11 7.5 7.5.1 7.5.2 7.5.3 7.5.4 7.5.5 7.5.6 7.5.7 7.5.8 7.5.9 7.5.10 7.6 7.6.1 7.6.1.1 7.6.1.2 (Continued) Title Page Time Bases . 7-2 Timer Channels . 7-2 Scheduler . 7-2 Microengine . 7-2 Host Interface . 7-2 Parameter RAM . 7-3 TPU Operation . 7-3 Event Timing . 7-3 Channel Orthogonality . 7-4 Interchannel Communication . 7-4 Programmable Channel Service Priority . 7-4 Coherency . 7-4 Emulation Support . 7-4 TPU Interrupts . 7-5 Standard and Enhanced Standard Time Functions . 7-6 Discrete Input/Output (DIO) . 7-6 Input Capture/Input Transition Counter (ITC) . 7-6 Output Compare (OC) . 7-6 Pulse-Width Modulation (PWM) . 7-7 Synchronized Pulse-Width Modulation (SPWM) . 7-7 Period Measurement with Additional Transition Detect (PMA) . 7-7 Period Measurement with Missing Transition Detect (PMM) . 7-7 Position-Synchronized Pulse Generator (PSP) . 7-7 Stepper Motor (SM) . 7-8 Period/Pulse-Width Accumulator (PPWA) . 7-8 Quadrature Decode (QDEC) . 7-9 Motion Control Time Functions . 7-9 Table Stepper Motor (TSM) . 7-9 New Input Capture/Transition Counter (NITC) . 7-9 Queued Output Match (QOM) . 7-10 Programmable Time Accumulator (PTA) . 7-10 Multichannel Pulse-Width Modulation (MCPWM) . 7-10 Fast Quadrature Decode (FQD) . 7-10 Universal Asynchronous Receiver/Transmitter (UART) . 7-11 Brushless Motor Commutation (COMM) . 7-11 Frequency Measurement (FQM) . 7-11 Hall Effect Decode (HALLD) . 7-11 Host Interface Registers . 7-11 System Configuration Registers . 7-12 Prescaler Control for TCR1 . 7-12 Prescaler Control for TCR2 . 7-12 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Title Paragraph Freescale Semiconductor, Inc. 7.6.1.3 7.6.1.4 7.6.2 7.6.2.1 7.6.2.2 7.6.2.3 7.6.2.4 7.6.2.5 7.6.3 Page Emulation Control . 7-13 Low-Power Stop Control . 7-13 Channel Control Registers . 7-14 Channel Interrupt Enable and Status Registers . 7-14 Channel Function Select Registers . 7-14 Host Sequence Registers . 7-14 Host Service Registers . 7-14 Channel Priority Registers . 7-14 Development Support and Test Registers . 7-15 SECTION 8STANDBY RAM WITH TPU EMULATION 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 General . 8-1 TPURAM Register Block . 8-1 TPURAM Array Address Mapping . 8-1 TPURAM Privilege Level . 8-2 Normal Operation . 8-2 Standby Operation . 8-2 Low-Power Stop Operation . 8-3 Reset . 8-3 TPU Microcode Emulation . 8-3 APPENDIX A ELECTRICAL CHARACTERISTICS APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION APPENDIX CDEVELOPMENT SUPPORT C.1 C.2 M68MMDS1632 M68MMDS1632 Modular Development System . C-1 M68MEVB1632 M68MEVB1632 Modular Evaluation Board . C-2 APPENDIX D REGISTER SUMMARY D.1 D.1.1 D.1.2 D.2 D.2.1 D.2.2 D.2.3 D.2.4 D.2.5 D.2.6 Central Processing Unit . D-1 CPU32 CPU32 Register Model . D-2 SR - Status Register . D-3 System Integration Module . D-3 SIMCR - Module Configuration Register . $YFFA00 YFFA00 D-5 SIMTR - System Integration Test Register . $YFFA02 YFFA02 D-6 SYNCR - Clock Synthesizer Control Register . $YFFA04 YFFA04 D-6 RSR - Reset Status Register . $YFFA07 YFFA07 D-7 SIMTRE - System Integration Test Register (ECLK) . $YFFA08 YFFA08 D-7 PORTE0/PORTE1 - Port E Data Register . $YFFA11 YFFA11, $YFFA13 YFFA13 D-8 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Freescale Semiconductor, Inc. Paragraph (Continued) Title Page D.2.7 DDRE - Port E Data Direction Register . $YFFA15 YFFA15 D-8 D.2.8 PEPAR - Port E Pin Assignment Register . $YFFA17 YFFA17 D-8 D.2.9 PORTF0/PORTF1 - Port F Data Register.$YFFA19 YFFA19, $YFFA1B D-9 D.2.10 DDRF - Port F Data Direction Register.$YFFA1D D-9 D.2.11 PFPAR - Port F Pin Assignment Register. $YFFA1F D-9 D.2.12 SYPCR - System Protection Control Register . $YFFA21 YFFA21 D-10 D.2.13 PICR - Periodic Interrupt Control Register. $YFFA22 YFFA22 D-11 D.2.14 PITR - Periodic Interrupt Timer Register . $YFFA24 YFFA24 D-11 D.2.15 SWSR - Software Service Register . $YFFA27 YFFA27 D-11 D.2.16 TSTMSRA - Master Shift Register A. $YFFA30 YFFA30 D-11 D.2.17 TSTMSRB - Master Shift Register B. $YFFA32 YFFA32 D-11 D.2.18 TSTSC - Test Module Shift Count . $YFFA34 YFFA34 D-12 D.2.19 TSTRC - Test Module Repetition Count . $YFFA36 YFFA36 D-12 D.2.20 CREG - Test Submodule Control Register . $YFFA38 YFFA38 D-12 D.2.21 DREG - Distributed Register.$YFFA3A D-12 D.2.22 PORTC - Port C Data Register . $YFFA41 YFFA41 D-12 D.2.23 CSPAR0 - Chip Select Pin Assignment Register 0. $YFFA44 YFFA44 D-12 D.2.24 CSPAR1 - Chip Select Pin Assignment Register 1. $YFFA46 YFFA46 D-13 D.2.25 CSBARBT - Chip Select Base Address Register Boot ROM $YFFA48 YFFA48 D13 D.2.26 CSBAR[0:10] - Chip Select Base Address Registers $YFFA4C­$YFFA74 YFFA74 D-13 D.2.27 CSORBT - Chip Select Option Register Boot ROM.$YFFA4A D-14 D.2.28 CSOR[0:10] - Chip Select Option Registers .$YFFA4E­$YFFA76 YFFA76 D-14 D.3 Standby RAM Module with TPU Emulation . D-16 D.3.1 TRAMMCR - TPURAM Module Configuration Register. $YFFB00 YFFB00 D-16 D.3.2 TRAMTST - TPURAM Test Register . $YFFB02 YFFB02 D-16 D.3.3 TRAMBAR - TPURAM Base Address and Status Register $YFFB04 YFFB04 D-16 D.4 Queued Serial Module . D-18 D.4.1 QSMCR - QSM Configuration Register . $YFFC00 YFFC00 D-18 D.4.2 QTEST - QSM Test Register . $YFFC02 YFFC02 D-19 D.4.3 QILR - QSM Interrupt Level Register.$YFFC04 YFFC04 QIVR - QSM Interrupt Vector Register$YFFC05 YFFC05 . D-19 D.4.4 SCCR0 - SCI Control Register 0 . $YFFC08 YFFC08 D-20 D.4.5 SCCR1 - SCI Control Register 1.$YFFC0A D-20 D.4.6 SCSR - SCI Status Register . $YFFC0C D-22 D.4.7 SCDR - SCI Data Register.$YFFC0E D-23 D.4.8 PORTQS - Port QS Data Register. $YFFC15 YFFC15 D-23 D.4.9 PQSPAR - PORT QS Pin Assignment Register .$YFFC16 YFFC16 DDRQS - PORT QS Data Direction Register$YFFC17 YFFC17 . D-23 D.4.10 SPCR0 - QSPI Control Register 0 . $YFFC18 YFFC18 D-25 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS Freescale Semiconductor, Inc. Paragraph (Continued) Title Page D.4.11 SPCR1 - QSPI Control Register 1 .$YFFC1A D-26 D.4.12 SPCR2 - QSPI Control Register 2 . $YFFC1C D-27 D.4.13 SPCR3 - QSPI Control Register 3 . $YFFC1E SPSR - QSPI Status Register $YFFC1F . D-27 D.4.14 RR[0:F] - Receive Data RAM. $YFFD00 YFFD00­$YFFD0E D-28 D.4.15 TR[0:F] - Transmit Data RAM . $YFFD20 YFFD20­$YFFD3E D-28 D.4.16 CR[0:F] - Command RAM. $YFFD40 YFFD40­$YFFD4F D-29 D.5.1 TPUMCR - TPU Module Configuration Register. $YFFE00 YFFE00 D-30 D.5.2 TCR - Test Configuration Register. $YFFE02 YFFE02 D-32 D.5.3 DSCR - Development Support Control Register. $YFFE04 YFFE04 D-32 D.5.4 DSSR - Development Support Status Register . $YFFE06 YFFE06 D-33 D.5.5 TICR - TPU Interrupt Configuration Register . $YFFE08 YFFE08 D-33 D.5.6 CIER - Channel Interrupt Enable Register.$YFFE0A D-34 D.5.7 CFSR0 - Channel Function Select Register 0 .$YFFE0C D-34 D.5.8 CFSR1 - Channel Function Select Register 1 .$YFFE0E D-34 D.5.9 CFSR2 - Channel Function Select Register 2 . $YFFE10 YFFE10 D-34 D.5.10 CFSR3 - Channel Function Select Register 3 . $YFFE12 YFFE12 D-34 D.5.11 HSQR0 - Host Sequence Register 0 . $YFFE14 YFFE14 D-35 D.5.12 HSQR1 - Host Sequence Register 1 . $YFFE16 YFFE16 D-35 D.5.13 HSRR0 - Host Service Request Register 0 . $YFFE18 YFFE18 D-35 D.5.15 CPR0 - Channel Priority Register 0 .$YFFE1C D-36 D.5.16 CPR1 - Channel Priority Register 1 . $YFFE1E D-36 D.5.17 CISR - Channel Interrupt Status Register. $YFFE20 YFFE20 D-36 D.5.18 LR - Link Register . $YFFE22 YFFE22 D-36 D.5.19 SGLR - Service Grant Latch Register. $YFFE24 YFFE24 D-36 D.5.20 DCNR - Decoded Channel Number Register . $YFFE26 YFFE26 D-37 D.5.21 TPU Parameter RAM . D-37 SUMMARY OF CHANGES MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. TABLE OF CONTENTS (Continued) Title Page Freescale Semiconductor, Inc. Paragraph MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Freescale Semiconductor, Inc. Figure 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 5-1 5-2 5-3 5-4 5-5 5-6 5-7 5-8 5-9 5-10 5-11 5-12 6-1 6-2 Title Page MCU Block Diagram . 3-3 Pin Assignments for 132-Pin Package . 3-4 Pin Assignments for 144-Pin Package . 3-5 Internal Register Memory Map . 3-10 Overall Memory Map . 3-11 Separate Supervisor and User Space Map . 3-12 Supervisor Space (Separate Program/Data Space) Map . 3-13 User Space (Separate Program/Data Space) Map . 3-14 System Integration Module Block Diagram . 4-2 System Configuration and Protection . 4-3 Periodic Interrupt Timer and Software Watchdog Timer . 4-7 System Clock Block Diagram . 4-9 System Clock Oscillator Circuit . 4-10 System Clock Filter Networks . 4-11 MCU Basic System . 4-17 Operand Byte Order . 4-21 Word Read Cycle Flowchart . 4-25 Write Cycle Flowchart . 4-26 CPU Space Address Encoding . 4-27 Breakpoint Operation Flowchart . 4-30 LPSTOP Interrupt Mask Level . 4-31 Bus Arbitration Flowchart for Single Request . 4-36 Data Bus Mode Select Conditioning . 4-40 Power-On Reset . 4-45 Basic MCU System . 4-50 Chip-Select Circuit Block Diagram . 4-51 CPU Space Encoding for Interrupt Acknowledge . 4-56 CPU32 CPU32 Block Diagram . 5-2 User Programming Model . 5-3 Supervisor Programming Model Supplement . 5-3 Data Organization in Data Registers . 5-4 Address Organization in Address Registers . 5-5 Memory Operand Addressing . 5-7 Common in-Circuit Emulator Diagram . 5-16 Bus State Analyzer Configuration . 5-17 Debug Serial I/O Block Diagram . 5-21 BDM Serial Data Word . 5-22 BDM Connector Pinout . 5-22 Loop Mode Instruction Sequence . 5-23 QSM Block Diagram . 6-1 QSPI Block Diagram . 6-6 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIST OF ILLUSTRATIONS Freescale Semiconductor, Inc. Figure 6-3 6-4 6-5 6-5 6-5 6-6 6-6 6-7 6-8 7-1 7-2 7-3 A-1 A-2 A-3 A-4 A-5 A-6 A-7 A-8 A-9 A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18 A-19 A-20 B-1 B-2 D-1 D-2 (Continued) Title Page QSPI RAM . 6-8 Flowchart of QSPI Initialization Operation . 6-11 Flowchart of QSPI Master Operation (Part 1) . 6-12 Flowchart of QSPI Master Operation (Part 2) . 6-13 Flowchart of QSPI Master Operation (Part 3) . 6-14 Flowchart of QSPI Slave Operation (Part 1) . 6-15 Flowchart of QSPI Slave Operation (Part 2) . 6-16 SCI Transmitter Block Diagram . 6-23 SCI Receiver Block Diagram . 6-24 TPU Block Diagram . 7-1 TCR1 Prescaler Control . 7-12 TCR2 Prescaler Control . 7-13 CLKOUT Output Timing Diagram . A-14 External Clock Input Timing Diagram . A-14 ECLK Output Timing Diagram . A-14 Read Cycle Timing Diagram . A-15 Write Cycle Timing Diagram . A-16 Fast Termination Read Cycle Timing Diagram . A-17 Fast Termination Write Cycle Timing Diagram . A-18 Bus Arbitration Timing Diagram -Active Bus Case . A-19 Bus Arbitration Timing Diagram - Idle Bus Case . A-20 Show Cycle Timing Diagram . A-20 Chip Select Timing Diagram . A-21 Reset and Mode Select Timing Diagram . A-21 Background Debugging Mode Timing Diagram - Serial Communication . A-23 Background Debugging Mode Timing Diagram - Freeze Assertion . A-23 ECLK Timing Diagram . A-25 QSPI Timing - Master, CPHA = 0 . A-27 QSPI Timing - Master, CPHA = 1 . A-27 QSPI Timing - Slave, CPHA = 0 . A-28 QSPI Timing - Slave, CPHA = 1 . A-28 TPU Timing Diagram . A-29 132-Pin Plastic Surface Mount Package Pin Assignments . B-2 144-Pin Plastic Surface Mount Package Pin Assignments . B-3 User Programming Model .D-2 Supervisor Programming Model Supplement .D-2 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIST OF TABLES Freescale Semiconductor, Inc. Table 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 5-1 5-2 5-3 5-4 5-5 5-6 6-1 6-2 6-3 6-4 Title Page MCU Driver Types. 3-6 MCU Pin Characteristics . 3-6 MCU Power Connections . 3-7 MCU Signal Characteristics . 3-7 MCU Signal Function . 3-8 SIM Reset Mode Selection. 3-15 Module Pin Functions. 3-16 Show Cycle Enable Bits . 4-4 Bus Monitor Period. 4-5 MODCLK Pin and SWP Bit During Reset . 4-6 Software Watchdog Ratio. 4-6 MODCLK Pin and PTP Bit at Reset . 4-7 Periodic Interrupt Priority. 4-8 Clock Control Multipliers. 4-12 System Frequencies from 32.768­kHz Reference. 4-14 Clock Control. 4-16 Size Signal Encoding . 4-19 Address Space Encoding . 4-19 Effect of DSACK Signals . 4-21 Operand Transfer Cases. 4-22 DSACK, BERR, and HALT Assertion Results . 4-32 Reset Source Summary . 4-38 Reset Mode Selection . 4-39 Module Pin Functions. 4-42 SIM Pin Reset States . 4-43 Chip-Select Pin Functions . 4-52 Pin Assignment Field Encoding. 4-52 Block Size Encoding. 4-53 Option Register Function Summary . 4-54 Chip Select Base and Option Register Reset Values . 4-57 CSBOOT Base and Option Register Reset Values. 4-58 Instruction Set Summary . 5-10 Exception Vector Assignments. 5-14 BDM Source Summary. 5-17 Polling the BDM Entry Source. 5-18 Background Mode Command Summary . 5-19 CPU Generated Message Encoding . 5-22 QSM Pin Function . 6-4 QSPI Pin Function. 6-9 BITS Encoding . 6-19 SCI Pin Function . 6-25 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. LIST OF TABLES Freescale Semiconductor, Inc. Table 6-5 6-6 7-1 7-2 7-3 A-1 A-2 A-2 a. A-3 A-4 A-4 a. A-5 A-5 a. A-6 A-6 a. A-7 A-8 A-8 a. A-9 A-10 A-11 B-1 B-2 C-1 D-1 D-2 D-3 D-4 D-5 D-6 D-7 D-8 (Continued) Title Page Serial Frame Formats. 6-26 Effect of Parity Checking on Data Size . 6-27 TCR1 Prescaler Control . 7-12 TCR2 Prescaler Control . 7-13 Channel Priority Encodings . 7-15 Maximum Ratings. A-1 Typical Ratings, 16.78 MHz Operation. A-2 Typical Ratings, 20.97 MHz Operation. A-2 Thermal Characteristics . A-3 16.78 MHz Clock Control Timing. A-4 20.97 MHz Clock Control Timing. A-5 16.78 MHz DC Characteristics . A-6 20.97 MHz DC Characteristics . A-7 16.78 MHz AC Timing . A-9 20.97 MHz AC Timing . A-11 Background Debugging Mode Timing . A-22 16.78 MHz ECLK Bus Timing. A-24 20.97 MHz ECLK Bus Timing. A-24 QSPI Timing . A-26 16.78 MHz Time Processor Unit Timing. A-29 20.97 MHz Time Processor Unit Timing. A-29 MCU Ordering Information . B-5 Quantity Order Suffix. B-7 MC68332 MC68332 Development Tools.C-1 Module Address Map .D-1 SIM Address Map.D-4 TPURAM Address Map .D-16 QSM Address Map .D-18 TPU Address Map .D-30 Parameter RAM Address Map .D-37 MC68332 MC68332 Module Address Map.D-38 Register Bit and Field Mnemonics.D-41 MC68332 MC68332 USER'S MANUAL For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. SECTION 1 INTRODUCTION Freescale Semiconductor, Inc. The MC68332 MC68332, a highly-integrated 32-bit microcontroller, combines high-performance data manipulation capabilities with powerful peripheral subsystems. The MCU is built up from standard modules that interface through a common intermodule bus (IMB). Standardization facilitates rapid development of devices tailored for specific applications. The MCU incorporates a 32-bit CPU (CPU32 CPU32), a system integration module (SIM), a time processor unit (TPU), a queued serial module (QSM), and a 2-Kbyte static RAM module with TPU emulation capability (TPURAM). The MCU can either synthesize an internal clock signal from an external reference or use an external clock input directly. Operation with a 32.768-kHz reference frequency is standard. System hardware and software allow changes in clock rate during operation. Because MCU operation is fully static, register and memory contents are not affected by clock rate changes. High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The CPU32 CPU32 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this capability. Documentation for the Modular Microcontroller Family follows the modular construction of the devices in the product line. Each microcontroller has a comprehensive user's manual that provides sufficient information for normal operation of the device. The user's manual is supplemented by module reference manuals that provide detailed inAdformation about module operation and applications. Refer to Freescale publication vanced Microcontroller Unit (AMCU) Literature (BR1116/D BR1116/D) for a complete listing of documentation. MC68332 MC68332 USER'S MANUAL INTRODUCTION For More Information On This Product, Go to: www.freescale.com 1-1 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. INTRODUCTION 1-2 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL Freescale Semiconductor, Inc. SECTION 2 NOMENCLATURE The following nomenclature is used throughout the manual. Nomenclature used only in certain sections, such as register bit mnemonics, is defined in those sections. Freescale Semiconductor, Inc. 2.1 Symbols and Operators + * / > < = · ; NOT : ± « % $ - - - - - - - - - - - - - - - - - - - - - Addition Subtraction or negation (two's complement) Multiplication Division Greater Less Equal Equal or greater Equal or less Not equal AND Inclusive OR (OR) Exclusive OR (EOR) Complementation Concatenation Transferred Exchanged Sign bit; also used to show tolerance Sign extension Binary value Hexadecimal value MC68332 MC68332 USER'S MANUAL NOMENCLATURE For More Information On This Product, Go to: www.freescale.com 2-1 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. 2.2 CPU32 CPU32 Registers A6­A0 A7 (SSP) A7 (USP) CCR D7­D0 DFC PC SFC SR VBR X N Z V C - - - - - - - - - - - - - - - Address registers (Index registers) Supervisor Stack Pointer User Stack Pointer Condition code register (user portion of SR) Data Registers (Index registers) Alternate function code register Program counter Alternate function code register Status register Vector base register Extend indicator Negative indicator Zero indicator Two's complement overflow indicator Carry/borrow indicator NOMENCLATURE 2-2 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. 2.3 Pin and Signal Mnemonics ADDR[23:0] AS AVEC BERR BG BGACK BKPT BR CLKOUT CS[10:0] CSBOOT DATA[15:0] DS DSACK[1:0] DSCLK DSI DSO EXTAL FC[2:0] FREEZE HALT IFETCH IPIPE IRQ[7:1] MISO MODCLK MOSI PC[6:0] PCS[3:0] PE[7:0] PF[7:0] PQS[7:0] QUOT R/W RESET RMC RXD SCK SIZ[1:0] SS T2CLK TPUCH[15:0] TSC TXD XFC XTAL MC68332 MC68332 USER'S MANUAL - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Address Bus Address Strobe Autovector Bus Error Bus Grant Bus Grant Acknowledge Breakpoint Bus Request System Clock Chip Selects Boot ROM Chip Select Data Bus Data Strobe Data and Size Acknowledge Development Serial Clock Development Serial Input Development Serial Output External Crystal Oscillator Connection Function Codes Freeze Halt Instruction Fetch Instruction Pipeline Interrupt Request Master In Slave Out Clock Mode Select Master Out Slave In SIM I/O Port C Peripheral Chip Selects SIM I/O Port E SIM I/O Port F QSM I/O Port Quotient Out Read/Write Reset Read-Modify-Write Cycle SCI Receive Data QSPI Serial Clock Size Slave Select TPU Clock In TPU Channel Signals Three-State Control SCI Transmit Data External Filter Capacitor External Crystal Oscillator Connection NOMENCLATURE For More Information On This Product, Go to: www.freescale.com 2-3 Freescale Semiconductor, Inc. 2.4 Register Mnemonics Freescale Semiconductor, Inc. CFSR[0:3] CIER CISR CPR[0:1] CREG CR[0:F] CSBARBT CSBAR[0:10] CSORBT CSOR[0:10] CSPAR[0:1] DCNR DDRE DDRF DDRQS DREG DSCR DSSR HSQR[0:1] HSRR[0:1] LR PEPAR PFPAR PICR PITR PORTC PORTE PORTF PORTQS PQSPAR QILR QIVR QSMCR QTEST RR[0:F] RSR SCCR[0:1] SCDR SCSR SGLR SIMCR SIMTR SIMTRE SPCR[0:3] SPSR - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Channel Function Select Registers [0:3] Channel Interrupt Enable Register Channel Interrupt Status Register Channel Priority Registers [0:1] Test Control Register C QSM Command RAM Chip-Select Base Address Register Boot ROM Chip-Select Base Address Registers [0:10] Chip-Select Option Register Boot ROM Chip-Select Option Registers [0:10] Chip-Select Pin Assignment Registers [0:1] Decoded Channel Number Register Port E Data Direction Register Port F Data Direction Register Port QS Data Direction Register SIM Test Module Distributed Register Development Support Control Register Development Support Status Register Host Sequence Registers [0:1] Host Service Request Registers [0:1] Link Register Port E Pin Assignment Register Port F Pin Assignment Register Periodic Interrupt Control Register Periodic Interrupt Timer Register Port C Data Register Port E Data Register Port F Data Register Port QS Data Register Port QS Pin Assignment Register QSM Interrupt Level Register QSM Interrupt Vector Register QSM Configuration Register QSM Test Register QSM Receive Data RAM Reset Status Register SCI Control Registers [0:1] SCI Data Register SCI Status Register Service Grant Latch Register SIM Module Configuration Register System Integration Test Register System Integration Test Register (ECLK) QSPI Control Registers [0:3] QSPI Status Register NOMENCLATURE 2-4 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. SWSR SYNCR SYPCR TCR TICR TPUMCR TRAMBAR TRAMMCR TRAMTST TR[0:F] TSTMSRA TSTMSRB TSTRC TSTSC - - - - - - - - - - - - - - Software Watchdog Service Register Clock Synthesizer Control Register System Protection Control Register TPU Test Configuration Register TPU Interrupt Configuration Register TPU Module Configuration Register TPURAM Base Address/Status Register TPURAM Module Configuration Register TPURAM Test Register QSM Transmit Data RAM Test Module Master Shift Register A Test Module Master Shift Register B Test Module Repetition Counter Test Module Shift Count Register 2.5 Conventions Logic level one is the voltage that corresponds to a Boolean true (1) state. Logic level zero is the voltage that corresponds to a Boolean false (0) state. Set refers specifically to establishing logic level one on a bit or bits. Clear refers specifically to establishing logic level zero on a bit or bits. Asserted means that a signal is in active logic state. An active low signal changes from logic level one to logic level zero when asserted, and an active high signal changes from logic level zero to logic level one. Negated means that an asserted signal changes logic state. An active low signal changes from logic level zero to logic level one when negated, and an active high signal changes from logic level one to logic level zero. A specific mnemonic within a range is referred to by mnemonic and number. A15 is bit 15 of accumulator A; ADDR7 is line 7 of the address bus; CSOR0 is chip-select option register 0. A range of mnemonics is referred to by mnemonic and the numbers that define the range. AM[35:30] are bits 35 to 30 of accumulator M; CSOR[0:5] are the first six option registers Parentheses are used to indicate the content of a register or memory location, rather than the register or memory location itself. (A) is the content of accumulator A. (M : M + 1) is the content of the word at address M. LSB means least significant bit or bits. MSB means most significant bit or bits. References to low and high bytes are spelled out. LSW means least significant word or words. MSW means most significant word or words. ADDR is the address bus. ADDR[7:0] are the eight LSB of the address bus. DATA is the data bus. DATA[15:8] are the eight MSB of the data bus. MC68332 MC68332 USER'S MANUAL NOMENCLATURE For More Information On This Product, Go to: www.freescale.com 2-5 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. NOMENCLATURE 2-6 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL Freescale Semiconductor, Inc. SECTION 3 OVERVIEW Freescale Semiconductor, Inc. This section contains information about the entire modular microcontroller. It lists the features of each module, shows device functional divisions and pin assignments, summarizes signal and pin functions, discusses the intermodule bus, and provides system memory maps. Timing and electrical specifications for the entire microcontroller and for individual modules are provided in APPENDIX A ELECTRICAL CHARACTERISTICS. Comprehensive module register descriptions and memory maps are provided in APPENDIX D REGISTER SUMMARY. 3.1 MC68332 MC68332 Features The following paragraphs highlight capabilities of each of the microcontroller modules. Each module is discussed separately in a subsequent section of this user's manual. 3.1.1 System Integration Module (SIM) · External Bus Support · Programmable Chip-Select Outputs · System Protection Logic · Watchdog Timer, Clock Monitor, and Bus Monitor · System Protection Logic · System Clock Based on 32.768-kHz Crystal for Low Power Operation · Test/Debug Submodule for Factory/User Test and Development 3.1.2 Central Processing Unit (CPU) · Upward Object Code Compatible · New Instructions for Controller Applications · 32-Bit Architecture · Virtual Memory Implementation · Loop Mode of Instruction Execution · Table Lookup and Interpolate Instruction · Improved Exception Handling for Controller Applications · Trace on Change of Flow · Hardware Breakpoint Signal, Background Mode · Fully Static Operation 3.1.3 Time Processor Unit (TPU) · Dedicated Microengine Operating Independently of CPU32 CPU32 · 16 Independent, Programmable Channels and Pins · Any Channel can Perform any Time Function · Two Timer Count Registers with Programmable Prescalers · Selectable Channel Priority Levels MC68332 MC68332 USER'S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-1 Freescale Semiconductor, Inc. 3.1.4 Queued Serial Module (QSM) · Enhanced Serial Communication Interface (SCI), Universal Asynchronous Receiver Transmitter (UART): Modulus Baud Rate, Parity · Queued Serial Peripheral Interface (SPI): 80-Byte RAM, Up to 16 Automatic Transfers · Dual Function I/O Ports · Continuous Cycling, 8­16 Bits per Transfer Freescale Semiconductor, Inc. 3.1.5 Static RAM Module with TPU Emulation Capability (TPURAM) · 2-Kbytes of Static RAM · May be Used as Normal RAM or TPU Microcode Emulation RAM 3.2 System Block Diagram and Pin Assignment Diagrams Figure 3-1 is a functional diagram of the MCU. Although diagram blocks represent the relative size of the physical modules, there is not a one-to-one correspondence between location and size of blocks in the diagram and location and size of integratedcircuit modules. Figure 3-2 shows the pin assignments of the 132-pin plastic surfacemount package. Figure 3-3 shows the pin assignments of the 144-pin plastic surfacemount package. Refer to APPENDIX B MECHANICAL DATA AND ORDERING INFORMATION for package dimensions. All pin functions and signal names are shown in this drawing. Refer to subsequent paragraphs in this section for pin and signal descriptions. OVERVIEW 3-2 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL Freescale Semiconductor, Inc. VSTBY CHIP SELECTS TPUCH[15:0] TPUCH[15:0] T2CLK FC2 FC1 FC0 2 KBYTES RAM TPU SIZ1 SIZ0 DS AS RMC AVEC DSACK1 DSACK0 EBI RXD PQS7/TXD PQS6/PCS3 PQS5/PCS2 PQS4/PCS1 PQS3/PCS0/SS PQS2/SCK PQS1/MOSI PQS0/MISO PORT QS CONTROL IMB TXD PCS3 PCS2 PCS1 PCS0/SS SCK MOSI MISO DATA[15:0] CONTROL PORT F CPU 32 MODCLK BKPT IFETCH IPIPE DSI DSO DSCLK FREEZE CLOCK R/W RESET HALT BERR PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/MODCLK CLKOUT XTAL EXTAL XFC VDDSYN TSC CONTROL BKPT/DSCLK IFETCH/DSI IPIPE/DSO TSC TEST QUOT PE7/SIZ1 PE6/SIZ0 PE5/DS PE4/AS PE3/RMC PE2/AVEC PE1/DSACK1 PE0/DSACK0 DATA[15:0] IRQ[7:1] QSM CSBOOT ADDR23/CS10 ADDR23/CS10 PC6/ADDR22/CS9 PC6/ADDR22/CS9 PC5/ADDR21/CS8 PC5/ADDR21/CS8 PC4/ADDR20/CS7 PC4/ADDR20/CS7 PC3/ADDR19/CS6 PC3/ADDR19/CS6 PC2/FC2/CS5 PC1/FC1/CS4 PC0/FC0/CS3 BGACK/CS2 BG/CS1 BR/CS0 ADDR[18:0] CONTROL PORT E ADDR[23:0] CONTROL Freescale Semiconductor, Inc. ADDR[23:19] T2CLK CONTROL PORT C BR BG BGACK CS[10:0] FREEZE/QUOT 332 BLOCK Figure 3-1 MCU Block Diagram MC68332 MC68332 USER'S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-3 ADDR23/CS10 ADDR23/CS10 PC6/ADDR22/CS9 PC6/ADDR22/CS9 PC5/ADDR21/CS8 PC5/ADDR21/CS8 PC4/ADDR20/CS7 PC4/ADDR20/CS7 PC3/ADDR19/CS6 PC3/ADDR19/CS6 PC2/FC2/CS5 PC1/FC1/CS4 PC0/FC0/CS3 VSS TPUCH12 TPUCH12 TPUCH13 TPUCH13 TPUCH14 TPUCH14 TPUCH15 TPUCH15 T2CLK VSS VDD TPUCH8 TPUCH9 TPUCH10 TPUCH10 TPUCH11 TPUCH11 VSS VDD TPUCH0 TPUCH1 TPUCH2 TPUCH3 TPUCH4 TPUCH5 TPUCH6 TPUCH7 VSS VDD 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 MC68332 MC68332 VDD BGACK/CS2 BG/CS1 BR/CS0 CSBOOT DATA0 DATA1 DATA2 DATA3 VDD VSS DATA4 DATA5 DATA6 DATA7 VSS DATA8 DATA9 DATA10 DATA10 DATA11 DATA11 VDD VSS DATA12 DATA12 DATA13 DATA13 DATA14 DATA14 DATA15 DATA15 ADDR0 PE0/DSACK0 PE1/DSACK1 PE2/AVEC PE3/RMC PE5/DS VDD EXTAL VDD XFC VDD CLKOUT VSS RESET HALT BERR PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/MODCLK R/W PE7/SIZ1 PE6/SIZ0 AS VSS 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 VDD VSTBY ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 VDD VSS ADDR9 ADDR10 ADDR10 ADDR11 ADDR11 ADDR12 ADDR12 VSS ADDR13 ADDR13 ADDR14 ADDR14 ADDR15 ADDR15 ADDR16 ADDR16 VDD VSS ADDR17 ADDR17 ADDR18 ADDR18 PQS0/MISO PQS1/MOSI PQS2/SCK PQS3/PCS0/SS PQS4/PCS1 PQS5/PCS2 PQS6/PCS3 VDD VSS PQS7/TXD RXD IPIPE/DSO IFETCH/DSI BKPT/DSCLK TSC FREEZE/QUOT VSS XTAL VDDSYN Freescale Semiconductor, Inc. 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 VSS Freescale Semiconductor, Inc. 332 132-PIN 132-PIN QFP Figure 3-2 Pin Assignments for 132-Pin Package OVERVIEW 3-4 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 MC68332 MC68332 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC VSS PE4/AS PE6/SIZ0 PE7/SIZ1 R/W PF0/MODCLK PF1/IRQ1 PF2/IRQ2 PF3/IRQ3 PF4/IRQ4 PF5/IRQ5 PF6/IRQ6 PF7/IRQ7 BERR HALT RESET VSS CLKOUT VDD NC XFC VDD EXTAL VDD XTAL VSS FREEZE/QUOT TSC BKPT/DSCLK IFETCH/DSI IPIPE/DSO RXD PQS7/TXD VSS NC 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 NC VSS FC0/CS3 FC1/CS4 FC2/CS5 ADDR19/CS6 ADDR19/CS6 ADDR20/CS7 ADDR20/CS7 ADDR21/CS8 ADDR21/CS8 ADDR22/CS9 ADDR22/CS9 ADDR23/CS10 ADDR23/CS10 VDD VSS T2CLK TPUCH15 TPUCH15 TPUCH14 TPUCH14 TPUCH13 TPUCH13 TPUCH12 TPUCH12 NC VDD VSS TPUCH11 TPUCH11 TPUCH10 TPUCH10 TPUCH9 TPUCH8 VDDE VSSE TPUCH7 TPUCH6 TPUCH5 TPUCH4 TPUCH3 TPUCH2 TPUCH1 TPUCH0 VSS NC VDD VSTBY ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 VDD VSS ADDR9 ADDR10 ADDR10 ADDR11 ADDR11 ADDR12 ADDR12 NC VSS NC ADDR13 ADDR13 ADDR14 ADDR14 ADDR15 ADDR15 NC ADDR16 ADDR16 VDD VSS ADDR17 ADDR17 ADDR18 ADDR18 PQS0/MISO PQS1/MOSI PQS2/SCK PQS3/PCS0/SS PQS4/PCS1 PQS5/PCS2 PQS6/PCS3 VDD Freescale Semiconductor, Inc. VDD BGACK/CS2 BG/CS1 BR/CS0 CSBOOT DATA0 DATA1 DATA2 DATA3 VDD VSS DATA4 DATA5 DATA6 DATA7 NC VSS DATA8 NC DATA9 DATA10 DATA10 NC DATA11 DATA11 VDD VSS DATA12 DATA12 DATA13 DATA13 DATA14 DATA14 DATA15 DATA15 ADDR0 PE0/DSACK0 PE1/DSACK1 PE2/AVEC PE3/RMC PE5/DS VDD Freescale Semiconductor, Inc. 332 144-PIN 144-PIN QFP Figure 3-3 Pin Assignments for 144-Pin Package 3.3 Pin Descriptions The following tables summarize functional characteristics of MCU pins. Table 3-1 shows types of output drivers. Table 3-2 shows all inputs and outputs. Digital inputs and outputs use CMOS logic levels. An entry in the Discrete I/O column indicates that a pin can also be used for general-purpose input, output, or both. The I/O port designation is given when it applies. Table 3-3 shows characteristics of power pins. Refer to Figure 3-1 for port organization. MC68332 MC68332 USER'S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-5 Freescale Semiconductor, Inc. Table 3-1 MCU Driver Types Type A Aw B I/O O O O Bo O Description Output-only signals that are always driven; no external pull-up required Type A output with weak P-channel pull-up during reset Three-state output that includes circuitry to pull up output before high impedance is established, to ensure rapid rise time. An external holding resistor is required to maintain logic level while the pin is in the high-impedance state. Type B output that can be operated in an open-drain mode Table 3-2 MCU Pin Characteristics Freescale Semiconductor, Inc. Pin Mnemonic ADDR23/CS10/ECLK ADDR23/CS10/ECLK ADDR[22:19]/CS[9:6] ADDR[18:0] AS AVEC BERR BG/CS1 BGACK/CS2 BKPT/DSCLK BR/CS0 CLKOUT CSBOOT DATA[15:0]1 DS DSACK1 DSACK0 DSI/IFETCH DSO/IPIPE EXTAL2 FC[2:0]/CS[5:3] FREEZE/QUOT HALT IRQ[7:1] MISO MODCLK1 MOSI PCS0/SS PCS[3:1] R/W RESET RMC RXD SCK SIZ[1:0] T2CLK TPUCH[15:0] TSC Output Driver A A A B B B B B - B A B Aw Input Synchronized Y Y Y Y Y Y - Y Y Y - - Y Input Hysteresis N N N N N N - N Y N - - N Discrete I/O O O - I/O I/O - - - - - - - - Port Designation - PC[6:3] - PE5 PE2 - - - - - - - - B B B A A - Y Y Y Y - - N N N Y - Special I/O I/O I/O - - - PE4 PE1 PE0 - - - A A Bo B Bo B Y - Y Y Y Y N - N Y Y N O - - I/O I/O I/O PC[2:0] - - PF[7:1] PQS0 PF0 Bo Bo Bo A Bo B - Bo B - A - Y Y Y Y Y Y N Y Y Y Y Y Y Y Y N Y N N Y N Y Y Y I/O I/O I/O - - I/O - I/O I/O - - - PQS1 PQS3 PQS[6:4] - - PE3 - PQS2 PE[7:6] - - - OVERVIEW 3-6 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL Freescale Semiconductor, Inc. Table 3-2 MCU Pin Characteristics (Continued) Pin Mnemonic TXD XFC2 Output Driver Bo - Input Synchronized Y - Input Hysteresis Y - Discrete I/O I/O Special Port Designation PQS7 - XTAL2 - - - Special - NOTES: 1. DATA[15:0] are synchronized during reset only. MODCLK is synchronized only when used as an input port pin. 2. EXTAL, XFC, and XTAL are clock reference connections. Table 3-3 MCU Power Connections Freescale Semiconductor, Inc. Pin Mnemonic VSTBY Description Standby RAM Power VDDSYN Clock Synthesizer Power VSSE/VDDE External Periphery Power (Source and Drain) VSSI/VDDI Internal Module Power (Source and Drain) 3.4 Signal Descriptions The following tables define MCU signals. Table 3-4 shows signal origin, type, and active state. Table 3-5 describes signal functions. Both tables are sorted alphabetically by mnemonic. MCU pins often have multiple functions. More than one description can apply to a pin. Table 3-4 MCU Signal Characteristics Signal Name ADDR[23:0] AS AVEC BERR BG BGACK BKPT BR CLKOUT CS[10:0] CSBOOT DATA[15:0] DS DSACK[1:0] DSCLK DSI DSO EXTAL FC[2:0] FREEZE HALT MC68332 MC68332 USER'S MANUAL MCU Module SIM SIM SIM SIM SIM SIM CPU32 CPU32 SIM SIM SIM SIM SIM SIM SIM CPU32 CPU32 CPU32 CPU32 CPU32 CPU32 SIM SIM SIM SIM Signal Type Bus Output Input Input Output Input Input Input Output Output Output Bus Output Input Input Input Output Input Output Output Input/Output Active State - 0 0 0 0 0 0 0 - 0 0 - 0 0 Serial Clock (Serial Data) (Serial Data) - - 1 0 OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-7 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. Table 3-4 MCU Signal Characteristics (Continued) Signal Name IFETCH IPIPE IRQ[7:1] MISO MODCLK MOSI PC[6:0] PCS[3:0] PE[7:0] PF[7:0] PQS[7:0] QUOT RESET RMC R/W RXD SCK SIZ[1:0] SS T2CLK TPUCH[15:0] TSC TXD XFC XTAL MCU Module CPU32 CPU32 CPU32 CPU32 SIM QSM SIM QSM SIM QSM SIM SIM QSM SIM SIM SIM SIM QSM QSM SIM QSM TPU TPU SIM QSM SIM SIM Signal Type Output Output Input Input/Output Input Input/Output Output Input/Output Input/Output Input/Output Input/Output Output Input/Output Output Output Input Input/Output Output Input Input Input/Output Input Output Input Output Active State - - 0 - - - (Port) - (Port) (Port) (Port) - 0 0 1/0 - - - 0 - 1 - - - - Table 3-5 MCU Signal Function Signal Name Address Bus Address Strobe Autovector Bus Error Bus Grant Bus Grant Acknowledge Breakpoint Bus Request System Clockout Chip Selects Boot Chip Select Data Bus Data Strobe Data and Size Acknowledge Development Serial In, Out, Clock Crystal Oscillator Mnemonic ADDR[23:0] AS AVEC BERR BG BGACK BKPT BR CLKOUT CS[10:0] CSBOOT DATA[15:0] DS Function 24-bit address bus Indicates that a valid address is on the address bus Requests an automatic vector during interrupt acknowledge Indicates that a bus error has occurred Indicates that the MCU has relinquished the bus Indicates that an external device has assumed bus mastership Signals a hardware breakpoint to the CPU Indicates that an external device requires bus mastership System clock output Select external devices at programmed addresses Chip select for external boot start-up ROM 16-bit data bus During a read cycle, indicates when it is possible for an external device to place data on the data bus. During a write cycle, indicates that valid data is on the data bus. Provide asynchronous data transfers and dynamic bus sizing Serial I/O and clock for background debugging mode DSACK[1:0] DSI, DSO, DSCLK EXTAL, XTAL Connections for clock synthesizer circuit reference; a crystal or an external oscillator can be used OVERVIEW 3-8 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL Freescale Semiconductor, Inc. Table 3-5 MCU Signal Function (Continued) Signal Name Function Codes Freeze Halt Instruction Pipeline Interrupt Request Level Master In Slave Out Mnemonic FC[2:0] FREEZE HALT IPIPE, IFETCH IRQ[7:1] MISO Freescale Semiconductor, Inc. Clock Mode Select Master Out Slave In MODCLK MOSI Port C Auxiliary Timer Clock Input Peripheral Chip Select Port E Port F Port QS Quotient Out Reset Read-Modify-Write Cycle Read/Write SCI Receive Data QSPI Serial Clock PC[6:0] PCLK PCS[3:0] PE[7:0] PF[7:0] PQS[7:0] QUOT RESET RMC R/W RXD SCK Size Slave Select SIZ[1:0] SS TCR2 Clock TPU Channel Pins Three-State Control SCI Transmit Data External Filter Capacitor T2CLK TPUCH[15:0] TSC TXD XFC Function Identify processor state and current address space Indicates that the CPU has entered background mode Suspend external bus activity Indicate instruction pipeline activity Provides an interrupt priority level to the CPU Serial input to QSPI in master mode; serial output from QSPI in slave mode Selects the source and type of system clock Serial output from QSPI in master mode; serial input to QSPI in slave mode SIM digital output port signals External clock dedicated to the GPT QSPI peripheral chip selects SIM digital I/O port signals SIM digital I/O port signals QSM digital I/O port signals Provides the quotient bit of the polynomial divider System reset Indicates an indivisible read-modify-write instruction Indicates the direction of data transfer on the bus Serial input to the SCI Clock output from QSPI in master mode; clock input to QSPI in slave mode Indicates the number of bytes to be transferred during a bus cycle Causes serial transmission when QSPI is in slave mode; causes mode fault in master mode External clock source for TCR2 counter Bidirectional pins associated with TPU channels Places all output drivers in a high-impedance state Serial output from the SCI Connection for external phase-locked loop filter capacitor 3.5 Intermodule Bus The intermodule bus (IMB) is a standardized bus developed to facilitate both design and operation of modular microcontrollers. It contains circuitry to support exception processing, address space partitioning, multiple interrupt levels, and vectored interrupts. The standardized modules in the MCU communicate with one another and with external components through the IMB. The IMB in the MCU uses 24 address and 16 data lines. 3.6 System Memory Map Figure 3-4 through Figure 3-8 are MCU memory maps. Figure 3-4 shows IMB addresses of internal registers. Figure 3-5 through Figure 3-8 show system memory maps that use different external decoding schemes. MC68332 MC68332 USER'S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-9 Freescale Semiconductor, Inc. 3.6.1 Internal Register Map In Figure 3-4, IMB ADDR[23:20] are represented by the letter Y. The value represented by Y determines the base address of MCU module control registers. In M68300 M68300 microcontrollers, Y is equal to M111, where M is the logic state of the module mapping (MM) bit in the system integration module configuration register (SIMCR). $YFF000 YFF000 $YFFA00 YFFA00 $YFFA80 YFFA80 Freescale Semiconductor, Inc. $YFFB00 YFFB00 $YFFB40 YFFB40 SIM RESERVED TPURAM CONTROL RESERVED 2-KBYTE TPURAM ARRAY $YFFC00 YFFC00 QSM $YFFE00 YFFE00 TPU $YFFFFF 332 ADDRESS MAP Figure 3-4 Internal Register Memory Map 3.6.2 Address Space Maps Figure 3-5 shows a single memory space. Function codes FC[2:0] are not decoded externally so that separate user/supervisor or program/data spaces are not provided. In Figure 3-6, FC2 is decoded, resulting in separate supervisor and user spaces. FC[1:0] are not decoded, so that separate program and data spaces are not provided. In Figure 3-7 and Figure 3-8, FC[2:0] are decoded, resulting in four separate memory spaces: supervisor/program, supervisor/data, user/program and user/data. All exception vectors are located in supervisor data space, except the reset vector, which is located in supervisor program space. Only the initial reset vector is fixed in the processor's memory map. Once initialization is complete, there are no fixed assignments. Since the vector base register (VBR) provides the base address of the vector table, the vector table can be located anywhere in memory. Refer to SECTION 5 CENTRAL PROCESSING UNIT for more information concerning memory management, extended addressing, and exception processing. Refer to SECTION 4 SYSTEM INTEGRATION MODULE for more information concerning function codes and address space types. OVERVIEW 3-10 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL Freescale Semiconductor, Inc. $000000 VECTOR VECTOR OFFSET NUMBER 0 0000 1 0004 2 0008 3 000C 4 0010 5 0014 6 0018 7 001C 8 0020 9 0024 10 0028 11 002C 12 0030 13 0034 14 0038 15 003C 0040­005C 16­23 24 006C 25 0064 26 0068 27 006C 28 0070 29 0074 30 0078 31 007C 0080­00BC 32­47 00C0­00EB 48­58 00EC­00FC 59­63 0100­03FC 64­255 Freescale Semiconductor, Inc. COMBINED SUPERVISOR AND USER SPACE TYPE OF EXCEPTION RESET - INITIAL STACK POINTER RESET - INITIAL PC BUS ERROR ADDRESS ERROR ILLEGAL INSTRUCTION ZERO DIVISION CHK, CHK2 INSTRUCTIONS TRAPcc, TRAPV INSTRUCTIONS PRIVILEGE VIOLATION TRACE LINE 1010 EMULATOR LINE 1111 EMULATOR HARDWARE BREAKPOINT (RESERVED COPROCESSOR PROTOCOL VIOLATION) FORMAT ERROR AND UNINITIALIZED INTERRUPT FORMAT ERROR AND UNINITIALIZED INTERRUPT (UNASSIGNED, RESERVED) SPURIOUS INTERRUPT LEVEL 1 INTERRUPT AUTOVECTOR LEVEL 2 INTERRUPT AUTOVECTOR LEVEL 3 INTERRUPT AUTOVECTOR LEVEL 4 INTERRUPT AUTOVECTOR LEVEL 5 INTERRUPT AUTOVECTOR LEVEL 6 INTERRUPT AUTOVECTOR LEVEL 7 INTERRUPT AUTOVECTOR TAP INSTRUCTION VECTORS (0­15) (RESERVED, COPROCESSOR) (UNASSIGNED, RESERVED) USER-DEFINED VECTORS $XX0000 XX0000 $XX03FC XX03FC $YFF000 YFF000 $YFFA00 YFFA00 SIM $7FF000 7FF000 INTERNAL REGISTERS (MM = 0) RESERVED $YFFA80 YFFA80 TPURAM CTL $YFFB00 YFFB00 RESERVED $YFFB40 YFFB40 $YFFC00 YFFC00 QSM $YFFE00 YFFE00 TPU $FF0000 FF0000 INTERNAL REGISTERS (MM = 1) $YFFFFF $FFFFFF NOTES: 1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector base register and the vector offset. 2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configure register. Y = M111, where M is the state of the MM bit. 3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally. 332 S/U COMB MAP Figure 3-5 Overall Memory Map MC68332 MC68332 USER'S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-11 Freescale Semiconductor, Inc. $000000 Freescale Semiconductor, Inc. SUPERVISOR SPACE VECTOR VECTOR OFFSET NUMBER 0 0000 1 0004 2 0008 3 000C 4 0010 5 0014 6 0018 7 001C 8 0020 9 0024 10 0028 11 002C 12 0030 13 0034 14 0038 15 003C 0040­005C 16­23 24 006C 25 0064 26 0068 27 006C 28 0070 29 0074 30 0078 31 007C 0080­00BC 32­47 00C0­00EB 48­58 00EC­00FC 59­63 0100­03FC 64­255 TYPE OF EXCEPTION RESET - INITIAL STACK POINTER RESET - INITIAL PC BUS ERROR ADDRESS ERROR ILLEGAL INSTRUCTION ZERO DIVISION CHK, CHK2 INSTRUCTIONS TRAPcc, TRAPV INSTRUCTIONS PRIVILEGE VIOLATION TRACE LINE 1010 EMULATOR LINE 1111 EMULATOR HARDWARE BREAKPOINT (RESERVED COPROCESSOR PROTOCOL VIOLATION) FORMAT ERROR AND UNINITIALIZED INTERRUPT FORMAT ERROR AND UNINITIALIZED INTERRUPT (UNASSIGNED, RESERVED) SPURIOUS INTERRUPT LEVEL 1 INTERRUPT AUTOVECTOR LEVEL 2 INTERRUPT AUTOVECTOR LEVEL 3 INTERRUPT AUTOVECTOR LEVEL 4 INTERRUPT AUTOVECTOR LEVEL 5 INTERRUPT AUTOVECTOR LEVEL 6 INTERRUPT AUTOVECTOR LEVEL 7 INTERRUPT AUTOVECTOR TAP INSTRUCTION VECTORS (0­15) (RESERVED, COPROCESSOR) (UNASSIGNED, RESERVED) USER-DEFINED VECTORS $000000 $XX0000 XX0000 USER SPACE $XX03FC XX03FC $YFF000 YFF000 $YFFA00 YFFA00 SIM $7FF000 7FF000 INTERNAL REGISTERS INTERNAL REGISTERS RESERVED $YFFA80 YFFA80 TPURAM CTL $YFFB00 YFFB00 RESERVED $7FF0004 7FF0004 $YFFB40 YFFB40 $YFFC00 YFFC00 QSM $YFFE00 YFFE00 TPU $FF0000 FF0000 $FFFFFF INTERNAL REGISTERS $YFFFFF INTERNAL REGISTERS $FF00004 FF00004 $FFFFFF NOTES: 1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector base register and the vector offset. 2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configure register. Y = M111, where M is the state of the MM bit. 3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally. 4. Some internal registers are not available in user space. 332 S/U SEP MAP Figure 3-6 Separate Supervisor and User Space Map OVERVIEW 3-12 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL Freescale Semiconductor, Inc. VECTOR OFFSET 0000 0004 Freescale Semiconductor, Inc. $000000 SUPERVISOR DATA SPACE VECTOR NUMBER 0 1 VECTOR VECTOR OFFSET NUMBER 0 0000 1 0004 2 0008 3 000C 4 0010 5 0014 6 0018 7 001C 8 0020 9 0024 10 0028 11 002C 12 0030 13 0034 14 0038 15 003C 0040­005C 16­23 24 006C 25 0064 26 0068 27 006C 28 0070 29 0074 30 0078 31 007C 0080­00BC 32­47 00C0­00EB 48­58 00EC­00FC 59­63 0100­03FC 64­255 EXCEPTION VECTORS LOCATED IN SUPERVISOR PROGRAM SPACE RESET - INITIAL STACK POINTER RESET - INITIAL PC EXCEPTION VECTORS LOCATED IN SUPERVISOR DATA SPACE RESET - INITIAL STACK POINTER RESET - INITIAL PC BUS ERROR ADDRESS ERROR ILLEGAL INSTRUCTION ZERO DIVISION CHK, CHK2 INSTRUCTIONS TRAPcc, TRAPV INSTRUCTIONS PRIVILEGE VIOLATION TRACE LINE 1010 EMULATOR LINE 1111 EMULATOR HARDWARE BREAKPOINT (RESERVED COPROCESSOR PROTOCOL VIOLATION) FORMAT ERROR AND UNINITIALIZED INTERRUPT FORMAT ERROR AND UNINITIALIZED INTERRUPT (UNASSIGNED, RESERVED) SPURIOUS INTERRUPT LEVEL 1 INTERRUPT AUTOVECTOR LEVEL 2 INTERRUPT AUTOVECTOR LEVEL 3 INTERRUPT AUTOVECTOR LEVEL 4 INTERRUPT AUTOVECTOR LEVEL 5 INTERRUPT AUTOVECTOR LEVEL 6 INTERRUPT AUTOVECTOR LEVEL 7 INTERRUPT AUTOVECTOR TAP INSTRUCTION VECTORS (0­15) (RESERVED, COPROCESSOR) (UNASSIGNED, RESERVED) USER-DEFINED VECTORS $000000 $XX0000 XX0000 $XX0004 XX0004 $XX0000 XX0000 SUPERVISOR PROGRAM SPACE $XX03FC XX03FC $YFF000 YFF000 $YFFA00 YFFA00 SIM $7FF000 7FF000 INTERNAL REGISTERS RESERVED $YFFA80 YFFA80 TPURAM CTL $YFFB00 YFFB00 RESERVED $YFFB40 YFFB40 $YFFC00 YFFC00 QSM $YFFE00 YFFE00 TPU $FF0000 FF0000 INTERNAL REGISTERS $FFFFFF $YFFFFF $FFFFFF NOTES: 1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector base register and the vector offset. 2. Location of the module control registers is determined by the state of the module mapping (MM) bit in the SIM configure register. Y = M111, where M is the state of the MM bit. 3. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally. 4. Some internal registers are not available in user space. 332 SUPER P/D MAP Figure 3-7 Supervisor Space (Separate Program/Data Space) Map MC68332 MC68332 USER'S MANUAL OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-13 Freescale Semiconductor, Inc. $000000 $000000 Freescale Semiconductor, Inc. USER PROGRAM SPACE USER DATA SPACE $YFF000 YFF000 $YFFA00 YFFA00 SIM $7FF000 7FF000 INTERNAL REGISTERS RESERVED $YFFA80 YFFA80 TPURAM CTL $YFFB00 YFFB00 RESERVED $YFFB40 YFFB40 $YFFC00 YFFC00 QSM $YFFE00 YFFE00 TPU $FF0000 FF0000 $FFFFFF INTERNAL REGISTERS $FFFFFF $YFFFFF NOTES: 1. Location of the exception vector table is determined by the vector base register. The vector address is the sum of the vector base register and the vector offset. 2. Unused addresses within the internal register block are mapped externally. "RESERVED" blocks are not mapped externally. 3. Some internal registers are not available in user space. 332 USER P/D MAP Figure 3-8 User Space (Separate Program/Data Space) Map OVERVIEW 3-14 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL Freescale Semiconductor, Inc. 3.7 System Reset The following information is a concise reference only. MC68332 MC68332 system reset is a complex operation. To understand operation during and after reset, refer to SECTION 4 SYSTEM INTEGRATION MODULE, paragraph 4.6 Reset for more complete discussion of the reset function. 3.7.1 SIM Reset Mode Selection The logic states of certain data bus pins during reset determine SIM operating configuration. In addition, the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines what happens during subsequent breakpoint assertions. Table 3-6 is a summary of reset mode selection options. Freescale Semiconductor, Inc. Table 3-6 SIM Reset Mode Selection Mode Select Pin DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA11 DATA11 MODCLK BKPT MC68332 MC68332 USER'S MANUAL Default Function (Pin Left High) CSBOOT 16-Bit CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS[7:6] CS[8:6] CS[9:6] CS[10:6] DSACK0, DSACK1, AVEC, DS, AS, SIZ[1:0] IRQ[7:1] MODCLK Test Mode Disabled VCO = System Clock Background Mode Disabled Alternate Function (Pin Pulled Low) CSBOOT 8-Bit BR BG BGACK FC0 FC1 FC2 ADDR19 ADDR19 ADDR[20:19] ADDR[21:19] ADDR[22:19] ADDR[23:19] PORTE PORTF Test Mode Enabled EXTAL = System Clock Background Mode Enabled OVERVIEW For More Information On This Product, Go to: www.freescale.com 3-15 Freescale Semiconductor, Inc. 3.7.2 MCU Module Pin Function During Reset Generally, pins associated with modules other than the SIM default to port functions, and input/output ports are set to input state. This is accomplished by disabling pin functions in the appropriate control registers, and by clearing the appropriate port data direction registers. Refer to individual module sections in this manual for more information. Table 3-7 is a summary of module pin function out of reset. Table 3-7 Module Pin Functions Module CPU32 CPU32 Freescale Semiconductor, Inc. TPU QSM Pin Mnemonic DSI/IFETCH DSO/IPIPE BKPT/DSCLK TPUCH[15:0] T2CLK PQS7/TXD PQS[6:4]/PCS[3:1] PQS3/PCS0/SS PQS2/SCK PQS1/MOSI PQS0/MISO RXD Function DSI/IFETCH DSO/IPIPE BKPT/DSCLK TPU Input TCR2 Clock Discrete Input Discrete Input Discrete Input Discrete Input Discrete Input Discrete Input RXD OVERVIEW 3-16 For More Information On This Product, Go to: www.freescale.com MC68332 MC68332 USER'S MANUAL Freescale Semiconductor, Inc. SECTION 4 SYSTEM INTEGRATION MODULE This section is an overview of SIM function. Refer to the SIM Reference Manual (SIMRM/AD) for a comprehensive discussion of SIM capabilities. Refer to APPENDIX D REGISTER SUMMARY for information concerning the SIM address map and register structure. Freescale Semiconductor, Inc. 4.1 General The system integration module (SIM) consists of five functional blocks. Figure 4-1 is a block diagram of the SIM. The system configuration and protection block controls configuration parameters and provides bus and software watchdog monitors. In addition, it provides a periodic interrupt generator to support execution of time-critical control routines. The system clock generates clock signals used by the SIM, other IMB modules, and external devices. The external bus interface handles the transfer of information between IMB modules and external address space. EBI pins can also be configured for use as general-purpose I/O ports E and F. The chip-select block provides 12 chip-select signals. Each chip-select signal has an associated base register and option register that contain the programmable characteristics of that chip select. Chip-select pins can also be configured for use as generalpurpose output port C. The system test block incorporates hardware necessary for testing the MCU. It is used to perform factory tests, and its use in normal applications is not supported. MC68332 MC68332 USER'S MANUAL SYSTEM INTEGRATION MODULE For More Information On This Product, Go to: www.freescale.com 4-1 Freescale Semiconductor, Inc. SYSTEM CONFIGURATION AND PROTECTION CLOCK SYNTHESIZER Freescale Semiconductor, Inc. CHIP SELECTS CLKOUT EXTAL MODCLK CHIP SELECTS EXTERNAL BUS EXTERNAL BUS INTERFACE RESET FACTORY TEST TSC FREEZE/QUOT S(C)IM BLOCK Figur