M68060 MC68060 MC68LC060 MC68EC060 M68060UM/AD M68000PM/AD M68000 - Datasheet Archive

 

Including the MC68060, MC68LC060, and MC68EC060 Motorola reserves the right to make changes without further notice to any

 

M68060 M68060 User's Manual Including the MC68060 MC68060, MC68LC060 MC68LC060, and MC68EC060 MC68EC060 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. µ © MOTOROLA, 1994 68K FAX-IT Documentation Comments FAX 512-891-8593-Documentation Comments Only The Motorola High-End Technical Publications Department provides a fax number for you to submit any questions or comments about this document or how to order other documents. We welcome your suggestions for improving our documentation. Please do not fax technical questions. Please provide the part number and revision number (located in upper right-hand corner of the cover) and the title of the document. When referring to items in the manual, please reference by the page number, paragraph number, figure number, table number, and line number if needed. When sending a fax, please provide your name, company, fax number, and phone number including area code. Applications and Technical Information For questions or comments pertaining to technical information, questions, and applications, please contact one of the following sales offices nearest you. MOTOROLA M68060 M68060 USER'S MANUAL iii - Sales Offices - Field Applications Engineering Available Through All Sales Offices UNITED STATES ALABAMA, Huntsville ARIZONA, Tempe CALIFORNIA, Agoura Hills CALIFORNIA, Los Angeles CALIFORNIA, Irvine CALIFORNIA, Rosevllle CALIFORNIA, San Diego CALIFORNIA, Sunnyvale COLORADO, Colorado Springs COLORADO, Denver CONNECTICUT, Wallingford FLORIDA, Maitland FLORIDA, Pompano Beach/ Fort Lauderdale FLORIDA, Clearwater GEORGlA, Atlanta IDAHO, Boise ILLINOIS, Chicago/Hoffman Estates INDlANA, Fort Wayne INDIANA, Indianapolis INDIANA, Kokomo IOWA, Cedar Rapids KANSAS, Kansas City/Mission MARYLAND, Columbia MASSACHUSETTS, Marborough MASSACHUSETTS, Woburn MICHIGAN, Detroit MINNESOTA, Minnetonka MISSOURI, St. Louis NEW JERSEY, Fairfield NEW YORK, Fairport NEW YORK, Hauppauge NEW YORK, Poughkeepsie/Fishkill NORTH CAROLINA, Raleigh OHIO, Cleveland OHIO, Columbus/Worthington OHIO, Dayton OKLAHOMA, Tulsa OREGON, Portland PENNSYLVANIA, Colmar Philadelphia/Horsham TENNESSEE, Knoxville TEXAS, Austin TEXAS, Houston TEXAS, Plano VIRGINIA, Richmond WASHINGTON, Bellevue Seattle Access WISCONSIN, Milwaukee/Brookfield CANADA BRITISH COLUMBIA, Vancouver ONTARIO, Toronto ONTARIO, Ottawa QUEBEC, Montreal INTERNATIONAL AUSTRALIA, Melbourne AUSTRALIA, Sydney BRAZIL, Sao Paulo CHINA, Beijing FINLAND, Helsinki Car Phone FRANCE, Paris/Vanves iv (205) 464-6800 (602) 897-5056 (818) 706-1929 (310) 417-8848 (714) 753-7360 (916) 922-7152 (619) 541-2163 (408) 749-0510 (719) 599-7497 (303) 337-3434 (203) 949-4100 (407) 628-2636 (305) 486-9776 (813) 538-7750 (404) 729-7100 (208) 323-9413 (708) 490-9500 (219) 436-5818 (317) 571-0400 (317) 457-6634 (319) 373-1328 (913) 451-8555 (410) 381-1570 (508) 481-8100 (617) 932-9700 (313) 347-6800 (612) 932-1500 (314) 275-7380 (201) 808-2400 (716) 425-4000 (516) 361-7000 (914) 473-8102 (919) 870-4355 (216) 349-3100 (614) 431-8492 (513) 495-6800 (800) 544-9496 (503) 641-3681 (215) 997-1020 (215) 957-4100 (615) 690-5593 (512) 873-2000 (800) 343-2692 (214) 516-5100 (804) 285-2100 (206) 454-4160 (206) 622-9960 (414) 792-0122 (604) 293-7605 (416) 497-8181 (613) 226-3491 (514) 731-6881 (61-3)887-0711 (61(2)906-3855 55(11)815-4200 86 505-2180 358-0-35161191 358(49)211501 33(1)40 955 900 GERMANY, Langenhagen/ Hanover 49(511)789911 GERMANY, Munich 49 89 92103-0 GERMANY, Nuremberg 49 911 64-3044 GERMANY, Sindelfingen 49 7031 69 910 GERMANY, Wiesbaden 49 611 761921 HONG KONG, Kwai Fong 852-4808333 Tai Po 852-6668333 INDIA, Bangalore (91-812)627094 ISRAEL, Tel Aviv 972(3)753-8222 ITALY, Milan 39(2)82201 JAPAN, Aizu 81(241)272231 JAPAN, Atsugi 81(0462)23-0761 JAPAN, Kumagaya 81(0485)26-2600 JAPAN, Kyushu 81(092)771-4212 JAPAN, Mito 81(0292)26-2340 JAPAN, Nagoya 81(052)232-1621 JAPAN, Osaka 81(06)305-1801 JAPAN, Sendai 81(22)268-4333 JAPAN, Tachikawa 81(0425)23-6700 JAPAN, Tokyo 81(03)3440-3311 JAPAN, Yokohama 81(045)472-2751 KOREA, Pusan 82(51)4635-035 KOREA, Seoul 82(2)554-5188 MALAYSIA, Penang 60(4)374514 MEXICO, Mexico City 52(5)282-2864 MEXICO, Guadalajara 52(36)21-8977 Marketing 52(36)21-9023 Customer Service 52(36)669-9160 NETHERLANDS, Best (31)49988 612 11 PUERTO RICO, San Juan (809)793-2170 SINGAPORE (65)2945438 SPAIN, Madrid 34(1)457-8204 or 34(1)457-8254 SWEDEN, Solna 46(8)734-8800 SWITZERLAND, Geneva 41(22)7991111 SWITZERLAND, Zurich 41(1)730 4074 TAlWAN, Taipei 886(2)717-7089 THAILAND, Bangkok (66-2)254-4910 UNITED KINGDOM, Aylesbury 44(296)395-252 FULL LINE REPRESENTATIVES COLORADO, Grand Junction Cheryl Lee Whltely (303) 243-9658 KANSAS, Wichita Melinda Shores/Kelly Greiving (316) 838 0190 NEVADA, Reno Galena Technology Group (702) 746 0642 NEW MEXICO, Albuquerque S&S Technologies, lnc. (505) 298-7177 UTAH, Salt Lake City Utah Component Sales, Inc. (801) 561-5099 WASHINGTON, Spokane Doug Kenley (509) 924-2322 ARGENTINA, Buenos Aires Argonics, S.A. (541) 343-1787 HYBRID COMPONENTS RESELLERS Elmo Semiconductor (818) 768-7400 Minco Technology Labs Inc. (512) 834-2022 Semi Dice Inc. (310) 594-4631 M68060 M68060 USER'S MANUAL MOTOROLA PREFACE The complete documentation package for the MC68060 MC68060, MC68LC060 MC68LC060, and MC68EC060 MC68EC060 (collectively called M68060 M68060) consists of the M68060UM/AD M68060UM/AD, M68060 M68060 User's Manual, and the M68000PM/AD M68000PM/AD, M68000 M68000 Family Programmer's Reference Manual. The M68060 M68060 User's Manual describes the capabilities, operation, and programming of the M68060 M68060 superscalar 32-bit microprocessors. The M68000 M68000 Family Programmer's Reference Manual contains the complete instruction set for the M68000 M68000 family. The introduction of this manual includes general information concerning the MC68060 MC68060 and summarizes the differences among the M68060 M68060 family devices. Additionally, appendices provide detailed information on how these M68060 M68060 derivatives operate differently from the MC68060 MC68060. When reading this manual, disregard information concerning the floating-point unit in reference to the MC68LC060 MC68LC060, and disregard information concerning the floating-point unit and memory management unit in reference to the MC68EC060 MC68EC060. The organization of this manual is as follows: Section 1 Introduction Section 2 Signal Description Section 3 Integer Unit Section 4 Memory Management Unit Section 5 Caches Section 6 Floating-Point Unit Section 7 Bus Operation Section 8 Exception Processing Section 9 IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes Section 10 Instruction Timings Section 11 Applications Section 12 Electrical and Thermal Characteristics Section 13 Ordering Information and Mechanical Data Appendix A MC68LC060 MC68LC060 Appendix B MC68EC060 MC68EC060 Appendix C MC68060 MC68060 Software Package Appendix D M68060 M68060 Instructions MOTOROLA M68060 M68060 USER'S MANUAL v MC68060 MC68060 ACRONYM LIST AGU-address generation unit ALU-arithmetic logic unit ATC-address translation cache BUSCR-bus control register CACR-cache control register CCR-condition code register CM-cache mode CPU-central processing unit DFC-destination function code DTTx-data transparent translation register DRAM-dynamic random access memory FPIAR-floating-point instruction address register FPCR-floating-point control register FPSP-floating-point software package FPSR-floating-point status register FPU-floating-point unit FP7­FP0-floating-point data registers 7­0 FSLW-fault status long word IEE-integer execute unit IFP-instruction fetch pipeline IFU-instruction fetch unit IPU-instruction pipe unit ISP-interrupt stack pointer ITTR-instruction transparent translation register IU-integer unit JTAG-Joint Test Action Group MMU-memory management unit MOTOROLA M68060 M68060 USER'S MANUAL vii MC68060 MC68060 Acronym List MMUSR-memory management unit status register M68060SP-M68060 M68060SP-M68060 software package NANs-not-a-numbers NOP-no operation OEP-operand execution pipeline OPU-operand pipe unit PC-program counter PCR-processor configuration register PGI-page index field PI-pointer index field PLL-phase-locked loop pOEP-primary operand execution pipeline RI-root index field SFC-source function code SNAN-signaling not-a-number sOEP-secondary operand execution pipeline SP-stack pointer SR-status register SRP-supervisor root pointer register SSP-supervisor stack pointer TAP-test access port TCR-translation control register TTL-transistor-transistor logic TTR-transparent translation register UPA-user page attribute URP-user root pointer register USP-user stack pointer VBR-vector base register VLSI-very large-scale integration viii M68060 M68060 USER'S MANUAL MOTOROLA TABLE OF CONTENTS Section 1 Introduction 1.1 1.1.1 1.1.2 1.1.2.1 1.1.2.2 1.2 1.3 1.4 1.4.1 1.4.2 1.4.2.1 1.4.2.2 1.4.2.3 1.4.2.4 1.4.2.5 1.4.2.6 1.4.2.6.1 1.4.2.6.2 1.4.3 1.5 1.6 1.7 1.8 1.9 1.10 Differences Among M68060 M68060 Family Members. 1-3 MC68LC060 MC68LC060. 1-3 MC68EC060 MC68EC060 . 1-3 Address Translation Differences . 1-3 Instruction Differences . 1-3 Features. 1-4 Architecture. 1-4 Processor Overview. 1-5 Functional Blocks. 1-5 Integer Unit . 1-7 Instruction Fetch Unit. 1-7 Integer Unit . 1-8 Floating-Point Unit . 1-8 Memory Units . 1-9 Address Translation Caches . 1-9 Instruction and Data Caches . 1-9 Cache Organization. 1-10 Cache Coherency. 1-10 Bus Controller . 1-10 Processing States . 1-10 Programming Model. 1-11 Data Format Summary. 1-14 Addressing Capabilities Summary . 1-14 Instruction Set Overview . 1-15 Notational Conventions. 1-21 Section 2 Signal Description 2.1 2.1.1 2.1.2 2.2 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 MOTOROLA Address and Control Signals . 2-3 Address Bus (A31­A0) . 2-3 Cycle Long-Word Address (CLA) . 2-4 Data Bus (D31­D0). 2-4 Transfer Attribute Signals . 2-4 Transfer Cycle Type (TT1, TT0) . 2-4 Transfer Cycle Modifier (TM2­TM0) . 2-4 Transfer Line Number (TLN1, TLN0). 2-5 User-Programmable Page Attributes (UPA1, UPA0). 2-5 Read/Write (R/W) . 2-6 M68060 M68060 USER'S MANUAL ix Table of Contents 2.3.6 2.3.7 2.3.8 2.3.9 2.3.10 2.4 2.4.1 2.4.2 2.4.3 2.5 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.6 2.7 2.7.1 2.7.2 2.7.3 2.7.4 2.7.5 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.9 2.9.1 2.9.2 2.9.3 2.10 2.10.1 2.10.2 2.10.3 2.11 2.11.1 2.11.2 2.11.3 2.11.4 2.11.5 2.11.6 2.12 2.13 2.14 x Transfer Size (SIZ1, SIZ0). 2-6 Bus Lock (LOCK). 2-6 Bus Lock End (LOCKE). 2-6 Cache Inhibit Out (CIOUT) . 2-7 Byte Select Lines (BS3­BS0). 2-7 Master Transfer Control Signals . 2-7 Transfer Start (TS). 2-8 Transfer in Progress (TIP) . 2-8 Starting Termination Acknowledge Signal Sampling (SAS) . 2-8 Slave Transfer Control Signals . 2-8 Transfer Acknowledge (TA). 2-8 Transfer Retry Acknowledge (TRA). 2-8 Transfer Error Acknowledge (TEA) . 2-9 Transfer Burst Inhibit (TBI) . 2-9 Transfer Cache Inhibit (TCI) . 2-9 Snoop Control (SNOOP) . 2-9 Arbitration Signals. 2-10 Bus Request (BR). 2-10 Bus Grant (BG). 2-10 Bus Grant Relinquish Control (BGR). 2-10 Bus Tenure Termination (BTT). 2-10 Bus Busy (BB) . 2-11 Processor Control Signals . 2-11 Cache Disable (CDIS) . 2-11 MMU Disable (MDIS). 2-12 Reset In (RSTI). 2-12 Reset Out (RSTO) . 2-12 Interrupt Control Signals . 2-12 Interrupt Priority Level (IPL2­IPL0) . 2-12 Interrupt Pending Status (IPEND) . 2-12 Autovector (AVEC) . 2-13 Status and Clock Signals. 2-13 Processor Status (PST4­PST0). 2-13 MC68060 MC68060 Processor Clock (CLK) . 2-14 Clock Enable (CLKEN) . 2-14 Test Signals . 2-15 JTAG Enable (JTAG). 2-15 Test Clock (TCK) . 2-15 Test Mode Select (TMS). 2-15 Test Data In (TDI). 2-16 Test Data Out (TDO) . 2-16 Test Reset (TRST) . 2-16 Thermal Sensing Pins (THERM1, THERM0). 2-16 Power Supply Connections. 2-16 Signal Summary . 2-16 M68060 M68060 USER'S MANUAL MOTOROLA Table of Contents Section 3 Integer Unit 3.1 3.2 3.2.1 3.2.1.1 3.2.1.2 3.2.1.3 3.2.1.4 3.2.1.5 3.2.2 3.2.2.1 3.2.2.2 3.2.2.3 3.2.2.4 3.2.2.5 Integer Unit Execution Pipelines . 3-1 Integer Unit Register Description . 3-2 Integer Unit User Programming Model . 3-2 Data Registers (D7­D0) . 3-2 Address Registers (A6­A0) . 3-2 User Stack Pointer (A7) . 3-2 Program Counter . 3-3 Condition Code Register . 3-3 Integer Unit Supervisor Programming Model. 3-3 Supervisor Stack Pointer . 3-4 Status Register . 3-4 Vector Base Register. 3-4 Alternate Function Code Registers. 3-5 Processor Configuration Register. 3-5 Section 4 Memory Management Unit 4.1 4.1.1 4.1.2 4.1.3 4.2 4.2.1 4.2.2 4.2.2.1 4.2.2.2 4.2.2.3 4.2.3 4.2.4 4.2.4.1 4.2.4.2 4.2.4.3 4.2.4.4 4.2.5 4.2.6 4.2.6.1 4.2.6.2 4.2.6.3 4.3 4.4 4.5 4.6 4.6.1 MOTOROLA Memory Management Programming Model. 4-3 User and Supervisor Root Pointer Registers . 4-3 Translation Control Register . 4-4 Transparent Translation Registers . 4-6 Logical Address Translation. 4-7 Translation Tables . 4-7 Descriptors. 4-12 Table Descriptors. 4-12 Page Descriptors . 4-12 Descriptor Field Definitions. 4-13 Translation Table Example . 4-15 Variations in Translation Table Structure. 4-16 Indirect Action . 4-16 Table Sharing Between Tasks. 4-17 Table Paging . 4-17 Dynamically Allocated Tables. 4-17 Table Search Accesses . 4-19 Address Translation Protection. 4-20 Supervisor and User Translation Tables . 4-21 Supervisor Only . 4-22 Write Protect . 4-22 Address Translation Caches. 4-24 Transparent Translation. 4-27 Address Translation Summary. 4-28 RSTI and MDIS Effect on the MMU . 4-28 Effect of RSTI on the MMUs . 4-28 M68060 M68060 USER'S MANUAL xi Table of Contents 4.6.2 4.7 4.7.1 4.7.2 4.7.3 Effect of MDIS on Address Translation . 4-30 MMU Instructions. 4-30 MOVEC . 4-30 PFLUSH . 4-30 PLPA . 4-30 Section 5 Caches 5.1 5.2 5.3 5.4 5.4.1 5.4.1.1 5.4.1.2 5.4.2 5.4.3 5.5 5.5.1 5.5.2 5.5.3 5.5.4 5.6 5.7 5.7.1 5.7.2 5.8 5.9 5.10 5.11 5.12 5.12.1 5.12.2 Cache Operation. 5-1 Cache Control Register . 5-5 Cache Management . 5-6 Caching Modes. 5-7 Cachable Accesses . 5-7 Writethrough Mode . 5-7 Copyback Mode . 5-8 Cache-Inhibited Accesses . 5-8 Special Accesses . 5-9 Cache Protocol . 5-9 Read Miss. 5-9 Write Miss. 5-9 Read Hit. 5-9 Write Hit. 5-10 Cache Coherency . 5-10 Memory Accesses for Cache Maintenance . 5-11 Cache Filling. 5-11 Cache Pushes . 5-13 Push Buffer . 5-13 Store Buffer. 5-13 Push Buffer and Store Buffer Bus Operation. 5-14 Branch Cache . 5-14 Cache Operation Summary . 5-15 Instruction Cache. 5-15 Data Cache. 5-16 Section 6 Floating-Point Unit 6.1 6.1.1 6.1.2 6.1.2.1 6.1.2.2 6.1.3 6.1.3.1 6.1.3.2 6.1.3.3 xii Floating-Point User Programming Model. 6-2 Floating-Point Data Registers (FP7­FP0) . 6-3 Floating-Point Control Register (FPCR) . 6-3 Exception Enable Byte . 6-3 Mode Control Byte. 6-3 Floating-Point Status Register (FPSR). 6-4 Floating-Point Condition Code Byte . 6-5 Quotient Byte. 6-5 Exception Status Byte . 6-5 M68060 M68060 USER'S MANUAL MOTOROLA Table of Contents 6.1.3.4 6.1.4 6.2 6.3 6.3.1 6.3.2 6.4 6.4.1 6.4.2 6.5 6.5.1 6.5.2 6.5.3 6.6 6.6.1 6.6.1.1 6.6.1.2 6.6.2 6.6.2.1 6.6.2.2 6.6.3 6.6.3.1 6.6.3.2 6.6.4 6.6.4.1 6.6.4.2 6.6.5 6.6.5.1 6.6.5.2 6.6.6 6.6.6.1 6.6.6.2 6.6.7 6.6.7.1 6.6.7.2 6.7 Accrued Exception Byte . 6-6 Floating-Point Instruction Address Register (FPIAR) . 6-7 Floating-Point Data Formats and Data Types. 6-7 Computational Accuracy . 6-11 Intermediate Result. 6-12 Rounding the Result . 6-13 Postprocessing Operation. 6-15 Underflow, Round, and Overflow. 6-15 Conditional Testing . 6-16 Floating-Point Exceptions . 6-19 Unimplemented Floating-Point Instructions . 6-19 Unsupported Floating-Point Data Types. 6-21 Unimplemented Effective Address Exception. 6-22 Floating-Point Arithmetic Exceptions . 6-22 Branch/Set on Unordered (BSUN). 6-24 Trap Disabled Results (FPCR BSUN Bit Cleared) . 6-24 Trap Enabled Results (FPCR BSUN Bit Set) . 6-24 Signaling Not-a-Number (SNAN) . 6-25 Trap Disabled Results (FPCR SNAN Bit Cleared) . 6-25 Trap Enabled Results (FPCR SNAN Bit Set) . 6-26 Operand Error. 6-26 Trap Disabled Results (FPCR OPERR Bit Cleared). 6-27 Trap Enabled Results (FPCR OPERR Bit Set). 6-27 Overflow. 6-28 Trap Disabled Results (FPCR OVFL Bit Cleared) . 6-29 Trap Enabled Results (FPCR OVFL Bit Set) . 6-29 Underflow. 6-30 Trap Disabled Results (FPCR UNFL Bit Cleared) . 6-31 Trap Enabled Results (FPCR UNFL Bit Set) . 6-31 Divide-by-Zero . 6-32 Trap Disabled Results (FPCR DZ Bit Cleared). 6-33 Trap Enabled Results (FPCR DZ Bit Set). 6-33 Inexact Result . 6-33 Trap Disabled Results (FPCR INEX1 Bit and INEX2 Bit Cleared. 6-34 Trap Enabled Results (Either FPCR INEX1 Bit or INEX2 Bit Set). 6-34 Floating-Point State Frames . 6-35 Section 7 Bus Operation 7.1 7.2 7.3 7.4 7.5 7.6 MOTOROLA Bus Characteristics . 7-1 Full-, Half-, and Quarter-Speed Bus Operation and BCLK . 7-3 Acknowledge Termination Ignore State Capability . 7-4 Bus Control Register. 7-4 Data Transfer Mechanism. 7-5 Misaligned Operands . 7-9 M68060 M68060 USER'S MANUAL xiii Table of Contents 7.7 7.7.1 7.7.2 7.7.3 7.7.4 7.7.5 7.7.6 7.7.7 7.8 7.8.1 7.8.1.1 7.8.1.2 7.8.1.3 7.8.2 7.8.2.1 7.9 7.9.1 7.9.2 7.9.3 7.10 7.11 7.11.1 7.11.2 7.11.3 7.12 7.13 7.14 7.14.1 7.14.2 7.14.3 Processor Data Transfers. 7-12 Byte, Word, and Long-Word Read Transfer Cycles . 7-12 Line Read Transfer. 7-15 Byte, Word, and Long-Word Write Cycles. 7-20 Line Write Cycles. 7-25 Locked Read-Modify-Write Cycles . 7-28 Emulating CAS2 and CAS Misaligned. 7-31 Using CLA to Increment A3 and A2. 7-32 Acknowledge Cycles. 7-32 Interrupt Acknowledge Cycles . 7-32 Interrupt Acknowledge Cycle (Terminated Normally) . 7-35 Autovector Interrupt Acknowledge Cycle . 7-35 Spurious Interrupt Acknowledge Cycle . 7-35 Breakpoint Acknowledge Cycle . 7-36 LPSTOP Broadcast Cycle . 7-38 Bus Exception Control Cycles . 7-46 Bus Errors. 7-46 Retry Operation . 7-48 Double Bus Fault . 7-51 Bus Synchronization . 7-52 Bus Arbitration . 7-52 MC68040-Arbitration Protocol (BB Protocol). 7-53 MC68060-Arbitration Protocol (BTT Protocol). 7-58 External Arbiter Considerations. 7-65 Bus Snooping Operation. 7-68 Reset Operation. 7-71 Special Modes of Operation . 7-74 Acknowledge Termination Ignore State Capability. 7-74 Acknowledge Termination Protocol . 7-76 Extra Data Write Hold Time Mode. 7-76 Section 8 Exception Processing 8.1 8.2 8.2.1 8.2.2 8.2.3 8.2.4 8.2.5 8.2.6 8.2.7 8.2.8 8.2.9 8.2.10 xiv Exception Processing Overview . 8-1 Integer Unit Exceptions. 8-4 Access Error Exception . 8-5 Address Error Exception. 8-7 Instruction Trap Exception. 8-7 Illegal Instruction and Unimplemented Instruction Exceptions . 8-8 Privilege Violation Exception . 8-10 Trace Exception. 8-10 Format Error Exception . 8-11 Breakpoint Instruction Exception . 8-11 Interrupt Exception . 8-12 Reset Exception . 8-14 M68060 M68060 USER'S MANUAL MOTOROLA Table of Contents 8.3 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.4.4.1 8.4.4.2 8.4.4.3 8.4.5 8.4.6 8.4.7 Exception Priorities . 8-17 Return from Exceptions . 8-19 Four-Word Stack Frame (Format $0) . 8-19 Six-Word Stack Frame (Format $2) . 8-20 Floating-Point Post-Instruction Stack Frame (Format $3) . 8-20 Eight-Word Stack Frame (Format $4). 8-21 Program Counter (PC). 8-21 Fault Address . 8-22 Fault Status Long Word (FSLW). 8-22 Recovering from an Access Error . 8-25 Bus Errors and Pending Memory Writes . 8-27 Branch Prediction Error . 8-29 Section 9 IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes 9.1 9.1.1 9.1.2 9.1.2.1 9.1.2.2 9.1.2.3 9.1.2.4 9.1.2.5 9.1.2.6 9.1.2.7 9.1.2.8 9.1.3 9.1.3.1 9.1.3.2 9.1.3.3 9.1.4 9.1.5 9.1.6 9.2 9.2.1 9.2.2 9.2.3 9.3 IEEE 1149.1 Test Access Port (Normal JTAG) Mode . 9-1 Overview. 9-2 JTAG Instruction Shift Register . 9-3 EXTEST. 9-4 LPSAMPLE. 9-5 Private Instructions . 9-5 SAMPLE/PRELOAD . 9-5 IDCODE. 9-5 CLAMP . 9-6 HIGHZ. 9-6 BYPASS . 9-6 JTAG Test Data Registers. 9-7 Idcode Register . 9-7 Boundary Scan Register. 9-7 Bypass Register . 9-15 Restrictions . 9-15 Disabling the IEEE 1149.1 Standard Operation . 9-15 Motorola MC68060 MC68060 BSDL Description. 9-17 Debug Pipe Control Mode. 9-24 Debug Command Interface. 9-25 Debug Pipe Control Mode Commands . 9-27 Emulator Mode . 9-31 Switching between JTAG and Debug Pipe ControlModes of Operation. 9-33 Section 10 Instruction Execution Timing 10.1 10.1.1 10.1.2 MOTOROLA Superscalar Operand Execution Pipelines . 10-1 Dispatch Test 1: sOEP Opword and Required Extension Words Are Valid . 10-2 Dispatch Test 2: Instruction Classification . 10-2 M68060 M68060 USER'S MANUAL xv Table of Contents 10.1.3 10.1.4 10.1.5 10.1.6 10.2 10.3 10.3.1 10.3.2 10.3.3 10.3.4 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.13 10.14 10.15 10.16 Dispatch Test 3: Allowable Effective Addressing Mode in the sOEP . 10-8 Dispatch Test 4: Allowable Operand Data Memory Reference . 10-8 Dispatch Test 5: No Register Conflicts on sOEP.AGU Resources . 10-8 Dispatch Test 6: No Register Conflicts on sOEP.IEE Resources . 10-9 Timing Assumptions . 10-10 Cache and ATC Performance Degradation Times . 10-12 Instruction ATC Miss . 10-12 Data ATC Miss . 10-13 Instruction Cache Miss . 10-13 Data Cache Miss . 10-13 Effective Address Calculation Times . 10-14 Move Instruction Execution Times. 10-14 Standard Instruction Execution Times . 10-16 Immediate Instruction Execution Times. 10-17 Single-Operand Instruction Execution Times . 10-18 Shift/Rotate Execution Times . 10-19 Bit Manipulation and Bit Field Execution Times. 10-19 Branch Instruction Execution Times . 10-21 LEA, PEA, and MOVEM Execution Times. 10-22 Multiprecision Instruction Execution Times. 10-22 Status Register, MOVES, and Miscellaneous Instruction Execution Times. 10-22 FPU Instruction Execution Times . 10-24 Exception Processing Times . 10-26 Section 11 Applications Information 11.1 11.1.1 11.1.2 11.1.2.1 11.1.2.1.1 11.1.2.1.2 11.1.2.1.3 11.1.2.1.4 11.1.2.1.5 11.1.2.2 11.1.2.2.1 11.1.2.2.2 11.1.2.2.3 11.1.2.2.4 11.1.2.3 11.1.2.4 11.1.2.5 11.1.3 xvi Guidelines for Porting Software to the MC68060 MC68060 . 11-1 User Code . 11-1 Supervisor Code. 11-1 Initialization Code (Reset Exception Handler) . 11-2 Processor Configuration Register (PCR) (MOVEC of PCR). . 11-2 Default Transparent Translation Register (MOVEC of TCR) . 11-2 MC68060 MC68060 Software Package (M68060SP M68060SP). . 11-2 Cache Control Register (CACR) (MOVEC of CACR). 11-3 Resource Checking (Access Error Handler) . 11-3 Virtual Memory Software . 11-3 Translation Control Register (MOVEC of TCR). 11-3 Descriptors in Cacheable Copyback Pages Prohibited. 11-4 Page and Descriptor Faults (Access Error Handler). . 11-4 PTEST, MOVEC of MMUSR, and PLPA. 11-4 Context Switch Interrupt Handlers. 11-5 Trace Handlers . 11-5 I/O Device Driver Software . 11-5 Precise Vs. Imprecise Exception Mode . 11-6 M68060 M68060 USER'S MANUAL MOTOROLA Table of Contents 11.1.4 11.2 11.2.1 11.2.1.1 11.2.1.1.1 11.2.1.1.2 11.2.1.2 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.2.7 11.2.8 11.3 11.4 11.5 Other Considerations. 11-6 Using an MC68060 MC68060 in an Existing MC68040 MC68040 System . 11-6 Power Considerations. 11-6 DC to DC Voltage Conversion . 11-6 Linear Voltage Regulator Solution. 11-7 Switching Regulator Solution. 11-7 Input Signals During Power-Up Requirement. 11-11 Output Hold Time Differences . 11-11 Bus Arbitration . 11-13 Snooping. 11-13 Special Modes . 11-13 Clocking . 11-14 PSTx Encoding . 11-14 Miscellaneous Pullup Resistors . 11-15 Example DRAM Access. 11-15 Thermal Management. 11-17 Support Devices. 11-20 Section 12 Electrical and Thermal Characteristics 12.1 12.2 12.3 12.4 12.5 12.6 12.7 Maximum Ratings . 12-1 Thermal Characteristics . 12-1 Power Dissipation . 12-1 DC Electrical Specifications (Vcc = 3.3 Vdc ± 5%) . 12-2 Clock Input Specifications (Vcc = 3.3 Vdc ± 5%). 12-3 Output AC Timing Specifications (Vcc = 3.3 Vdc ± 5%) . 12-4 Input AC Timing Specifications (Vcc = 3.3 Vdc ± 5%) . 12-6 Section 13 Ordering Information and Mechanical Data 13.1 13.2 13.2.1 13.2.2 13.3 Ordering Information . 13-1 Pin Assignments . 13-1 MC68060 MC68060, MC68LC060 MC68LC060, and MC68EC060 MC68EC060 Pin Grid Array (RC Suffix) . 13-2 MC68060 MC68060, MC68LC060 MC68LC060, and MC68EC060 MC68EC060 Quad Flat Pack (FE Suffix). 13-3 Mechanical Data . 13-4 Appendix A MC68LC060 MC68LC060 Appendix B MC68EC060 MC68EC060 B.1 B.2 MOTOROLA Address Translation Differences.B-1 Instruction Differences .B-1 M68060 M68060 USER'S MANUAL xvii Table of Contents Appendix C MC68060 MC68060 Software Package C.1 C.2 C.2.1 C.2.2 C.2.2.1 C.2.2.2 C.2.2.3 C.2.3 C.3 C.3.1 C.3.2 C.3.2.1 C.3.2.2 C.3.2.2.1 C.3.2.2.2 C.3.2.2.3 C.3.2.2.4 C.3.2.3 C.3.2.3.1 C.3.2.3.2 C.3.2.3.3 C.3.2.3.4 C.3.2.3.5 C.3.2.4 C.3.2.4.1 C.3.2.4.2 C.3.3 C.3.4 C.4 C.4.1 C.4.2 C.5 C.5.1 C.5.2 C.5.3 C.5.4 Module Format.C-2 Unimplemented Integer Instructions .C-4 Integer Emulation Results .C-5 Module 1: Unimplemented Integer Instruction Exception (MC68060ISP MC68060ISP).C-5 Unimplemented Integer Instruction Exception Module Entry Points .C-6 Unimplemented Integer Instruction Exception Module Call-Outs .C-6 CAS Misaligned Address and CAS2 Emulation-Related Call-Outs and Entry Points .C-6 Module 2: Unimplemented Integer Instruction Library (MC68060ILSP MC68060ILSP) .C-9 Floating-Point Emulation Package (MC68060FPSP MC68060FPSP) .C-11 Floating-Point Emulation Results .C-13 Module 3: Full Floating-Point Kernel .C-14 Full Floating-Point Kernel Module Entry Points .C-14 Full Floating-Point Kernel Module Call-Outs .C-14 The F-Line Exception Call-Outs .C-14 System-Supplied Floating-Point Arithmetic Exception Handler Call-Outs .C-15 Exception-Related Call-Outs .C-15 Exit Point Call-Outs .C-15 Bypassing Module-Supplied Floating-Point Arithmetic Handlers .C-15 Overflow/Underflow .C-16 Signalling Not-A-Number, Operand Error.C-17 Inexact Exception .C-18 Divide-by-Zero Exception .C-19 Branch/Set on Unordered Exception.C-19 Exceptions During Emulation .C-20 Trap-Disabled Operation .C-20 Trap-Enabled Operation.C-21 Module 4: Partial Floating-Point Kernel .C-21 Module 5: Floating-Point Library (M68060FPLSP M68060FPLSP).C-22 Operating System Dependencies .C-23 Instruction and Data Fetches.C-23 Instructions Not Recommended .C-26 Installation Notes .C-27 Installing the Library Modules.C-27 Installing the Kernel Modules .C-27 Release Notes and Module Offset Assignments .C-28 AESOP Electronic Bulletin Board .C-29 Appendix D MC68060 MC68060 Instructions xviii M68060 M68060 USER'S MANUAL MOTOROLA LIST OF ILLUSTRATIONS 1-1 1-2 2-1 3-1 3-2 3-3 3-4 3-5 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 5-1 5-2 5-3 5-4 5-5 5-6 5-7 6-1 6-2 6-3 MC68060 MC68060 Block Diagram . 1-6 Programming Model . 1-12 Functional Signal Groups . 2-3 MC68060 MC68060 Integer Unit Pipeline . 3-1 Integer Unit User Programming Model. 3-2 Integer Unit Supervisor Programming Model . 3-3 Status Register. 3-4 Processor Configuration Register . 3-5 Memory Management Unit . 4-2 Memory Management Programming Model . 4-3 URP and SRP Register Formats. 4-3 Translation Control Register Format . 4-4 Transparent Translation Register Format . 4-6 Translation Table Structure . 4-8 Logical Address Format . 4-8 Detailed Flowchart of Table Search Operation . 4-10 Detailed Flowchart of Descriptor Fetch Operation . 4-11 Table Descriptor Formats. 4-12 Page Descriptor Formats . 4-12 Example Translation Table. 4-15 Translation Table Using Indirect Descriptors . 4-16 Translation Table Using Shared Tables . 4-18 Translation Table with Nonresident Tables . 4-19 Translation Table Structure for Two Tasks . 4-21 Logical Address Map with Shared Supervisor and User Address Spaces. 4-22 Translation Table Using S-Bit and W-Bit To Set Protection . 4-23 ATC Organization. 4-24 ATC Entry and Tag Fields . 4-25 Address Translation Flowchart. 4-29 MC68060 MC68060 Instruction and Data Caches . 5-2 Instruction Cache Line Format . 5-2 Data Cache Line Format . 5-2 Caching Operation . 5-3 Cache Control Register . 5-5 Instruction Cache Line State Diagram. 5-16 Data Cache Line State Diagrams. 5-18 Floating-Point Unit Block Diagram . 6-2 Floating-Point User Programming Model . 6-3 Floating-Point Control Register Format. 6-4 MOTOROLA M68060 M68060 USER'S MANUAL xix List of Illustrations 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 7-1 7-2 7-3 7-4 7-5 7-6 7-7 7-8 7-9 7-10 7-11 7-12 7-13 7-14 7-15 7-16 7-17 7-18 7-19 7-20 7-21 7-22 7-23 7-24 7-25 7-26 7-27 7-28 7-29 7-30 7-31 7-32 7-33 7-34 7-35 7-36 7-37 xx Floating-Point Condition Code (FPSR) . 6-5 Floating-Point Quotient Byte (FPSR) . 6-5 Floating-Point Exception Status Byte (FPSR). 6-6 Floating-Point Accrued Exception Byte (FPSR). 6-6 Intermediate Result Format. 6-12 Rounding Algorithm Flowchart . 6-14 Floating-Point State Frame . 6-35 Status Word Contents . 6-36 Signal Relationships to Clocks. 7-2 Full-Speed Clock. 7-2 Half-Speed Clock . 7-2 Quarter-Speed Clock . 7-3 Bus Control Register Format. 7-4 Internal Operand Representation. 7-5 Data Multiplexing. 7-6 Byte Select Signal Generation and PAL Equation . 7-8 Example of a Misaligned Long-Word Transfer. 7-10 Example of Misaligned Word Transfer . 7-10 Misaligned Long-Word Read Bus Cycle Timing. 7-11 Byte, Word, and Long-Word Read Cycle Flowchart . 7-13 Byte, Word, and Long-Word Read Bus Cycle Timing . 7-14 Line Read Cycle Flowchart . 7-17 Line Read Transfer Timing. 7-18 Burst-Inhibited Line Read Cycle Flowchart . 7-20 Burst-Inhibited Line Read Bus Cycle Timing. 7-21 Byte, Word, and Long-Word Write Transfer Flowchart . 7-22 Long-Word Write Bus Cycle Timing . 7-23 Line Write Cycle Flowchart . 7-26 Line Write Burst-Inhibited Cycle Flowchart . 7-27 Line Write Bus Cycle Timing . 7-28 Locked Bus Cycle for TAS Instruction Timing. 7-30 Using CLA in a High-Speed DRAM Design . 7-33 Interrupt Pending Procedure . 7-33 Assertion of IPEND . 7-34 Interrupt Acknowledge Cycle Flowchart. 7-36 Interrupt Acknowledge Bus Cycle Timing . 7-37 Autovector Interrupt Acknowledge Bus Cycle Timing . 7-38 Breakpoint Interrupt Acknowledge Cycle Flowchart. 7-39 Breakpoint Interrupt Acknowledge Bus Cycle Timing . 7-40 LPSTOP Broadcast Cycle Flowchart . 7-41 LPSTOP Broadcast Bus Cycle Timing, BG Negated . 7-42 LPSTOP Broadcast Bus Cycle Timing, BG Asserted . 7-43 Exiting LPSTOP Mode Flowchart. 7-44 Exiting LPSTOP Mode Timing Diagram. 7-45 Word Write Access Bus Cycle Terminated with TEA Timing . 7-48 M68060 M68060 USER'S MANUAL MOTOROLA List of Illustrations 7-38 7-39 7-40 7-41 7-42 7-43 7-44 7-45 7-46 7-47 7-48 7-49 7-50 7-51 7-52 8-1 8-2 8-3 8-4 8-5 8-6 9-1 9-2 9-3 9-4 9-5 9-6 9-7 9-8 9-9 9-10 9-11 9-12 9-13 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 Line Read Access Bus Cycle Terminated with TEA Timing. 7-49 Retry Read Bus Cycle Timing . 7-50 Line Write Retry Bus Cycle Timing. 7-51 MC68040-Arbitration Protocol State Diagram . 7-57 MC68060-Arbitration Protocol State Diagram . 7-64 Processor Bus Request Timing. 7-67 Arbitration During Relinquish and Retry Timing . 7-68 Implicit Bus Ownership Arbitration Timing. 7-69 Effect of BGR on Locked Sequences. 7-70 Snooped Bus Cycle. 7-71 Initial Power-On Reset Timing. 7-72 Normal Reset Timing. 7-73 Data Bus Usage During Reset . 7-74 Acknowledge Termination Ignore State Example . 7-75 Extra Data Write Hold Example. 7-77 General Exception Processing Flowchart . 8-2 General Form of Exception Stack Frame . 8-3 Interrupt Recognition Examples . 8-13 Interrupt Exception Processing Flowchart. 8-15 Reset Exception Processing Flowchart. 8-16 Fault Status Long-Word Format . 8-22 JTAG Test Logic Block Diagram . 9-3 JTAG Idcode Register Format. 9-7 Output Pin Cell (O.Pin). 9-8 Observe-Only Input Pin Cell (I.Obs). 9-8 Input Pin Cell (I.Pin) . 9-9 Output Control Cell (IO.Ctl) . 9-9 General Arrangement of Bidirectional Pin Cells . 9-10 JTAG Bypass Register . 9-15 Circuit Disabling IEEE Standard 1149.1. 9-16 Debug Command Interface Schematic . 9-25 Interface Timing. 9-26 Transition from JTAG to Debug Mode Timing Diagram . 9-34 Transition from Debug to JTAG Mode Timing Diagram . 9-35 Linear Voltage Regulator Solution. 11-7 LTC1147 LTC1147 Voltage Regulator Solution. 11-8 LTC1148 LTC1148 Voltage Regulator Solution. 11-9 MAX767 MAX767 Voltage Regulator Solution. 11-10 MC68040 MC68040 Address Hold Time . 11-11 MC68060 MC68060 Address Hold Time . 11-12 MC68060 MC68060 Address Hold Time Fix . 11-12 Simple CLK Generation. 11-14 Generic CLK Generation . 11-14 MC68040 MC68040 BCLK to CLKEN Relationship. 11-15 DRAM Timing Analysis. 11-15 MOTOROLA M68060 M68060 USER'S MANUAL xxi List of Illustrations 12-12 12-13 12-14 12-15 12-16 12-17 12-18 12-19 12-20 13-1 13-2 C-1 C-2 C-3 C-4 C-5 C-6 C-7 C-8 C-9 C-10 C-11 C-12 xxii Clock Input Timing Diagram. 12-3 Drive Levels and Test Points for AC Specifications . 12-7 Reset Configuration Timing. 12-8 Read/Write Timing . 12-9 Bus Arbitration Timing. 12-10 Bus Arbitration Timing (Continued) . 12-11 CLA Timing . 12-12 Snoop Timing . 12-13 Other Signals Timing. 12-14 PGA Package Dimensions (RC Suffix) . 13-4 QFP Package Dimensions (FE Suffix) . 13-5 Call-Out Dispatch Table Example .C-2 Example Pseudo-Assembly File .C-3 Module Call-In, Call-Out Example.C-4 CAS and CAS2 Call-Outs and Entry Points .C-9 C-Code Representation of Integer Library Routines .C-10 MUL Instruction Call Example.C-11 CMP2 Instruction Call Example .C-11 SNAN/OPERR Exception Handler Pseudo-Code .C-18 Disabled vs. Enabled Exception Actions.C-20 _mem_read Pseudo-Code .C-23 Register Usage of {i,d}mem_{read,write}_{b,w,l} .C-25 Vector Table and M68060SP M68060SP Relationship .C-28 M68060 M68060 USER'S MANUAL MOTOROLA LIST OF TABLES 1-1 1-2 1-3 1-4 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 4-1 4-2 5-1 5-2 5-3 6-1 6-2 6-3 6-4 6-5 6-6 6-7 6-8 6-9 6-10 6-11 6-12 6-13 6-14 6-15 6-16 7-1 7-2 7-3 7-4 7-5 7-6 Data Formats. 1-14 Effective Addressing Modes. 1-15 Instruction Set Summary . 1-16 Notational Conventions . 1-21 Signal Index. 2-1 Transfer-Type Encoding. 2-4 Normal and MOVE16 MOVE16 Access TMx Encoding. 2-5 Alternate Access TMx Encoding . 2-5 SIZx Encoding . 2-6 Data Bus Byte Select Signals. 2-7 PSTx Encoding. 2-14 Signal Summary . 2-17 Updating U-Bit and M-Bit for Page Descriptors. 4-20 SFC and DFC Values. 4-20 TLNx Encoding. 5-11 Instruction Cache Line State Transitions. 5-15 Data Cache Line State Transitions. 5-18 RND Encoding. 6-4 PREC Encoding . 6-4 MC68060 MC68060 FPU Data Formats and Data Types . 6-7 Single-Precision Real Format Summary . 6-8 Double-Precision Real Format Summary. 6-9 Extended-Precision Real Format Summary . 6-10 Packed Decimal Real Format Summary . 6-11 Floating-Point Condition Code Encoding . 6-16 Floating-Point Conditional Tests . 6-18 Floating-Point Exception Vectors . 6-19 Unimplemented Instructions. 6-20 Possible Operand Errors Exceptions . 6-27 Overflow Rounding Mode Values. 6-29 Underflow Rounding Mode Values. 6-31 Possible Divide-by-Zero Exceptions. 6-33 Rounding Mode Values . 6-34 Data Bus Requirements for Read and Write Cycles . 7-7 Summary of Access Types vs. Bus Signal Encoding. 7-9 Memory Alignment Influence on Noncachable and Writethrough Bus Cycles. 7-12 Interrupt Acknowledge Termination Summary . 7-34 Termination Result Summary. 7-46 MC68040-Arbitration Protocol Transition Conditions . 7-55 MOTOROLA M68060 M68060 USER'S MANUAL xxiii List of Tables 7-7 7-8 7-9 7-10 8-1 8-2 8-3 9-1 9-2 9-3 9-4 9-5 10-1 10-2 10-3 10-4 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 10-15 10-16 10-17 10-18 10-19 10-20 10-21 10-22 10-23 10-24 10-25 10-26 11-1 11-2 11-3 11-4 C-1 C-2 C-3 xxiv MC68040-Arbitration Protocol State Description . 7-56 MC68060-Arbitration Protocol State Transition Conditions. 7-62 MC68060-Arbitration Protocol State Description . 7-63 Special Mode vs. IPLx Signals. 7-74 Exception Vector Assignments . 8-4 Interrupt Levels and Mask Values. 8-12 Exception Priority Groups . 8-17 JTAG States. 9-2 JTAG Instructions. 9-4 Boundary Scan Bit Definitions. 9-10 Debug Command Interface Pins . 9-25 Command Summary . 9-28 Superscalar OEP Dispatch Test Algorithm . 10-4 MC68060 MC68060 Superscalar Classification of M680x0 Integer Instructions. 10-4 Superscalar Classification of M680x0 Privileged Instructions. 10-7 Superscalar Classification of M680x0 Floating-Point Instructions . 10-7 Effective Address Calculation Times. 10-14 Move Byte and Word Execution Times . 10-15 Move Long Execution Times. 10-15 MOVE16 MOVE16 Execution Times . 10-15 Standard Instruction Execution Time . 10-16 Immediate Instruction Execution Times . 10-17 Single-Operand Instruction Execution Times. 10-18 Clear (CLR) Execution Times . 10-18 Shift/Rotate Execution Times. 10-19 Bit Manipulation (Dynamic Bit Count) Execution Times. 10-19 Bit Manipulation (Static Bit Count) Execution Times. 10-20 Bit Field Execution Times. 10-20 Branch Execution Times . 10-21 JMP, JSR Execution Times. 10-21 Return Instruction Execution Times . 10-21 LEA, PEA, and MOVEM Instruction Execution Times . 10-22 Multiprecision Instruction Execution Times . 10-22 Status Register (SR) Instruction Execution Times . 10-23 MOVES Execution Times. 10-23 Miscellaneous Instruction Execution Times . 10-23 Floating-Point Instruction Execution Times. 10-24 Exception Processing Times. 10-26 With Heat Sink, No Air Flow. 11-18 With Heat Sink, with Air Flow . 11-18 No Heat Sink . 11-19 Support Devices and Products. 11-20 Call-Out Dispatch Table and Module Size .C-4 FPU Comparison.C-12 Unimplemented Instructions.C-13 M68060 M68060 USER'S MANUAL MOTOROLA List of Tables C-4 C-5 C-6 C-7 D-1 D-2 D-3 Unimplemented Data Formats and Data Types . C-13 UNIX Operating System Calls . C-23 Instructions Not Handled by the M68060SP M68060SP . C-26 Files Provided in an M68060SP M68060SP Release. C-27 M68000 M68000 Family Instruction Set and Processor Cross-Reference . D-1 M68000 M68000 Family Instruction Set. D-6 Exception Vector Assignments for the M68000 M68000 Family. D-10 MOTOROLA M68060 M68060 USER'S MANUAL xxv List of Tables xxvi M68060 M68060 USER'S MANUAL MOTOROLA SECTION 1 INTRODUCTION The superscalar MC68060 MC68060 represents a new line of Motorola microprocessor products. The first generation of the M68060 M68060 product line consists of the MC68060 MC68060, MC68LC060 MC68LC060, and MC68EC060 MC68EC060. All three microprocessors offer superscalar integer performance of over 100 MIPS at 66 MHz. The MC68060 MC68060 comes fully equipped with both a floating-point unit (FPU) and a memory management unit (MMU) for high-performance embedded control and desktop applications. For cost-sensitive embedded control and desktop applications where an MMU is required, but the additional cost of a FPU is not justified, the MC68LC060 MC68LC060 offers high-performance at a low cost. Specifically designed for low-cost embedded control applications, the MC68EC060 MC68EC060 eliminates both the FPU and MMU, permitting designers to leverage MC68060 MC68060 performance while avoiding the cost of unnecessary features. Throughout this product brief, all references to the MC68060 MC68060 also refer to the MC68LC060 MC68LC060 and the MC68EC060 MC68EC060, unless otherwise noted. Leveraging many of the same performance enhancements used by RISC designs as well as providing innovative architectural techniques, the MC68060 MC68060 harnesses new levels of performance for the M68000 M68000 family. Incorporating 2.5 million transistors on a single piece of silicon, the MC68060 MC68060 employs a deep pipeline, dual issue superscalar execution, a branch cache, a high-performance floating-point unit (MC68060 MC68060 only), eight Kbytes each of on-chip instruction and data caches, and dual on-chip demand paging MMUs (MC68060 MC68060 and MC68LC060 MC68LC060 only). The MC68060 MC68060 allows simultaneous execution of two integer instructions (or an integer and a float instruction) and one branch instruction during each clock. The MC68060 MC68060 features a full internal Harvard architecture. The instruction and data caches are designed to support concurrent instruction fetch, operand read and operand write references on every clock. Separate 8-Kbyte instruction and 8-Kbyte data caches can be frozen to prevent allocation over time-critical code or data. The independent nature of the caches allows instruction stream fetches, data-stream fetches, and external accesses to occur simultaneously with instruction execution. The operand data cache is four-way banked to permit simultaneous read and write access each clock. A very high bandwidth internal memory system coupled with the compact nature of the M68000 M68000 family code allows the MC68060 MC68060 to achieve extremely high levels of performance, even when operating from low-cost memory such as a 32-bit wide dynamic random access memory system. Instructions are fetched from the internal cache or external memory by a four-stage instruction fetch pipeline. The MC68060 MC68060 variable-length instruction system is internally decoded into a fixed-length representation and channeled into an instruction buffer. The instruction buffer acts as a FIFO which provides a decoupling mechanism between the instruction fetch MOTOROLA M68060 M68060 USER'S MANUAL 1-1 Introduction unit and the operand execution units. Fixed format instructions are dispatched to dual fourstage pipelined RISC operand execution engines where they are then executed. The branch cache also plays a major role in achieving the high performance levels of the MC68060 MC68060. It has been implemented such that most branches are executed in zero cycles. Using a technique known as branch folding, the branch cache allows the instruction fetch pipeline to detect and change the instruction prefetch stream before the change of flow affects the instruction execution engines, minimizing the need for pipeline refill. In addition to substantial cost and performance benefits, the MC68060 MC68060 also offers advantages in power consumption and power management. The MC68060 MC68060 automatically minimizes power dissipation by using a fully-static design, dynamic power management, and low-voltage operation. It automatically powers-down internal functional blocks that are not needed on a clock-by-clock basis. Explicitly the MC68060 MC68060 power consumption can be controlled from the operating system. Although the MC68060 MC68060 operates at a lower operating voltage, it directly interfaces to both 3-V and 5-V peripherals and logic. Complete code compatibility with the M68000 M68000 family allows the designer to draw on existing code and past experience to bring products to market quickly. There is also a broad base of established development tools, including real-time kernels, operating systems, languages, and applications, to assist in product design. The functionality provided by the MC68060 MC68060 makes it the ideal choice for a range of high-performance embedded applications and computing applications. With M68000 M68000 family code compatibility, the MC68060 MC68060 provides a range of upgrade opportunities to virtually any existing MC68040 MC68040 application. 1-2 M68060 M68060 USER'S MANUAL MOTOROLA Introduction 1.1 DIFFERENCES AMONG M68060 M68060 FAMILY MEMBERS Because the functionality of individual M68060 M68060 family members are similar, this manual is organized so that the reader will take the following differences into account while reading the rest of this manual. Unless otherwise noted, all references to MC68060 MC68060, with the exception of the differences outlined below, will apply to the MC68060 MC68060, MC68LC060 MC68LC060, and MC68EC060 MC68EC060. The following paragraphs describe how the MC68LC060 MC68LC060 and the MC68EC060 MC68EC060 differ from the MC68060 MC68060. 1.1.1 MC68LC060 MC68LC060 The MC68LC060 MC68LC060 is a derivative of the MC68060 MC68060. The MC68LC060 MC68LC060 has the same execution unit and MMU as the MC68060 MC68060, but has no FPU. The MC68LC060 MC68LC060 is 100% pin compatible with the MC68060 MC68060. Disregard all information concerning the FPU when reading this manual. The following difference exists between the MC68LC060 MC68LC060 and the MC68060 MC68060: · The MC68LC060 MC68LC060 does not contain an FPU. When floating-point instructions are encountered, a floating-point disabled exception is taken. 1.1.2 MC68EC060 MC68EC060 The MC68EC060 MC68EC060 is a derivative of the MC68060 MC68060. The MC68EC060 MC68EC060 has the same execution unit as the MC68060 MC68060, but has no FPU or paged MMU, which embedded control applications generally do not require. Disregard information concerning the FPU and MMU when reading this manual. The MC68EC060 MC68EC060 is pin compatible with the MC68060 MC68060. The following differences exist between the MC68EC060 MC68EC060 and the MC68060 MC68060: · The MC68EC060 MC68EC060 does not contain an FPU. When floating-point instructions are encountered, a floating-point disabled exception is taken. · The MDIS pin name has been changed to the JS0 pin and is included for boundary scan purposes only. 1.1.2.1 ADDRESS TRANSLATION DIFFERENCES. Although the MC68EC060 MC68EC060 has no paged MMU, the four transparent translation registers (ITT0, ITT1, DTT0, and DTT1) and the default transparent translation (defined by certain bits in the translation control register (TCR) operate normally and can still be used to assign cache modes and supervisor and write protection for given address ranges. All addresses can be mapped by the four transparent translation registers (TTRs) and the default transparent translation. 1.1.2.2 INSTRUCTION DIFFERENCES. The PFLUSH and PLPA instructions, the supervisor root pointer (SRP) and user root pointer (URP) registers, and the E- and P-bits of the TCR are not supported by the MC68EC060 MC68EC060 and must not be used. Use of these instructions and registers in the MC68EC060 MC68EC060 exhibits poor programming practice since no useful results can be achieved. Any functional anomalies that may result from their use will require system software modification (to remove offending instructions) to achieve proper operation. The PLPA instruction operates normally except that when an address misses in the four TTRs, instead of performing a table search operation, the access cache mode and write protection properties are defined by the default transparent translation bits in the TCR. The address register contents are never changed since all addresses are always transparently MOTOROLA M68060 M68060 USER'S MANUAL 1-3 Introduction translated. The PLPA instruction can only generate an access error exception only on supervisor or write protection violation cases. The PFLUSH instruction operates as a virtual NOP instruction. When the MOVEC instruction is used to access the SRP and URP registers and the E- and P-bits in the TCR, no exceptions are reported. However, those bits are undefined for the MC68EC060 MC68EC060 and must not be used. 1.2 FEATURES The main features of the MC68060 MC68060 are as follows: · 1.6­1.7 Times the MC68040 MC68040 Performance at the Same Clock Rate with Existing Compliers. 3.2­3.4 Times the Performance of a 25 MHZ MC68040 MC68040. · Harvard Architecture with Independent, Decoupled Fetch and Execution Pipelines. · Branch Prediction Logic with a 256-Entry, 4-Way Set-Associative, Virtual-Mapped Branch Cache for Improved Branch Instruction Performance. · A Superscalar Pipeline and Dual Integer Execution Units Achieving Simultaneous, but not Out-of-Order Instruction Execution. · An IEEE Standard, MC68040- MC68040- and MC68881-/MC68882-Compatible FPU. · An MC68040-Compatible Paged Memory Management Unit with Dual 64-Entry Address Translation Caches · Dual 8-Kbyte Caches (Instruction Cache and Data Cache) · A Flexible, High-Bandwidth Synchronous Bus Interface · User Object-Code Compatible with All Earlier M68000 M68000 Microprocessors 1.3 ARCHITECTURE The instruction fetch unit (IFU) is a four-stage pipeline for prefetching instructions. The dual operand execution pipelines (OEPs) (named primary" (pOEP) and secondary (sOEP) are four-stage pipelines for decoding the instructions, fetching the required operand(s), and then performing the actual execution of the instructions. Since the IFU and OEP are decoupled by a first-in-first-out (FIFO) instruction buffer, the IFU is able to prefetch instructions in advance of their actual use by the OEPs. The MC68060 MC68060 is designed to maximize the OEP's efficiency through the use of a superscalar pipeline architecture. This architectural advance improves processor performance dramatically by exploiting instruction-level parallelism. The term superscalar denotes the ability to detect, dispatch, execute, and return results from more than one instruction during each machine cycle from an otherwise conventional instruction stream. As a result, multiple instructions may be executed in a single machine cycle. Since the dual OEPs perform in a lock-step mode of operation, the multiple instruction execution is performed simultaneously, but not out-of-order. The net effect is a software-invisible pipeline architecture capable of sustained execution rates of < 1 machine cycle per instruction of the M68000 M68000 instruction set. 1-4 M68060 M68060 USER'S MANUAL MOTOROLA Introduction Architectural highlights of the MC68060 MC68060 include: · Four-Stage Instruction Fetch Unit (IFU) - 64-Entry Instruction Address Translation Cache (ATC), Organized as 4-Way SetAssociative, for Fast Virtual-to-Physical Address Translations - 8- Kbyte, 4-Way Set-Associative, Physically-Mapped Instruction Cache -256-Entry, 4-Way Set-Associative, Virtually-Mapped Branch Cache, Which Predicts the Direction of Branches Based on Their Past Execution History -96-Byte FIFO Instruction Buffer to Allow Decoupling of the IFP and OEPs · Four-Stage Execution Pipelines Featuring Primary Pipeline (pOEP), Secondary Pipeline (sOEP), and Register File (RGF) Containing Program-Visible General Registers - 64-Entry Operand Data ATC, Organized as 4-Way Set-Associative, for Fast Virtualto-Physical Address Translations - 8- Kbyte, 4-Way Set-Associative, Physically-Mapped Operand Data Cache - The Operand Data Cache Is Organized in a Banked Structure to Allow Simultaneous Read/Write Accesses - Integer Execute Engines Optimized to Perform Most Instruction Executions in a Single Machine Cycle -Floating-Point Execute Engine, with Floating-Point Register File, Optimized for Performance with Extended-Precision-Wide Internal Datapaths. -Four-Entry Store Buffer and One-Entry Push Buffer That Provide the Performance Feature of Decoupling the Processor Pipeline from External Memory for Certain Cache Modes of Operation. This pipeline architecture supports extremely high data transfer rates within the MC68060 MC68060 processor. The on-chip instruction and operand data caches provide 600 MBytes/sec @ 50 MHz to the pipelines, while the integer execute engines can support sustained transfer rates of 1.2 GBytes/sec. 1.4 PROCESSOR OVERVIEW The following paragraphs provide a general description of the MC68060 MC68060. 1.4.1 Functional Blocks Figure 1-1 illustrates a simplified block diagram of the MC68060 MC68060. MOTOROLA M68060 M68060 USER'S MANUAL 1-5 Introduction The architecture of the MC68060 MC68060 processor is implemented in the following major blocks: · Execution Unit -Instruction Fetch Unit -Integer Unit -FPU · Memory Units -Instruction Memory Unit · Instruction ATC · Instruction Cache · Instruction Cache Controller -Data Memory Unit · Data ATC · Data Cache · Data Cache Controller · Bus Controller These major units execute concurrently to maximize sustained performance. Note that the caches reside on separate buses allowing concurrent instruction fetch, data read, and data write operations (internal Harvard architecture). EXECUTION UNIT INSTRUCTION FETCH UNIT IAG IA CALCULATE INSTRUCTION IC FETCH IED EARLY DECODE BRANCH CACHE IB INSTRUCTION BUFFER pOEP EA FETCH FP EXECUTE INSTRUCTION CACHE ADDRESS INSTRUCTION CACHE CONTROLLER INSTRUCTION MEMORY UNIT DS DS DECODE EA CALCULATE AG EA CALCULATE AG OC EA FETCH OC EA FETCH OC EX INT EXECUTE EX INT EXECUTE EX DATA CACHE CONTROLLER DATA ATC INTEGER UNIT DATA AVAILABLE DA WRITE-BACK B U S C O N T R O L L E R sOEP DECODE FLOATINGPOINT UNIT INSTRUCTION ATC DATA CACHE DATA CONTROL DATA MEMORY UNIT WB OPERAND DATA BUS Figure 1-1. MC68060 MC68060 Block Diagram 1-6 M68060 M68060 USER'S MANUAL MOTOROLA Introduction The integer unit implements a subset of the MC68040 MC68040 instruction set. The FPU implements a subset of the MC68881/2 MC68881/2 coprocessor instruction set. The instruction and data memory units manage the ATCs and the instruction and data caches. The ATCs provide on-chip storage for the paged MMU's most recently used address translations. The data and instruction caches include the logic necessary to read, write, update, invalidate, and flush the caches. The bus controller manages the interface between the MMUs and the external bus. Snoop invalidation is supported to maintain cache consistency by monitoring the external bus when the processor is not the current master. 1.4.2 Integer Unit The MC68060 MC68060's integer unit carries out logical and arithmetic operations. The integer unit contains an instruction fetch controller, an instruction execution controller, and a branch target cache. The superscalar design of the MC68060 MC68060 provides dual execution pipelines in the instruction execution controller, providing simultaneous execution. The superscalar operation of the integer unit can be disabled in software, turning off the second execution pipeline for debugging. Disabling the superscalar operation also lowers performance and power consumption. 1.4.2.1 INSTRUCTION FETCH UNIT. The instruction fetch unit contains an instruction fetch pipeline and the logic that interfaces to the branch cache. The instruction fetch pipeline consists of four stages, providing the ability to prefetch instructions in advance of their actual use in the instruction execution controller. The continuous fetching of instructions keeps the instruction execution controller busy for the greatest possible performance. Every instruction passes through each of the four stages before entering the instruction execution controller. The four stages in the instruction fetch pipeline are: 1. Instruction Address Calculation (IAG)-The virtual address of the instruction is determined. 2. Instruction Fetch (IC)-The instruction is fetched from memory. 3. Early Decode (IED)-The instruction is pre-decoded for pipeline control information. 4. Instruction Buffer (IB)-The instruction and its pipeline control information are buffered until the integer execution pipeline is ready to process the instruction. The branch cache plays a major role in achieving the performance levels of the MC68060 MC68060. The concept of the branch cache is to provide a mechanism that allows the instruction fetch pipeline to detect and change the instruction stream before the change of flow affects the instruction execution controller. The branch cache is examined for a valid branch entry after each instruction fetch address is generated in the instruction fetch pipeline. If a hit does not occur in the branch target cache, the instruction fetch pipeline continues to fetch instructions sequentially. If a hit occurs in the branch cache, indicating a branch taken instruction, the current instruction stream is discarded and a new instruction stream is fetched starting at the location indicated by the branch cache. MOTOROLA M68060 M68060 USER'S MANUAL 1-7 Introduction 1.4.2.2 INTEGER UNIT. The integer unit contains dual integer execution pipelines, interface logic to the FPU, and control logic for data written to the data cache and MMU. The superscalar design of the dual integer execution pipelines provide for simultaneous instruction execution, which allows for processing more than on