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MC68060 Datasheet

Part Manufacturer Description PDF Type
MC68060 Motorola Product Brief Superscalar 32-Bit Microprocessors Original
MC68060AR Motorola Porting MC68040 Software to the MC68060 Original
MC68060CO Motorola MC68060ZU 304-TBGA Package Dimensions Case Outline 1137B-01 Original
MC68060DE Motorola MC68060 Production Device Errata Rev 4.0 Original
MC68060RC50 Motorola Superscalar 68K Microprocessor Original
MC68060RC60 Freescale Semiconductor Embedded - Microprocessors, Integrated Circuits (ICs), IC MPU 32BIT 68K 60MHZ 206-PGA Original
MC68060RC60 Motorola Superscalar 68K Microprocessor Original
MC68060UM Motorola M68060 Users Manual Includes MC68060, MC68LC060, and MC68EC060 Original
MC68060UMAD Freescale Semiconductor MC68060 User Manual Addendum Original
MC68060UMAD Motorola MC68060 User Manual Addendum Original
MC68060UMAD2 Freescale Semiconductor MC68060 Users Manual Addendum Original
MC68060ZUPOD Motorola MC68LC060 MC68LC060 and MC68EC060 304-TBGA Pinout Diagram Original

MC68060

Catalog Datasheet MFG & Type PDF Document Tags

MC68060

Abstract: 5Bp power control diagram of the MC68060. EXECUTION UNIT INSTRUCTION FETCH UNIT IAG IA CALCULATE INSTRUCTION IC , performance levels of the MC68060. It has been implemented such that most branches are executed in zero , . BRANCH CACHE The branch cache plays a major role in achieving the performance levels of the MC68060. The , detailed information on the MC68060. These documents may be obtained from the Literature Distribution , Technologies Group MC68060 MC68LC060 MC68EC060 Product Brief Freescale Semiconductor, Inc
Freescale Semiconductor
Original
M68060 5Bp power control M68060SP M68000 64 pin M68000PM/AD SAS controller chip M68000 M68060/D

M68882

Abstract: MC68040 MC68060 system. Both the MC68060ISP and MC68060FPSP are designed to be position-independent and , except for the new functions needed by the MC68060ISP. Although the main goal of the MC68060 Software , MC68060.This difference should not cause any problems since the MC68060 always treats external non-cacheable , discusses the software challenges that may arise when porting software to the new MC68060. The superscalar , both provide the full integer performance as the MC68060. However, these products are targeted for
Motorola
Original
MC68040 M68882 DSA0039258 MC68040-

MC68060

Abstract: M68060 MC68060. Refer to Section 7 Bus Operation for detailed information about the relationship of the , (CLK) CLK is the synchronous clock of the MC68060. This signal is used internally to clock or sequence , SECTION 2 SIGNAL DESCRIPTION This section contains brief descriptions of the MC68060 signals in , MC68060 signal names, mnemonics, and functional descriptions of the signals. Timing specifications for , Indicates the MC68060 will begin sampling the termination acknowledge signals. Transfer Acknowledge TA
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A31-A0 D31-D0 MOVE16

M680

Abstract: M68000 performanceAutomatic the MC68060. ItUnused Blocks of Lo - levels of Power-Down of has been implemented such that , Freescale Semiconductor, Inc. MC68060 SIGNALS Microprocessor and Memory Technologies Group Figure 2 shows the MC68060 functional signal groups. ADDRESS BUS AND CONTROL Freescale , TBI TCI CDIS MDIS RSTI RSTO MC68060 IPL2 IPL1 IPL0 IPEND AVEC BUS SNOOP CONTROL , new line of Mo M68060 product line consists of the MC68060, MC68 superscalar integer performance of
Freescale Semiconductor
Original
M680 MC68 mc68 motorola

M68882

Abstract: MC68040 Software Package (MC68060ISP) and the MC68060 Floating-Point Software Package (MC68060FPSP). The , MC68060 system. Both the MC68060ISP and MC68060FPSP are designed to be position-independent and , except for the new functions needed by the MC68060ISP. Although the main goal of the MC68060 Software , "cache-inhibited precise" when using the MC68060.This difference should not cause any problems since the MC68060 , software to the new MC68060. The superscalar MC68060 represents the latest generation of Freescale
Freescale Semiconductor
Original

M68000

Abstract: M68060 , unless otherwise noted. Figure 1 illustrates a block diagram of the MC68060. EXECUTION UNIT , performance levels of the MC68060. It has been implemented such that most branches are executed in zero , . BRANCH CACHE The branch cache plays a major role in achieving the performance levels of the MC68060. The , table contain detailed information on the MC68060. These documents may be obtained from the Literature , Order this document by M68060/D Microprocessor and Memory Technologies Group MC68060
Motorola
Original
BR1407

PROCESSOR

Abstract: EQUIVALENT replacement for Tip 41C M68060 derivatives operate differently from the MC68060. When reading this manual, disregard , MC68060-Arbitration Protocol (BTT Protocol). 7-58 External Arbiter , M68060 User's Manual Including the MC68060, MC68LC060, and MC68EC060 Motorola reserves the , USER'S MANUAL MOTOROLA PREFACE The complete documentation package for the MC68060, MC68LC060 , of this manual includes general information concerning the MC68060 and summarizes the differences
Motorola
Original
PROCESSOR EQUIVALENT replacement for Tip 41C HIGH VOLTAGE ISOLATION DZ 2101 DL128 TL431 7490

MC68060

Abstract: MC68LC060 secondary OEP (sOEP). Figure 3-1 shows the integer unit of the MC68060. EXECUTION UNIT FLOATINGPOINT UNIT EA , bits are configured with the value which identifies this device as an MC68060. These bits are ignored , support debug of designs that include the MC68060. When this bit is cleared, operation proceeds in a , SECTION 3 INTEGER UNIT This section describes the organization of the MC68060 integer unit and , EXECUTION PIPELINES The MC68060 integer unit execution pipelines are four-stage pipelines which perform
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idle bus

MC68040

Abstract: MC68060 Interfacing the MC68060 to the MC68360 This document describes the problems associated with interfacing the MC68060 to the QUICC and how to work around them. This document is describes the pertinent differences in bus timing between the MC68040 family and the MC68060. Other relevant information on power and clocking can be found in section 11 of the MC68060 users manual. Specification Differences There are 2 bus specification on the MC68060 that do not match the specifications of the MC68360. The following
Motorola
Original

MC68060FPSP

Abstract: M68000 of the MC68060. It has been implemented such that most branches are executed in zero cycles. Using a , MC68LC060 and the MC68EC060 differ from the MC68060. 1.1.1 MC68LC060 The MC68LC060 is a derivative of the MC68060. The MC68LC060 has the same execution unit and MMU as the MC68060, but has no FPU. The MC68LC060 is 100% pin compatible with the MC68060. Disregard all information concerning the FPU when reading , exception is taken. 1.1.2 MC68EC060 The MC68EC060 is a derivative of the MC68060. The MC68EC060 has the same
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cpu11

Abstract: CPU18 chips to match the MC68060's 32-bit bus, and standard system logic such as a decoder and a PLD. The , 3 Volt Intel® StrataFlashTM Memory to Motorola MC68060 CPU Design Guide Application Note 703 , . 1 3.0 Interfacing 3 Volt Intel® StrataFlashTM Memory to MC68060 at 66 MHz , StrataFlash memory's interface to the Motorola MC68060 processor. This document was written with preliminary , Interfacing 3 Volt Intel® StrataFlashTM Memory to MC68060 at 66 MHz The MC68060 series of microprocessors by
Intel
Original
28F128J3A 28F640J3A cpu11 CPU18 28F640J3 INTEL application notes 28F320J3A AP-703 38F320J3A AP-677 AP-664

M68000

Abstract: M68060 , unless otherwise noted. Figure 1 illustrates a block diagram of the MC68060. EXECUTION UNIT , plays a major role in achieving the high performance levels of the MC68060. It has been implemented , . BRANCH CACHE The branch cache plays a major role in achieving the performance levels of the MC68060. The , documents listed in the following table contain detailed information on the MC68060. These documents may be , Order this document by M68060/D Microprocessor and Memory Technologies Group MC68060
Motorola
Original

Motorola MC68030, MC68040 and MC68060 family

Abstract: MC68000 entries up to, and including the MC68060. This may be useful for writing handlers that apply to multiple , applies to the MC68060. In general, instruction descriptions that apply to the M68000 family, MC68040 or M68040FPSP apply also to the MC68060 or MC68060SP, unless otherwise provided in this appendix. Table D , , MC68LC040, MC68EC060, and MC68LC060. 3. These are software-supported instructions on the MC68040 and MC68060. , Save Internal Floating-Point State (MC68060 only) FSAVE The following state frames apply to the MC68060.
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MC68008 MC68882 MC68851 Motorola MC68030, MC68040 and MC68060 family MC68000 pin assignment of mc68008 MC68000/ MC68010 MC68020 MC68030 MC68881/

M68060SP

Abstract: MC68060FPSP : Unimplemented Integer Instruction Exception (MC68060ISP) When the MC68060 encounters an unimplemented integer , the MC68060ISP. 2. The MC68060ISP then calls the "core" emulation code for either "cas" or "cas2". The , the locked bus region for TAS and aligned CAS instructions. The MC68060ISP emulates the MC68060 , 'S MANUAL C-11 C.3 FLOATING-POINT EMULATION PACKAGE (MC68060FPSP) MC68060 Software Package The , APPENDIX C MC68060 SOFTWARE PACKAGE The purpose of the M68060 software package (M68060SP) is to
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c3231 026 MC68060ILSP VT100

MC68LC060

Abstract: M68000 , unless otherwise noted. Figure 1 illustrates a block diagram of the MC68060. EXECUTION UNIT , performance levels of the MC68060. It has been implemented such that most branches are executed in zero , CACHE The branch cache plays a major role in achieving the performance levels of the MC68060. The , documents listed in the following table contain detailed information on the MC68060. These documents may be , Order this document by M68060/D Microprocessor and Memory Technologies Group MC68060
Motorola
Original

M68060

Abstract: MC68020 internal operation or timing of the MC68060. Its main purpose is to allow for easier system design. CLKEN , SECTION 7 BUS OPERATION The MC68060 bus interface supports synchronous data transfers between the , , refer to Section 12 Electrical and Thermal Characteristics. 7.1 BUS CHARACTERISTICS The MC68060 uses the , terminating it using the control signals. The MC68060 CLK is distributed internally to provide logic timing , rising CLK edges when CLKEN is negated. Inputs to the MC68060 (other than the IPLx and RSTI signals) are
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MC68150 A31A0

MC88926

Abstract: 6ca DIODE MC68060-based node, or vice-versa. The floating-point frames are different between an MC68040 and MC68060 , the MC68060. 11.1 GUIDELINES FOR PORTING SOFTWARE TO THE MC68060 The following paragraphs describe the , M68040FPSP does not work properly with the MC68060. The M68060SP must be installed before any of the new , , the stack frame generated by the MC68040 is significantly different from that of the MC68060. Resource , MC68040 TCR writes probably write these new bits as zeroes, which would mean that the MC68060's default
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MC88926 6ca DIODE MC68681 "pin compatible" MC68EC040 BR1333/D MC88915/916 MCM62940 DL113 MC68150/D

MC68060FE

Abstract: MC68060RC50 MC68060RC50 PGAâ'"RC Suffix 66 MHz 110° C 0° C MC68060RC66 PGAâ'"RC Suffix 50 MHz 110° C 0° C , , pin assignments, and package dimensions of the MC68060, MC68LC060, and MC68EC060. 13.1 ORDERING INFORMATION The following table provides ordering information pertaining to the MC68060, MC68LC060, and , MC68EC060RC66 208-Pin QFPâ'"FE Suffix 50 MHz 110° C 0° C MC68060FE50 208-Pin QFPâ'"FE Suffix 66 MHz 110° C 0° C MC68060FE66 208-Pin QFPâ'"FE Suffix 50 MHz 110° C 0° C MC68LC060FE50 208-Pin QFPâ'"FE Suffix 66
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MC68LC060RC50 MC68LC060RC66 MC68EC060RC50 MC68060FE TEA 1530 9940-1 MC68EC060RC40 208-P MC68LC060FE66

M68060

Abstract: M68060SP paragraphs describe the FPU portion of the user programming model for the MC68060. The model, which is , data formats and data types supported by the MC68060. Table 6-4 through Table 6-7 summarize the , floating-point instructions which are unimplemented on the MC68060. Refer to 8.2.4 Illegal Instruction and , that includes floating-point emulation for the MC68060. Refer to Appendix C for software porting , MC68060-implemented instructions. 6.5.2 Unsupported Floating-Point Data Types An unsupported data type exception
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MC68881 MC68881/MC68882

solna d30

Abstract: M68060 these M68060 derivatives operate differently from the MC68060. When reading this manual, disregard , MC68060-Arbitration Protocol (BTT Protocol). 7-58 External Arbiter , Instruction Library (MC68060ILSP) .C-9 Floating-Point Emulation Package (MC68060FPSP , M68060 User's Manual Including the MC68060, MC68LC060, and MC68EC060 Motorola reserves the , MC68060, MC68LC060, and MC68EC060 (collectively called M68060) consists of the M68060UM/AD, M68060 User
Motorola
Original
solna d30

MC68060

Abstract: XBS2 , which are available on the MC68060. 9.1 IEEE 1149.1 TEST ACCESS PORT (NORMAL JTAG) MODE The MC68060 , the LPSTOP function interact. This case is not formally addressed by the standard, but the MC68060 , those items that are specific to the MC68060 implementation. The MC68060 JTAG test architecture , and restrictions set forth for the use of a JTAG compliance enable pin. The MC68060 JTAG , continuity, 2. Bypass the MC68060 by reducing the shift register path to a single cell, 3. Sample the MC68060
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XBS2 MC68060 version
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