56F8356/56F8156 56F8300 MC56F8356 56F8156 56F8356 256KB GPIOA8-13 A8-15 - Datasheet Archive

 

Data Sheet Preliminary Technical Data 56F8300 16-bit Digital Signal Controllers MC56F8356 Rev. 10.0 12/2005 freescale.com

 

56F8356/56F8156 56F8356/56F8156 Data Sheet Preliminary Technical Data 56F8300 56F8300 16-bit Digital Signal Controllers MC56F8356 MC56F8356 Rev. 10.0 12/2005 freescale.com Document Revision History Version History Description of Change Rev 1.0 Initial Public Release Rev 2.0 Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO). Added "Typical Min" values to Table 10-18. Editing grammar, spelling, consistency of language throughout family. Updated values in Regulator Parameters Table 10-9, External Clock Operation Timing Requirements Table 10-13, SPI Timing Table 10-18, ADC Parameters Table 10-24, and IO Loading Coefficients at 10MHz Table 10-25. Rev 3.0 Added Part 4.8, added the word "access" to FM Error Interrupt in Table 4-5, documenting only Typ. numbers for LVI in Table 10-6, updated EMI numbers and writeup in Part 10.8. Rev 4.0 Updated numbers in Table 10-7 and Table 10-8 with more recent data, Corrected typo in Table 10-3 in Pd characteristics. Rev 5.0 Replace any reference to Flash Interface Unit with Flash Memory Module; corrected thermal numbers for 144 LQFP in Table 10-3; removed unneccessary notes in Table 10-12; corrected temperature range in Table 10-14; added ADC calibration information to Table 10-24 and new graphs in Figure 10-22 Rev 6.0 Adding/clarifing notes to Table 4-4 to help clarify independent program flash blocks and other Program Flash modes, clarification to Table 10-23, corrected Digital Input Current Low (pull-up enabled) numbers in Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1. Rev 7.0 Added 56F8156 56F8156 information; edited to indicate differences in 56F8356 56F8356 and 56F8156 56F8156. Reformatted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then updated balance of electrical tables for consistency throughout family. Clarified I/O power description in Table 2-2, added note to Table 10-7 and clarified Section 12.3. Rev 8.0 Added output voltage maximum value and note to clarify in Table 10-1; also removed overall life expectancy note, since life expectancy is dependent on customer usage and must be determined by reliability engineering. Clarified value and unit measure for Maximum allowed PD in Table 10-3. Corrected note about average value for Flash Data Retention in Table 10-4. Added new RoHS-compliant orderable part numbers in Table 13-1. Rev 9.0 Updated Table 10-24 to reflect new value for maximum Uncalibrated Gain Error Rev 10.0 Deleted RSTO from Pin Group 2 (listed after Table 10-1). Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in Table 10-4. Added RoHS-compliance and "pb-free" language to back cover. Please see http://www.freescale.com for the most current Data Sheet revision. 56F8356 56F8356 Technical Data, Rev. 10.0 2 Freescale Semiconductor Preliminary 56F8356/56F8156 56F8356/56F8156 General Description Note: Features in italics are NOT available in the 56F8156 56F8156 device. · Up to 60 MIPS at 60MHz core frequency · Temperature Sensor · DSP and MCU functionality in a unified, C-efficient architecture · Up to two Quadrature Decoders · Access up to 1MB of off-chip program and data memory · FlexCAN module · Chip Select Logic for glueless interface to ROM and SRAM · Two Serial Communication Interfaces (SCIs) · Optional on-chip regulator · Up to two Serial Peripheral Interfaces (SPIs) · 256KB 256KB of Program Flash · Up to four general-purpose Quad Timers · 4KB of Program RAM · Computer Operating Properly (COP) / Watchdog · 8KB of Data Flash · 16KB of Data RAM · JTAG/Enhanced On-Chip Emulation (OnCETM) for unobtrusive, real-time debugging · 16KB of Boot Flash · Up to 62 GPIO lines · Up to two 6-channel PWM modules · 144-pin LQFP Package · Four 4-channel, 12-bit ADCs RSTO EXTBOOT RESET Current Sense Inputs or GPIOC Fault Inputs 3 6 3 4 4 PWM Outputs PWM Outputs Current Sense Inputs or GPIOD Fault Inputs Program Controller and Hardware Looping Unit 4 AD1 ADCA Program Memory 128K x 16 Flash 2K x 16 RAM ADCB AD1 TEMP_SENSE 4 4 Quadrature Decoder 0 or Quad Timer A or GPIOC Quad Timer C or GPIOE 2 FlexCAN Bit Manipulation Unit 6 External Address Bus Switch 2 8 PAB 8K x 16 Boot Flash Data Memory 4K x 16 Flash 8K x 16 RAM A0-5 or GPIOA8-13 GPIOA8-13 A6-7 or GPIOE2-3 A8-15 A8-15 or GPIOA0-7 GPIOB0 or A16 System Bus Control PDB CDBR CDBW 7 External Data Bus Switch D0-6 or GPIOF9-15 GPIOF9-15 9 D7-15 D7-15 or GPIOF0-8 Bus Control 2 WR RD IPBus Bridge (IPBB) GPIOD0-1 or CS2-3 PS or CS0 or GPIOD8 Peripheral Device Selects Decoding RW Control IPAB IPWDB Quad Timer D or GPIOE 2 Analog Reg Data ALU 16 x 16 + 36 -> 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Address Generation Unit VSSA Low Voltage Supervisor XDB2 XAB1 XAB2 Quadrature Decoder 1 or Quad Timer B or SPI1 or GPIOC 1 VDDA 2 5 Digital Reg 16-Bit 56800E 56800E Core Memory AD0 4 7 R/W Control VREF 4 4 PAB PDB CDBR CDBW AD0 5 OCR_DIS VDD Vss JTAG/ EOnCE Port PWMA PWMB VCAP 2 5 External Bus Interface Unit 6 3 VPP EMI_MODE DS or CS1 or GPIOD9 IPRDB Peripherals Clock resets SPI0 or GPIOE 4 SCI1 or GPIOD 2 SCI0 or GPIOE 2 COP/ Watchdog Interrupt Controller IRQA IRQB P System O Integration R Module PLL O Clock S Generator C XTAL EXTAL CLKO CLKMODE 56F8356 56F8356 / 56F8156 56F8156 Block Diagram 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 3 Table of Contents Part 1: Overview . . . . . . . . . . . . . . . . . . . . . . . 5 1.1. 1.2. 1.3. 1.4. 1.5. 1.6. 56F8356/56F8156 56F8356/56F8156 Features . . . . . . . . . . . . . 5 Device Description . . . . . . . . . . . . . . . . . . . . 7 Award-Winning Development Environment . 9 Architecture Block Diagram . . . . . . . . . . . . 10 Product Documentation . . . . . . . . . . . . . . . 14 Data Sheet Conventions . . . . . . . . . . . . . . 14 Part 2: Signal/Connection Descriptions . . . 15 2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18 Part 3: On-Chip Clock Synthesis (OCCS) . . 37 3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 37 3.2. External Clock Operation . . . . . . . . . . . . . . 37 3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Part 4: Memory Map . . . . . . . . . . . . . . . . . . . 39 4.1. 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . Program Map . . . . . . . . . . . . . . . . . . . . . . . Interrupt Vector Table . . . . . . . . . . . . . . . . . Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . Flash Memory Map . . . . . . . . . . . . . . . . . . . EOnCE Memory Map . . . . . . . . . . . . . . . . . Peripheral Memory Mapped Registers . . . . Factory Programmed Memory . . . . . . . . . . 39 40 42 46 46 48 49 76 Part 5: Interrupt Controller (ITCN) . . . . . . . . 77 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 77 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Functional Description . . . . . . . . . . . . . . . . 77 Block Diagram . . . . . . . . . . . . . . . . . . . . . . 79 Operating Modes . . . . . . . . . . . . . . . . . . . . 79 Register Descriptions . . . . . . . . . . . . . . . . . 80 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Part 6: System Integration Module (SIM) . 107 6.1. 6.2. 6.3. 6.4. 6.5. 6.6. 6.7. 6.8. 6.9. Overview . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Modes . . . . . . . . . . . . . . . . . . . Operating Mode Register . . . . . . . . . . . . . Register Descriptions . . . . . . . . . . . . . . . . Clock Generation Overview . . . . . . . . . . . Power-Down Modes Overview . . . . . . . . . Stop and Wait Mode Disable Function . . . Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 107 108 108 109 122 123 123 124 Part 8: General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . . . . . 127 8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 127 8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 128 8.3. Configuration . . . . . . . . . . . . . . . . . . . . . . . 128 Part 9: Joint Test Action Group (JTAG) . 133 9.1. 56F8356 56F8356 Information . . . . . . . . . . . . . . . . . 133 Part 10: Specifications . . . . . . . . . . . . . . . 134 10.1. General Characteristics . . . . . . . . . . . . . . 134 10.2. DC Electrical Characteristics . . . . . . . . . . 138 10.3. AC Electrical Characteristics . . . . . . . . . . 142 10.4. Flash Memory Characteristics . . . . . . . . . 142 10.5. External Clock Operation Timing . . . . . . . 143 10.6. Phase Locked Loop Timing . . . . . . . . . . . 143 10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 144 10.8. External Memory Interface Timing . . . . . . 144 10.9. Reset, Stop, Wait, Mode Select, and Interrupt Timing . . . . . . . . . . . . . . 147 10.10. Serial Peripheral Interface (SPI) Timing . 149 10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 153 10.12. Quadrature Decoder Timing . . . . . . . . . . 153 10.13. Serial Communication Interface (SCI) Timing . . . . . . . . . . . . . . . . . . . . . 154 10.14. Controller Area Network (CAN) Timing . 155 10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 155 10.16. Analog-to-Digital Converter (ADC) Parameters . . . . . . . . . . . . . . . . . 157 10.17. Equivalent Circuit for ADC Inputs . . . . . . 160 10.18. Power Consumption . . . . . . . . . . . . . . . . 160 Part 11: Packaging . . . . . . . . . . . . . . . . . . 162 11.1. 56F8356 56F8356 Package and Pin-Out Information . . . . . . . . . . . . . . . . . . 162 11.2. 56F8156 56F8156 Package and Pin-Out Information . . . . . . . . . . . . . . . . . . 165 Part 12: Design Considerations . . . . . . . . 169 12.1. Thermal Design Considerations . . . . . . . . 169 12.2. Electrical Design Considerations . . . . . . . 170 12.3. Power Distribution and I/O Ring Implementation . . . . . . . . . . . . . . 171 Part 13: Ordering Information . . . . . . . . . 172 Part 7: Security Features . . . . . . . . . . . . . . 124 7.1. Operation with Security Enabled . . . . . . . 124 7.2. Flash Access Blocking Mechanisms . . . . 125 56F8356 56F8356 Technical Data, Rev. 10.0 4 Freescale Semiconductor Preliminary 56F8356/56F8156 56F8356/56F8156 Features Part 1 Overview 1.1 56F8356/56F8156 56F8356/56F8156 Features 1.1.1 · · · · · · · · · · · · · · 1.1.2 Core Efficient 16-bit 56800E 56800E family controller engine with dual Harvard architecture Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Four 36-bit accumulators, including extension bits Arithmetic and logic multi-bit shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal address buses Four internal data buses Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/EOnCE debug programming interface Differences Between Devices Table 1-1 outlines the key differences between the 56F8356 56F8356 and 56F8156 56F8156 devices. Table 1-1 Device Differences Feature 56F8356 56F8356 56F8156 56F8156 Guaranteed Speed 60MHz/60 MIPS 40MHz/40 MIPS Program RAM 4KB Not Available Data Flash 8KB Not Available PWM 2x6 1x6 CAN 1 Not Available Quad Timer 4 2 Quadrature Decoder 2x4 1x4 Temperature Sensor 1 Not Available Dedicated GPIO - 5 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 5 1.1.3 Memory Note: Features in italics ae NOT available in the 56F8156 56F8156 device. · · · Harvard architecture permits as many as three simultaneous accesses to program and data memory Flash security protection feature On-chip memory, including a low-cost, high-volume Flash solution - 256KB 256KB of Program Flash - 4KB of Program RAM - 8KB of Data Flash - 16KB of Data RAM - 16KB of Boot Flash · Off-chip memory expansion capabilities programmable for 0 - 30 wait states - Access up to 1MB of program memory or 1MB of data memory - Chip select logic for glueless interface to ROM and SRAM · 1.1.4 EEPROM emulation capability Peripheral Circuits Note: Features in italics are NOT available in the 56F8156 56F8156 device. · Pulse Width Modulator: - In the 56F8356 56F8356, two Pulse Width Modulator modules, each with six PWM outputs, three Current Sense inputs, and three Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned modes - In the 56F8156 56F8156, one Pulse Width Modulator module with six PWM outputs, three Current Sense inputs, and three Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and edge-aligned modes · · Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer C, channels 2 and 3 Quadrature Decoder: - In the 56F8356 56F8356, two four-input Quadrature Decoders or two additional Quad Timers - In the 56F8156 56F8156, one four-input Quadrature Decoder, which works in conjunction with Quad Timer A · · Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the on-chip temperature Quad Timer: - In the 56F8356 56F8356, four dedicated general-purpose Quad Timers totaling three dedicated pins: Timer C with one pin and Timer D with two pins - In the 56F8156 56F8156, two Quad Timers; Timer A and Timer C both work in conjunction with GPIO · · Optional on-chip regulator FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive 56F8356 56F8356 Technical Data, Rev. 10.0 6 Freescale Semiconductor Preliminary Device Description · · Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO lines) - In the 56F8356 56F8356, SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B - In the 56F8156 56F8156, SPI1 can alternately be used only as GPIO · · · · · · · · 1.1.5 · · · · · · Computer Operating Properly (COP) / Watchdog timer Two dedicated external interrupt pins 62 General Purpose I/O (GPIO) pins External reset input pin for hardware reset External reset output pin for system reset Integrated low-voltage interrupt module JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock Energy Information Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available ADC smart power management Each peripheral can be individually disabled to save power 1.2 Device Description The 56F8356 56F8356 and 56F8156 56F8156 are members of the 56800E 56800E core-based family of controllers. Each combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8356 56F8356 and 56F8156 56F8156 are well-suited for many applications. The devices include many peripherals that are especially useful for motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control (56F8156 56F8156 only), engine management, noise suppression, remote utility metering, industrial control for power, lighting, and automation applications. The 56800E 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C/C+ Compilers to enable rapid development of optimized control applications. The 56F8356 56F8356 and 56F8156 56F8156 support program execution from either internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide two external dedicated interrupt lines and up to 62 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 7 1.2.1 56F8356 56F8356 Features The 56F8356 56F8356 controller includes 256KB 256KB of Program Flash and 8KB of Data Flash (each programmable through the JTAG port) with 4KB of Program RAM and 16KB of Data RAM. It also supports program execution from external memory. A total of 16KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot and Data Flash page erase size is 512 bytes. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F8356 56F8356 is the inclusion of two Pulse Width Modulator (PWM) modules. These modules each incorporate three complementary, individually programmable PWM signal output pairs (each module is also capable of supporting six independent PWM functions, for a total of 12 PWM outputs) to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A "smoke-inhibit", write-once protection feature for key parameters is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM modules provide reference outputs to synchronize the Analog-to-Digital Converters through two channels of Quad Timer C. The 56F8356 56F8356 incorporates two Quadrature Decoders capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder can be programmed with a time-out value to alert when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and four Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. A Flex Controller Area Network (FlexCAN) interface (CAN Version 2.0 B-compliant) and an internal interrupt controller are a part of the 56F8356 56F8356. 1.2.2 56F8156 56F8156 Features The 56F8156 56F8156 controller includes 256KB 256KB of Program Flash, programmable through the JTAG port, with 16KB of Data RAM. It also supports program execution from external memory. A total of 16KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program Flash memory areas, which can be independently bulk erased or erased in pages. Program Flash page erase size is 1KB. Boot Flash page erase size is 512 bytes. and the Boot Flash memory can also be either bulk or page erased. 56F8356 56F8356 Technical Data, Rev. 10.0 8 Freescale Semiconductor Preliminary Award-Winning Development Environment A key application-specific feature of the 56F8156 56F8156 is the inclusion of one Pulse Width Modulator (PWM) module. This module incorporates three complementary, individually programmable PWM signal output pairs and can also support six independent PWM functions to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge-aligned and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors); both BDC and BLDC (Brush and Brushless DC motors); SRM and VRM (Switched and Variable Reluctance Motors); and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A "smoke-inhibit", write-once protection feature for key parameters is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM module provides reference outputs to synchronize the Analog-to-Digital Converters through two channels of Quad Timer C. The 56F8156 56F8156 incorporates a Quadrature Decoder capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder can be programmed with a time-out value to alert when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCIs); two Serial Peripheral Interfaces (SPIs); and two Quad Timers. Any of these interfaces can be used as General Purpose Input/Outputs (GPIOs) if that function is not required. An internal interrupt controller are a part of the 56F8156 56F8156. 1.3 Award-Winning Development Environment Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The CodeWarrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, CodeWarrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 9 1.4 Architecture Block Diagram Note: Features in italics are NOT available in the 56F8156 56F8156 device and are shaded in the following figures. The 56F8356/56F8156 56F8356/56F8156 architecture is shown in Figure 1-1 and Figure 1-2. Figure 1-1 illustrates how the 56800E 56800E system buses communicate with internal memories, the external memory interface and the IPBus Bridge. Table 1-2 lists the internal buses in the 56800E 56800E architecture and provides a brief description of their function. Figure 1-2 shows the peripherals and control blocks connected to the IPBus Bridge. The figures do not show the on-board regulator and power and ground signals. They also do not show the multiplexing between peripherals or the dedicated GPIOs. Please see Part 2, Signal/Connection Descriptions, to see which signals are multiplexed with those of other peripherals. Also shown in Figure 1-2 are connections between the PWM, Timer C and ADC blocks. These connections allow the PWM and/or Timer C to control the timing of the start of ADC conversions. The Timer C channel indicated can generate periodic start (SYNC) signals to the ADC to start its conversions. In another operating mode, the PWM load interrupt (SYNC output) signal is routed internally to the Timer C input channel as indicated. The timer can then be used to introduce a controllable delay before generating its output signal. The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals. 56F8356 56F8356 Technical Data, Rev. 10.0 10 Freescale Semiconductor Preliminary Architecture Block Diagram 5 JTAG / EOnCE Boot Flash pdb_m[15:0] pab[20:0] Program Flash cdbw[31:0] Program RAM 56800E 56800E 17 CHIP TAP Controller EMI 16 6 Address Data Control TAP Linking xab1[23:0] xab2[23:0] External JTAG Port Data RAM Data Flash cdbr_m[31:0] xdb2_m[15:0] IPBus Bridge To Flash Control Logic Flash Module NOT available on the 56F8156 56F8156 device. IPBus Figure 1-1 System Bus Interfaces Note: Flash memories are encapsulated within the Flash Module(FM). Flash control is accomplished by the I/O to the FM over the peripheral bus, while reads and writes are completed between the core and the Flash memories. Note: The primary data RAM port is 32 bits wide. Other data ports are 16 bits. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 11 To/From IPBus Bridge Interrupt Controller CLKGEN (OSC/PLL) Low Voltage Interrupt Timer A POR & LVI 4 System POR Quadrature Decoder 0 RESET SIM 2 Timer D COP Reset Timer B 4 COP 2 FlexCAN Quadrature Decoder 1 SPI 1 12 PWMA SYNC Output GPIOA 13 PWMB GPIOB SYNC Output GPIOC ch2i ch3i 1 Timer C GPIOD ch2o ch3o GPIOE GPIOF 4 2 ADCB SPI0 8 ADCA SCI0 TEMP_SENSE 2 8 1 SCI1 NOT available on the 56F8156 56F8156 device. IPBus Note: ADCA and ADCB use the same voltage reference circuit with VREFH, VREFP, VREFMID, VREFN, and VREFLO pins. Figure 1-2 Peripheral Subsystem 56F8356 56F8356 Technical Data, Rev. 10.0 12 Freescale Semiconductor Preliminary Architecture Block Diagram Table 1-2 Bus Signal Names Name Function Program Memory Interface pdb_m[15:0] Program data bus for instruction word fetches or read operations. cdbw[15:0] Primary core data bus used for program memory writes. (Only these 16 bits of the cdbw[31:0] bus are used for writes to program memory.) pab[20:0] Program memory address bus. Data is returned on pdb_m bus. Primary Data Memory Interface Bus cdbr_m[31:0] Primary core data bus for memory reads. Addressed via xab1 bus. cdbw[31:0] Primary core data bus for memory writes. Addressed via xab1 bus. xab1[23:0] Primary data address bus. Capable of addressing bytes1, words, and long data types. Data is written on cdbw and returned on cdbr_m. Also used to access memory-mapped I/O. Secondary Data Memory Interface xdb2_m[15:0] Secondary data bus used for secondary data address bus xab2 in the dual memory reads. xab2[23:0] Secondary data address bus used for the second of two simultaneous accesses. Capable of addressing only words. Data is returned on xdb2_m. Peripheral Interface Bus IPBus [15:0] Peripheral bus accesses all on-chip peripherals registers. This bus operates at the same clock rate as the Primary Data Memory and therefore generates no delays when accessing the processor. Write data is obtained from cdbw. Read data is provided to cdbr_m. 1. Byte accesses can only occur in the bottom half of the memory address space. The MSB of the address will be forced to 0. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 13 1.5 Product Documentation The documents in Table 1-3 are required for a complete description and proper design with the 56F8356/56F8156 56F8356/56F8156 devices. Documentation is available from local Freescale distributors, Freescale semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com. Table 1-3 Chip Documentation Topic Description Order Number DSP56800E DSP56800E Reference Manual Detailed description of the 56800E 56800E family architecture, and 16-bit controller core processor and the instruction set DSP56800ERM DSP56800ERM 56F8300 56F8300 Peripheral User Manual Detailed description of peripherals of the 56F8300 56F8300 devices MC56F8300UM MC56F8300UM 56F8300 56F8300 SCI/CAN Bootloader User Manual Detailed description of the SCI/CAN Bootloaders 56F8300 56F8300 family of devices MC56F83xxBLUM 56F8356/56F8156 56F8356/56F8156 Technical Data Sheet Electrical and timing specifications, pin descriptions, and package descriptions (this document) MC56F8356 MC56F8356 Errata Details any chip issues that might be present MC56F8356E MC56F8356E MC56F8156E MC56F8156E 1.6 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. "asserted" A high true (active high) signal is high or a low true (active low) signal is low. "deasserted" A high true (active high) signal is low or a low true (active low) signal is high. Examples: Signal/Symbol Logic State Signal State Voltage1 PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56F8356 56F8356 Technical Data, Rev. 10.0 14 Freescale Semiconductor Preliminary Introduction Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F8356 56F8356 and 56F8156 56F8156 are organized into functional groups, as detailed in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2, each table row describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Number of Pins in Package Functional Group 56F8356 56F8356 56F8156 56F8156 Power (VDD or VDDA) 9 9 Power Option Control 1 1 Ground (VSS or VSSA) 6 6 Supply Capacitors1 & VPP 6 6 PLL and Clock 4 4 Address Bus 17 17 Data Bus 16 16 Bus Control 6 6 Interrupt and Program Control 6 6 Pulse Width Modulator (PWM) Ports 25 13 Serial Peripheral Interface (SPI) Port 0 4 4 Serial Peripheral Interface (SPI) Port 1 - 4 Quadrature Decoder Port 02 4 4 Quadrature Decoder Port 13 4 - Serial Communications Interface (SCI) Ports 4 4 CAN Ports 2 - Analog to Digital Converter (ADC) Ports 21 21 Quad Timer Module Ports 3 1 JTAG/Enhanced On-Chip Emulation (EOnCE) 5 5 Temperature Sense 1 - Dedicated GPIO - 5 1. If the on-chip regulator is disabled, the VCAP pins serve as 2.5V VDD_CORE power inputs 2. Alternately, can function as Quad Timer pins or GPIO 3. Pins in this section can function as Quad Timer, SPI #1, or GPIO 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 15 Power VDD_IO Power VDDA_ADC Power VDDA_OSC_PLL Ground VSS Ground VSSA_ADC OCR_DIS Other Supply Ports PLL and Clock VCAP1 - VCAP4 VPP1 & VPP2 CLKMODE EXTAL XTAL CLKO A0 - A5 (GPIOA8 - 13) External Address Bus or GPIO External Data Bus or GPIO A6 - A7 (GPIOE2 - 3) A8 - A15 (GPIOA0 - 7) GPIOB0 (A16) D0 - D6 (GPIOF9 - 15) D7 - D15 (GPIOF0 - 8) RD External Bus Control or GPIO WR PS / CS0 (GPIOD8) DS / CS1 (GPIOD9) GPIOD0 - 1 (CS2 - 3) 7 1 1 1 1 1 5 1 1 1 4 2 1 1 1 1 56F8356 56F8356 1 1 1 1 1 1 1 1 SCI 0 or GPIO 6 8 1 3 7 6 3 9 3 4 8 1 1 1 5 8 1 2 1 1 1 1 1 SCI 1 or GPIO JTAG/ EOnCE Port TXD1 (GPIOD6) RXD1 (GPIOD7) TCK TMS TDI TDO TRST HOME0 (TA3, GPIOC7) SCLK0 (GPIOE4) MOSI0 (GPIOE5) MISO0 (GPIOE6) SPI0 or GPIO SS0 (GPIOE7) PHASEA1(TB0, SCLK1, GPIOC0) PHASEB1 (TB1, MOSI1, GPIOC1) INDEX1 (TB2, MISO1, GPIOC2) HOME1 (TB3, SS1, GPIOC3) Quadrature Decoder 1 or Quad Timer B or SPI 1 or GPIO PWMA0 - 5 ISA0 - 2 (GPIOC8 - 10) FAULTA0 - 2 PWMA or GPIO 6 2 1 TXD0 (GPIOE0) RXD0 (GPIOE1) Quadrature Decoder 0 or Quad Timer A or GPIO PHASEA0 (TA0, GPIOC4) PHASEB0 (TA1, GPIOC5) INDEX0 (TA2, GPIOC6) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 PWMB0 - 5 ISB0 - 2 (GPIOD10 GPIOD10 - 12) FAULTB0 - 3 ANA0 - 7 VREF PWMB or GPIO ADCA ADCB ANB0 - 7 TEMP_SENSE Temperature Sensor CAN_RX CAN_TX FlexCAN TC0 (GPIOE8) TD0 - 1 (GPIOE10 GPIOE10 - 11) QUAD TIMER C and D or GPIO IRQA IRQB EXTBOOT EMI_MODE RESET INTERRUPT/ PROGRAM CONTROL RSTO Figure 2-1 56F8356 56F8356 Signals Identified by Functional Group1 (144-pin LQFP) 1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. 56F8356 56F8356 Technical Data, Rev. 10.0 16 Freescale Semiconductor Preliminary Introduction Power VDD_IO Power VDDA_ADC Power VDDA_OSC_PLL Ground VSS Ground VSSA_ADC OCR_DIS VCAP1 - VCAP4 Other Supply Ports VPP1 & VPP2 CLKMODE EXTAL XTAL CLKO PLL and Clock A0 - A5 (GPIOA8 - 13) External Address Bus or GPIO External Data Bus or GPIO A6 - A7 (GPIOE2 - 3) A8 - A15 (GPIOA0 - 7) GPIOB0 (A16) D0 - D6 (GPIOF9 - 15) D7 - D15 (GPIOF0 - 8) RD External Bus Control or GPIO WR PS / CS0 (GPIOD8) DS / CS1 (GPIOD9) GPIOD0 - 1 (CS2 - 3) SCI 0 or GPIO TXD0 (GPIOE0) RXD0 (GPIOE1) SCI 1 or GPIO TXD1 (GPIOD6) RXD1 (GPIOD7) JTAG/ EOnCE Port TCK TMS TDI TDO TRST 7 1 1 1 1 5 1 1 PHASEA0 (TA0, GPIOC4) PHASEB0 (TA1, GPIOC5) INDEX0 (TA2, GPIOC6) HOME0 (TA3, GPIOC7) Quadrature Decoder 0 or Quad Timer A or GPIO 1 1 4 2 56F8356 56F8356 1 1 1 1 1 1 1 1 1 1 1 1 SCLK0 (GPIOE4) MOSI0 (GPIOE5) MISO0 (GPIOE6) SPI0 or GPIO SS0 (GPIOE7) (SCLK1, GPIOC0) (MOSI1, GPIOC1) (MISO1, GPIOC2) SPI 1 or GPIO (SS1, GPIOC3) 6 2 8 1 7 9 3 6 3 4 8 1 1 5 8 (GPIOC8 - 10) PWMB0 - 5 ISB0 - 2 (GPIOD10 GPIOD10 - 12) FAULTB0 - 3 ANA0 - 7 VREF GPIO PWMB or GPIO ADCA ADCB ANB0 - 7 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 TC0 (GPIOE8) TD0 - 1 (GPIOE10 GPIOE10 - 11) QUAD TIMER C or GPIO IRQA IRQB EXTBOOT EMI_MODE RESET INTERRUPT/ PROGRAM CONTROL RSTO Figure 2-2 56F8156 56F8156 Signals Identified by Functional Group1 (144-pin LQFP) 1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 17 2.2 Signal Pins After reset, each pin is configured for its primary function (listed first). Any alternate functionality must be programmed. If the "State During Reset" lists more than one state for a pin, the first state is the actual reset state. Other states show the reset condition of the alternate function, which you get if the alternate pin function is selected without changing the configuration of the alternate peripheral. For example, the A8/GPIOA0 pin shows that it is tri-stated during reset. If the GPIOA_PER is changed to select the GPIO function of the pin, it will become an input if no other registers are changed. Table 2-2 Signal and Package Information for the 144-Pin LQFP State During Reset Signal Name Pin No. Type Signal Description VDD_IO 1 Supply VDD_IO 16 I/O Power - This pin supplies 3.3V power to the chip I/O interface and also the Processor core throught the on-chip voltage regulator, if it is enabled. VDD_IO 31 VDD_IO 38 VDD_IO 66 VDD_IO 84 VDD_IO 119 VDDA_ADC 102 Supply ADC Power - This pin supplies 3.3V power to the ADC modules. It must be connected to a clean analog power supply. VDDA_OSC_PLL 80 Supply Oscillator and PLL Power - This pin supplies 3.3V power to the OSC and to the internal regulator that in turn supplies the Phase Locked Loop. It must be connected to a clean analog power supply. VSS 27 Supply VSS - These pins provide ground for chip logic and I/O drivers. VSS 37 VSS 63 VSS 69 VSS 144 VSSA_ADC 103 Supply ADC Analog Ground - This pin supplies an analog ground to the ADC modules. 56F8356 56F8356 Technical Data, Rev. 10.0 18 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset OCR_DIS 79 Input Input Signal Description On-Chip Regulator Disable - Tie this pin to VSS to enable the on-chip regulator Tie this pin to VDD to disable the on-chip regulator This pin is intended to be a static DC signal from power-up to shut down. Do not try to toggle this pin for power savings during operation. VCAP1 51 VCAP2 128 VCAP3 83 VCAP4 15 VPP1 125 VPP2 2 CLKMODE 87 Supply Supply VCAP1 - 4 - When OCR_DIS is tied to VSS (regulator enabled), connect each pin to a 2.2µF or greater bypass capacitor in order to bypass the core logic voltage regulator, required for proper chip operation. When OCR_DIS is tied to VDD (regulator disabled), these pins become VDD_CORE and should be connected to a regulated 2.5V power supply. Input Input VPP1 - 2 - These pins should be left unconnected as an open circuit for normal functionality. Input Input Clock Input Mode Selection - This input determines the function of the XTAL and EXTAL pins. 1 = External clock input on XTAL is used to directly drive the input clock of the chip. The EXTAL pin should be grounded. 0 = A crystal or ceramic resonator should be connected between XTAL and EXTAL. EXTAL 82 Input Input XTAL 81 Input/ Output Chip-driven External Crystal Oscillator Input - This input can be connected to an 8MHz external crystal. Tie this pin low if XTAL is driven by an external clock source. Crystal Oscillator Output - This output connects the internal crystal oscillator output to an external crystal. If an external clock is used, XTAL must be used as the input and EXTAL connected to GND. The input clock can be selected to provide the clock directly to the core. This input clock can also be selected as the input clock for the on-chip PLL. CLKO 3 Output Tri-Stated Clock Output - This pin outputs a buffered clock signal. Using the SIM CLKO Select Register (SIM_CLKOSR), this pin can be programmed as any of the following: disabled, CLK_MSTR (system clock), IPBus clock, oscillator output, prescaler clock and postscaler clock. Other signals are also available for test purposes. See Part 6.5.7 for details. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 19 Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset A0 138 Output Tri-stated Signal Description Address Bus - A0 - A5 specify six of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A0 - A5 and EMI control signals are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. (GPIOA8) Input/ Output A1 (GPIOA9) 10 A2 (GPIOA10 GPIOA10) 11 A3 (GPIOA11 GPIOA11) 12 A4 (GPIOA12 GPIOA12) 13 A5 (GPIOA13 GPIOA13) 14 A6 17 Port A GPIO - These six GPIO pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOA_PUR register. Example: GPIOA8, clear bit 8 in the GPIOA_PUR register. Output Tri-stated Address Bus - A6 - A7 specify two of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A6 - A7 and EMI control signals are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. (GPIOE2) A7 18 Schmitt Input/ Output Input Port E GPIO - These two GPIO pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. (GPIOE3) To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOE_PUR register. Example: GPIOE2, clear bit 2 in the GPIOE_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 20 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset A8 19 Output Tri-stated Signal Description Address Bus- A8 - A15 specify eight of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A8 - A15 and EMI control signals are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. (GPIOA0) A9 (GPIOA1) 20 A10 (GPIOA2) 21 A11 (GPIOA3) 22 A12 (GPIOA4) 25 A15 (GPIOA7) Port A GPIO - These eight GPIO pins can be individually programmed as input or output pins. 24 A14 (GPIOA6) Input 23 A13 (GPIOA5) Schmitt Input/ Output 26 After reset, the default state is Address Bus. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOA_PUR register. Example: GPIOA0, clear bit 0 in the GPIOA_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 21 Table 2-2 Signal and Package Information for the 144-Pin LQFP State During Reset Signal Name Pin No. Type GPIOB0 33 Schmitt Input/ Output Input Port B GPIO - This GPIO pin can be programmed as an input or output pin. Output Tri-stated Address Bus - A16 specifies one of the address lines for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), A16 and EMI control signals are tri-stated when the external bus is inactive. (A16) Signal Description Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. After reset, the start-up state of GPIOB0 (GPIO or address) is determined as a function of EXTBOOT, EMI_MODE and the Flash security setting. See Table 4-4 for further information on when this pin is configured as an address pin at reset. In all cases, this state may be changed by writing to GPIOB_PER. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOB_PUR register. D0 59 Input/ Output Tri-stated Data Bus - D0 - D6 specify part of the data for external program or data memory accesses. Depending upon the state of the DRV bit in the EMI bus control register (BCR), D0 - D6 are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. (GPIOF9) Input/ Output D1 (GPIOF10 GPIOF10) 72 D3 (GPIOF12 GPIOF12) 75 D4 (GPIOF13 GPIOF13) 76 D5 (GPIOF14 GPIOF14) 77 D6 (GPIOF15 GPIOF15) Port F GPIO - These seven GPIO pins can be individually programmed as input or output pins. 60 D2 (GPIOF11 GPIOF11) Input 78 At reset, these pins default to the EMI Data Bus function. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOF_PUR register. Example: GPIOF9, clear bit 9 in the GPIOF_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 22 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type D7 28 Input/ Output State During Reset Tri-stated Signal Description Data Bus - D7 - D14 specify part of the data for external program or data memory accesses. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. (GPIOF0) Input/ Output D8 (GPIOF1) 30 D10 (GPIOF3) 32 D11 (GPIOF4) 133 D12 (GPIOF5) 134 D13 (GPIOF6) 135 D14 (GPIOF7) 136 D15 137 Port F GPIO - These eight GPIO pins can be individually programmed as input or output pins. 29 D9 (GPIOF2) Input At reset, these pins default to Data Bus functionality. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOF_PUR register. Example: GPIOF0, clear bit 0 in the GPIOF_PUR register. Input/ Output Tri-stated Data Bus - D15 specifies part of the data for external program or data memory accesses. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. (GPIOF8) Input/ Output Input Port F GPIO - This GPIO pin can be individually programmed as an input or output pin. At reset, this pin defaults to the Data Bus function. To deactivate the internal pull-up resistor, clear bit 8 in the GPIOF_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 23 Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset RD 45 Output Tri-stated Signal Description Read Enable - RD is asserted during external memory read cycles. When RD is asserted low, pins D0 - D15 become inputs and an external device is enabled onto the data bus. When RD is deasserted high, the external data is latched inside the device. When RD is asserted, it qualifies the A0 - A16, PS, DS, and CSn pins. RD can be connected directly to the OE pin of a Static RAM or ROM. Depending upon the state of the DRV bit in the EMI bus control register (BCR), RD is tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. To deactivate the internal pull-up resistor, set the CTRL bit in the SIM_PUDR register. WR 44 Output Tri-stated Write Enable - WR is asserted during external memory write cycles. When WR is asserted low, pins D0 - D15 become outputs and the device puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0 - A16, PS, DS, and CSn pins. WR can be connected directly to the WE pin of a static RAM. Depending upon the state of the DRV bit in the EMI bus control register (BCR), WR is tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. To deactivate the internal pull-up resistor, set the CTRL bit in the SIM_PUDR register. PS 46 Output Tri-stated (CS0) Program Memory Select - This signal is actually CS0 in the EMI, which is programmed at reset for compatibility with the 56F80x PS signal. PS is asserted low for external program memory access. Depending upon the state of the DRV bit in the EMI bus control register (BCR), CS0 is tri-stated when the external bus is inactive. CS0 resets to provide the PS function as defined on the 56F80x devices. (GPIOD8) Input/ Output Input Port D GPIO - This GPIO pin can be individually programmed as an input or output pin. To deactivate the internal pull-up resistor, clear bit 8 in the GPIOD_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 24 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset DS 47 Output Tri-stated (CS1) Signal Description Data Memory Select - This signal is actually CS1 in the EMI, which is programmed at reset for compatibility with the 56F80x DS signal. DS is asserted low for external data memory access. Depending upon the state of the DRV bit in the EMI bus control register (BCR), DS is tri-stated when the external bus is inactive. CS1 resets to provide the DS function as defined on the 56F80x devices. (GPIOD9) Input/ Output Input Port D GPIO - This GPIO pin can be individually programmed as an input or output pin. To deactivate the internal pull-up resistor, clear bit 9 in the GPIOD_PUR register. GPIOD0 48 Input Output (CS2) GPIOD1 Input/ Output Port D GPIO - These two GPIO pins can be individually programmed as input or output pins. Chip Select - CS2 - CS3 may be programmed within the EMI module to act as chip selects for specific areas of the external memory map. 49 (CS3) Depending upon the state of the DRV bit in the EMI bus control register (BCR), A0­A16 and EMI control signals are tri-stated when the external bus is inactive. Most designs will want to change the DRV state to DRV = 1 instead of using the default setting. At reset, these pins are configured as GPIO. To deactivate the internal pull-up resistor, clear the appropriate GPIO bit in the GPIOD_PUR register. Example: GPIOD0, clear bit 0 in the GPIOD_PUR register. TXD0 4 (GPIOE0) Output Tri-stated Input/ Output Input Transmit Data - SCI0 transmit data output Port E GPIO - This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOE_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 25 Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset RXD0 5 Input Input Receive Data - SCI0 receive data input Input/ Output Input Port E GPIO - This GPIO pin can be individually programmed as an input or output pin. (GPIOE1) Signal Description After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOE_PUR register. TXD1 42 Tri-stated Input/ Output (GPIOD6) Output Input Transmit Data - SCI1 transmit data output Port D GPIO - This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI output. To deactivate the internal pull-up resistor, clear bit 6 in the GPIOD_PUR register. RXD1 43 Input Receive Data - SCI1 receive data input Input/ Output (GPIOD7) Input Input Port D GPIO - This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCI input. To deactivate the internal pull-up resistor, clear bit 7 in the GPIOD_PUR register. TCK 121 Schmitt Input Input, pulled low internally Test Clock Input - This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/EOnCE port. The pin is connected internally to a pull-down resistor. TMS 122 Schmitt Input Input, pulled high internally Test Mode Select Input - This input pin is used to sequence the JTAG TAP controller's state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register. TDI 123 Schmitt Input Input, pulled high internally Test Data Input - This input pin provides a serial input data stream to the JTAG/EOnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register. 56F8356 56F8356 Technical Data, Rev. 10.0 26 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset TDO 124 Output Tri-stated Test Data Output - This tri-stateable output pin provides a serial output data stream from the JTAG/EOnCE port. It is driven in the shift-IR and shift-DR controller states, and changes on the falling edge of TCK. TRST 120 Schmitt Input Input, pulled high internally Test Reset - As an input, a low signal on this pin provides a reset signal to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware device reset is required and the JTAG/EOnCE module must not be reset. In this case, assert RESET, but do not assert TRST. Signal Description To deactivate the internal pull-up resistor, set the JTAG bit in the SIM_PUDR register. PHASEA0 139 Schmitt Input Input Phase A - Quadrature Decoder 0, PHASEA input (TA0) Schmitt Input/ Output Input TA0 - Timer A, Channel 0 (GPIOC4) Schmitt Input/ Output Input Port C GPIO - This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is PHASEA0. To deactivate the internal pull-up resistor, clear bit 4 of the GPIOC_PUR register. Schmitt Input Input Phase B - Quadrature Decoder 0, PHASEB input (TA1) Schmitt Input/ Output Input TA1 - Timer A, Channel (GPIOC5) Schmitt Input/ Output Input Port C GPIO - This GPIO pin can be individually programmed as an input or output pin. PHASEB0 140 After reset, the default state is PHASEB0. To deactivate the internal pull-up resistor, clear bit 5 of the GPIOC_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 27 Table 2-2 Signal and Package Information for the 144-Pin LQFP State During Reset Signal Name Pin No. Type Signal Description INDEX0 141 Schmitt Input Input Index - Quadrature Decoder 0, INDEX input (TA2) Schmitt Input/ Output Input TA2 - Timer A, Channel 2 (GPOPC6) Schmitt Input/ Output Input Port C GPIO - This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is INDEX0. To deactivate the internal pull-up resistor, clear bit 6 of the GPIOC_PUR register. HOME0 142 Schmitt Input Input Home - Quadrature Decoder 0, HOME input (TA3) Schmitt Input/ Output Input TA3 - Timer A, Channel 3 (GPIOC7) Schmitt Input/ Output Input Port C GPIO - This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is HOME0. To deactivate the internal pull-up resistor, clear bit 7 of the GPIOC_PUR register. SCLK0 (GPIOE4) 130 Schmitt Input/ Output Input SPI 0 Serial Clock - In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. Schmitt Input/ Output Input Port E GPIO - This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCLK0. To deactivate the internal pull-up resistor, clear bit 4 in the GPIOE_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 28 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP State During Reset Signal Name Pin No. Type MOSI0 132 Input/ Output Tri-stated SPI 0 Master Out/Slave In - This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. Input/ Output Input Port E GPIO - This GPIO pin can be individually programmed as an input or output pin. (GPIOE5) Signal Description After reset, the default state is MOSI0. To deactivate the internal pull-up resistor, clear bit 5 in the GPIOE_PUR register. MISO0 131 Input SPI 0 Master In/Slave Out - This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. Input/ Output (GPIOE6) Input/ Output Input Port E GPIO - This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is MISO0. To deactivate the internal pull-up resistor, clear bit 6 in the GPIOE_PUR register. SS0 129 (GPIOE7) Input Input SPI 0 Slave Select - SS0 is used in slave mode to indicate to the SPI module that the current transfer is to be received. Input/ Output Input Port E GPIO - This GPIO pin can be individually programmed as input or output pin. After reset, the default state is SS0. To deactivate the internal pull-up resistor, clear bit 7 in the GPIOE_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 29 Table 2-2 Signal and Package Information for the 144-Pin LQFP State During Reset Signal Description Schmitt Input Input Phase A1 - Quadrature Decoder 1, PHASEA input for decoder 1. (TB0) Schmitt Input/ Output Input TB0 - Timer B, Channel 0 (SCLK1) Schmitt Input/ Output Input SPI 1 Serial Clock - In the master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. To activate the SPI function, set the PHSA_ALT bit in the SIM_GPS register. For details, see Part 6.5.8. (GPIOC0) Schmitt Input/ Output Input Port C GPIO - This GPIO pin can be individually programmed as an input or output pin. Signal Name Pin No. Type PHASEA1 6 In the 56F8356 56F8356, the default state after reset is PHASEA1. In the 56F8156 56F8156, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 0 in the GPIOC_PUR register. PHASEB1 7 Schmitt Input Input Phase B1 - Quadrature Decoder 1, PHASEB input for decoder 1. (TB1) Schmitt Input/ Output Input TB1 - Timer B, Channel 1 (MOSI1) Schmitt Input/ Output Tri-stated SPI 1 Master Out/Slave In - This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge the slave device uses to latch the data. To activate the SPI function, set the PHSB_ALT bit in the SIM_GPS register. For details, see Part 6.5.8. (GPIOC1) Schmitt Input/ Output Input Port C GPIO - This GPIO pin can be individually programmed as an input or output pin. In the 56F8356 56F8356, the default state after reset is PHASEB1. In the 56F8156 56F8156, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 1 in the GPIOC_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 30 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP State During Reset Signal Name Pin No. Type Signal Description INDEX1 8 Schmitt Input Input Index1 - Quadrature Decoder 1, INDEX input (TB2) Schmitt Input/ Output Input TB2 - Timer B, Channel 2 (MISO1) Schmitt Input/ Output Input SPI 1 Master In/Slave Out - This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. The slave device places data on the MISO line a half-cycle before the clock edge the master device uses to latch the data. To activate the SPI function, set the INDEX_ALT bit in the SIM_GPS register. For details, see Part 6.5.8. (GPIOC2) Schmitt Input/ Output Input Port C GPIO - This GPIO pin can be individually programmed as an input or output pin. In the 56F8356 56F8356, the default state after reset is INDEX1. In the 56F8156 56F8156, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 2 in the GPIOC_PUR register. Schmitt Input Input Home - Quadrature Decoder 1, HOME input (TB3) Schmitt Input/ Output Input TB3 - Timer B, Channel 3 (SS1) Schmitt Input Input SPI 1 Slave Select - In the master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. To activate the SPI function, set the HOME_ALT bit in the SIM_GPS register. For details, see Part 6.5.8. (GPIOC3) Schmitt Input/ Output Input Port C GPIO - This GPIO pin can be individually programmed as an input or output pin. HOME1 9 In the 56F8356 56F8356, the default state after reset is HOME1. In the 56F8156 56F8156, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear bit 3 in the GPIOC_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 31 Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset PWMA0 62 Output Tri-State PWMA1 64 PWMA2 65 PWMA3 67 PWMA4 68 PWMA5 70 ISA0 113 Schmitt Input Input ISA0 - 2 - These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMA. Schmitt Input/ Output Input Port C GPIO - These GPIO pins can be individually programmed as input or output pins. (GPIOC8) ISA1 (GPIOC9) 114 ISA2 (GPIOC10 GPIOC10) 115 Signal Description PWMA0 - 5 - These are six PWMA outputs. In the 56F8356 56F8356, these pins default to ISA functionality after reset. In the 56F8156 56F8156, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pull-up resistor, clear the appropriate bit of the GPIOC_PUR register. For details, see Part 6.5.8. FaultA0 71 FaultA1 73 FaultA2 74 PWMB0 34 PWMB1 35 PWMB2 36 PWMB3 39 PWMB4 40 PWMB5 Schmitt Input Input FaultA0 - 2 - These three fault input pins are used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. 41 To deactivate the internal pull-up resistor, set the PWMA0 bit in the SIM_PUDR register. For details, see Part 6.5.8. Output Tri-State PWMB0 - 5 - Six PWMB output pins. 56F8356 56F8356 Technical Data, Rev. 10.0 32 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP State During Reset Signal Name Pin No. Type ISB0 50 Schmitt Input Input ISB0 - 2 - These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMB. Schmitt Input/ Output Input Port D GPIO - These GPIO pins can be individually programmed as input or output pins. (GPIOD10 GPIOD10) ISB1 (GPIOD11 GPIOD11) 52 ISB2 (GPIOD12 GPIOD12) 53 FaultB0 56 FaultB1 57 FaultB2 58 FaultB3 61 ANA0 88 ANA1 89 ANA2 90 ANA3 91 ANA4 92 ANA5 93 ANA6 94 ANA7 95 VREFH Signal Description At reset, these pins default to ISB functionality. To deactivate the internal pull-up resistor, clear the appropriate bit of the GPIOD_PUR register. For details, see Part 6.5.8. Schmitt Input Input FaultB0 - 3 - These four fault input pins are used for disabling selected PWMB outputs in cases where fault conditions originate off-chip. To deactivate the internal pull-up resistor, set the PWMB bit in the SIM_PUDR register. For details, see Part 6.5.8. Input Input ANA0 - 3 - Analog inputs to ADC A, channel 0 Input Input ANA4 - 7 - Analog inputs to ADC A, channel 1 101 Input Input VREFH - Analog Reference Voltage High. VREFH must be less than or equal to VDDA_ADC. VREFP 100 Input/ Output Input/ Output VREFMID 99 VREFN 98 VREFLO 97 Input Input VREFP, VREFMID & VREFN - Internal pins for voltage reference which are brought off-chip so they can be bypassed. Connect to a 0.1µF low ESR capacitor. VREFLO - Analog Reference Voltage Low. This should normally be connected to a low-noise VSS. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 33 Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type State During Reset ANB0 104 Input Input ANB0 - 3 - Analog inputs to ADC B, channel 0 ANB1 105 ANB2 106 ANB3 107 ANB4 108 Input Input ANB4 - 7 - Analog inputs to ADC B, channel 1 ANB5 109 ANB6 110 ANB7 111 TEMP_SENSE 96 Output Output Temperature Sense Diode - This signal connects to an on-chip diode that can be connected to one of the ADC inputs and used to monitor the temperature of the die. Must be bypassed with a 0.01µF capacitor. CAN_RX 127 Schmitt Input Input FlexCAN Receive Data - This is the CAN input. This pin has an internal pull-up resistor. Signal Description To deactivate the internal pull-up resistor, set the CAN bit in the SIM_PUDR register. CAN_TX 126 Open Drain Output Open Drain Output TC0 118 Schmitt Input/ Output Input TC0 - Timer C, Channel 0 Schmitt Input/ Output Input Port E GPIO - This GPIO pin can be individually programmed as an input or output pin. (GPIOE8) FlexCAN Transmit Data - CAN output At reset, this pin defaults to timer functionality. To deactivate the internal pull-up resistor, clear bit 8 of the GPIOE_PUR register. 56F8356 56F8356 Technical Data, Rev. 10.0 34 Freescale Semiconductor Preliminary Signal Pins Table 2-2 Signal and Package Information for the 144-Pin LQFP State During Reset Signal Name Pin No. Type TD0 116 Schmitt Input/ Output Input TD0 - 1 - Timer D, Channels 0 and 1 Schmitt Input/ Output Input Port E GPIO - These GPIO pins can be individually programmed as input or output pins. (GPIOE10 GPIOE10) TD1 (GPIOE11 GPIOE11) 117 Signal Description At reset, these pins default to Timer functionality. To deactivate the internal pull-up resistor, clear the appropriate bit of the GPIOE_PUR register. See Part 6.5.6 for details. IRQA 54 IRQB Schmitt Input Input 55 External Interrupt Request A and B - The IRQA and IRQB inputs are asynchronous external interrupt requests during Stop and Wait mode operation. During other operating modes, they are synchronized external interrupt requests, which indicate an external device is requesting service. They can be programmed to be level-sensitive or negative-edge triggered. To deactivate the internal pull-up resistor, set the IRQ bit in the SIM_PUDR register. See Part 6.5.6 for details. RESET 86 Schmitt Input Input Reset - This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and the JTAG/EOnCE module must not be reset. In this case, assert RESET but do not assert TRST. Note: The internal Power-On Reset will assert on initial power-up. To deactivate the internal pull-up resistor, set the RESET bit in the SIM_PUDR register. See Part 6.5.6 for details. RSTO 85 Output Output Reset Output - This output reflects the internal reset state of the chip. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 35 Table 2-2 Signal and Package Information for the 144-Pin LQFP Signal Name Pin No. Type EXTBOOT 112 Schmitt Input State During Reset Input Signal Description External Boot - This input is tied to VDD to force the device to boot from off-chip memory (assuming that the on-chip Flash memory is not in a secure state). Otherwise, it is tied to ground. For details, see Table 4-4. Note: When this pin is tied low, the customer boot software should disable the internal pull-up resistor by setting the XBOOT bit of the SIM_PUDR; see Part 6.5.6. EMI_MODE 143 Schmitt Input Input External Memory Mode - The EMI_MODE input is internally tied low (to VSS). This device will boot from internal flash memory under normal operation. This function is also affected by EXTBOOT and the Flash security mode. For details, see Table 4-4. If a 20-bit address bus is not desired, then this pin is tied to ground. Note: When this pin is tied low, the customer boot software should disable the internal pull-up resistor by setting the EMI_MODE bit of the SIM_PUDR; see Part 6.5.6. 56F8356 56F8356 Technical Data, Rev. 10.0 36 Freescale Semiconductor Preliminary Introduction Part 3 On-Chip Clock Synthesis (OCCS) 3.1 Introduction Refer to the OCCS chapter of the 56F8300 56F8300 Peripheral User Manual for a full description of the OCCS. The material contained here identifies the specific features of the OCCS design. Figure 3-1 shows the specific OCCS block diagram to reference from the OCCS chapter of the 56F8300 56F8300 Peripheral User Manual. CLKMODE XTAL ZSRC MUX Crystal OSC PLLCID PLL FOUT x (1 to 128) FEEDBACK MSTR_OSC PLLCOD PLLDB FREF Prescaler ÷ (1,2,4,8) MUX Prescaler CLK EXTAL ÷2 FOUT/2 Postscaler ÷ (1,2,4,8) Postscaler CLK Bus Interface & Control Bus Interface LCK Lock Detector Loss of Reference Clock Detector SYS_CLK2 Source to SIM Loss of Reference Clock Interrupt Figure 3-1 OCCS Block Diagram 3.2 External Clock Operation The system clock can be derived from an external crystal, ceramic resonator, or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal or ceramic resonator must be connected between the EXTAL and XTAL pins. 3.2.1 Crystal Oscillator The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 10-15. A recommended crystal oscillator circuit is shown in Figure 3-2. Follow the crystal supplier's recommendations when selecting a crystal, since crystal 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 37 parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as near as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. Crystal Frequency = 4 - 8MHz (optimized for 8MHz) EXTAL XTAL Rz EXTAL XTAL Rz Sample External Crystal Parameters: Rz = 750 K Note: If the operating temperature range is limited to below 85oC (105oC junction), then Rz = 10 Meg CLKMODE = 0 CL1 CL2 Figure 3-2 Connecting to a Crystal Oscillator Note: The OCCS_COHL bit must be set to 1 when a crystal oscillator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 56F8300 Peripheral User Manual. 3.2.2 Ceramic Resonator (Default) It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in Figure 3-3. Refer to the supplier's recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as near as possible to the EXTAL and XTAL pins. Resonator Frequency = 4 - 8MHz (optimized for 8MHz) 3 Terminal 2 Terminal EXTAL XTAL EXTAL Rz CL1 XTAL Rz Sample External Ceramic Resonator Parameters: Rz = 750 K CLKMODE = 0 CL2 C1 C2 Figure 3-3 Connecting a Ceramic Resonator Note: The OCCS_COHL bit must be set to 0 when a ceramic resonator is used. The reset condition on the OCCS_COHL bit is 0. Please see the COHL bit in the Oscillator Control (OSCTL) register, discussed in the 56F8300 56F8300 Peripheral User Manual. 56F8356 56F8356 Technical Data, Rev. 10.0 38 Freescale Semiconductor Preliminary Registers 3.2.3 External Clock Source The recommended method of connecting an external clock is given in Figure 3-4. The external clock source is connected to XTAL and the EXTAL pin is grounded. Set OCCS_COHL bit high when using an external clock source as well. XTAL EXTAL External Clock VSS Note: When using an external clocking source with this configuration, the input "CLKMODE" should be high and the COHL bit in the OSCTL register should be set to 1. Figure 3-4 Connecting an External Clock Register 3.3 Registers When referring to the register definitions for the OCCS in the 56F8300 56F8300 Peripheral User Manual, use the register definitions without the internal Relaxation Oscillator, since the 56F8356/56F8156 56F8356/56F8156 devices do NOT contain this oscillator. Part 4 Memory Map 4.1 Introduction The 56F8356 56F8356 and 56F8156 56F8156 devices are 16-bit motor-control chips based on the 56800E 56800E core. These parts use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip RAM and Flash memories are used in both spaces. This section provides memory maps for: · · Program Address Space, including the Interrupt Vector Table Data Address Space, including the EOnCE Memory and Peripheral Memory Maps On-chip memory sizes for each device are summarized in Table 4-1. Flash memories' restrictions are identified in the "Use Restrictions" column of Table 4-1. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 39 Note: Data Flash and Program RAM are NOT available on the 56F8156 56F8156 device. Table 4-1 Chip Memory Configurations On-Chip Memory 56F8356 56F8356 56F8156 56F8156 Use Restrictions Program Flash 256KB 256KB 256KB 256KB Erase / Program via Flash interface unit and word writes to CDBW Data Flash 8KB - Erase / Program via Flash interface unit and word writes to CDBW. Data Flash can be read via either CDBR or XDB2, but not by both simultaneously Program RAM 4KB - None Data RAM 16KB 16KB None Program Boot Flash 16KB 16KB Erase / Program via Flash Interface unit and word to CDBW 4.2 Program Map The operating mode control bits (MA and MB) in the Operating Mode Register (OMR) control the Program memory map. At reset, these bits are set as indicated in Table 4-2. Table 4-4 shows the memory map configurations that are possible at reset. After reset, the OMR MA bit can be changed and will have an effect on the P-space memory map, as shown in Table 4-3. Changing the OMR MB bit will have no effect. Table 4-2 OMR MB/MAL Value at Reset OMR MB = Flash Secured State1, 2 OMR MA = EXTBOOT Pin 0 0 Mode 0 ­ Internal Boot; EMI is configured to use 16 address lines; Flash Memory is secured; external P-space is not allowed; the EOnCE is disabled 0 1 Not valid; cannot boot externally if the Flash is secured and will actually configure to 00 state 1 0 Mode 0 ­ Internal Boot; EMI is configured to use 16 address lines 1 1 Mode 1 ­ External Boot; Flash Memory is not secured; EMI configuration is determined by the state of the EMI_MODE pin Chip Operating Mode 1. This bit is only configured at reset. If the Flash secured state changes, this will not be reflected in MB until the next reset. 2. Changing MB in software will not affect Flash memory security. 56F8356 56F8356 Technical Data, Rev. 10.0 40 Freescale Semiconductor Preliminary Program Map Table 4-3 Changing OMR MA Value During Normal Operation OMR MA Chip Operating Mode 0 Use internal P-space memory map configuration 1 Use external P-space memory map configuration ­ If MB = 0 at reset, changing this bit has no effect. The device's external memory interface (EMI) can operate much like the 56F80x family's EMI, or it can be operated in a mode similar to that used on other products in the 56800E 56800E family. Initially, CS0 and CS1 are configured as PS and DS, in a mode compatible with earlier 56800 devices. Eighteen address lines are required to shadow the first 192K of internal program space when booting externally for development purposes. Therefore, the entire complement of on-chip memory cannot be accessed using a 16-bit 56800-compatible address bus. To address this situation, the EMI_MODE pin can be used to configure four GPIO pins as Address[19:16] upon reset (only one of these pins [A16] is usable in the 56F8356/56F8156 56F8356/56F8156). The EMI_MODE pin also affects the reset vector address, as provided in Table 4-4. Additional pins must be configured as address or chip select signals to access addresses at P:$10 0000 and above. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 41 Note: Program RAM is NOT available on the 56F8156 56F8156 device. Table 4-4 Program Memory Map at Reset Mode 0 (MA = 0) Begin/End Address Mode 11 (MA = 1) Internal Boot External Boot Internal Boot 16-Bit External Address Bus P:$1F FFFF P:$10 0000 External Program Memory5 EMI_MODE = 02,3 16-Bit External Address Bus External Program Memory5 EMI_MODE = 14 20-Bit External Address Bus External Program Memory5 P:$0F FFFF P:$03 0000 P:$02 FFFF P:$02 F800 On-Chip Program RAM 4KB P:$02 F7FF P:$02 2000 Reserved 116KB 116KB P:$02 1FFF P:$02 0000 Boot Flash 16KB COP Reset Address = 02 0002 Boot Location = 02 0000 External Program RAM Boot Flash COP Reset Address = 02 00026 16KB (Not Used for Boot in this Mode) Boot Location = 02 00006 P:$01 FFFF P:$01 0000 Internal Program Flash7 128KB 128KB Internal Program Flash 128KB 128KB P:$00 FFFF P:$00 0000 Internal Program Flash7 128KB 128KB External Program RAM COP Reset Address = 00 0002 Boot Location = 00 0000 1. If Flash Security Mode is enabled, EXTBOOT Mode 1 cannot be used. See Security Features, Part 7. 2. This mode provides maximum compatibility with 56F80x parts while operating externally. 3. "EMI_MODE =0" when EMI_MODE pin is tied to ground at boot up. 4. "EMI_MODE =1" when EMI_MODE pin is tied to VDD at boot up. 5. Not accessible in reset configuration, since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip selects) pins must be reconfigured before this external memory is accessible. 6. Booting from this external address allows prototyping of the internal Boot Flash. 7. Two independent program flash blocks allow one to be programmed/erased while executing from another. Each block must have its own mass erase. 4.3 Interrupt Vector Table Table 4-5 provides the reset and interrupt priority structure, including on-chip peripherals. The table is organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The priority of an interrupt can be assigned to different levels, as indicated, allowing some control over interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority level, the lowest vector number has the highest priority. 56F8356 56F8356 Technical Data, Rev. 10.0 42 Freescale Semiconductor Preliminary Interrupt Vector Table The location of the vector table is determined by the Vector Base Address (VBA) register. Please see Part 5.6.12 for the reset value of the VBA. In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the interrupt vector table. In these instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR instructions. Note: PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the 56F8156 56F8156 device. Table 4-5 Interrupt Vector Table Contents1 Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function Reserved for Reset Overlay2 Reserved for COP Reset Overlay2 core 2 3 P:$04 Illegal Instruction core 3 3 P:$06 SW Interrupt 3 core 4 3 P:$08 HW Stack Overflow core 5 3 P:$0A Misaligned Long Word Access core 6 1-3 P:$0C OnCE Step Counter core 7 1-3 P:$0E OnCE Breakpoint Unit 0 Reserved core 9 1-3 P:$12 OnCE Trace Buffer core 10 1-3 P:$14 OnCE Transmit Register Empty core 11 1-3 P:$16 OnCE Receive Register Full Reserved core 14 2 P:$1C SW Interrupt 2 core 15 1 P:$1E SW Interrupt 1 core 16 0 P:$20 SW Interrupt 0 core 17 0-2 P:$22 IRQA core 18 0-2 P:$24 IRQB Reserved LVI 20 0-2 P:$28 Low-Voltage Detector (power sense) PLL 21 0-2 P:$2A PLL FM 22 0-2 P:$2C FM Access Error Interrupt FM 23 0-2 P:$2E FM Command Complete FM 24 0-2 P:$30 FM Command, data and address Buffers Empty 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 43 Table 4-5 Interrupt Vector Table Contents1 (Continued) Peripheral Vector Number Priority Level Vector Base Address + Interrupt Function Reserved FLEXCAN 26 0-2 P:$34 FLEXCAN Bus Off FLEXCAN 27 0-2 P:$36 FLEXCAN Error FLEXCAN 28 0-2 P:$38 FLEXCAN Wake Up FLEXCAN 29 0-2 P:$3A FLEXCAN Message Buffer Interrupt GPIOF 30 0-2 P:$3C GPIOF GPIOE 31 0-2 P:$3E GPIOE GPIOD 32 0-2 P:$40 GPIOD GPIOC 33 0-2 P:$42 GPIOC GPIOB 34 0-2 P:$44 GPIOB GPIOA 35 0-2 P:$46 GPIOA Reserved SPI1 38 0-2 P:$4C SPI 1 Receiver Full SPI1 39 0-2 P:$4E SPI 1 Transmitter Empty SPI0 40 0-2 P:$50 SPI 0 Receiver Full SPI0 41 0-2 P:$52 SPI 0 Transmitter Empty SCI1 42 0-2 P:$54 SCI 1 Transmitter Empty SCI1 43 0-2 P:$56 SCI 1 Transmitter Idle Reserved SCI1 45 0-2 P:$5A SCI 1 Receiver Error SCI1 46 0-2 P:$5C SCI 1 Receiver Full DEC1 47 0-2 P:$5E Quadrature Decoder #1 Home Switch or Watchdog DEC1 48 0-2 P:$60 Quadrature Decoder #1 INDEX Pulse DEC0 49 0-2 P:$62 Quadrature Decoder #0 Home Switch or Watchdog DEC0 50 0-2 P:$64 Quadrature Decoder #0 INDEX Pulse Reserved TMRD 52 0-2 P:$68 Timer D, Channel 0 TMRD 53 0-2 P:$6A Timer D, Channel 1 TMRD 54 0-2 P:$6C Timer D, Channel 2 TMRD 55 0-2 P:$6E Timer D, Channel 3 TMRC 56 0-2 P:$70 Timer C, Channel 0 TMRC 57 0-2 P:$72 Timer C, Channel 1 56F8356 56F8356 Technical Data, Rev. 10.0 44 Freescale Semiconductor Preliminary Interrupt Vector Table Table 4-5 Interrupt Vector Table Contents1 (Continued) Vector Number Priority Level Vector Base Address + TMRC 58 0-2 P:$74 Timer C, Channel 2 TMRC 59 0-2 P:$76 Timer C, Channel 3 TMRB 60 0-2 P:$78 Timer B, Channel 0 TMRB 61 0-2 P:$7A Timer B, Channel 1 TMRB 62 0-2 P:$7C Timer B, Channel 2 TMRB 63 0-2 P:$7E Timer B, Channel 3 TMRA 64 0-2 P:$80 Timer A, Channel 0 TMRA 65 0-2 P:$82 Timer A, Channel 1 TMRA 66 0-2 P:$84 Timer A, Channel 2 TMRA 67 0-2 P:$86 Timer A, Channel 3 SCI0 68 0-2 P:$88 SCI 0 Transmitter Empty SCI0 69 0-2 P:$8A SCI 0 Transmitter Idle Peripheral Interrupt Function Reserved SCI0 71 0-2 P:$8E SCI 0 Receiver Error SCI0 72 0-2 P:$90 SCI 0 Receiver Full ADCB 73 0-2 P:$92 ADC B Conversion Compete / End of Scan ADCA 74 0-2 P:$94 ADC A Conversion Complete / End of Scan ADCB 75 0-2 P:$96 ADC B Zero Crossing or Limit Error ADCA 76 0-2 P:$98 ADC A Zero Crossing or Limit Error PWMB 77 0-2 P:$9A Reload PWM B PWMA 78 0-2 P:$9C Reload PWM A PWMB 79 0-2 P:$9E PWM B Fault PWMA 80 0-2 P:$A0 PWM A Fault core 81 -1 P:$A2 SW Interrupt LP 1. Two words are allocated for each entry in the vector table. This does not allow the full address range to be referenced from the vector table, providing only 19 bits of address. 2. If the VBA is set to $0200 (or VBA = 0000 for Mode 1, EMI_MODE = 0), the first two locations of the vector table are the chip reset addresses; therefore, these locations are not interrupt vectors. 2. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 45 4.4 Data Map Note: Data Flash is NOT available on the 56F8156 56F8156 device. Table 4-6 Data Memory Map1 Begin/End Address EX = 02 EX = 1 X:$FF FFFF X:$FF FF00 EOnCE 256 locations allocated EOnCE 256 locations allocated X:$FF FEFF X:$01 0000 External Memory External Memory X:$00 FFFF X:$00 F000 On-Chip Peripherals 4096 locations allocated On-Chip Peripherals 4096 locations allocated X:$00 EFFF X:$00 3000 External Memory External Memory X:$00 2FFF X:$00 2000 On-Chip Data Flash 8KB X:$00 1FFF X:$00 0000 On-Chip Data RAM 16KB3 16KB3 1. All addresses are 16-bit Word addresses, not byte addresses. 2. In the Operation Mode Register (OMR). 3. The Data RAM is organized as a 2K x 32-bit memory to allow single-cycle long-word operations. 4.5 Flash Memory Map Figure 4-1 illustrates the Flash Memory (FM) map on the system bus. The Flash Memory is divided into three functional blocks. The Program and boot memories reside on the Program Memory buses. They are controlled by one set of banked registers. Data Memory Flash resides on the Data Memory buses and is controlled separately by its own set of banked registers. The top nine words of the Program Memory Flash are treated as special memory locations. The content of these words is used to control the operation of the Flash Controller. Because these words are part of the Flash Memory content, their state is maintained during power-down and reset. During chip initialization, the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash Memory chapter of the 56F8300 56F8300 Peripheral User Manual. These configuration parameters are located between $01_FFF7 and $01_FFFF. 56F8356 56F8356 Technical Data, Rev. 10.0 46 Freescale Semiconductor Preliminary Flash Memory Map Program Memory BOOT_FLASH_START + $1FFF BOOT_FLASH_START = $20_0000 PROG_FLASH_START + $01_FFFF PROG_FLASH_START + $01_FFF7 PROG_FLASH_START + $01_FFF6 Data Memory FM_BASE + $14 16KB Boot Configure Field FM_BASE + $00 Banked Registers Unbanked Registers FM_PROG_MEM_TOP = $01_FFFF DATA_FLASH_START + $0FFF 128KB 128KB Program 8KB DATA_FLASH_START + $0000 BLOCK 1 Odd (2 Bytes) $01_0003 BLOCK 1 Even (2 Bytes) $01_0002 BLOCK 1 Odd (2 Bytes) $01_0001 BLOCK 1 Even (2 Bytes) $01_0000 PROG_FLASH_START + $01_0000 PROG_FLASH_START + $00_FFFF Note: Data Flash is NOT available in the 56F8156 56F8156 device. 128KB 128KB Program BLOCK 0 Odd (2 Bytes) $00_0003 BLOCK 0 Even (2 Bytes) $00_0002 BLOCK 0 Odd (2 Bytes) $00_0001 BLOCK 0 Even (2 Bytes) $00_0000 PROG_FLASH_START = $00_0000 Figure 4-1 Flash Array Memory Maps Table 4-7 shows the page and sector sizes used within each Flash memory block on the chip. Note: Data Flash is NOT available in the 56F8156 56F8156 device. Table 4-7. Flash Memory Partitions Flash Size Sectors Sector Size Page Size Program Flash 256KB 256KB 16 8K x 16 bits 512 x 16 bits Data Flash 8KB 16 256 x 16 bits 256 x 16 bits Boot Flash 16KB 4 2K x 16 bits 256 x 16 bits Please see 56F8300 56F8300 Peripheral User Manual for additional Flash information. 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 47 4.6 EOnCE Memory Map Table 4-8 EOnCE Memory Map Address Register Acronym Register Name Reserved X:$FF FF8A OESCR External Signal Control Register Reserved X:$FF FF8E OBCNTR Breakpoint Unit [0] Counter Reserved X:$FF FF90 OBMSK (32 bits) Breakpoint 1 Unit [0] Mask Register X:$FF FF91 - Breakpoint 1 Unit [0] Mask Register X:$FF FF92 OBAR2 (32 bits) Breakpoint 2 Unit [0] Address Register X:$FF FF93 - Breakpoint 2 Unit [0] Address Register X:$FF FF94 OBAR1 (24 bits) Breakpoint 1 Unit [0] Address Register X:$FF FF95 - Breakpoint 1 Unit [0] Address Register X:$FF FF96 OBCR (24 bits) Breakpoint Unit [0] Control Register X:$FF FF97 - Breakpoint Unit [0] Control Register X:$FF FF98 OTB (21-24 bits/stage) Trace Buffer Register Stages X:$FF FF99 - Trace Buffer Register Stages X:$FF FF9A OTBPR (8 bits) Trace Buffer Pointer Register X:$FF FF9B OTBCR Trace Buffer Control Register X:$FF FF9C OBASE (8 bits) Peripheral Base Address Register X:$FF FF9D OSR Status Register X:$FF FF9E OSCNTR (24 bits) Instruction Step Counter X:$FF FF9F - Instruction Step Counter :X:$FF FFA0 OCR (bits) Control Register Reserved X:$FF FFFC OCLSR (8 bits) Core Lock / Unlock Status Register X:$FF FFFD OTXRXSR (8 bits) Transmit and Receive Status and Control Register X:$FF FFFE OTX / ORX (32 bits) Transmit Register / Receive Register X:$FF FFFF OTX1 / ORX1 Transmit Register Upper Word Receive Register Upper Word 56F8356 56F8356 Technical Data, Rev. 10.0 48 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers 4.7 Peripheral Memory Mapped Registers On-chip peripheral registers are part of the data memory map on the 56800E 56800E series. These locations may be accessed with the same addressing modes used for ordinary Data memory, except all peripheral registers should be read/written using word accesses only. Table 4-9 summarizes base addresses for the set of peripherals on the 56F8356 56F8356 and 56F8156 56F8156 devices. Peripherals are listed in order of the base address. The following tables list all of the peripheral registers required to control or access the peripherals. Note: Features in italics are NOT available in the 56F8156 56F8156 device. Table 4-9 Data Memory Peripheral Base Address Map Summary Peripheral Prefix Base Address Table Number External Memory Interface EMI X:$00 F020 4-10 Timer A TMRA X:$00 F040 4-11 Timer B TMRB X:$00 F080 4-12 Timer C TMRC X:$00 F0C0 4-13 Timer D TMRD X:$00 F100 4-14 PWM A PWMA X:$00 F140 4-15 PWM B PWMB X:$00 F160 4-16 Quadrature Decoder 0 DEC0 X:$00 F180 4-17 Quadrature Decoder 1 DEC1 X:$00 F190 4-18 ITCN ITCN X:$00 F1A0 4-19 ADC A ADCA X:$00 F200 4-20 ADC B ADCB X:$00 F240 4-21 Temperature Sensor TSENSOR X:$00 F270 4-22 SCI #0 SCI0 X:$00 F280 4-23 SCI #1 SCI1 X:$00 F290 4-24 SPI #0 SPI0 X:$00 F2A0 4-25 SPI #1 SPI1 X:$00 F2B0 4-26 COP COP X:$00 F2C0 4-27 PLL, OSC CLKGEN X:$00 F2D0 4-28 GPIO Port A GPIOA X:$00 F2E0 4-29 GPIO Port B GPIOB X:$00 F300 4-30 GPIO Port C GPIOC X:$00 F310 4-31 GPIO Port D GPIOD X:$00 F320 4-32 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 49 Table 4-9 Data Memory Peripheral Base Address Map Summary (Continued) Peripheral Prefix Base Address Table Number GPIO Port E GPIOE X:$00 F330 4-33 GPIO Port F GPIOF X:$00 F340 4-34 SIM SIM X:$00 F350 4-35 Power Supervisor LVI X:$00 F360 4-36 FM FM X:$00 F400 4-37 FlexCAN FC X:$00 F800 4-38 Table 4-10 External Memory Integration Registers Address Map (EMI_BASE = $00 F020) Register Acronym CSBAR 0 Address Offset $0 Register Description Chip Select Base Address Register 0 Reset Value 0x0004 = 64K when EXT_BOOT = 0 or EMI_MODE = 0 0x0008 = 1M when EMI_MODE = 1 (Selects entire program space for CS0) Note that A17-A19 A17-A19 are not available in the package CSBAR 1 $1 Chip Select Base Address Register 1 0x0004 = 64K when EMI_MODE = 0 0x0008 = 1M when EMI_MODE = 1 (Selects A0-A19 A0-A19 addressable data space for CS1) Note that A17-A19 A17-A19 are not available in the package CSBAR 2 $2 Chip Select Base Address Register 2 CSBAR 3 $3 Chip Select Base Address Register 3 CSBAR 4 $4 Chip Select Base Address Register 4 CSBAR 5 $5 Chip Select Base Address Register 5 CSBAR 6 $6 Chip Select Base Address Register 6 CSBAR 7 $7 Chip Select Base Address Register 7 56F8356 56F8356 Technical Data, Rev. 10.0 50 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-10 External Memory Integration Registers Address Map (Continued) (EMI_BASE = $00 F020) Register Acronym Address Offset Register Description Reset Value CSOR 0 $8 Chip Select Option Register 0 0x5FCB programmed for chip select for program space, word wide, read and write, 11 waits CSOR 1 $9 Chip Select Option Register 1 0x5FAB programmed for chip select for data space, word wide, read and write, 11 waits CSOR 2 $A Chip Select Option Register 2 CSOR 3 $B Chip Select Option Register 3 CSOR 4 $C Chip Select Option Register 4 CSOR 5 $D Chip Select Option Register 5 CSOR 6 $E Chip Select Option Register 6 CSOR 7 $F Chip Select Option Register 7 CSTC 0 $10 Chip Select Timing Control Register 0 CSTC 1 $11 Chip Select Timing Control Register 1 CSTC 2 $12 Chip Select Timing Control Register 2 CSTC 3 $13 Chip Select Timing Control Register 3 CSTC 4 $14 Chip Select Timing Control Register 4 CSTC 5 $15 Chip Select Timing Control Register 5 CSTC 6 $16 Chip Select Timing Control Register 6 CSTC 7 $17 Chip Select Timing Control Register 7 BCR $18 Bus Control Register 0x016B sets the default number of wait states to 11 for both read and write accesses Table 4-11 Quad Timer A Registers Address Map (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA0_CMP1 $0 Compare Register 1 TMRA0_CMP2 $1 Compare Register 2 TMRA0_CAP $2 Capture Register TMRA0_LOAD $3 Load Register TMRA0_HOLD $4 Hold Register TMRA0_CNTR $5 Counter Register TMRA0_CTRL $6 Control Register 56F8356 56F8356 Technical Data, Rev. 10.0 Freescale Semiconductor Preliminary 51 Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA0_SCR $7 Status and Control Register TMRA0_CMPLD1 $8 Comparator Load Register 1 TMRA0_CMPLD2 $9 Comparator Load Register 2 TMRA0_COMSCR $A Comparator Status and Control Register Reserve TMRA1_CMP1 $10 Compare Register 1 TMRA1_CMP2 $11 Compare Register 2 TMRA1_CAP $12 Capture Register TMRA1_LOAD $13 Load Register TMRA1_HOLD $14 Hold Register TMRA1_CNTR $15 Counter Register TMRA1_CTRL $16 Control Register TMRA1_SCR $17 Status and Control Register TMRA1_CMPLD1 $18 Comparator Load Register 1 TMRA1_CMPLD2 $19 Comparator Load Register 2 TMRA1_COMSCR $1A Comparator Status and Control Register Reserved TMRA2_CMP1 $20 Compare Register 1 TMRA2_CMP2 $21 Compare Register 2 TMRA2_CAP $22 Capture Register TMRA2_LOAD $23 Load Register TMRA2_HOLD $24 Hold Register TMRA2_CNTR $25 Counter Register TMRA2_CTRL $26 Control Register TMRA2_SCR $27 Status and Control Register TMRA2_CMPLD1 $28 Comparator Load Register 1 TMRA2_CMPLD2 $29 Comparator Load Register 2 TMRA2_COMSCR $2A Comparator Status and Control Register Reserved TMRA3_CMP1 $30 Compare Register 1 TMRA3_CMP2 $31 Compare Register 2 TMRA3_CAP $32 Capture Register 56F8356 56F8356 Technical Data, Rev. 10.0 52 Freescale Semiconductor Preliminary Peripheral Memory Mapped Registers Table 4-11 Quad Timer A Registers Address Map (Continued) (TMRA_BASE = $00 F040) Register Acronym Address Offset Register Description TMRA3_LOAD $33 Load Register TMRA3_HOLD $34 Hold Register TMRA3_CNTR $35 Counter Register